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PCM1798
SLES102B – DECEMBER 2003 – REVISED MARCH 2015
PCM1798 24-Bit, 192-kHz Sampling, Advanced Segment,
Audio Stereo Digital-to-Analog Converter
1 Features
2 Applications
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24-Bit Resolution
Analog Performance:
– Dynamic Range: 123 dB
– THD+N: 0.0005%
Differential Current Output: 4 mAp-p
8× Oversampling Digital Filter:
– Stop-Band Attenuation: –98 dB
– Pass-Band Ripple: ±0.0002 dB
Sampling Frequency: 10 kHz to 200 kHz
System Clock: 128, 192, 256, 384, 512, or 768 fS
With Autodetect
Accepts 16- and 24-Bit Audio Data
PCM Data Formats: Standard, I2S, and LeftJustified
Interface Available for Optional External Digital
Filter or DSP
Digital De-Emphasis
Digital Filter Rolloff: Sharp or Slow
Soft Mute
Zero Flag
Dual-Supply Operation: 5-V Analog, 3.3-V Digital
5-V Tolerant Digital Inputs
Small 28-Lead SSOP Package
Pin Assignment Compatible With PCM1794
A/V Receivers
DVD Players
Musical Instruments
HDTV Receivers
Car Audio Systems
Digital Multitrack Recorders
Other Applications Requiring 24-Bit Audio
3 Description
The PCM1798 device is a monolithic CMOS
integrated circuit that includes stereo digital-to-analog
converters (DACs) and support circuitry in a small 28lead SSOP package. The data converters use TI’s
advanced segment DAC architecture to achieve
excellent dynamic performance and improved
tolerance to clock jitter. The PCM1798 device
provides balanced current outputs, allowing the user
to optimize analog performance externally. Sampling
rates up to 200 kHz are supported.
Device Information(1)
PART NUMBER
PCM1798
PACKAGE
SSOP (28)
BODY SIZE (NOM)
10.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
IOUT L–
LRCK
BCK
DATA
Audio
Data Input
I/F
Current
Segment
DAC
VOUT L
IOUTL+
MUTE
FMT1
FMT0
MONO
CHSL
Function
Control
I/F
´8
Oversampling
Digital
Filter
and
Function
Control
VCOM L
Advanced
Segment
DAC
Modulator
Bias
and
Vref
I/V and Filter
IREF
VCOM R
IOUT R–
Current
Segment
DAC
DEM
RST
VOUT R
IOUT R+
I/V and Filter
System
Clock
Manager
VCC2R
VCC1
VCC2L
AGND3R
AGND2
AGND3L
VDD
AGND1
Power Supply
DGND
Zero
Detect
SCK
ZERO
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1798
SLES102B – DECEMBER 2003 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements ................................................ 7
Typical Characteristics for Digital Filter ................. 10
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1 Trademarks ........................................................... 24
11.2 Electrostatic Discharge Caution ............................ 24
11.3 Glossary ................................................................ 24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Revision A (November 2006) to Revision B
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Recommended Operating Conditions table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
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SLES102B – DECEMBER 2003 – REVISED MARCH 2015
5 Pin Configuration and Functions
DB Package
28-Lead SSOP
Top View
MONO
CHSL
DEM
LRCK
DATA
BCK
SCK
DGND
VDD
MUTE
FMT0
FMT1
ZERO
RST
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC2L
AGND3L
IOUTL–
IOUTL+
AGND2
VCC1
VCOML
VCOMR
IREF
AGND1
IOUTR–
IOUTR+
AGND3R
VCC2R
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND1
19
—
Analog ground (internal bias)
AGND2
24
—
Analog ground (internal bias)
AGND3L
27
—
Analog ground (L-channel DACFF)
AGND3R
16
—
Analog ground (R-channel DACFF)
BCK
6
Input
Bit clock input (1)
CHSL
2
Input
L-, R-channel select (1)
DATA
5
Input
Serial audio data input (1)
DEM
3
Input
De-emphasis enable (1)
DGND
8
—
FMT0
11
Input
Audio data format select (1)
FMT1
12
Input
Audio data format select (1)
IOUTL+
25
Output
L-channel analog current output +
IOUTL–
26
Output
L-channel analog current output –
IOUTR+
17
Output
R-channel analog current output +
IOUTR–
18
Output
R-channel analog current output –
IREF
20
—
Output current reference bias pin
LRCK
4
Input
Left and right clock (fS) input (1)
MONO
1
Input
Monaural mode enable (1)
MUTE
10
Input
Mute control (1)
RST
14
Input
Reset (1)
SCK
7
Input
System clock input (1)
VCC1
23
—
Analog power supply, 5 V
VCC2L
28
—
Analog power supply (L-channel DACFF), 5 V
VCC2R
15
—
Analog power supply (R-cahnnel DACFF), 5 V
VCOML
22
—
L-channel internal bias decoupling pin
VCOMR
21
—
R-channel internal bias decoupling pin
VDD
9
—
Digital power supply, 3.3 V
ZERO
13
Output
(1)
Digital ground
Zero flag
Schmitt-trigger input, 5-V tolerant
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SLES102B – DECEMBER 2003 – REVISED MARCH 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
(1)
MIN
MAX
VCC1, VCC2L, VCC2R
–0.3
6.5
VDD
–0.3
4
UNIT
V
Supply voltage differences: VCC1, VCC2L, VCC2R
±0.1
V
Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND
±0.1
V
Digital input
voltage
LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE,
RST
–0.3
6.5
ZERO
–0.3
(VDD + 0.3 V) < 4
–0.3
(VCC + 0.3 V) < 6.5
V
±10
mA
125
°C
150
°C
260
°C
150
°C
Analog input voltage
Input current (any pins except supplies)
Ambient temperature under bias
–40
Junction temperature
Package temperature (IR reflow, peak)
Storage temperature, Tstg
(1)
–55
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VDD Digital supply voltage
MIN
NOM
MAX
3.0
3.3
3.6
UNIT
V
4.7525
5
5.25
V
85
°C
VCC1
VCC2L
Analog supply voltage
VCC2R
Operating temperature
–25
6.4 Thermal Information
PCM1798
THERMAL METRIC (1)
DB (SSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
70.4
RθJC(top)
Junction-to-case (top) thermal resistance
29.2
RθJB
Junction-to-board thermal resistance
31.5
ψJT
Junction-to-top characterization parameter
3.1
ψJB
Junction-to-board characterization parameter
31.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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SLES102B – DECEMBER 2003 – REVISED MARCH 2015
6.5 Electrical Characteristics
All specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit
data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
24
UNIT
Bits
DATA FORMAT
Standard, I2S, left-justified
Audio data interface format
Audio data bit length
16-, 24-bit selectable
Audio data format
fS
MSB first, 2s complement
Sampling frequency
10
System clock frequency
200
kHz
128, 192, 256, 384, 512, 768 fS
DIGITAL INPUT/OUTPUT
Logic family
VIH
VIL
IIH
IIL
VOH
VOL
TTL compatible
2
Input logic level
Input logic current
Output logic level
0.8
VIN = VDD
10
VIN = 0 V
–10
IOH = –2 mA
2.4
IOL = 2 mA
0.4
VDC
µA
VDC
DYNAMIC PERFORMANCE (1) (2)
fS = 44.1 kHz
THD+N at VOUT = 0 dB
0.0005%
fS = 96 kHz
fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
Dynamic range
0.0015%
120
EIAJ, A-weighted, fS = 96 kHz
Signal-to-noise ratio
Level linearity error
123
123
EIAJ, A-weighted, fS = 192 kHz
123
116
dB
119
fS = 96 kHz
118
fS = 192 kHz
117
VOUT = –120 dB
dB
123
120
EIAJ, A-weighted, fS = 96 kHz
fS = 44.1 kHz
Channel separation
123
123
EIAJ, A-weighted, fS = 192 kHz
EIAJ, A-weighted, fS = 44.1 kHz
0.001%
0.00%
±1
dB
dB
DYNAMIC PERFORMANCE (MONO MODE) (1) (2) (3)
fS = 44.1 kHz
THD+N at VOUT = 0 dB
Dynamic range
Signal-to-noise ratio
(1)
(2)
(3)
0.0005%
fS = 96 kHz
0.001%
fS = 192 kHz
0.0015%
EIAJ, A-weighted, fS = 44.1 kHz
126
EIAJ, A-weighted, fS = 96 kHz
126
EIAJ, A-weighted, fS = 192 kHz
126
EIAJ, A-weighted, fS = 44.1 kHz
126
EIAJ, A-weighted, fS = 96 kHz
126
EIAJ, A-weighted, fS = 192 kHz
126
dB
dB
Filter conditions:
THD+N: 20-Hz HPF, 20-kHz AES17 LPF
Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted
Channel separation: 20-Hz HPF, 20-kHz AES17 LPF
Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in
the averaging mode.
Dynamic performance and dc accuracy are specified at the output of the post amplifier as shown in Figure 32.
Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 33.
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Electrical Characteristics (continued)
All specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit
data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain error
–7
±2
7
% of
FSR
Gain mismatch, channel-tochannel
–3
±0.5
3
% of
FSR
–2
±0.5
2
% of
FSR
ANALOG OUTPUT
Bipolar zero error
At BPZ
Output current
Full scale (0 dB)
Center current
At BPZ
4
mAp-p
–3.5
mA
DIGITAL FILTER PERFORMANCE
De-emphasis error
±0.1
dB
FILTER CHARACTERISTICS–1: SHARP ROLLOFF
±0.0002 dB
Pass band
0.454 fS
–3 dB
0.49 fS
Stop band
0.546 fS
Pass-band ripple
Stop-band attenuation
±0.0002
Stop band = 0.546 fS
–98
Delay time
dB
dB
38/fS
s
FILTER CHARACTERISTICS–2: SLOW ROLLOFF
Pass band
±0.001 dB
0.21 fS
–3 dB
0.448 fS
Stop band
0.79 fS
Pass-band ripple
Stop-band attenuation
±0.001
Stop band = 0.732 fS
–80
Delay time
dB
dB
38/fS
s
POWER SUPPLY REQUIREMENTS
VDD
VCC1
VCC2L
Voltage range
36
3.3
3.6
4.7525
5
5.25
7
9
VDC
VCC2R
fS = 44.1 kHz
IDD
Supply current (4)
ICC
Power dissipation (4)
fS = 96 kHz
13
fS = 192 kHz
25
fS = 44.1 kHz
18
fS = 96 kHz
19
fS = 192 kHz
20
fS = 44.1 kHz
115
fS = 96 kHz
140
fS = 192 kHz
180
mA
23
mA
150
mW
TEMPERATURE RANGE
Operation temperature
(4)
6
–25
85
°C
Input is BPZ data.
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6.6 Timing Requirements
MIN
MAX
UNIT
SYSTEM CLOCK INPUT TIMING
t(SCY)
System clock pulse cycle time
13
ns
t(SCKH)
System clock pulse duration, HIGH
0.4t(SCY)
ns
t(SCKL)
System clock pulse duration, LOW
0.4t(SCY)
ns
20
ns
EXTERNAL RESET TIMING
t(RST)
Reset pulse duration, Low
TIMING OF AUDIO INTERFACE
t(BCY)
BCK pulse cycle time
70
ns
t(BCL)
BCK pulse duration, LOW
30
ns
t(BCH)
BCK pulse duration, HIGH
30
ns
t(BL)
BCK rising edge to LRCK edge
10
ns
t(LB)
LRCK edge to BCK rising edge
10
ns
t(DS)
DATA setup time
10
ns
t(DH)
DATA hold time
10
ns
LRCK clock data
50% ± 2 bit clocks
AUDIO INTERFACE TIMING FOR EXTERNAL DIGITAL FILTER
t(BCY)
BCK pulse cycle time
20
ns
t(BCL)
BCK pulse duration, LOW
7
ns
t(BCH)
BCK pulse duration, HIGH
7
ns
t(BL)
BCK rising edge to WDCK falling edge
5
ns
t(LB)
WDCK falling edge to BCK rising edge
5
ns
t(DS)
DATA setup time
5
ns
t(DH)
DATA hold time
5
ns
t(SCKH)
H
2V
System Clock (SCK)
0.8 V
L
t(SCKL)
t(SCY)
Figure 1. System Clock Input Timing
VDD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
Figure 2. Power-On Reset Timing
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RST (Pin 14)
1.4 V
t(RST)
Reset
Reset Removal
Internal Reset
1024 System Clocks
System Clock
Figure 3. External Reset Timing
1.4 V
LRCK
t(BCH)
t(BCL)
t(LB)
1.4 V
BCK
t(BCY)
t(BL)
1.4 V
DATA
t(DS)
t(DH)
Figure 4. Timing of Audio Interface
1/fS
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 16-Bit
DATA
14 15 16
1
2
MSB
15 16
1
2
15 16
LSB
Audio Data Word = 24-Bit
DATA
22 23 24
1
2
23 24
MSB
1
2
23 24
LSB
(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW
Figure 5. Auto Data Input Format (1 of 3)
8
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1/fS
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 24-Bit
DATA
1
2
23 24
MSB
1
2
23 24
1
2
LSB
(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
Figure 6. Auto Data Input Format (2 of 3)
1/fS
LRCK
L-Channel
R-Channel
BCK
Audio Data Word = 24-Bit
DATA
1
23 24
2
MSB
1
2
23 24
1
2
LSB
(3) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
Figure 7. Auto Data Input Format (3 of 3)
WDCK
1.4 V
t(BCH)
t(BCL)
t(LB)
1.4 V
BCK
t(BCY)
t(BL)
1.4 V
DATA
t(DS)
t(DH)
Figure 8. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application
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6.7 Typical Characteristics for Digital Filter
0
5
0.0005
−20
0.0004
4
−40
3
0.0003
Amplitude – dB
2
0.0002
Amplitude − dB
−60
−80
−100
1
0.0001
0
−1
−0.0001
−2
−0.0002
−120
−3
−0.0003
−140
−4
−0.0004
−160
0
1
2
3
4
−5
−0.0005
0.0
0.1
0.2
0.3
0.4
0.5
Frequency [× fS]
Frequency [× fS]
Pass-Band Ripple, Sharp Rolloff
Frequency Response, Sharp Rolloff
Figure 10. Amplitude vs Frequency
Figure 9. Amplitude vs Frequency
0
0
−2
−20
−4
−40
Amplitude – dB
Amplitude – dB
−6
−60
−80
−100
−8
−10
−12
−14
−120
−16
−140
−18
−160
0
1
2
3
−20
0.0
4
0.1
0.2
Frequency [× fS]
Frequency Response, Slow Rolloff
0.5
0.6
Figure 11. Amplitude vs Frequency
Figure 12. Amplitude vs Frequency
0
0
fS = 44.1 kHz
fS = 44.1 kHz
−1
−2
De-Emphasis Level – dB
−2
De-Emphasis Level – dB
0.4
Transition Characteristics, Slow Rolloff
−1
−3
−4
−5
−6
−7
−8
−3
−4
−5
−6
−7
−8
−9
−9
−10
−10
0
10
0.3
Frequency [× fS]
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
f – Frequency – kHz
f – Frequency – kHz
Figure 13. De-emphasis Level vs Frequency
Figure 14. De-emphasis Error vs Frequency
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6.7.1 Analog Dynamic Performance
126
124
fS = 96 kHz
Dynamic Range – dB
THD+N – Total Harmonic Distortion + Noise – %
0.01
0.001
fS = 192 kHz
fS = 48 kHz
4.75
5.00
5.25
fS = 192 kHz
120
118
fS = 96 kHz
0.0001
4.50
fS = 48 kHz
122
116
4.50
5.50
4.75
VCC – Supply Voltage – V
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit
is Figure 32.
Figure 15. Total Harmonic Distortion + Noise
vs Supply Voltage
Figure 16. Dynamic Range vs Supply Voltage
122
fS = 48 kHz
fS = 96 kHz
120
Channel Separation – dB
SNR – Signal-to-Noise Ratio – dB
fS = 96 kHz
fS = 192 kHz
120
118
118
fS = 48 kHz
fS = 192 kHz
116
114
4.75
5.00
5.25
112
4.50
5.50
4.75
VCC – Supply Voltage – V
5.00
5.25
5.50
VCC – Supply Voltage – V
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit
is Figure 32.
Figure 17. Signal-to-Noise Ratio vs Supply Voltage
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit
is Figure 32.
Figure 18. Channel Separation vs Supply Voltage
126
0.01
124
Dynamic Range – dB
THD+N – Total Harmonic Distortion + Noise – %
5.50
122
124
0.001
5.25
NOTE: PCM mode, TA = 25°C, VDD = 3.3 V, measurement circuit
is Figure 32.
126
116
4.50
5.00
VCC – Supply Voltage – V
fS = 96 kHz
fS = 192 kHz
fS = 96 kHz
fS = 48 kHz
122
fS = 192 kHz
120
fS = 48 kHz
118
0.0001
−50
−25
0
25
50
75
116
−50
100
TA – Free-Air Temperature – °C
−25
0
25
50
75
100
TA – Free-Air Temperature – °C
NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V, measurement circuit
is Figure 32.
Figure 19. Total Harmonic Distortion + Noise
vs Free-air Temperature
NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V, measurement circuit
is Figure 32.
Figure 20. Dynamic Range vs Free-air Temperature
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Analog Dynamic Performance (continued)
122
fS = 96 kHz
120
124
fS = 96 kHz
122
Channel Separation – dB
SNR – Signal-to-Noise Ratio – dB
126
fS = 48 kHz
fS = 192 kHz
120
fS = 192 kHz
118
fS = 48 kHz
116
114
118
116
−50
−25
0
25
50
75
112
−50
100
−25
0
25
50
75
100
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V, measurement circuit
is Figure 32.
Figure 21. Signal-to-noise Ratio vs Free-air Temperature
Figure 22. Channel Separation vs Free-air Temperature
0
0
−20
−20
−40
−40
Amplitude – dB
Amplitude – dB
NOTE: PCM mode, VDD = 3.3 V, VCC = 5 V, measurement circuit
is Figure 32.
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
2
4
6
8
10
12
14
16
18
0
20
10
f – Frequency – kHz
20
30
40
50
60
70
80
90 100
f – Frequency – kHz
NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C,
VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 32.
NOTE: fS = 96 kHz, 32768 point 8 average, TA = 25°C,
VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 32.
Figure 23. Amplitude vs Frequency
Figure 24. Amplitude vs Frequency
THD+N – Total Harmonic Distortion + Noise – %
10
1
0.1
0.01
0.001
0.0001
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Level – dBFS
NOTE: fS = 48 kHz, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 32.
Figure 25. Total Harmonic Distortion + Noise vs Input Level
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7 Detailed Description
7.1 Overview
The PCM1798 is a 24-bit, 192-kHz, differential current output DAC that comes in a 28-pin SSOP package. The
PCM1798 is a hardware controlled and utilizes the advanced segment DAC architecture from TI in order to
perform with a Stereo Dynamic Range of 123 dB (126 dB Mono) and SNR of 123 dB (126 dB Mono) with a THD
of 0.0005%. The PCM1798 will use the SCK input as its system clock and automatically detect the sampling rate
of the Digital Audio input and has a high tolerance for clock jitter. The internal filter can be bypassed to allow for
an external digital filter to be used.
7.2 Functional Block Diagram
IOUT L–
LRCK
BCK
DATA
Audio
Data Input
I/F
Current
Segment
DAC
VOUT L
IOUTL+
MUTE
FMT1
FMT0
MONO
CHSL
Function
Control
I/F
´8
Oversampling
Digital
Filter
and
Function
Control
VCOM L
Advanced
Segment
DAC
Modulator
Bias
and
Vref
I/V and Filter
IREF
VCOM R
IOUT R–
Current
Segment
DAC
DEM
RST
VOUT R
IOUT R+
I/V and Filter
VCC2R
VCC2L
VCC1
AGND3R
AGND3L
AGND2
DGND
AGND1
Power Supply
VDD
Zero
Detect
SCK
ZERO
System
Clock
Manager
7.3 Feature Description
7.3.1 System Clock and Reset Functions
7.3.1.1 System Clock Input
The PCM1798 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1798 has a system clock detection
circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples
of system clock frequencies for common audio sampling rates.
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Feature Description (continued)
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. One of the Texas Instruments PLL1700 family of multiclock
generators is an excellent choice for providing the PCM1798 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
192 fS
256 fS
384 fS
512 fS
768 fS
32 kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1 kHz
5.6488
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.144
9.216
12.288
18.432
24.576
36.864
96 kHz
12.288
18.432
24.576
36.864
49.152
73.728
73.728
(1)
See (1)
192 kHz
(1)
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
128 fS
24.576
36.864
49.152
See
This system clock rate is not supported for the given sampling frequency.
7.3.2 Power-On and External Reset Functions
The PCM1798 includes a power-on reset function. Figure 2 shows the operation of this function. With VDD > 2 V,
the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time
VDD > 2 V.
The PCM1798 also includes an external reset capability using the RST input (pin 14). This allows an external
controller or master reset circuit to force the PCM1798 to initialize to its default reset state.
Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns.
The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system
clock periods. The external reset is especially useful in applications where there is a delay between the
PCM1798 power up and system clock activation.
7.3.3 Audio Data Interface
7.3.3.1 Audio Serial Interface
The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is
the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of
the audio interface. Serial data is clocked into the PCM1798 on the rising edge of BCK. LRCK is the serial audio
left/right word clock.
The PCM1798 requires the synchronization of LRCK and the system clock, but does not need a specific phase
relation between LRCK and the system clock.
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is
initialized within 1/fS and the analog outputs are forced to the bipolar zero level until resynchronization between
LRCK and the system clock is completed.
7.3.3.2 PCM Audio Data Formats and Timing
The PCM1798 supports industry-standard audio data formats, including standard right-justified, I2S, and leftjustified. The data formats are shown in Figure 5, Figure 6, and Figure 7. Data formats are selected using FMT0
(pin 11) and FMT1 (pin 12) as shown in Table 2. All formats require binary twos-complement, MSB-first audio
data. Figure 4 shows a detailed timing diagram for the serial audio interface.
7.3.4 Function Descriptions
7.3.4.1 Audio Data Format
Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1798 also supports monaural mode
and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1798 can select the DF rolloff
characteristics.
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Table 2. Audio Data Format Select
MONO
CHSL
FMT1
FMT0
FORMAT
STEREO/MONO
DF ROLLOFF
0
0
0
0
I2S
Stereo
Sharp
0
0
0
1
Left-justified format
Stereo
Sharp
0
0
1
0
Standard, 16-bit
Stereo
Sharp
0
0
1
1
Standard, 24-bit
Stereo
Sharp
0
1
0
0
I2S
Stereo
Slow
0
1
0
1
Left-justified format
Stereo
Slow
0
1
1
0
Standard, 16-bit
Stereo
Slow
0
1
1
1
Digital filter bypass
Mono
—
2
1
0
0
0
I S
Mono, L-channel
Sharp
1
0
0
1
Left-justified format
Mono, L-channel
Sharp
1
0
1
0
Standard, 16-bit
Mono, L-channel
Sharp
1
0
1
1
Standard, 24-bit
Mono, L-channel
Sharp
1
1
0
0
I2S
Mono, R-channel
Sharp
1
1
0
1
Left-justified format
Mono, R-channel
Sharp
1
1
1
0
Standard, 16-bit
Mono, R-channel
Sharp
1
1
1
1
Standard, 24-bit
Mono, R-channel
Sharp
7.3.4.2 Soft Mute
The PCM1798 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are
transitioned to the bipolar zero level in –0.5-dB steps with a transition speed of 1/fS per step. This system
provides pop-free muting of the DAC output.
7.3.4.3 De-Emphasis
The PCM1798 has a de-emphasis filter for the sampling frequency of 44.1 kHz. The de-emphasis filter is
controlled using DEM (pin 3).
7.3.4.4 Zero Detection
When the PCM1798 detects that the audio input data in the L-channel and the R-channel is continuously zero for
1024 LRCKs in the PCM mode, or that the audio input data is continuously zero for 1024 WDCKs in the external
filter mode, the PCM1798 sets ZERO (pin 13) to HIGH.
7.4 Device Functional Modes
The PCM1798 is a hardware controlled device. The pins CHSL, DEM, FMT0, FMT1, MONO, and MUTE control
the functionality of this part. See the Pin Functions table or the Feature Description section for more detail.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PCM1798 device is a hardware-controlled, differential current output DAC that can accept multiple formats
of 16- or 24-bit PCM audio data. Because the PCM1798 is a current output part, in most cases a current to
voltage stage is required before the signal is passed to the amplifier stage. A microcontroller or DSP can use
GPIO to manipulate the control pins CHSL, DEM, FMT0, FMT1, MONO, and MUTE. The PCM1798 requires a 5V analog supply, as well as a 3.3-V digital supply.
8.2 Typical Applications
8.2.1 Application for External Digital Filter Interface
VDD
1
MONO
2
VCC2L
28
CHSL
AGND3L
27
3
DEM
IOUTL–
26
WDCK
4
LRCK
IOUTL+
25
DATA
5
DATA
AGND2
24
BCK
6
BCK
SCK
7
SCK
External
Filter
Device
VCC 1 23
VCOM L 22
PCM1798
8
DGND
9
VDD
VCOM R 21
IREF
20
10 MUTE
AGND1
19
11 FMT0
IOUTR–
18
12 FMT1
IOUTR+
17
13 ZERO
AGND3R
16
VCC2R
15
14 RST
Analog
Output Stage
Figure 26. Connection Diagram for External Digital Filter (Internal DF Bypass Mode) Application
8.2.1.1 Design Requirements
•
•
•
Control: Host controller with SPI communication
Audio Output: I/V output circuitry
Audio Input: Digital Audio Filter with I2S or DSD output
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Application for Interfacing With an External Digital Filter
For some applications, it may be desirable to use a programmable digital signal processor as an external digital
filter to perform the interpolation function. The following pin settings enable the external digital filter application
mode.
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Typical Applications (continued)
•
•
•
•
MONO (pin 1) = LOW
CHSL (pin 2) = HIGH
FMT0 (pin 11) = HIGH
FMT1 (pin 12) = HIGH
The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of
Figure 26. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, fS.
Pin assignment when using the external digital filter interface:
• LRCK (pin 4): WDCK as word clock input
• DATA (pin 5): Monaural audio data input
• BCK (pin 6): Bit clock input
8.2.1.2.2 Audio Format
The PCM1798 in the external digital filter interface mode supports the 24-bit right-justified audio format as shown
in Figure 27.
1/4 fS or 1/8 fS
WDCK
BCK
Audio Data Word = 24-Bit
DATA
23 24
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
Figure 27. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application
8.2.1.2.3 Analog Output
Table 3 and Figure 28 show the relationship between the digital input code and analog output.
Table 3. Analog Output Current and Voltage (1)
(1)
800000 (–FS)
000000 (BPZ)
7FFFFF (+FS)
IOUTN [mA]
–1.5
–3.5
–5.5
IOUTP [mA]
–5.5
–3.5
–1.5
VOUTN [V]
–1.23
–2.87
–4.51
VOUTP [V]
–4.51
–2.87
–1.23
VOUT [V]
–2.98
0
2.98
VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the measurement circuit of Figure 23.
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0
−1
IO – Output Current – mA
IOUTN
−2
−3
−4
−5
IOUTP
−6
800000(–FS)
000000(BPZ)
7FFFFF(+FS)
Input Code – Hex
Figure 28. Relationship Between Digital Input and Analog Output
8.2.1.3 Application Curves
0
5
0.0005
−2
0.0004
4
−4
3
0.0003
−6
Amplitude – dB
Amplitude − dB
2
0.0002
1
0.0001
0
−1
−0.0001
−12
−2
−0.0002
−14
−3
−0.0003
−16
−4
−0.0004
−18
−5
−0.0005
0.0
0.1
0.2
0.3
0.4
−20
0.0
0.5
0.1
0.2
0.3
0.4
0.5
0.6
Frequency [× fS]
Frequency [× fS]
Transition Characteristics, Slow Rolloff
Pass-Band Ripple, Sharp Rolloff
Figure 29. Amplitude vs Frequency
18
−8
−10
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Figure 30. Amplitude vs Frequency
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8.2.2 PCM1798 Typical Application
Cf
5V
Rf
VCC2L
1
28
2
CHSL
AGND3L
27
3
DEM
IOUTL–
26
4
LRCK
IOUTL+
25
5
DATA
AGND2
24
6
BCK
VCC1
23
7
SCK
VCOML
22
VCOMR
21
IREF
20
10 MUTE
AGND1
19
11 FMT0
IOUTR–
18
12 FMT1
IOUTR+
17
13 ZERO
AGND3R
16
VCC2R
15
+
0.1 µF
MONO
10 µF
–
PCM
Audio
Data
Source
+
Cf
Rf
5V
–
+
PCM1798
0.1 µF
Controller
8
DGND
9
VDD
Differential
to
Single
Converter
With
Low-Pass
Filter
VOUT
R-Channel
Cf
Rf
47 µF
10 kΩ
–
+
Cf
0.1 µF
Rf
5V
+
14 RST
VOUT
L-Channel
+
+
10 µF
Differential
to
Single
Converter
With
Low-Pass
Filter
10 µF
–
+
3.3 V
+
10 µF
Figure 31. Typical Application Circuit
8.2.2.1 Design Requirements
The design of the application circuit is very important in order to actually realize the high S/N ratio of which the
PCM1798 is capable. This is because noise and distortion that are generated in an application circuit are not
negligible.
In the third-order LPF circuit of Figure 32, the output level is 2.1 V RMS, and 123 dB S/N is achieved.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 I/V Section
The current of the PCM1798 on each of the output pins (IOUTL+, IOUTL–, IOUTR+, IOUTR–) is 4 mA p-p at 0 dB (full
scale). The voltage output level of the I/V converter (Vi) is given by following equation:
VI = 4 mAp–p × Rf (Rf : feedback resistance of I/V converter)
(1)
TI recommends an NE5534 operational amplifier for the I/V circuit to obtain the specified performance. Dynamic
performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the
audio dynamic performance of the I/V section.
8.2.2.2.2 Differential Section
The PCM1798 voltage outputs are followed by differential amplifier stages, which sum the differential signals for
each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a lowpass filter function.
The operational amplifier recommended for the differential circuit is the low-noise type.
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C1
2700 pF
R1
820 Ω
VCC
VCC
C11
0.1 µF
C17
22 pF
7
IOUT–
5
2
8
–
3
R5
200 Ω
6
+
U1
NE5534
4
R3
220 Ω
C3
8200 pF
R7
180 Ω
C15
0.1 µF
C19
22 pF
7
2
C5
27000 pF
3
5
–
6
+
4
C12
0.1 µF
VEE
R4
220 Ω
R6
200 Ω
8
R8
180 Ω
R9
100 Ω
U3
NE5534
C16
0.1 µF
C4
8200 pF
VEE
C2
2700 pF
R2
820 Ω
VCC
C13
0.1 µF
C18
22 pF
7
IOUT+
2
3
5
–
8
6
+
4
U2
NE5534
VCC = 15 V
VEE = –15 V
fc = 50 kHz
C14
0.1 µF
VEE
Figure 32. Measurement Circuit
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IOUTL– (Pin 26)
IOUT–
Circuit
IOUTL+ (Pin 25)
OUT+
IOUT+
3
1
2
IOUTR– (Pin 18)
IOUT–
Circuit
IOUTR+ (Pin 17)
IOUT+
OUT–
Balanced Out
Figure 33. Measurement Circuit for Monaural Mode
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9 Power Supply Recommendations
The PCM1798 requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the analog
circuitry powered by pins VCC1, VCC2L, and VCC2R pins. The 3.3-V supply is for the digital circuitry powered
by the Vdd pin. The decoupling capacitors for the power supplies should be placed close to the device terminals.
10 Layout
10.1 Layout Guidelines
Designers should try to use the same ground between AGND and DGND to avoid any potential voltage
difference between them. Ensure that the return currents for digital signals will avoid the AGND pin or the input
signals to the I/V stage. Avoid running high frequency clock and control signals near AGND, or any of the Vout
pins where possible. The pin layout of the PCM1798 partitions into two parts - analog section and digital section.
Providing the system is partitioned in such a way that digital signals are routed away from the analog sections,
then no digital return currents (for example, clocks) should be generated in the analog circuitry.
• Decoupling capacitors should be placed as close to the VCC1, VCC2L, VCCR2, VCOML, VCOMR, and VDD pins as
possible.
• Further guidelines can be found in Figure 34.
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10.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around PCM1785 and connect to lower main PCB
ground plane by multiple vias
5V
Hardware select
pins or Host
control
These resistors help prevent
overshoot and reduce
coupling, Start at 10? for
MCLK and 27? for others.
1
MONO
VCC2L
28
2
CHSL
AGND3L
27
3
DEM
IoutL-
26
4
LRCK
IoutL+
25
5
DATA
AGND2
24
6
BCK
VCC1
23
+
0.1 µF
Left I/V
Output
circuit
5V
47 µF
7
SCK
VcomL
22
10 µF
+
+
10 µF
PCM1798
3.3V
8
DGND
VcomR
21
9
VDD
Iref
20
10
MUTE
AGND1
19
11
FMT0
IoutR-
18
12
FMT1
IoutR+
17
13
ZERO
AGND3R
16
14
RST
VCC2R
15
+
10 KO
10 µF
0.1 µF
Hardware select
or host control
Right I/V
Output
circuit
5V
+
0.1 µF
Top Layer Ground Pour
Top Layer Signal Traces
10 µF
Via to bottom Ground Plane
Pad to top layer ground pour
Figure 34. PCM1785 Layout Example
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11 Device and Documentation Support
11.1 Trademarks
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1798DB
ACTIVE
SSOP
DB
28
47
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
PCM1798
PCM1798DBG4
ACTIVE
SSOP
DB
28
47
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
PCM1798
PCM1798DBR
ACTIVE
SSOP
DB
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
PCM1798
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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