PCM1800

® PCM 49% 180 FPO 0 PCM1800 Single-Ended Analog Input 20-Bit Stereo ANALOG-TO-DIGITAL CONVERTER FEATURES q DUAL 20-BIT MONOLITHIC ∆Σ ADC q SINGLE-ENDED VOLTAGE INPUT q 64X OVERSAMPLING DECIMATION FILTER: Passband Ripple: ±0.05dB Stopband Attenuation: –65dB q HIGH PERFORMANCE: THD+N: -88dB (typ) SNR: 95dB (typ) Dynamic Range: 95dB (typ) Internal High Pass Filter q PCM AUDIO INTERFACE: Master/Slave Modes 4 Data Formats q SAMPLING RATE: 32kHz, 44.1kHz, 48kHz q SYSTEM CLOCK: 256fS, 384fS, or 512fS q SINGLE +5V POWER SUPPLY q SMALL 24-PIN SSOP PACKAGE DESCRIPTION PCM1800 is a low cost, single chip stereo analog-todigital converter with single-ended analog voltage inputs. The PCM1800 uses a delta-sigma modulator with 64X oversampling, including a digital decimation filter and serial interface which supports both Master and Slave Modes and four data formats. PCM1800 is suitable for a wide variety of cost-sensitive consumer applications where high performance is required. PCM1800 is fabricated on a highly advanced CMOS process. Analog Input (L) Analog Front-End Analog Input (R) Delta-Sigma Modulator Digital Output Decimation Digital Filter Serial Interface and Format Control Mode/Format Control System Clock International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1997 Burr-Brown Corporation PDS-1387 1 PCM1800 Printed in U.S.A. August, 1997 SPECIFICATIONS All specifications at +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and 20-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1800E PARAMETER RESOLUTION DIGITAL INPUT/OUTPUT Input Logic Level: VIH(1) VIL(1) Input Logic Current: IIN(2) IIN(3) Output Logic Level: VOH(4) VOL(4) Sampling Frequency System Clock Frequency CONDITIONS MIN 20 TYP MAX UNITS Bits 2.0 0.8 ±1 +100 IOH = –1.6mA IOL = +3.2mA 256fS 384fS 512fS 4.5 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 ±1.0 ±2.0 ±20 ±2.0 ±20 –88 –92 95 95 93 94 94 92 2.828 2.1 30 170 0.454fS 0.583fS –65 17.4/fS –3dB +VCC +VDD = +VDD = +5V = +VDD = +5V +4.5 +4.5 +5.0 +5.0 18 90 0.019fS +5.5 +5.5 25 125 +85 +125 100 ±0.05 0.5 48 12.2880 18.4320 24.5760 ±2.5 ±5.0 V V µA µA V V kHz MHz MHz MHz % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C dB dB dB dB dB dB dB dB Vp-p V kΩ kHz Hz Hz dB dB sec mHz VDC VDC mA mW °C °C °C/W DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(5) THD+N at FS (–0.5dB) THD+N at –60dB Dynamic Range Signal-To-Noise Ratio Channel Separation DYNAMIC PERFORMANCE(5) Dynamic Range Signal-To-Noise Ratio Channel Separation ANALOG OUTPUT Input Range Center Voltage Input Impedance Anti-Aliasing Filter Frequency Response DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time (Latency) High Pass Frequency Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Power Dissipation TEMPERATURE RANGE Operation Storage Thermal Resistance, θJA Current(6) High Pass Filter Bypass High Pass Filter Bypass –80 EIAJ, A-weighted EIAJ, A-weighted 90 90 88 16-Bit, A-weighted 16-Bit, A-weighted 16-Bit FS (VIN = 0dB) CEXT = 470pF, –3dB +VCC +VCC –25 –55 NOTES: (1) Pins 6, 7, 8, 9, 10, 11, 16 and 12, 13, 14: RSTB, BYPAS, FMT0, FMT1, MODE0, MODE1, SYSCLK, and FSYNC, LRCK, BCK under Slave Mode. (2) Pins 16 and 12, 13, 14: SYSCLK and FSYNC, LRCK, BCK under Slave Mode (Schmitt Trigger input). (3) Pins 6, 7, 8, 9, 10, 11: RSTB, BYPAS, FMT0, FMT1, MODE0, MODE1 (Schmitt Trigger input, with 100kΩ typical pull-down resistor). (4) Pins 15 and 12, 13, 14: DOUT and FSYNC, LRCK, BCK under Master Mode. (5) fIN = 1kHz, using Audio Precisions System II, rms Mode with 20kHz LPF and 400Hz HPF in calculation. (6) No load on DOUT (pin 15) in the Slave Mode. ® PCM1800 2 PIN CONFIGURATION Top View SSOP PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME VINL VREF1 REFCOM VREF2 VINR RSTB BYPAS FMT0 FMT1 MODE0 MODE1 FSYNC LRCK BCK DOUT SYSCLK DGND VDD CINNR CINPR CINNL CINPL VCC AGND I/O IN — — — IN IN IN IN IN IN IN IN/OUT IN/OUT IN/OUT OUT IN — — — — — — — — DESCRIPTION Analog Input, Lch Reference 1 Decoupling Capacitor Reference Decoupling Common Reference 2 Decoupling Capacitor Input Reference, Rch Reset Input, Active LOW(1) High Pass Filter Bypass Control(1) Audio Data Format 0(1) Audio Data Format 1(1) Master/Slave Mode Selection 0(1) Master/Slave Mode Selection 1(1) Frame Synchronization Sampling Clock Input/Output (fS) Bit Clock Input/Output Audio Data Output System Clock Input, 256fS, 384fS, or 512fS Digital Ground Digital Power Supply Anti-alias Filter Capacitor (–), Rch Anti-alias Filter Capacitor (+), Rch Anti-alias Filter Capacitor (–), Lch Anti-alias Filter Capacitor (+), Lch Analog Power Supply Analog Ground 1 2 3 4 5 6 7 8 9 10 11 12 VINL VREF1 REFCOM VREF2 VINR RSTB PCM1800 BYPAS FMT0 FMT1 MODE0 MODE1 FSYNC AGND 24 VCC 23 CINPL 22 CINNL 21 CINPR 20 CINNR 19 VDD 18 DGND 17 SYSCLK 16 DOUT 15 BCK 14 LRCK 13 PACKAGE INFORMATION PRODUCT PCM1800E PACKAGE 24-Pin SSOP PACKAGE DRAWING NUMBER(1) 338 NOTE: (1) With 100kΩ typical pull-down resistor. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS Supply Voltage: +VDD, +VCC ...................................................................................... +6.5V Supply Voltage Differences ............................................................... ±0.1V GND Voltage Differences .................................................................. ±0.1V Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V) Analog Input Voltage ................................................ –0.3V to (VCC + 0.3V) Input Current (any pin except supplies) .......................................... ±10mA Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C (reflow, 10s) ..................................................... +235°C The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1800 BLOCK DIAGRAM ADC CINPL CINNL VINL Single-End/ Differential Converter (+) (–) 5th-Order Delta-Sigma Modulator x1/64 Decimation and High Pass Filter (–) (+) 5th-Order Delta-Sigma Modulator BCK VREF1 REFCOM VREF2 LRCK Serial Data Interface FSYNC Reference VINR CINNR CINPR Single-End/ Differential Converter DOUT MODE0 Mode/Format Control Interface MODE1 FMT0 FMT1 BYPAS Clock/Timing Control Reset/Power Control SYSCLK RSTB Power Supply VCC AGND DGND VDD ANALOG FRONT-END (Single-Channel) CEXT 470pF CINPL 22 21 CINNL 1.0µF + 1 VINL 30kΩ 1kΩ (+) Delta-Sigma Modulator 1kΩ 4 + 4.7µF 3 4.7µF + 2 REFCOM VREF VREF2 (–) VREF1 ® PCM1800 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and 20-bit input data, SYSCLK = 384fS, unless otherwise noted. THD+N vs TEMPERATURE 0.010 4.0 98 SNR, DYNAMIC RANGE vs TEMPERATURE 4.0 Dynamic Range THD+N at –0.5dB (%) THD+N at –60dB (%) –60dB 0.006 –0.5dB 0.004 1.0 2.0 SNR 94 2.0 92 1.0 0.002 –25 0 0 25 50 75 85 100 Temperature (°C) 90 –25 0 25 50 75 85 100 Temperature (°C) 0 THD+N vs POWER SUPPLY 0.010 4.0 98 SNR and DYNAMIC RANGE vs POWER SUPPLY 98 Dynamic Range THD+N at –0.5dB (%) THD+N at –60dB (%) –60dB 0.006 –0.5dB 0.004 1.0 2.0 94 SNR 94 92 92 0.002 4.5 4.75 5.0 5.25 5.5 Supply Voltage (V) 0 90 4.5 4.75 5.0 5.25 5.50 90 Supply Voltage (V) THD+N vs SYSTEM CLOCK and SAMPLING FREQUENCY 0.010 4.0 THD+N vs OUTPUT DATA RESOLUTION 0.010 4.0 THD+N at –0.5dB (%) THD+N at –0.5dB (%) THD+N at –60dB (%) 32kHz –60dB 44.1kHz 48kHz 32kHz –60dB 0.006 2.0 0.006 2.0 0.004 –0.5dB 44.1kHz 0.002 256fS 48kHz 384fS System Clock 512fS 1.0 0.004 –0.5dB 1.0 0 0.002 16-Bit Resolution 20-Bit 0 5 PCM1800 THD+N at –60dB (%) ® 0.008 3.0 0.008 3.0 Dynamic Range (dB) 0.008 3.0 96 SNR (dB) 96 Dynamic Range (dB) 0.008 3.0 96 SNR (dB) 3.0 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and 20-bit input data, SYSCLK = 384fS, unless otherwise noted. –60dBFS FFT 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 0 2 4 6 8 10 12 14 16 18 20 Frequency (kHz) 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 THD+N vs AMPLITUDE Amplitude (dB) THD+N (dB) –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 Amplitude (dBr) THD+N vs FREQUENCY –80 –81 –82 –83 –84 –85 –86 –87 –88 –89 –90 –91 –92 –93 –94 –95 –96 –97 –98 –99 –100 THD+N (dB) 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) ® PCM1800 6 TYPICAL PERFORMANCE CURVES DIGITAL FILTER OVERALL CHARACTERISTICS 0 0 STOPBAND ATTENUATION CHARACTERISTICS –50 Amplitude (dB) Amplitude (dB) –20 –40 –100 –60 –150 –80 –200 0 8 16 24 32 Normalized Frequency (x fS Hz) –100 0 0.25 0.50 0.75 1.00 Normalized Frequency (x fS Hz) PASSBAND RIPPLE CHARACTERISTICS 0.2 0.0 0 –1 –2 Amplitude (dB) –3 –4 –5 –6 –7 –8 –9 –1.0 0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (x fS Hz) TRANSIENT BAND CHARACTERISTICS Amplitude (dB) –0.2 –0.4 –0.6 –0.8 –10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Normalized Frequency (x fS Hz) HIGH PASS FILTER HIGH PASS FILTER RESPONSE 0 –10 –20 0.0 0.2 HIGH PASS FILTER RESPONSE Amplitude (dB) –40 –50 –60 –70 –80 –90 –100 0 0.05 0.1 0.15 0.2 0.25 0.3 -0.35 0.4 Normalized Frequency (x fS /1000Hz) Amplitude (dB) –30 –0.2 –0.4 –0.6 –0.8 –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (x fS /1000Hz) ® 7 PCM1800 TYPICAL PERFORMANCE CURVES ANTI-ALIASING FILTER ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE (CEXT = 470pF, 1000pF) 470pF –10 Amplitude (dB) Amplitude (dB) 0 0.2 0.0 –0.2 –0.4 ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE (CEXT = 470pF, 1000pF) 470pF –20 –30 1000pF –40 1000pF –0.6 –0.8 –0.1 –50 0 10 100 1k 10k 100k 1M 10M Frequency (Hz) 0 10 100 1k 10k 100k Frequency (Hz) ® PCM1800 8 THEORY OF OPERATION PCM1800 consists of a bandgap reference, two channels of a single-to-differential converter, a fully differential 5thorder delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The Block Diagram illustrates the total architecture of PCM1800, the Analog Front-End diagram illustrates the architecture of the single-to-differential converter, and the anti-aliasing filter is illustrated in the Block Diagram. Figure 1 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. An internal high precision reference with two external capacitors provides all reference voltages which are required by the converter, and defines the full-scale voltage range of both channels. The internal single-to-differential voltage converter saves the design, space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64X oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a 1-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64fS, 1-bit stream from the modulator is converted to 1fS, 20-bit digital data by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. The DC components are removed by a high pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial interface which provides flexible serial formats and Master/Slave Modes. SYSTEM CLOCK The system clock for PCM1800 must be either 256fS, 384fS, or 512fS, where fS is the audio sampling frequency. The system clock must be supplied on SYSCLK (pin 16). PCM1800 also has a system clock detection circuit which automatically senses if the system clock is operating at 256fS, 384fS, or 512fS. When 384fS and 512fS system clock is in Slave Mode, the system clock is divided into 256fS automatically. The 256fS clock is used to operate the digital filter and the modulator. Table I lists the relationship of typical sampling frequencies and system clock frequencies. Figure 2 illustrates the system clock timing. SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz) 256fS 32 44.1 48 8.1920 11.2896 12.2880 384fS 12.2880 16.9340 18.4320 512fS 16.3840 22.5792 24.5760 TABLE I. System Clock Frequencies. Analog In X(z) + – – 1st SW-CAP Integrator + 2nd SW-CAP Integrator 3rd SW-CAP Integrator + – 4th SW-CAP Integrator 5th SW-CAP Integrator Qn(z) + + H(z) Comparator + + + + + + Digital Out Y(z) 1-Bit DAC Y(z) = STF(z) • X(z) + NTF(z) • Qn(z) Signal Transfer Function Noise Transfer Function STF(z) = H(z)/[1 + H(z)] NTF(z) = 1/[1 + H(z)] FIGURE 1. Simplified Diagram of the PCM1800 5th-Order Delta-Sigma Modulator. tCLKIH tCLKIL 2.0V SYSCLK 0.8V System Clock Pulse Width High System Clock Pulse Width Low tCLKIH tCLKIL 12ns (min) 12ns (min) FIGURE 2. System Clock Timing. ® 9 PCM1800 RESET PCM1800 has both an internal power-on reset circuit and an external forced reset (RSTB, pin 6). The internal power-on reset initializes (resets) when the supply voltage (VCC/VDD) exceeds 4.0V (typ). To initiate the reset sequence externally, apply a logic level LOW to the RSTB pin. The RSTB pin is terminated by an internal pull-down resistor. If the RSTB pin is unconnected, the ADC will remain in the reset state. During VCC/VDD < 4.0V (typ), RSTB = LOW and 1024 system clock periods after V CC/ VDD 4.0V and RSTB = HIGH. The PCM1800 stays in the reset state and the digital output is forced to zero. The digital output is valid after reset state release and 18436f S periods. During reset, the logic circuits and the digital filter stop operating. Figures 3 and 4 illustrate the internal power-on reset and external reset timing. communications between the PCM1800 and the digital audio processor or external circuit. While in the case of the Slave Mode, the PCM1800 receives the timing of data transfer from an external controller. MODE1 0 0 1 1 MODE0 0 1 0 1 INTERFACE MODE Slave Mode (256/384/512fS) Master Mode (512fS) Master Mode (384fS) Master Mode (256fS) TABLE II. Interface Modes. Master Mode In the Master Mode, BCK, LRCK, and FSYNC are output pins and are controlled by timing generated in clock circuitry of the PCM1800. FSYNC is used to designate the valid data from the PCM1800. The rising edge of FSYNC indicates the starting point of the converted audio data and the following edge of this signal indicates the ending points of data. The frequency of this signal is fixed at 2xLRCK and duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64X LRCK. Slave Mode In Slave Mode, BCK, LRCK, and FSYNC are input pins. FSYNC is used to enable BCK signal, and the PCM1800 can shift out the converted data when FSYNC is HIGH. SERIAL AUDIO DATA INTERFACE The PCM1800 interfaces the audio system through BCK (pin 14), LRCK (pin 13), FSYNC (pin 12) and DOUT (pin 15). INTERFACE MODE The PCM1800 supports Master and Slave Modes as interface modes and are selected by MODE1 (pin 11) and MODE0 (pin 10), as shown in Table II. In case of the Master Mode, the PCM1800 provides the timing of serial audio data 4.4V VCC/VDD 4.0V 3.6V Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 3. Internal Power-On Reset Timing. tRST = 40ns minimum RSTB-pin tRST Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 4. RSTB-Pin Reset Timing. ® PCM1800 10 FORMAT 0: FMT[1:0] = “00” 20-Bit, MSB-First, Left-Justified FSYNC LRCK BCK DOUT 1 2 MSB 3 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB 1 L–ch R–ch FORMAT 1: FMT[1:0] = “01” 20-Bit, MSB-First, I2S FSYNC LRCK BCK DOUT 1 2 MSB 3 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB L-ch R-ch FORMAT 2: FMT[1:0] = “10” 16-Bit, MSB-First, Right-Justified FSYNC LRCK BCK DIN 16 1 2 MSB 3 14 15 16 LSB 1 2 MSB 3 14 15 16 LSB L–ch R–ch FORMAT 3: FMT[1:0] = “11” 20-Bit, MSB-First, Right-Justified FSYNC LRCK BCK DOUT 20 1 2 MSB 3 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB L–ch R–ch FIGURE 5. Audio Data Format (Slave Mode: FSYNC, LRCK, and BCK are inputs). DATA FORMAT PCM1800 supports four audio data formats in both Master and Slave Modes, and are selected by FMT1 (pin 9) and FMT0 (pin 8), as shown in Table III. FORMAT # 0 1 2 3 FMT1 0 0 1 1 FMT0 0 1 0 1 DATA FORMAT 20-bit, Left-justified 20-bit, I2S 16-bit, Right-justified 20-bit, Right-justified NOTE: FMT1 and FMT0 must be stable at RSTB changing from LOW to HIGH. TABLE III. Data Format. ® 11 PCM1800 FORMAT 0: FMT[1:0] = “00” 20-Bit, MSB-First, Left-Justified FSYNC LRCK BCK DOUT 1 2 MSB 3 L–ch R–ch 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB 1 FORMAT 1: FMT[1:0] = “01” 20-Bit, MSB-First, I2S FSYNC LRCK BCK DOUT 1 2 MSB 3 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB L-ch R-ch FORMAT 2: FMT[1:0] = “10” 16-Bit, MSB-First, Right-Justified FSYNC LRCK BCK DIN 16 1 2 MSB 3 14 15 16 LSB 1 2 MSB 3 14 15 16 LSB L–ch R–ch FORMAT 3: FMT[1:0] = “11” 20-Bit, MSB-First, Right-Justified FSYNC LRCK BCK DOUT 20 1 2 MSB 3 L–ch R–ch 18 19 20 LSB 1 2 MSB 3 18 19 20 LSB FIGURE 6. Audio Data Format (Master Mode: FSYNC, LRCK, and BCK are outputs). ® PCM1800 12 FSYNC tFSSU tLRCP LRCK tLRHD tLRSU tFSHD 1.4V 1.4V tBCKH BCK tBCKP DOUT tBCKL 1.4V tCKDO tLRDO 0.5VDD DESCRIPTION BCK Period BCK Pulsewidth HIGH BCK Pulsewidth LOW LRCK Set Up Time to BCK Rising Edge LRCK Hold Time to BCK Rising Edge LRCK Period FSYNC Set Up Time to BCK Rising Edge FSYNC Hold Time to BCK Rising Edge Delay Time BCK Falling Edge to DOUT Valid Delay Time LRCK Edge to DOUT Valid Rising Time of All Signals Falling Time of All Signals SYMBOL tBCKP tBCKH tBCKL tLRSU tLRHD tLRCP tFSSU tFSHD tCKDO tLRDO tRISE tFALL MIN 300 120 120 80 40 20 40 40 –20 –20 TYP MAX UNITS ns ns ns ns ns µs ns ns ns ns ns ns 40 40 20 20 NOTE: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from 10% to 90% of I/O signals’ swing. Load capacitance of DOUT signal is 20pF. FIGURE 7. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK are inputs). tFSYP FSYNC tCKFS LRCIN tCKLR 0.5VDD tBCKP DOUT tCKDO tLRDO 0.5VDD tLRCP 0.5VDD tBCKH BCKIN tBCKL 0.5VDD DESCRIPTION BCK Period BCK Pulsewidth HIGH BCK Pulsewidth LOW Delay Time BCK Falling Edge to LRCK Valid LRCK Period Delay Time BCK Falling Edge to FSYNC Valid FSYNC Period Delay Time BCK Falling Edge to DOUT Valid Delay Time LRCK Edge to DOUT Valid Rising Time of All Signals Falling Time of All SIgnals SYMBOL tBCKP tBCKH tBCKL tCKLR tLRCP tCKFS tFSYP tCKDO tLRDO tRISE tFALL MIN 300 150 150 –20 20 –20 10 –20 –20 TYP 1/64fS MAX 600 300 300 40 40 40 40 40 40 20 20 UNITS ns ns ns ns µs ns µs ns ns ns ns 1/fS 1/2 fS NOTE: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from 10% to 90% of I/O signals’ swing. Load capacitance of DOUT signal is 20pF. FIGURE 8. Audio Data Interface Timing (Master Mode: FSYNC, LRCK, and BCK are outputs). ® 13 PCM1800 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In Slave Mode, PCM1800 operates with LRCK synchronized to the system clock (SYSCLK). PCM1800 does not require a specific phase relationship between LRCK and SYSCLK, but does require the synchronization of LRCK and SYSCLK. If the relationship between LRCK and SYSCLK changes more than 6 bit clocks (BCK) during one sample period due to LRCK or SYSCLK jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code until resynchronization between LRCK and SYSCLK is completed. In case of changes less than 5 bit clocks (BCK), resynchronization does not occur and above digital output control and discontinuity does not occur. ADC DATA OUTPUT AT RESET Figures 9 and 10 illustrate the ADC digital output when the reset operation is done and synchronization is lost. During undefined data, it may generate some noise in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity of data on the digital output, and may generate some noise in the audio signal. BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD PINS The digital and analog power supply lines to the PCM1800 should be bypassed to the corresponding ground pins with both 0.1µF ceramic and 10µF tantalum capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. Although PCM1800 has two power lines to maximize the potential of dynamic performance, using one common power supply is recommended to avoid unexpected power supply problems, such as latch-up or power supply sequence. AGND, DGND PINS To maximize the dynamic performance of the PCM1800, the analog and digital grounds are not internally connected. These points should have very low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the parts to reduce potential noise problems. Power ON RSTB ON Internal Reset Reset Reset Release Ready/Operation 18436/fS DOUT(1) Zero Data Normal Data(2) NOTES: (1) In the Master Mode, FSYNC, BCK, and LRCK are outputs similar to DOUT. (2) The HPF transient response (exponentially attenuationed signal from ±0.2% DC of FSR with 200ms time constant) appears initially. FIGURE 9. ADC Output for Power-On Reset and RSTB Control. Synchronization Lost State of Synchronization Resynchronization Synchronous Asynchronous Synchronous 1/fS 32/fS DOUT(1 ) Normal Undefined Data Zero Data Normal(2 ) NOTES: (1) Applies only for Slave Mode—the loss of synchronization never occurs in Master Mode. (2) The HPF transient response (exponentially attenuationed signal from ±0.2% DC of FSR with 200ms time constant) appears initially. FIGURE 10. ADC Output When Synchronization is Lost and for Resynchronization. ® PCM1800 14 Line In Left-Channel 1.0µF(2) + 4.7µF + 1 2 3 4.7µF + Ref Analog Front-End Analog Front-End 24 23 22 21 20 Reset Delta-Sigma 19 18 Decimation Filter Clock 17 16 15 Digital Audio Interface 14 13 SYSCLK DOUT BCK LRCK Audio Data Processor + 0.1µF/10µF(1) Line In Right-Channel 1.0µF(2) 4 5 CEXT 470pF CEXT 470pF + +5V 0.1µF/10µF(1) GND + /RESET BYPASS 6 7 8 9 10 11 12 Pin Program or Control FORMAT0 FORMAT1 MODE0 MODE1 SYNC NOTES: (1) Bypass capacitor = 0.1µF ceramic and 10µF tantalum, depending on layout and power supply. (2) A 1.0µF capacitor gives 5.3Hz (τ = 1µF x 30kΩ) cut-off frequency of input HPF in normal operation and requires power-on settling time with 60ms time constant in power on initialization period. FIGURE 11. Typical Circuit Connection. VIN PINS A 1.0µF tantalum capacitor is recommended as an ACcoupling capacitor which establishes a 5.3Hz cut-off frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a series resistor to the VIN pins. VREF INPUTS A 4.7µF tantalum capacitor is recommended between VREF1, VREF2, and REFCOM to ensure low source impedance for the ADC’s references. These capacitors should be located as close as possible to the VREF1 or VREF2 pin to reduce dynamic errors on the ADC’s references. The REFCOM pin should also be connected directly to AGND under the parts. CINP and CINN INPUTS A 470pF to 1000pF film capacitor is recommended between CINPL and CINNL, CINPR and CINNR to create an antialiasing filter, which will have an 170kHz to 80kHz cut-off frequency. These capacitors should be located as close as possible to the CINP and CINN pins to avoid introducing unexpected noise or dynamic errors into the delta-sigma modulator. DOUT, BCK, LRCK, FSYNC PINS The DOUT, BCK, LRCK and FSYNC pins in Master Mode have a large load drive capability, but locating the buffer near the PCM1800 and minimizing the load capacitance is recommended in order to minimize the digital analog crosstalk and to maximize dynamic performance potential. SYSTEM CLOCK The quality of the system clock can influence dynamic performance in the PCM1800. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCK), and a word clock (LRCK) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit is exceeded. RSTB Control If the capacitance between VREF1 and VREF2 exceeds 4.7µF, an external reset control delay time circuit must be used. ® 15 PCM1800