PCM1801

® PCM 49% 1801 FPO PCM1801 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit, Stereo, Audio ANALOG-TO-DIGITAL CONVERTER FEATURES q DUAL 16-BIT MONOLITHIC ∆Σ ADC q SINGLE-ENDED VOLTAGE INPUT q 64X OVERSAMPLING DECIMATION FILTER: Passband Ripple: ±0.05dB Stopband Attenuation: –65dB q ANALOG PERFORMANCE: THD+N: –88dB (typ) SNR: 93dB (typ) Dynamic Range: 93dB (typ) Internal High-Pass Filter q PCM AUDIO INTERFACE: Left Justified, I2S q SAMPLING RATE: 4kHz to 48kHz q SYSTEM CLOCK: 256fS, 384fS, or 512fS q SINGLE +5V POWER SUPPLY q SMALL SO-14 PACKAGE PCM1801 (+) (–) DESCRIPTION PCM1801 is a low cost, single chip stereo analog-todigital converter with single-ended analog voltage inputs. The PCM1801 uses a delta-sigma modulator with 64x oversampling, a digital decimation filter, and a serial interface which supports Slave mode operation and two data formats. The PCM1801 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. VINL Single-Endedto-Differential Converter 5th-Order ∆Σ Modulator x1/64 Decimation and High-Pass Filter Serial Data Interface BCK VREF1 Reference VREF2 LRCK VINR Single-Endedto-Differential Converter (–) (+) 5th-Order ∆Σ Modulator DOUT Format Control FMT BYPAS Clock/Timing Control SCKI Power Supply VCC AGND DGND VDD International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1554B Printed in U.S.A. May, 2000 SPECIFICATIONS All specifications at +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and 16-bit data, SYSCLK = 384fS, unless otherwise noted. PCM1801U PARAMETER RESOLUTION DIGITAL INPUT/OUTPUT Input Logic Level: VIH(1) VIL(1) Input Logic Current: IIN(2) IIN(3) Output Logic Level: VOH(4) VOL(4) Sampling Frequency System Clock Frequency CONDITIONS MIN TYP 16 MAX UNITS Bits 2.0 0.8 ±1 +100 IOH = –1.6mA IOL = +3.2mA 256fS 384fS 512fS 4.5 4 1.024 1.536 2.024 44.1 11.2896 16.9344 22.5792 ±1.0 ±2.0 ±20 ±2.0 ±20 –88 –90 93 93 91 2.828 2.1 30 170 0.454fS 0.583fS –65 17.4/fS –3dB +VCC +VDD = +VDD = +5V = +VDD = +5V +4.5 +4.5 +5.0 +5.0 18 90 0.019fS +5.5 +5.5 25 125 +85 +125 100 ±0.05 0.5 48 12.2880 18.4320 24.5760 ±2.5 ±5.0 V V µA µA V V kHz MHz MHz MHz % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C dB dB dB dB dB Vp-p V kΩ kHz Hz Hz dB dB sec mHz VDC VDC mA mW °C °C °C/W DC ACCURACY Gain Mismatch Channel-to-Channel Gain Error Gain Drift Bipolar Zero Error Bipolar Zero Drift DYNAMIC PERFORMANCE(5) THD+N at FS (–0.5dB) THD+N at –60dB Dynamic Range Signal-To-Noise Ratio Channel Separation ANALOG INPUT Input Range Center Voltage Input Impedance Anti-Aliasing Filter Frequency Response DIGITAL FILTER PERFORMANCE Passband Stopband Passband Ripple Stopband Attenuation Delay Time (Latency) High Pass Frequency Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Current(6) Power Dissipation TEMPERATURE RANGE Operation Storage Thermal Resistance, θJA High-Pass Filter Bypass High-Pass Filter Bypass –80 EIAJ, A-weighted EIAJ, A-weighted 90 90 88 FS (VIN = 0dB) –3dB +VCC +VCC –25 –55 NOTES: (1) Pins 5, 6, 7, 9, and 10 (SCKI, BCK, LRCK, BYPAS, FMT). (2) Pins 5, 6, 7 (SCKI, BCK, LRCK) Schmitt-Trigger input. (3) Pins 9, 10 (BYPAS, FMT) Schmitt-Trigger input with 100kΩ typical pull-down resistor). (4) Pin 8 (DOUT). (5) fIN = 1kHz, using Audio Precisions System II, r ms Mode with 20kHz LPF and 400Hz HPF enabled. (6) No load on DOUT (pin 8). ® PCM1801 2 PIN CONFIGURATION Top View SOIC PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME VINL VINR DGND VDD SCKI BCK LRCK DOUT BYPAS FMT VCC AGND VREF2 VREF1 I/O IN IN — — IN IN IN OUT IN IN — — — — DESCRIPTION Analog Input, Lch. Analog Input, Rch. Digital Ground Digital Power Supply System Clock Input; 256fS, 384fS, or 512fS. Bit Clock Input Sampling Clock Input Audio Data Output HPF Bypass Control(1) L: HPF Enabled H: HPF Disabled Audio Data Format(1) L: MSB-First, Left-Justified H: MSB-First, I2S Analog Power Supply Analog Ground Reference 2 Decoupling Capacitor Reference 1 Decoupling Capacitor 1 2 3 4 5 6 7 VINL VINR DGND PCM1801U VDD SCKI BCK LRCK VREF1 14 VREF2 13 AGND 12 VCC 11 FMT 10 BYPAS DOUT 9 8 NOTE: (1) With 100kΩ typical pull-down resistor. ABSOLUTE MAXIMUM RATINGS Supply Voltage: +VDD, +VCC .............................................................. +6.5V Supply Voltage Differences ............................................................... ±0.1V GND Voltage Differences .................................................................. ±0.1V Digital Input Voltage ................................................. –0.3V to (VDD + 0.3V) Analog Input Voltage ................................................ –0.3V to (VCC + 0.3V) Input Current (any pin except supplies) .......................................... ±10mA Power Dissipation .......................................................................... 300mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C (reflow, 10s) ..................................................... +235°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER 235 SPECIFIED TEMPERATURE RANGE –25°C to +85°C PACKAGE MARKING PCM1801U ORDERING NUMBER(1) PCM1801U PCM1801U/2K TRANSPORT MEDIA Rails Tape and Reel PRODUCT PCM1801U PACKAGE SO-14 " " " " " NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1801U/2K” will get a single 2000-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1801 BLOCK DIAGRAM PCM1801 (+) (–) VINL Single-Endedto-Differential Converter 5th-Order ∆Σ Modulator x1/64 Decimation and High-Pass Filter Serial Data Interface BCK VREF1 Reference VREF2 LRCK VINR Single-Endedto-Differential Converter (–) (+) 5th-Order ∆Σ Modulator DOUT Format Control FMT BYPAS Clock/Timing Control SCKI Power Supply VCC AGND DGND VDD ANALOG FRONT-END (Single-Channel) 1.0µF + 1 VINL 30kΩ 1kΩ (+) Delta-Sigma Modulator 1kΩ 13 4.7µF + VREF 4.7µF + 14 VREF1 VREF2 (–) ® PCM1801 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. ANALOG DYNAMIC PERFORMANCE TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE 0.006 3.0 96 SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE vs TEMPERATURE 96 THD+N at –0.5dB (%) THD+N at –60dB (%) –60dB 0.004 –0.5dB 0.003 2.4 2.6 94 Dynamic Range 94 93 SNR 93 0.002 –25 2.2 0 25 50 75 85 100 Temperature (°C) 92 –25 0 25 50 75 85 100 Temperature (°C) 92 TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE 0.006 3.0 SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE vs SUPPLY VOLTAGE 96 96 THD+N at –0.5dB (%) THD+N at –60dB (%) Dynamic Range 94 94 0.004 –0.5dB 2.6 0.003 2.4 93 SNR 93 0.002 4.5 4.75 5.0 5.25 5.5 Supply Voltage (V) 2.2 92 4.5 4.75 5.0 5.25 5.5 Supply Voltage (V) 92 TOTAL HARMONIC DISTORTION + NOISE vs SAMPLING RATE 0.006 3.0 96 SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE vs SAMPLING RATE 96 THD+N at –0.5dB (%) THD+N at –60dB (%) –60dB 0.004 –0.5dB 0.003 2.4 2.6 Dynamic Range 94 94 93 SNR 93 0.002 32 44.1 Sampling Rate (kHz) 48 2.2 92 32 44.1 Sampling Rate (kHz) 48 92 ® 5 PCM1801 Dynamic Range (dB) 0.005 2.8 95 SNR (dB) 95 Dynamic Range (dB) 0.005 –60dB 2.8 95 SNR (dB) 95 Dynamic Range (dB) 0.005 2.8 95 SNR (dB) 95 TYPICAL PERFORMANCE CURVES ANALOG DYNAMIC PERFORMANCE (cont.) SUPPLY CURRENT vs TEMPERATURE 20 ICC + IDD 16 (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE 20 ICC + IDD 16 Supply Current (mA) 12 Supply Current (mA) ICC IDD 12 ICC 8 IDD 4 8 4 0 –25 0 25 50 75 100 Temperature (°C) 0 4.25 4.5 4.75 5.0 5.5 5.75 Supply Voltage (V) SUPPLY CURRENT vs SAMPLING RATE 20 ICC + IDD 16 Supply Current (mA) 12 ICC 8 IDD 4 0 0 10 20 30 40 50 Sampling Rate (kHz) ® PCM1801 6 TYPICAL PERFORMANCE CURVES OUTPUT SPECTRUM Full-Scale FFT 0 –20 –40 (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. –60dBFS FFT 0 –20 –40 Amplitude (dB) –60 –80 –100 –120 –140 0 5 10 Frequency (kHz) 15 20 Amplitude (dB) –60 –80 –100 –120 –140 0 5 10 Frequency (kHz) 15 20 TOTAL HARMONIC DISTORTION + NOISE vs AMPLITUDE 100 0.1 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 THD+N (%) 1 0.1 THD+N (%) 0.01 0.001 0.01 0.001 –100 0.0001 –80 –60 –40 –20 0 20 100 1k Frequency (Hz) 10k 20k Amplitude (dBV) ® 7 PCM1801 TYPICAL PERFORMANCE CURVES DIGITAL FILTER OVERALL CHARACTERISTICS 0 (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. STOPBAND ATTENUATION CHARACTERISTICS 0 –50 –20 Amplitude (dB) Amplitude (dB) 0 8 16 24 32 –40 –100 –60 –150 –80 –200 Normalized Frequency (x fS Hz) –100 0 0.25 0.50 0.75 1.00 Normalized Frequency (x fS Hz) PASSBAND RIPPLE CHARACTERISTICS 0.2 0.0 0 –1 –2 TRANSITION BAND CHARACTERISTICS Amplitude (dB) Amplitude (dB) 0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (x fS Hz) –0.2 –0.4 –0.6 –0.8 –1.0 –3 –4 –5 –6 –7 –8 –9 –10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Normalized Frequency (x fS Hz) HIGH PASS FILTER RESPONSE 0 –10 –20 0.0 0.2 HIGH PASS FILTER RESPONSE Amplitude (dB) –40 –50 –60 –70 –80 –90 –100 0 0.05 0.1 0.15 0.2 0.25 0.3 -0.35 0.4 Normalized Frequency (x fS /1000Hz) Amplitude (dB) –30 –0.2 –0.4 –0.6 –0.8 –1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Normalized Frequency (x fS /1000Hz) ® PCM1801 8 TYPICAL PERFORMANCE CURVES ANTI-ALIASING ANTI-ALIASING FILTER STOPBAND FREQUENCY RESPONSE 0 –5 –10 (Cont.) At TA = +25°C, +VDD = +VCC = +5V, fS = 44.1kHz, and SYSCLK = 384fS, unless otherwise noted. ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE 0 –0.1 –0.2 Amplitude (dB) Amplitude (dB) –15 –20 –25 –30 –35 –40 –45 –50 100 1k 100k 10k Frequency (Hz) 1M 10M –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1 1 10 1K 100 Frequency (Hz) 10K 100K ® 9 PCM1801 THEORY OF OPERATION PCM1801 consists of a bandgap reference, two channels of a single-to-differential converter, a fully differential 5thorder delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The Block Diagram illustrates the total architecture of PCM1801, the Analog Front-End diagram illustrates the architecture of the single-to-differential converter, and the anti-aliasing filter is illustrated in the Block Diagram. Figure 1 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. An internal high precision reference with two external capacitors provides all reference voltages which are required by the converter, and defines the full-scale voltage range of both channels. The internal single-ended to differential voltage converter saves the design, space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64x oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a 1-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64fS, 1-bit stream from the modulator is converted to 1fS, 16-bit digital data by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The DC components are removed by a digital highpass filter, and the filtered output is converted to timemultiplexed serial signals through a serial interface which provides flexible serial formats. SYSTEM CLOCK The system clock for PCM1801 must be either 256fS, 384fS, or 512fS, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 5). PCM1801 also has a system clock detection circuit which automatically senses if the system clock is operating at 256fS, 384fS, or 512fS. When 384fS and 512fS system clock are used, the PCM1801 automatically divides these clocks down to 256fS internally. This 256fS clock is used to operate the digital filter and the modulator. Table I lists the relationship of typical sampling frequencies and system clock frequencies. Figure 2 illustrates the system clock timing. SYSTEM CLOCK FREQUENCY (MHz) 256fS 8.1920 11.2896 12.2880 384fS 12.2880 16.9340 18.4320 512fS 16.3840 22.5792 24.5760 SAMPLING RATE FREQUENCY (kHz) 32 44.1 48 TABLE I. System Clock Frequencies. Analog In X(z) + – – 1st SW-CAP Integrator + 2nd SW-CAP Integrator 3rd SW-CAP Integrator + – 4th SW-CAP Integrator 5th SW-CAP Integrator Qn(z) + + H(z) Comparator + + + + + + Digital Out Y(z) 1-Bit DAC Y(z) = STF(z) • X(z) + NTF(z) • Qn(z) Signal Transfer Function Noise Transfer Function STF(z) = H(z) / [1 + H(z)] NTF(z) = 1/ [1 + H(z)] FIGURE 1. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator. tCLKIH tCLKIL 2.0V SCKI 0.8V System Clock Pulse Width High System Clock Pulse Width Low tCLKIH tCLKIL 12ns (min) 12ns (min) FIGURE 2. System Clock Timing. ® PCM1801 10 RESET PCM1801 has an internal power-on reset circuit, which initializes (resets) when the supply voltage (VCC /VDD) exceeds 4.0V (typ). The PCM1801 stays in the reset state and the digital output is forced to zero. The digital output is valid after reset state release and 18436fS periods. During reset, the logic circuits and the digital filter stop operating. Figure 3 illustrates the internal power-on reset timing. SERIAL AUDIO DATA INTERFACE The PCM1801 interfaces the audio system through BCK (pin 6), LRCK (pin 7), and DOUT (pin 8). DATA FORMAT PCM1801 supports two audio data formats in Slave Mode, and are selected by the FMT control input (pin 10) as shown in Table II. FMT 0 (L) 1 (H) DATA FORMAT 16-Bit, Left-Justified 16-Bit, I2S TABLE II. Data Format. 4.4V VCC/VDD 4.0V 3.6V Reset Reset Removal Internal Reset 1024 System Clock Periods System Clock FIGURE 3. Internal Power-On Reset Timing. FMT = L 16-Bit, MSB-First, Left-Justified LRCK BCK DOUT 1 2 MSB 3 L–ch R–ch 14 15 16 LSB 1 2 MSB 3 14 15 16 LSB 1 FMT = H 16-Bit, MSB-First, I2S LRCK BCK DOUT 1 2 MSB 3 L-ch R-ch 14 15 16 LSB 1 2 MSB 3 14 15 16 LSB FIGURE 4. Audio Data Format (Slave Mode: LRCK, and BCK are inputs). ® 11 PCM1801 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM PCM1801 operates with LRCK synchronized to the system clock (SCKI). PCM1801 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than 6 bit clocks (BCK) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and the digital output is forced to BPZ until resynchronization between LRCK and SCKI is completed. In case of changes less than 5 bit clocks (BCK), resynchronization does not occur and above digital output control and discontinuity does not occur. ADC DATA OUTPUT AT RESET Figures 6 and 7 illustrate the ADC digital output for the reset operation and loss of synchronization state. During undefined data, it may generate some noise in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal makes a discontinuity of data on the digital output, and may generate some noise in the audio signal. recommended to avoid unexpected power supply problems, such as latch-up due to power supply sequencing. AGND, DGND PINS To maximize the dynamic performance of the PCM1801, the analog and digital grounds are not internally connected. These points should have very low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the PCM1801 package to reduce potential noise problems. VIN PINS A 1.0µF tantalum capacitor is recommended as an ACcoupling capacitor which establishes a 5.3Hz cut-off frequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding a series resistor to the VIN pins. VREF INPUTS A 4.7µF tantalum capacitor is recommended between ground and the VREF1 and VREF2 references to ensure low source impedance. These capacitors should be located as close as possible to the VREF1 or VREF2 pins to reduce dynamic errors on the ADC’s references. SYSTEM CLOCK The quality of the system clock can influence dynamic performance in the PCM1801. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit is exceeded. BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD PINS The digital and analog power supply lines to the PCM1801 should be bypassed to the corresponding ground pins with both 0.1µF and 10µF capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. Although PCM1801 has two power lines to maximize the potential of dynamic performance, using one common power supply is tLRCP LRCK tLRHD tLRSU 1.4V tBCKP DOUT tCKDO tLRDO 0.5VDD 1.4V tBCKH BCK tBCKL DESCRIPTION BCK Period BCK Pulse Width HIGH BCK Pulse Width LOW LRCK Set Up Time to BCK Rising Edge LRCK Hold Time to BCK Rising Edge LRCK Period Delay Time BCK Falling Edge to DOUT Valid Delay Time LRCK Edge to DOUT Valid Rising Time of All Signals Falling Time of All Signals SYMBOL tBCKP tBCKH tBCKL tLRSU tLRHD tLRCP tCKDO tLRDO tRISE tFALL MIN 300 120 120 80 40 20 –20 –20 TYP MAX UNITS ns ns ns ns ns µs ns ns ns ns 40 40 20 20 NOTE: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from 10% to 90% of I/O signals’ swing. Load capacitance of DOUT signal is 20pF. FIGURE 5. Audio Data Interface Timing (LRCK and BCK are inputs). ® PCM1801 12 Power ON Internal Reset Reset Reset Release Ready/Operation 18436/fS DOUT Zero Data Normal Data(1) NOTE: (1) The HPF transient response (exponentially attenuationed signal from ±0.2% DC of FSR with 200ms time constant) appears initially. FIGURE 6. ADC Output for Power-On Reset and RSTB Control. Synchronization Lost State of Synchronization Resynchronization Synchronous Asynchronous Synchronous 1/fS 32/fS DOUT(1 ) Normal Undefined Data Zero Data Normal(2 ) NOTES: (1) Applies only for Slave Mode—the loss of synchronization never occurs in Master Mode. (2) The HPF transient response (exponentially attenuationed signal from ±0.2% DC of FSR with 200ms time constant) appears initially. FIGURE 7. ADC Output for Loss of Synchronization. Lch IN Rch IN C1(1) C2(1) + + 1 2 3 C3(2) 4 VINL VINR DGND VDD SCKI BCK LRCK VREF1 VREF2 AGND VCC FMT BYPAS DOUT 14 13 12 + + C6(3) C5(3) 0V C4(2) 11 10 9 8 Format Bypass +5V Pin Program or Control System Clock Audio Data Processor Data Clock Latch Enable 5 6 7 Data Out NOTES: (1) C1 and C2: A 1µF capacitor gives 5.3Hz (τ = 1µF * 30kΩ) cut-off frequency for input HPF in normal operation and requires power-on setting time of 6ms at power up. (2) C3 and C4: Bypass capacitor 0.1µF ceramic and 10µF tantalum or aluminum electrolytic, depending on layout and power supply. (3) C5 and C6: 4.7µF tantalum or aluminum electrolytic capacitor. FIGURE 8. Typical Circuit Connection. ® 13 PCM1801