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PCM1803A
SLES142B – JUNE 2005 – REVISED JULY 2016
PCM1803A Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D Converter
1 Features
2 Applications
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
24-Bit Delta-Sigma Stereo A/D Converter
Single-Ended Voltage Input: 3 Vp-p
Oversampling Decimation Filter:
– Oversampling Frequency: ×64, ×128
– Pass-Band Ripple: ±0.05 dB
– Stop-Band Attenuation: –65 dB
– On-Chip High-Pass Filter: 0.84 Hz (44.1 kHz)
High-Performance:
– THD+N: –95 dB (Typically)
– SNR: 103 dB (Typically)
– Dynamic Range: 103 dB (Typically)
PCM Audio Interface:
– Master or Slave Mode Selectable
– Data Formats:
– 24-Bit Left-Justified
– 24-Bit I2S
– 20-, 24-Bit Right-Justified
Sampling Rate: 16 kHz to 96 kHz
System Clock: 256 fS, 384 fS, 512 fS, 768 fS
Dual Power Supplies: 5 V for Analog, 3.3 V for
Digital
Package: 20-Pin SSOP
AV Amplifier Receivers
MD Players
CD Recorders
Multitrack Receivers
Electric Musical Instruments
3 Description
The PCM1803A device is high-performance, lowcost, single-chip stereo analog-to-digital converter
with single-ended analog voltage input. The
PCM1803A uses a delta-sigma modulator with 64and 128-times oversampling, and includes a digital
decimation filter and high-pass filter, which removes
the DC component of the input signal. For various
applications, the PCM1803A supports master and
slave modes and four data formats in serial interface.
The PCM1803A is suitable for a wide variety of costsensitive consumer applications where good
performance and operation from a 5-V analog supply
and 3.3-V digital supply are required. The PCM1803A
is fabricated using a highly-advanced CMOS process
and is available in a small 20-pin SSOP package.
Device Information(1)
PART NUMBER
PCM1803A
PACKAGE
SSOP (20)
BODY SIZE (NOM)
7.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
Delta-Sigma
Modulator
VINL
BCK
LRCK
×1/64 , ×1/128
Decimation
Filter
With
High-Pass Filter
VREF1
Reference
VREF2
Serial
Interface
Mode/
Format
Control
Delta-Sigma
Modulator
VINR
DOUT
FMT0
FMT1
MODE0
MODE1
BYPAS
TEST
OSR
Clock and Timing Control
Power Supply
PDWN
SCKI
VCC
AGND DGND
VDD
B0004-06
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM1803A
SLES142B – JUNE 2005 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 12
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2006) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Changed RθJA value from 115 °C/W to 84.4 °C/W in Thermal Information ............................................................................ 5
•
Changed the Thermal Information table ................................................................................................................................ 5
2
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SLES142B – JUNE 2005 – REVISED JULY 2016
5 Pin Configuration and Functions
DB Package
20-Pin SSOP
Top View
VINL
1
20
MODE1
VINR
2
19
MODE0
VREF1
3
18
FMT1
VREF2
4
17
FMT0
VCC
5
16
OSR
AGND
6
15
SCKI
PDWN
7
14
BYPAS
8
13
VDD
DGND
TEST
9
12
DOUT
LRCK
10
11
BCK
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AGND
6
–
BCK
11
I/O
BYPAS
8
I
HPF bypass control. LOW: Normal mode (DC reject); HIGH: Bypass mode (through) (2)
DGND
13
–
Digital GND
DOUT
12
O
Audio data digital output
FMT0
17
I
Audio data format select input 0. See Data Format. (2)
FMT1
18
I
Audio data format select input 1. See Data Format. (2)
LRCK
10
I/O
MODE0
19
I
Mode select input 0. See Data Format. (2)
MODE1
20
I
Mode select input 1. See Data Format. (2)
OSR
16
I
Oversampling ratio select input. LOW: ×64 fS, HIGH: ×128 fS (2)
PDWN
7
I
Power-down control, active-low
SCKI
15
I
System clock input: 256 fS, 384 fS, 512 fS, or 768 fS (3)
TEST
9
I
Test, must be connected to DGND (2)
VCC
5
–
Analog power supply, 5-V
VDD
14
–
Digital power supply, 3.3-V
VINL
1
I
Analog input, L-channel
VINR
2
I
Analog input, R-channel
VREF1
3
–
Reference-voltage-1 decoupling capacitor
VREF2
4
–
Reference-voltage-2 decoupling capacitor
(1)
(2)
(3)
Analog GND
Audio data bit clock input/output (1)
Audio data latch enable input/output (1)
(2)
Schmitt-trigger input
Schmitt-trigger input with internal pulldown (50 kΩ, typically), 5-V tolerant
Schmitt-trigger input, 5-V tolerant
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VCC
–0.3
6.5
VDD
–0.3
4
LRCK, BCK, DOUT
–0.3
(VDD + 0.3) < 4
Digital input voltage, VI
PDWN, BYPAS, TEST, SCKI, OSR, FMT0, FMT1,
MODE0, MODE1
–0.3
6.5
Analog input voltage, VI
VINL, VINR, VREF1, VREF2
–0.3
(VCC + 0.3) < 6.5
V
Input current, II
Any pins except supplies
±10
mA
125
°C
150
°C
260
°C
260
°C
150
°C
Supply voltage
Ground voltage differences
AGND, DGND
–40
Junction temperature, TJ
5s
Package temperature (IR reflow, peak)
Storage temperature, Tstg
(1)
V
±0.1
Ambient temperature under bias, Tbias
Lead temperature (soldering)
UNIT
–55
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range
MIN
NOM
MAX
Analog supply voltage, VCC
4.5
5
5.5
Digital supply voltage, VDD
2.7
3.3
3.6
Analog input voltage, full-scale (–0 dB)
3
Digital input logic family
Digital input clock frequency
V
V
Vp-p
TTL
System clock
Sampling clock
8.192
49.152
MHz
32
96
kHz
20
pF
85
°C
Digital output load capacitance
Operating free-air temperature, TA
4
UNIT
–25
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6.4 Thermal Information
PCM1803A
THERMAL METRIC (1)
DB (SSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
84.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
42.4
°C/W
RθJB
Junction-to-board thermal resistance
41.4
°C/W
ψJT
Junction-to-top characterization parameter
8.3
°C/W
ψJB
Junction-to-board characterization parameter
40.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS,
oversampling ratio = ×128, 24-bit data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
24
Bits
DATA FORMAT
Left-justified, I2S, right-justified
Audio data interface format
Audio data bit length
20, 24
Audio data format
fS
Sampling frequency
System clock frequency
Bits
MSB-first, 2s complement
16
44.1
96
256 fS
4.096
11.2896
24.576
384 fS
6.144
16.9344
36.864
512 fS
8.192
22.5792
49.152
768 fS
12.288
33.8688
kHz
MHz
INPUT LOGIC
VIH
(1)
VIL
(1)
VIH
(2) (3)
VIL
(2) (3)
Input logic-level voltage
IIH
(1) (2)
VIN = VDD
IIL
(1) (2)
VIN = 0
IIH
(3)
IIL
(3)
Input logic-level current
2
VDD
0
0.8
2
5.5
0
0.8
Vdc
±10
±10
VIN = VDD
65
VIN = 0
μA
100
±10
OUTPUT LOGIC
VOH
(4)
VOL
(4)
Output logic-level voltage
IOUT = –4 mA
2.8
IOUT = 4 mA
Vdc
0.5
DC ACCURACY
Gain mismatch, channel-to-channel
±1
±3
% of FSR
Gain error
±2
±4
% of FSR
Bipolar zero error
(1)
(2)
(3)
(4)
HPF bypass
±0.4
% of FSR
Pins 10 to 11: LRCK, BCK (Schmitt-trigger input, in slave mode)
Pin 15: SCKI (Schmitt-trigger input, 5-V tolerant)
Pins 7 to 9, 16 to 20: PDWN, BYPAS, TEST, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-kΩ typical pulldown
resistor, 5-V tolerant)
Pins 10 to 12: LRCK, BCK (in master mode), DOUT
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Electrical Characteristics (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS,
oversampling ratio = ×128, 24-bit data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN = –0.5 dB, fS = 44.1 kHz
–95
–89
VIN = –0.5 dB, fS = 96 kHz (6)
–93
VIN = –60 dB, fS = 44.1 kHz
–41
UNIT
DYNAMIC PERFORMANCE (5)
THD+N
Total harmonic distortion + noise
VIN = –60 dB, fS = 96 kHz (6)
Dynamic range
SNR
Signal-to-noise ratio
Channel separation
fS = 44.1 kHz, A-weighted
–41
100
fS = 96 kHz, A-weighted (6)
fS = 44.1 kHz, A-weighted
fS = 96 kHz, A-weighted
103
dB
103
100
(6)
fS = 44.1 kHz
dB
103
dB
103
95
fS = 96 kHz (6)
98
dB
99
ANALOG INPUT
VI
Input voltage
0.6 × VCC
Vp-p
Center voltage (VREF1)
0.5 × VCC
V
Input impedance
40
kΩ
DIGITAL FILTER PERFORMANCE
Pass band
0.454 × fS
Stop band
0.583 × fS
Hz
Pass-band ripple
±0.05
Stop-band attenuation
tGD
–65
Group delay time
HPF frequency response
dB
dB
17.4 / fS
–3 dB
Hz
s
0.019 × fS
mHz
POWER SUPPLY REQUIREMENTS
VCC
VDD
Supply voltage range
ICC
4.5
5
5.5
Vdc
2.7
3.3
3.6
Vdc
7.7
10
mA
9
mA
Power down (8)
Supply current (7)
IDD
Power dissipation
5
μA
fS = 44.1 kHz
6.5
fS = 96 kHz (6)
11.7
Power down (8)
1
fS = 44.1 kHz
60
fS = 96 kHz (6)
77
mW
Power down (8)
28
μW
mA
μA
80
mW
TEMPERATURE RANGE
TA
(5)
(6)
(7)
(8)
6
Operating free-air temperature
–40
85
°C
Analog performance specifications are tested using the System Two™ audio measurement system by Audio Precision™, using 400-Hz
HPF, 20-kHz LPF in rms mode.
fS = 96 kHz, system clock = 256 fS, oversampling ratio = ×64.
Minimum load on DOUT (pin 12), BCK (pin 11), LRCK (pin 10)
Halt SCKI, BCK, LRCK
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6.6 Typical Characteristics
6.6.1 Typical Curves of Internal Filter
6.6.1.1 Decimation Filter Frequency Response
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS,
oversampling ratio = ×128, 24-bit data (unless otherwise noted)
50
50
Oversampling Ratio = y64
Oversampling Ratio = y128
0
Amplitude − dB
Amplitude − dB
0
−50
−100
−50
−100
−150
−150
−200
−200
0
8
16
24
32
40
48
56
Normalized Frequency [× fS]
0
64
8
16
24
32
Normalized Frequency [× fS]
G001
Figure 1. Overall Characteristics
G002
Figure 2. Overall Characteristics
0
0.2
−10
0.0
−20
Amplitude − dB
Amplitude − dB
−30
−40
−50
−60
−70
−80
−90
−0.2
−0.4
−0.6
−0.8
Oversampling
Ratio = y128 and y64
−100
0.00
0.25
Oversampling
Ratio = y128 and y64
0.50
0.75
Normalized Frequency [× fS]
−1.0
0.0
1.00
0.1
0.2
0.3
0.4
0.5
0.6
Normalized Frequency [× fS]
G003
Figure 3. Stop-Band Attenuation Characteristics
G004
Figure 4. Pass-Band Ripple Characteristics
6.6.1.2 Low-Cut Filter Frequency Response
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS,
oversampling ratio = ×128, 24-bit data (unless otherwise noted)
0.2
0
−10
0.0
−20
Amplitude − dB
Amplitude − dB
−30
−40
−50
−60
−70
−80
−0.2
−0.4
−0.6
−0.8
−90
−100
0.0
−1.0
0.1
0.2
0.3
Normalized Frequency [× fS/1000]
0.4
0
Figure 5. HPF Stop-Band Characteristics
1
2
3
Normalized Frequency [× fS/1000]
G005
4
G006
Figure 6. HPF Pass-Band Characteristics
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6.6.2 Typical Performance Curves
−90
110
−91
109
−92
108
Dynamic Range and SNR − dB
THD+N − Total Harmonic Distortion + Noise − dB
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS,
oversampling ratio = ×128, 24-bit data (unless otherwise noted)
−93
−94
−95
−96
−97
−98
−99
−25
0
25
50
75
Dynamic Range
104
103
SNR
102
−25
−91
109
−92
108
Dynamic Range and SNR − dB
110
−94
−95
−96
−97
−98
25
50
75
100
G008
Figure 8. Dynamic Range and Signal-to-Noise Ratio vs
Temperature
−90
−93
0
TA − Free-Air Temperature − °C
G007
Figure 7. Total Harmonic Distortion + Noise vs
Temperature
THD+N − Total Harmonic Distortion + Noise − dB
105
100
−50
100
TA − Free-Air Temperature − °C
−99
107
106
105
Dynamic Range
104
103
SNR
102
101
−100
4.25
4.50
4.75
5.00
5.25
5.50
VCC − Supply Voltage − V
100
4.25
5.75
109
−92
108
Dynamic Range and SNR − dB
−91
−94
−95
−96
−97
(1)f
S
= 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
(2)f = 96 kHz, System Clock = 256 f ,
S
S
Oversampling Ratio = ×64.
−99
5.00
5.25
5.50
5.75
G010
Figure 10. Dynamic Range and Signal-to-Noise Ratio vs
Supply Voltage
110
−93
4.75
VCC − Supply Voltage − V
−90
−98
4.50
G009
Figure 9. Total Harmonic Distortion + Noise vs Supply
Voltage
THD+N − Total Harmonic Distortion + Noise − dB
106
101
−100
−50
(1)f
S
= 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
(2)f = 96 kHz, System Clock = 256 f ,
S
S
Oversampling Ratio = ×64.
107
106
105
Dynamic Range
104
103
SNR
102
101
100
−100
0
10
20(1)
30(2)
44.1
48
96
fSAMPLE Condition − kHz
0
40
10
44.1
20(1)
48
30(2)
96
fSAMPLE Condition − kHz
G011
Figure 11. Total Harmonic Distortion + Noise vs fSAMPLE
Condition
8
107
40
G012
Figure 12. Dynamic Range and Signal-to-Noise Ratio vs
fSAMPLE Condition
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6.6.3 Output Spectrum
0
0
Input Level = −60 dB
Data Points = 8192
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
Input Level = −0.5 dB
Data Points = 8192
−60
−80
−60
−80
−100
−100
−120
−120
−140
−140
0
5
10
15
20
0
5
f − Frequency − kHz
G013
15
20
G014
Figure 13. Output Spectrum
THD+N − Total Harmonic Distortion + Noise − dB
10
f − Frequency − kHz
Figure 14. Output Spectrum
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Signal Level − dB
G015
Figure 15. Total Harmonic Distortion + Noise vs Signal Level
6.6.4 Supply Current
ICC and IDD − Supply Current − mA
15
IDD
10
ICC
5
(1)f
S
= 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
= 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
(2)f
S
0
0
10
44.1
20(1)
48
30(2)
96
40
fSAMPLE Condition − kHz
G016
Figure 16. Supply Current vs fSAMPLE Condition
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7 Detailed Description
7.1 Overview
The PCM1803A is suitable for a wide variety of cost-sensitive consumer applications where good performance
and operation from a 5-V analog supply and 3.3-V digital supply are required. With hardware control and
straightforward operation, the PCM1803A can quickly be implemented into an application. The PCM1803A
supports sampling rates from 16 kHz to 96 kHz as well as left justified, right justified, and I2S formats, allowing its
use in a variety of audio systems.
7.2 Functional Block Diagram
Delta-Sigma
Modulator
VINL
BCK
LRCK
×1/64 , ×1/128
Decimation
Filter
With
High-Pass Filter
VREF1
Reference
VREF2
Serial
Interface
Mode/
Format
Control
Delta-Sigma
Modulator
VINR
DOUT
FMT0
FMT1
MODE0
MODE1
BYPAS
TEST
OSR
Clock and Timing Control
Power Supply
PDWN
SCKI
VCC
AGND DGND
VDD
B0004-06
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7.3 Feature Description
7.3.1 Hardware Control
Pins FMT0, FMT1, OSR, BYPASS, MD0, and MD1 allow the device to be controlled by either tying these pins to
GND, or VDD, as well as GPIO, from a host IC. These controls allow full configuration of the PCM1803A.
7.3.2 Power-On-Reset Sequence
The PCM1803A has an internal power-on-reset circuit, and initialization (reset) is performed automatically at the
time when power-supply voltage (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical) and for 1024 system
clock cycles after VDD > 2.2 V (typical), the PCM1803A stays in the reset state, and the digital output is forced to
zero. The digital output becomes valid when a time period of 4480/fS has elapsed following release from the
reset state. Figure 17 illustrates the internal power-on-reset timing and the digital output for power-on reset.
10
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Feature Description (continued)
VDD
2.6 V
2.2 V
1.8 V
Reset
Reset Removal
Internal Reset
1024 System Clocks
4480 / fS
System Clock
DOUT
Zero Data
Normal Data
T0014-05
Figure 17. Internal Power-On-Reset Timing
7.3.3 System Clock
The PCM1803A supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling
frequency. The system clock must be supplied on SCKI (pin 15).
The PCM1803A has a system clock-detection circuit that automatically senses if the system clock is operating at
256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected by
MODE0 (pin 19) and MODE1 (pin 20), and 768 fS is not available. The system clock is divided automatically into
128 fS and 64 fS, and these frequencies are used to operate the digital filter and the delta-sigma modulator.
Table 1 shows the relationship of typical sampling frequency and system clock frequency, and Figure 18 shows
system clock timing.
Table 1. Sampling Frequency and System Clock Frequency
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING FREQUENCY (kHz)
(1)
256 fS
384 fS
512 fS
768 fS
(1)
32
8.1920
12.2880
16.3840
24.5760
44.1
11.2896
16.9344
22.5792
33.8688
48
12.2880
18.4320
24.5760
36.8640
64
16.3840
24.5760
32.7680
49.1520
88.2
22.5792
33.8688
45.1584
–
96
24.5760
36.8640
49.1520
–
Slave mode only
tw(SCKH)
tw(SCKL)
SCKI
2V
SCKI
0.8 V
T0005B07
Figure 18. System Clock Timing
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Table 2. System Clock Timing Requirements
PARAMETER
MIN
MAX
UNIT
tw(SCKH)
System clock pulse duration, HIGH
8
ns
tw(SCKL)
System clock pulse duration, LOW
8
ns
The quality of the system clock can influence the dynamic performance, because the PCM1803A operates based
on a system clock. Therefore, it may be required to consider the system-clock duty, jitter, and the time difference
between system-clock transition and BCK or LRCK transition in the slave mode.
7.4 Device Functional Modes
7.4.1 Serial Audio Data Interface
The PCM1803A interfaces the audio system through BCK (pin 11), LRCK (pin 10), and DOUT (pin 12).
7.4.1.1 Interface Mode
The PCM1803A supports master mode and slave mode as interface modes, and they are selected by MODE1
(pin 20) and MODE0 (pin 19) as shown in Table 3.
In master mode, the PCM1803A provides the timing of serial audio data communications between the
PCM1803A and the digital audio processor or external circuit. While in slave mode, the PCM1803A receives the
timing for data transfers from an external controller.
Table 3. Interface Mode
MODE1
MODE0
0
0
Slave mode (256 fS, 384 fS, 512 fS, 768 fS)
INTERFACE MODE
0
1
Master mode (512 fS)
1
0
Master mode (384 fS)
1
1
Master mode (256 fS)
7.4.1.1.1 Master Mode
In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing, which is generated
in the clock circuit of the PCM1803A. The frequency of BCK is fixed at LRCK × 64. The 768-fS system clock is
not available in master mode.
7.4.1.1.2 Slave Mode
In slave mode, BCK and LRCK work as input pins. The PCM1803A accepts the 64-BCK/LRCK or 48-BCK/LRCK
format (only for 384 fS and 768 fS system clocks), not the 32-BCK/LRCK format.
7.4.1.2 Data Format
The PCM1803A supports four audio data formats in both master and slave modes, and the data formats are
selected by FMT1 (pin 18) and FMT0 (pin 17) as shown in Table 4. Figure 19 illustrates the data formats in slave
and master modes.
Table 4. Data Formats
12
FORMAT
FMT1
FMT0
DESCRIPTION
0
0
0
Left-justified, 24-bit
1
0
1
I2S, 24-bit
2
1
0
Right-justified, 24-bit
3
1
1
Right-justified, 20-bit
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FORMAT 0: FMT[1:0] = 00
24-Bit, MSB-First, Left-Justified
Left-Channel
LRCK
Right-Channel
BCK
DOUT
1
2
3
22 23 24
MSB
1
LSB
2
3
22 23 24
MSB
1
LSB
FORMAT 1: FMT[1:0] = 01
24-Bit, MSB-First, I2S
LRCK
Left-Channel
Right-Channel
BCK
DOUT
1
2
3
22 23 24
1
LSB
MSB
2
3
22 23 24
LSB
MSB
FORMAT 2: FMT[1:0] = 10
24-Bit, MSB-First, Right-Justified
LRCK
Left-Channel
Right-Channel
BCK
DOUT
24
1
2
3
22 23 24
MSB
LSB
1
2
3
22 23 24
MSB
LSB
FORMAT 3: FMT[1:0] = 11
20-Bit, MSB-First, Right-Justified
LRCK
Left-Channel
Right-Channel
BCK
DOUT
20
1
2
3
MSB
18 19 20
LSB
1
2
MSB
3
18 19 20
LSB
T0016-11
Figure 19. Audio Data Formats (LRCK and BCK Work as Inputs in Slave Mode and as Outputs in Master
Mode)
7.4.1.3 Interface Timing
Figure 20 illustrates the interface timing in slave mode; Figure 21 and Figure 22 illustrate the interface timing in
master mode.
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t(LRCP)
1.4 V
LRCK
t(BCKL)
t(LRSU)
t(BCKH)
t(LRHD)
1.4 V
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DOUT
T0017-02
Figure 20. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)
Table 5. Audio Data Interface Slave Mode Timing Requirements (1)
PARAMETER
MIN
TYP
MAX
UNIT
t(BCKP)
BCK period
1/(64 fS)
ns
t(BCKH)
BCK pulse duration, HIGH
1.5 × t(SCKI)
ns
t(BCKL)
BCK pulse duration, LOW
1.5 × t(SCKI)
ns
t(LRSU)
LRCK setup time to BCK rising edge
40
ns
t(LRHD)
LRCK hold time to BCK rising edge
20
ns
t(LRCP)
LRCK period
10
t(CKDO)
Delay time, BCK falling edge to DOUT valid
–10
40
ns
t(LRDO)
Delay time, LRCK edge to DOUT valid
–10
40
ns
tr
Rising time of all signals
20
ns
tf
Falling time of all signals
20
ns
(1)
μs
Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rising and falling time is measured from 10% to 90% of
IN/OUT signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) means SCKI period time.
t(LRCP)
0.5 VDD
LRCK
t(BCKL)
t(BCKH)
t(CKLR)
0.5 VDD
BCK
t(BCKP)
t(CKDO)
t(LRDO)
0.5 VDD
DOUT
T0018-02
Figure 21. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)
14
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Table 6. Audio Data Interface Master Mode Timing Requirements (1)
PARAMETER
MIN
TYP
MAX
UNIT
150
1/(64 fS)
1000
ns
65
600
ns
65
600
ns
–10
20
ns
65
μs
–10
20
ns
–10
20
ns
Rising time of all signals
20
ns
Falling time of all signals
20
ns
t(BCKP)
BCK period
t(BCKH)
BCK pulse duration, HIGH
t(BCKL)
BCK pulse duration, LOW
t(CKLR)
Delay time, BCK falling edge to LRCK valid
t(LRCP)
LRCK period
t(CKDO)
Delay time, BCK falling edge to DOUT valid
t(LRDO)
Delay time, LRCK edge to DOUT valid
tr
tf
(1)
10
1/fS
Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rising and falling time is measured from 10% to 90% of
IN/OUT signal swing. Load capacitance of all signals is 20 pF.
1.4 V
SCKI
t(SCKBCK)
t(SCKBCK)
0.5 VDD
BCK
T0074-01
Figure 22. Audio Clock Interface Timing (Master Mode: BCK Works as Output)
Table 7. Audio Data Interface Master Mode BCK Timing Requirements (1)
PARAMETER
t(SCKBCK)
(1)
MIN
Delay time, SCKI rising edge to BCK edge
TYP
5
MAX
UNIT
30
ns
Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF.
7.4.2 Synchronization With Digital Audio System
In slave mode, the PCM1803A operates under LRCK, synchronized with system clock SCKI. The PCM1803A
does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of
LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48
BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS,
and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI occurs.
In case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does
not occur and the previously explained digital output control and discontinuity do not occur.
Figure 23 illustrates the digital output response for loss of synchronization and resynchronization. During
undefined data, the PCM1803A can generate some noise in the audio signal. Also, the transition of normal to
undefined data and undefined or zero data to normal creates a discontinuity in the data of the digital output,
which can generate some noise in the audio signal.
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Synchronization Lost
State of Synchronization
SYNCHRONOUS
Resynchronization
ASYNCHRONOUS
SYNCHRONOUS
1/fS
DOUT
UNDEFINED
DATA
NORMAL DATA
32/fS
ZERO DATA
NORMAL DATA
T0020-05
Figure 23. ADC Digital Output for Loss of Synchronization and Resynchronization
7.4.3 Power Down
PDWN (pin 7) controls operation of the entire ADC. During power-down mode, supply current for the analog
portion is shut down and the digital portion is reset; also, DOUT (pin 12) is disabled. It is acceptable to halt the
system clock during power-down mode so that power dissipation is minimized. The minimum LOW pulse
duration on the PDWN pin is 100 ns.
TI recommends setting PWDN (pin 7) to LOW once to obtain stable analog performance when the sampling rate,
interface mode, data format, or oversampling control is changed.
Table 8. Power-Down Control
PWDN
POWER-DOWN MODE
LOW
Power-down mode
HIGH
Normal operation mode
7.4.4 HPF Bypass
The built-in function for DC-component rejection can be bypassed by BYPAS (pin 8) control. In bypass mode, the
DC component of the input analog signal, internal DC offset, and so forth, also are converted and included in the
digital output data.
Table 9. HPF Bypass Control
BYPAS
HPF (HIGH-PASS FILTER) MODE
LOW
Normal (no DC component in DOUT) mode
HIGH
Bypass (DC component in DOUT) mode
7.4.5 Oversampling Ratio Control
OSR (pin 16) controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128. The ×128 mode is
available for fS ≤ 48 kHz.
Table 10. Oversampling Control
16
OSR
OVERSAMPLING RATIO
LOW
×64
HIGH
×128 (fS ≤ 48 kHz)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The PCM1803A device is suitable for wide variety of cost-sensitive consumer applications requiring good
performance and operation with a 5-V analog supply and 3.3-V digital supply.
8.2 Typical Application
Figure 24 illustrates a typical circuit connection diagram where the cutoff frequency of the input HPF is about
160 kHz.
C1
L-Ch IN
C2
R-Ch IN
+
R1
+
R2
1
VINL
MODE1
20
2
VINR
MODE0
19
3
VREF1
FMT1
18
Mode [1:0]
C7
C8
C5
C6
+
+
4
VREF2
5
VCC
6
Power Down
LCF Bypass
+5 V
+
C4
Control
Format [1:0]
FMT0
17
OSR
16
Oversampling
AGND
SCKI
15
System Clock
7
PDWN
VDD
14
8
BYPAS
DGND
13
9
TEST
DOUT
12
Data Out
10 LRCK
BCK
11
Data Clock
PCM1803A
+
Control
C3
+3.3 V
Audio Data
Processor
L/R Clock
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A.
C1, C2: A 1-μF electrolytic capacitor gives a 4-Hz (τ = 1 μF × 40 kΩ) cutoff frequency for the input HPF in normal
operation and requires a power-on settling time with a 40-ms time constant during the power-on initialization period.
B.
C3, C4: Bypass capacitors are 0.1-μF ceramic and 10-μF electrolytic, depending on layout and power supply.
C.
C5, C6: Recommended capacitors are 0.1-μF ceramic and 10-μF electrolytic.
D.
C7, C8, R1, R2: A 0.01-μF film-type capacitor and 100-Ω resistor give a 160-kHz (τ = 0.01 μF × 100 Ω) cutoff
frequency for the anti-aliasing filter in normal operation.
Figure 24. Typical Application Diagram
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Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 11 as the input parameters.
Table 11. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Analog Input Voltage Range
0 Vp-p to 3 Vp-p
Output
PCM audio data
System Clock Input Frequency
2.048 MHz to 49.152 MHz
Output Sampling Frequency
8 kHz to 96 kHz
Power Supply
3.3 V and 5 V
8.2.2 Detailed Design Procedure
8.2.2.1 Control Pins
The control pins such as the FMT, MODE, OSR, and BYPASS can be controlled by tying up to VDD, down to
GND, or driven with GPIO from the DSP or audio processor.
8.2.2.2 DSP or Audio Processor
In this application a DSP or audio processor is acting as the audio master, and the PCM1803A is acting as the
audio slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1803A
can use to process audio signals.
8.2.2.3 Input Filters
For the analog input circuit an AC coupling capacitor must be placed in series with the input. This removes the
DC component of the input signal. An RC filter can also be implemented to filter out of band noise to reduce
aliasing. Equation 1 can be used to calculate the cutoff frequency of the optional RC filter for the input.
1
fc =
2pRC
(1)
THD+N − Total Harmonic Distortion + Noise − dB
8.2.3 Application Curve
−90
−91
−92
−93
−94
−95
−96
−97
−98
(1)f
S
−99
(2)f
S
= 48 kHz, System Clock = 256 fS,
Oversampling Ratio = ×128.
= 96 kHz, System Clock = 256 fS,
Oversampling Ratio = ×64.
−100
0
10
20(1)
30(2)
44.1
48
96
fSAMPLE Condition − kHz
40
G011
Figure 25. Total Harmonic Distortion + Noise vs fSAMPLE Condition
18
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9 Power Supply Recommendations
The PCM1803A requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the analog
circuitry powered by the VCC pin. The 3.3-V supply is for the digital circuitry powered by the VDD pin. The
decoupling capacitors for the power supplies must be placed close to the device terminals.
10 Layout
10.1 Layout Guidelines
10.1.1 VCC, VDD Pins
The digital and analog power-supply lines to the PCM1803A must be bypassed to the corresponding ground pins
with 0.1-μF ceramic and 10-μF electrolytic capacitors, as close to the pins as possible, to maximize the dynamic
performance of the ADC.
10.1.2 AGND, DGND Pins
To maximize the dynamic performance of the PCM1803A, the analog and digital grounds are not connected
internally. These grounds must have low impedance to avoid digital noise feeding back into the analog ground.
Therefore, they must be connected directly to each other under the part to reduce potential noise problems.
10.1.3 VINL, VINR Pins
The VINL and VINR pins need a simple external RC filter (fC = 160 kHz) as an antialiasing filter to remove out-ofband noise from the audio band. If the input signal includes noise with a frequency near the oversampling
frequency (64 fS or 128 fS), the noise is folded into the baseband (audio band) signal through A-to-D conversion.
The recommended R value is 100 Ω. Film-type capacitors of 0.01 μF must be placed as close as possible to the
VINL and VINR pins and must be terminated to GND as close as possible to the AGND pin to maximize the
dynamic performance of ADC, by suppressing kickback noise from the PCM1803A.
10.1.4 VREF1 Pin
TI recommends a 0.1-μF ceramic capacitor and 10-μF electrolytic capacitor between VREF1 and AGND to ensure
low source impedance of the ADC references. These capacitors must be placed as close as possible to the
VREF1 pin to reduce dynamic errors on the ADC reference.
10.1.5 VREF2 Pin
The differential voltage between VREF2 and AGND sets the analog input full-scale range. A 0.1-μF ceramic
capacitor and 10-μF electrolytic capacitor are recommended between VREF2 and AGND. These capacitors must
be placed as close as possible to the VREF2 pin to reduce dynamic errors on the ADC reference.
10.1.6 DOUT Pin
The DOUT pin has enough load drive capability, but if the DOUT line is long, placing a buffer near the
PCM1803A and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and
maximize the dynamic performance of the ADC.
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10.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around PCM1803A and connect to lower main PCB
ground plane by multiple vias
Option External RC
antialiasing circuit
1 F
R-ch IN
+
L-ch IN
VINL
MODE1
20
2
VINR
MODE0
19
3
VREF1
FMT1
18
4
VREF2
FMT0
17
5
VCC
OSR
16
6
AGND
SCKI
15
7
PDWN
VDD
14
+
1
1 F
+
Control
+
Make sure to have
ground pour separating
the Left and Right
channel traces to help
prevent crosstalk
Bypass Capacitors are
0.1 uF and 10 uF
5V
PCM1803A
Make sure to have
ground pour separating
the clock signals from
surrounding traces
+
10 F
0.1 F
3.3V
+
Control
8
BYPAS
DGND
13
9
TEST
DOUT
12
10
LRCK
BCK
11
Top Layer Ground Pour
Top Layer Signal Traces
0.1 F
10 F
Clock signals to
DSP or Audio
Processor
Via to bottom Ground Plane
Pad to top layer ground pour
Figure 26. Layout Recommendation
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1803ADB
ACTIVE
SSOP
DB
20
65
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1803A
PCM1803ADBG4
ACTIVE
SSOP
DB
20
65
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1803A
PCM1803ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1803A
PCM1803ADBRG4
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PCM1803A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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