PCM1804
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz
STEREO A/D CONVERTER
FEATURES
APPLICATIONS
• 24-Bit Delta-Sigma Stereo A/D Converter
• High Performance:
– Dynamic Range: 112 dB (Typical)
– SNR: 111 dB (Typical)
– THD+N: –102 dB (Typical)
• High-Performance Linear Phase Antialias
Digital Filter:
– Pass-Band Ripple: ±0.005 dB
– Stop-Band Attenuation: –100 dB
• Fully Differential Analog Input: ±2.5 V
• Audio Interface: Master- or Slave-Mode
Selectable
• Data Formats: Left-Justified, I2S, Standard
24-Bit, and DSD
• Function:
– Peak Detection
– High-Pass Filter (HPF): –3 dB at 1 Hz,
fS = 48 kHz
• Sampling Rate up to 192 kHz
• System Clock: 128 fS, 256 fS, 384 fS,
512 fS, or 768 fS
• Dual Power Supplies:
– 5 V for Analog
– 3.3 V for Digital
• Power Dissipation: 225 mW
• Small 28-Pin SSOP
• DSD Output: 1 Bit, 64 fS
•
•
•
•
•
1
23
AV Amplifier
MD Player
Digital VTR
Digital Mixer
Digital Recorder
DESCRIPTION
The PCM1804 is a high-performance, single-chip
stereo A/D converter with fully differential analog
voltage input. The PCM1804 uses a precision
delta-sigma modulator and includes a linear phase
antialias digital filter and high-pass filter (HPF) that
removes dc offset from the input signal. The
PCM1804 is suitable for a wide variety of mid- to
high-grade consumer and professional applications,
where excellent performance and 5-V analog supply
and 3.3-V digital power-supply operation are required.
The PCM1804 can achieve both PCM audio and
DSD format due to the precision delta-sigma
modulator. The PCM1804 is fabricated using an
advanced CMOS process and is available in a small
28-pin SSOP package.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two, Audio Precision are trademarks of Audio Precision, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated
PCM1804
www.ti.com
SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields.
These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic
voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Electrostatic Discharge (ESD) (SSYA008), available from Texas Instruments.
PIN ASSIGNMENTS
PCM1804 PACKAGE
(TOP VIEW)
VREFL
AGNDL
VCOML
VINL+
VINL−
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VREFR
AGNDR
VCOMR
VINR+
VINR−
AGND
VCC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
P0007-02
2
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
FUNCTIONAL BLOCK DIAGRAM
OSR0
CLK
Control
SCKI
OSR1
OSR2
VINL+
VINL−
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
FMT0
VCOML
AGNDL
VREFL
VREFR
AGNDR
FMT1
VREFL
Serial
Output
Interface
VREFR
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
VCOMR
VINR+
VINR−
Decimation
Filter (R)
Delta-Sigma
Modulator (R)
HPF
OVFL
OVFR
BYPAS
Power Supply
VCC AGND
DGND
RST
VDD
B0029-01
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3
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
PIN
AGND
23
–
Analog ground
AGNDL
2
–
Analog ground for VREFL
AGNDR
27
–
Analog ground for VREFR
BCK/DSDL
16
I/O Bit clock input/output in PCM mode. L-channel audio data output in DSD mode.
(1)
(1)
BYPAS
12
I
HPF bypass control. High: HPF disabled, Low: HPF enabled
DATA/DSDR
15
O
L-channel and R-channel audio data output in PCM mode. R-channel audio data output in DSD mode. (DSD
output, when in DSD mode)
DGND
13
–
Digital ground
FMT0
6
I
Audio data format 0. See Table 5.
(2)
FMT1
7
I
Audio data format 1. See Table 5.
(2)
LRCK/DSDBCK
17
I/O Sampling clock input/output in PCM and DSD modes.
(1)
OSR0
9
I
Oversampling ratio 0. See Table 1 and Table 2.
(2)
OSR1
10
I
Oversampling ratio 1. See Table 1 and Table 2.
(2)
OSR2
11
I
Oversampling ratio 2. See Table 1 and Table 2.
(2)
OVFL
21
O
Overflow signal of L-channel in PCM mode. This is available in PCM mode only.
OVFR
20
O
Overflow signal of R-channel in PCM mode. This is available in PCM mode only.
RST
19
I
Reset, power-down input, active-low
SCKI
18
I
System clock input; 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
(2)
(3)
(2)
S/M
8
I
Slave/master mode selection. See Table 4.
VCC
22
–
Analog power supply
VCOML
3
–
L-channel analog common-mode voltage (2.5 V)
VCOMR
26
–
R-channel analog common-mode voltage (2.5 V)
VDD
14
–
Digital power supply
VINL–
5
I
L-channel analog input, negative pin
VINL+
4
I
L-channel analog input, positive pin
VINR–
24
I
R-channel analog input, negative pin
VINR+
25
I
R-channel analog input, positive pin
VREFL
1
–
L-channel voltage reference output, requires capacitors for decoupling to AGND
VREFR
28
–
R-channel voltage reference output, requires capacitors for decoupling to AGND
(1)
(2)
(3)
4
Schmitt-trigger input
Schmitt-trigger input with internal pulldown (51 kμ typically), 5-V tolerant.
Schmitt-trigger input, 5-V tolerant.
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
VCC
–0.3 V to 6.5 V
VDD
–0.3 V to 4 V
Ground voltage differences
AGND, AGNDL, AGNDR, DGND
Supply voltage difference
VCC, VDD
Digital input voltage
Analog input voltage
±0.1 V
VCC – VDD < 3 V
FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST
–0.3 V to 6.5 V
BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK, OVFL, OVFR
–0.3 V to (VDD + 0.3 V)
VREFL, VREFR, VCOML, VCOMR, VINL+, VINR+, VINL–, VINR–
–0.3 V to (VCC + 0.3 V)
Input current (any pins except supplies)
±10 mA
TA
Ambient temperature under bias
–40°C to 125°C
Tstg
Storage temperature
–55°C to 150°C
TJ
Junction temperature
150°C
Lead temperature (soldering)
260°C, 5 s
Package temperature (IR reflow, peak)
(1)
260°C
Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range
Analog supply voltage, VCC
Digital supply voltage, VDD
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
3
3.3
3.6
Analog input voltage, full-scale (–0 dB), differential input
5
Digital input logic family
Digital input clock frequency
V
Vp-p
TTL compatible
System clock
Sampling clock
8.192
36.864
MHz
32
192
kHz
10
pF
70
°C
Digital output load capacitance
Operating free-air temperature, TA
–10
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,
24-bit data, unless otherwise noted.
PARAMETER
TEST CONDITIONS
PCM1804DB
MIN
Resolution
TYP
MAX
24
UNIT
Bits
DATA FORMAT
Standard, I2S, left-justified
Audio data interface format
Audio data bit length
24
Bits
MSB first,
2s complement, DSD
Audio data format
DIGITAL INPUT/OUTPUT
Logic family
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
VOH
High-level output voltage
VOL
Low-level output voltage
TTL compatible
(1) (2)
2
5.5
(3)
2
VDD
(1) (2) (3)
0.8
VIN = VDD
(1)
VIN = VDD
(2)
±10
VIN = VDD
(3)
±100
65
(1) (2)
±10
VIN = 0 V
(3)
±50
IOL = 1 mA
(4)
Vdc
100
VIN = 0 V
IOH = –1 mA
Vdc
2.4
μA
μA
Vdc
(4)
0.4
Vdc
192
kHz
CLOCK FREQUENCY
fS
Sampling frequency
System clock frequency
32
256 fS, single rate
(5)
12.288
384 fS, single rate
(5)
18.432
512 fS, single rate
(5)
24.576
768 fS, single rate
(5)
36.864
256 fS, dual rate
(6)
24.576
384 fS, dual rate
(6)
36.864
128 fS, quad rate
(7)
24.576
192 fS, quad rate
(7)
36.864
MHz
DC ACCURACY
Gain mismatch, channelto-channel
±3
% of FSR
Gain error (VIN = –0.5 dB)
±4
% of FSR
Bipolar zero error
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
HPF bypass
±0.2
% of FSR
Pins 6–11, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST [Schmitt-trigger input with internal pulldown (51 kμ typically), 5-V tolerant]
Pin 18: SCKI (Schmitt-trigger input, 5-V tolerant)
Pins 12, 16–17: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input)
Pins 15–17, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL
Single rate, fS = 48 kHz
Dual rate, fS = 96 kHz
Quad rate, fS = 192 kHz
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,
24-bit data, unless otherwise noted.
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
TYP
MAX
–102
–95
UNIT
(8)
VIN = –0.5 dB
VIN = –60 dB
VIN = –0.5 dB
THD+N
PCM1804DB
MIN
Total harmonic distortion
plus noise
VIN = –60 dB
VIN = –0.5 dB
VIN = –60 dB
fS = 48 kHz, system clock = 256 fS
–49
–101
fS = 96 kHz, system clock = 256 fS
–47
fS = 192 kHz, system clock = 128 fS
–47
VIN = –0.5 dB DSD mode
fS = 48 kHz, system clock = 256 fS
Dynamic range
(A-weighted)
VIN = –60 dB
–100
106
112
fS = 192 kHz, system clock = 128 fS
112
dB
112
fS = 48 kHz, system clock = 256 fS
105
111
fS = 96 kHz, system clock = 256 fS
111
fS = 192 kHz, system clock = 128 fS
111
DSD mode
dB
111
fS = 48 kHz, system clock = 256 fS
Channel separation
112
fS = 96 kHz, system clock = 256 fS
DSD mode
SNR (A-weighted)
dB
–101
97
109
fS = 96 kHz, system clock = 256 fS
107
fS = 192 kHz, system clock = 128 fS
107
dB
Differential input
±2.5
V
2.5
Vdc
10
kμ
ANALOG INPUT
Input voltage
Center voltage
Input impedance
Single-ended
DIGITAL FILTER PERFORMANCE
(8)
Pass-band edge
Single rate, dual rate
Stop-band edge
Single rate, dual rate
0.453 fS
Pass-band ripple
Single rate, dual rate
Stop-band attenuation
Single rate, dual rate
Pass-band edge (–0.005
dB)
Quad rate
Pass-band edge (–3 dB)
Quad rate
Stop-band edge
Quad rate
Pass-band ripple
Quad rate
Stop-band attenuation
Quad rate
Group delay
Single rate, dual rate
37/fS
Group delay
Quad rate
9.5/fS
HPF frequency response
–3 dB
0.547 fS
Hz
Hz
±0.005
–100
dB
dB
0.375 fS
Hz
0.49 fS
Hz
0.77 fS
Hz
±0.005
–135
dB
dB
fS/48000
s
s
Hz
fIN = 1 kHz, using System Two™ audio measurement system by Audio Precision™ in RMS mode, with 20-kHz LPF and 400-Hz HPF in
calculation for single rate, or with 40-kHz LPF in calculation for dual and quad rates.
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS,
24-bit data, unless otherwise noted.
PARAMETER
TEST CONDITIONS
PCM1804DB
MIN
TYP
MAX
4.75
5
5.25
3
3.3
3.6
(9) (10) (11)
35
45
VDD = 3.3 V
(9) (12)
15
20
VDD = 3.3 V
(10) (12)
27
VDD = 3.3 V
(11) (12)
UNIT
POWER SUPPLY REQUIREMENTS
VCC
VDD
Supply voltage range
ICC
IDD
PD
VCC = 5 V
Supply current
Power dissipation
Vdc
mA
18
Operation, VCC = 5 V, VDD = 3.3 V
(9) (12)
225
Operation, VCC = 5 V, VDD = 3.3 V
(10) (12)
265
Operation, VCC = 5 V, VDD = 3.3 V
(11) (12)
235
Power down, VCC = 5 V, VDD = 3.3 V
290
mW
5
TEMPERATURE RANGE
Operation temperature
θJA
(9)
(10)
(11)
(12)
8
–10
Thermal resistance
70
100
°C
°C/W
Single rate, fS = 48 kHz
Dual rate, fS = 96 kHz
Quad rate, fS = 192 kHz
Minimum load on DATA/DSDR (pin 15)
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless
otherwise noted.
DYNAMIC RANGE AND SNR
vs
TEMPERATURE
−35
−95
−40
−100
−45
−0.5 dB
−105
−110
−20
−50
−60 dB
−55
0
20
40
60
80
120
Dynamic Range and SNR − dB
−90
THD+N − Total Harmonic Distortion + Noise − dB (−60 dB)
THD+N − Total Harmonic Distortion + Noise − dB (−0.5 dB)
TOTAL HARMONIC DISTORTION + NOISE
vs
TEMPERATURE
115
Dynamic Range
110
105
100
−20
T − Temperature − °C
SNR
0
20
60
TOTAL HARMONIC DISTORTION + NOISE
vs
SUPPLY VOLTAGE
DYNAMIC RANGE AND SNR
vs
SUPPLY VOLTAGE
−95
−40
−100
−45
−0.5 dB
−105
−50
−60 dB
−55
4.75
5.00
5.25
VCC − Supply Voltage − V
5.50
120
Dynamic Range and SNR − dB
−35
80
G002
Figure 2.
−90
−110
4.50
40
T − Temperature − °C
Figure 1.
THD+N − Total Harmonic Distortion + Noise − dB (−60 dB)
THD+N − Total Harmonic Distortion + Noise − dB (−0.5 dB)
G001
115
Dynamic Range
110
SNR
105
100
4.50
G003
Figure 3.
4.75
5.00
5.25
VCC − Supply Voltage − V
5.50
G004
Figure 4.
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless
otherwise noted.
DYNAMIC RANGE AND SNR
vs
SAMPLING FREQUENCY
−35
−95
−40
−100
−45
−0.5 dB
−105
−50
−60 dB
−110
−55
32
44.1
48
120
Dynamic Range and SNR − dB
−90
THD+N − Total Harmonic Distortion + Noise − dB (−60 dB)
THD+N − Total Harmonic Distortion + Noise − dB (−0.5 dB)
TOTAL HARMONIC DISTORTION + NOISE
vs
SAMPLING FREQUENCY
115
Dynamic Range
110
SNR
105
100
32
fS − Sampling Frequency − kHz
G005
44.1
48
fS − Sampling Frequency − kHz
Figure 5.
G006
Figure 6.
THD+N − Total Harmonic Distortion + Noise − dB
TOTAL HARMONIC DISTORTION + NOISE
vs
SIGNAL LEVEL
0
−20
−40
−60
−80
−100
−120
−100
−80
−60
−40
−20
0
Signal Level − dB
G009
Figure 7.
10
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless
otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
Output Spectrum:
−0.5 dB,
N = 8192
−20
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
Output Spectrum:
−60 dB,
N = 8192
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
12000
0
24000
12000
24000
f − Frequency − Hz
f − Frequency − Hz
G008
G007
Figure 8.
Figure 9.
TYPICAL PERFORMANCE CURVES - DUAL RATE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, and 24-bit data, unless otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
fS = 96 kHz,
System Clock = 256 fS
−20
−40
−40
Output Spectrum:
−0.5 dB,
N = 8192
−60
Amplitude − dB
Amplitude − dB
fS = 96 kHz,
System Clock = 256 fS
−20
−80
−100
−80
−100
−120
−120
−140
−140
−160
Output Spectrum:
−60 dB,
N = 8192
−60
−160
0
24000
48000
0
f − Frequency − Hz
G010
Figure 10.
24000
48000
f − Frequency − Hz
G011
Figure 11.
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES - QUAD RATE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, 24-bit data, unless otherwise noted.
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0
0
fS = 192 kHz,
System Clock = 128 fS
−20
−40
−40
Output Spectrum:
−0.5 dB,
N = 8192
−60
Amplitude − dB
Amplitude − dB
fS = 192 kHz,
System Clock = 128 fS
−20
−80
−100
−80
−100
−120
−120
−140
−140
−160
Output Spectrum:
−60 dB,
N = 8192
−60
−160
0
48000
96000
0
48000
f − Frequency − Hz
96000
f − Frequency − Hz
G012
G013
Figure 12.
Figure 13.
TYPICAL PERFORMANCE CURVES - DSD MODE
All specifications at TA = 25°C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 44.1 kHz, system clock = 16.9344 MHz, unless
otherwise noted.
AMPLITUDE
vs
FREQUENCY
0
0
−20
−20
−40
−40
Amplitude − dB
Amplitude − dB
AMPLITUDE
vs
FREQUENCY
−60
Output Spectrum:
−0.5 dB,
N = 8192
−80
−100
−60
−100
−120
−120
−140
−140
−160
Output Spectrum:
−60 dB,
N = 8192
−80
−160
0
11025
22050
0
f − Frequency − Hz
11025
G014
Figure 14.
12
22050
f − Frequency − Hz
G015
Figure 15.
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Single-Rate
OVERALL CHARACTERISTICS
FOR SINGLE-RATE FILTER
STOP-BAND ATTENUATION CHARACTERISTICS
FOR SINGLE-RATE FILTER
50
0
−10
fS = 48 kHz
fS = 48 kHz
−20
0
−30
Amplitude − dB
Amplitude − dB
−40
−50
−100
−50
−60
−70
−80
−90
−100
−110
−150
−120
−130
−140
−200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Normalized Frequency − y fS
−150
0.00
4.0
0.50
0.75
Normalized Frequency − y fS
G016
Figure 16.
Figure 17.
PASS-BAND RIPPLE CHARACTERISTICS
FOR SINGLE-RATE FILTER
TRANSIENT BAND CHARACTERISTICS
FOR SINGLE-RATE FILTER
0.02
1.00
G017
0
fS = 48 kHz
fS = 48 kHz
−1
0.00
−2
−3
−0.02
Amplitude − dB
Amplitude − dB
0.25
−0.04
−0.06
−4
−5
−6.04 dB at 0.5 fS
−6
−7
−8
−0.08
−9
−0.10
0.0
0.1
0.2
0.3
0.4
Normalized Frequency − y fS
0.5
0.6
−10
0.45
G018
Figure 18.
0.47
0.49
0.51
0.53
Normalized Frequency − y fS
0.55
G019
Figure 19.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Dual-Rate
OVERALL CHARACTERISTICS
FOR DUAL-RATE FILTER
STOP-BAND ATTENUATION CHARACTERISTICS
FOR DUAL-RATE FILTER
50
0
fS = 96 kHz
−10
fS = 96 kHz
−20
0
−30
Amplitude − dB
Amplitude − dB
−40
−50
−100
−50
−60
−70
−80
−90
−100
−110
−150
−120
−130
−140
−200
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Normalized Frequency − y fS
−150
0.00
0.50
0.75
Normalized Frequency − y fS
G020
Figure 20.
Figure 21.
PASS-BAND RIPPLE CHARACTERISTICS
FOR DUAL-RATE FILTER
TRANSIENT BAND CHARACTERISTICS
FOR DUAL-RATE FILTER
0.02
1.00
G021
0
fS = 96 kHz
fS = 96 kHz
−1
0.00
−2
−3
−0.02
Amplitude − dB
Amplitude − dB
0.25
−0.04
−0.06
−4
−5
−6.02 dB at 0.5 fS
−6
−7
−8
−0.08
−9
−0.10
0.0
0.1
0.2
0.3
0.4
Normalized Frequency − y fS
0.5
0.6
−10
0.45
G022
Figure 22.
14
0.47
0.49
0.51
0.53
Normalized Frequency − y fS
0.55
G023
Figure 23.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Quad-Rate
OVERALL CHARACTERISTICS
FOR QUAD-RATE FILTER
STOP-BAND ATTENUATION CHARACTERISTICS
FOR QUAD-RATE FILTER
50
0
fS = 192 kHz
−10
fS = 192 kHz
−20
0
−30
Amplitude − dB
Amplitude − dB
−40
−50
−100
−50
−60
−70
−80
−90
−100
−110
−150
−120
−130
−140
−200
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Frequency − y fS
−150
0.00
0.25
0.50
0.75
Normalized Frequency − y fS
G024
Figure 24.
Figure 25.
PASS-BAND RIPPLE CHARACTERISTICS
FOR QUAD-RATE FILTER
TRANSIENT BAND CHARACTERISTICS
FOR QUAD-RATE FILTER
0.02
G025
0
fS = 192 kHz
fS = 192 kHz
−1
0.00
−2
−3
−0.02
Amplitude − dB
Amplitude − dB
1.00
−0.04
−0.06
−4
−5
−3.9 dB at 0.5 fS
−6
−7
−8
−0.08
−9
−0.10
0.0
0.1
0.2
0.3
0.4
Normalized Frequency − y fS
0.5
0.6
−10
0.45
G026
Figure 26.
0.47
0.49
0.51
0.53
Normalized Frequency − y fS
0.55
G027
Figure 27.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued)
HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE
STOP-BAND CHARACTERISTICS
PASS-BAND CHARACTERISTICS
0.2
0
−10
0.0
−20
Amplitude − dB
Amplitude − dB
−30
−40
−50
−60
−70
−80
−0.2
−0.4
−0.6
−0.8
−90
−100
0.0
0.1
0.2
0.3
0.4
Normalized Frequency − y fS/1000
−1.0
0.0
G028
0.5
1.0
1.5
2.0
2.5
3.0
Normalized Frequency − y fS/1000
Figure 28.
3.5
4.0
G029
Figure 29.
PRINCIPLES OF OPERATION
THEORY OF OPERATION
The PCM1804 consists of a band-gap reference, a delta-sigma modulator with full-differential architecture for
L-channel and R-channel, a decimation filter with a high-pass filter, and a serial interface circuit. Figure 30
illustrates the total architecture of the PCM1804. An on-chip, high-precision reference with 10-μF external
capacitor(s) provides all the reference voltage needed in the PCM1804, and it defines the full-scale voltage range
of both channels. Full-differential architecture provides a wide dynamic range and excellent power-supply
rejection performance. The input signal is sampled at ×128, ×64, and ×32 oversampling rates according to the
overasmpling ratio control, OSR[0:2]. The single rate, dual rate, and quad rate eliminate the external sample-hold
amplifier. Figure 31 illustrates how for each oversampling ratio the PCM1804 decimates the modulator output
down to PCM data when the modulator is running at 6.144 MHz. The delta-sigma modulation randomizes the
modulator outputs and reduces the idle tone level. The oversampled data stream from the delta-sigma modulator
is converted to a 1-fS, 24-bit digital signal, while removing high-frequency noise components using a decimation
filter. The dc components of the signal are removed by the HPF, and the HPF output is converted to a
time-multiplexed serial signal through the serial interface, which provides flexible serial formats and master/slave
modes. The PCM1804 also has a DSD output mode. The PCM1804 can output the signal directly from the
modulators to DSDL (pin 16) and DSDR (pin 15).
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PRINCIPLES OF OPERATION (continued)
OSR0
CLK
Control
SCKI
OSR1
OSR2
VINL+
VINL−
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
FMT0
VCOML
AGNDL
VREFL
VREFR
AGNDR
FMT1
VREFL
Serial
Output
Interface
VREFR
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
VCOMR
VINR+
VINR−
Decimation
Filter (R)
Delta-Sigma
Modulator (R)
OVFL
HPF
OVFR
BYPAS
Power Supply
VCC AGND
RST
DGND
VDD
B0029-01
Figure 30. Total Block Diagram of PCM1804
0
Quad-Rate Filter
−20
Amplitude − dB
−40
Dual-Rate Filter
−60
−80
Modulator
SingleRate
Filter
−100
−120
−140
−160
0
48
96
144
192
f − Frequency − kHz
G030
Figure 31. Spectrum of Modulator Output and Decimation Filter
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PRINCIPLES OF OPERATION (continued)
SYSTEM CLOCK INPUT
The PCM1804 supports 128 fS, 192 fS (only in master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as a
system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18).
Table 3 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32
shows system clock timing. In master mode, the system clock rate is selected by OSR2 (pin 11), OSR1 (pin 10),
and OSR0 (pin 9) as shown in Table 1. In slave mode, the system clock rate is automatically detected. In DSD
mode, OSR2 (pin 11), OSR1 (pin 10), OSR0 (pin 9), and the system clock frequency are fixed as shown in
Table 1 and Table 3.
tw(SCKH)
tw(SCKL)
SCKI
2V
SCKI
0.8 V
T0005B07
PARAMETER
tw(SCKH)
tw(SCKL)
System clock pulse duration, HIGH
System clock pulse duration, LOW
MIN
11
11
UNIT
ns
ns
Figure 32. System Clock Input Timing
POWER-ON AND RESET FUNCTIONS
The PCM1804 has both an internal power-on-reset circuit and RST (pin 19). For internal power-on reset,
initialization (reset) is performed automatically at the time when the power supply VDD exceeds 2 V (typical) and
VCC exceeds 4 V (typical). RST accepts external forced reset, and a low level on RST initiates the reset
sequence. Because an internal pulldown resistor terminates RST, no connection of RST is equivalent to a
low-level input. Because the system clock is used as a clock signal for the reset circuit, the system clock must be
supplied as soon as power is supplied; more specifically, at least three system clocks are required prior to VDD >
2 V, VCC > 4 V, and RST = high. While VDD < 2 V (typical), VCC < 4 V (typical), or RST = low, and 1/fS (maximum)
count after VDD > 2 V (typical),VCC > 4 V (typical) and RST = high, the PCM1804 stays in the reset state and the
digital output is forced to zero. The digital output is valid after the reset state is released and the time of 1116/fS
has passed. Figure 33 and Figure 34 illustrate the internal power-on-reset and external-reset timing, respectively.
Figure 35 illustrates the digital output for power-on reset and RST control. The PCM1804 needs RST = low when
control pins are changed or in slave mode when SCKI, LRCK, and BCK are changed.
POWER-DOWN FUNCTION
The PCM1804 has a power-down feature that is controlled by RST (pin 19). Entering the power-down mode is
done by keeping the RST input level low for more than 65536/fS. In the master mode, the SCKI (pin 18) is used
as the clock signal for the power-down counter. While in the slave mode, SCKI (pin 18) and LRCK (pin 17) are
used as the clock signal. The clock(s) must be supplied until the power-down sequence completes. As soon as
RST goes high, the PCM1804 starts the reset-release sequence described in the Power-On and Reset Functions
section.
OVERSAMPLING RATIO
The oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1 and
Table 2. The PCM1804 needs RST = low when logic levels on the OSR2, OSR1, and OSR0 pins are changed.
18
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Table 1. Oversampling Ratio in Master Mode
OSR2
OSR1
OSR0
OVERSAMPLING RATIO
SYSTEM CLOCK RATE
Low
Low
Low
Single rate (× 128 fS)
768 fS
Low
Low
High
Single rate (× 128 fS)
512 fS
Low
High
Low
Single rate (× 128 fS)
384 fS
Low
High
High
Single rate (× 128 fS)
256 fS
High
Low
Low
Dual rate (× 64 fS)
384 fS
High
Low
High
Dual rate (× 64 fS)
256 fS
High
High
Low
Quad rate (× 32 fS)
192 fS
High
High
High
Quad rate (× 32 fS)
128 fS
High
Low
Low
DSD mode (× 64 fS)
384 fS
High
Low
High
DSD mode (× 64 fS)
256 fS
Table 2. Oversampling Ratio in Slave Mode
(1)
OSR2
OSR1
OSR0
OVERSAMPLING RATIO
SYSTEM CLOCK RATE
Low
Low
Low
Single rate (× 128 fS)
Automatically detected
Low
Low
High
Dual rate (× 64 fS)
Automatically detected
Low
High
Low
Quad rate (× 32 fS) (1)
Automatically detected
Low
High
High
Reserved
–
High
Low
Low
Reserved
–
High
Low
High
Reserved
–
High
High
Low
Reserved
–
High
High
High
Reserved
–
Only at the 128-fS system clock rate
Table 3. Sampling Frequency and System Clock Frequency
OVERSAMPLING RATIO
Single rate (2)
Dual rate (3)
Quad rate (4)
DSD mode (3)
(1)
(2)
(3)
(4)
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING
FREQUENCY (kHz)
128 fS
192 fS (1)
256 fS
384 fS
512 fS
768 fS
32
–
–
8.192
12.288
16.384
24.576
44.1
–
–
11.2896
16.9344
22.5792
33.8688
48
–
–
12.288
18.432
24.576
36.864
88.2
–
–
22.5792
33.8688
–
–
96
–
–
24.576
36.864
–
–
176.4
22.5792
33.8688
–
–
–
–
192
24.576
36.864
–
–
–
–
44.1
–
–
11. 2896
16.9344
–
–
Only available in master mode at the quad rate
Modulator is running at 128 fS.
Modulator is running at 64 fS.
Modulator is running at 32 fS.
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VCC, VDD
4.4 V / 2.2 V
4V/2V
3.6 V / 1.8 V
Reset
Reset Removal
Internal Reset
1024 System Clock + 1/fS (Max)
System Clock
T0014-07
Figure 33. Internal Power-On-Reset Timing
RST
t(RST)
RST Pulse Duration (t(RST)) = 40 ns (Min)
Reset
Reset Removal
Internal Reset
1/fS (Max)
System Clock
T0015-05
Figure 34. External Reset Timing
Power ON
RST ON
Internal Reset
Reset Removal
Ready / Operation
Reset
1116/fS
Data(1)
Zero Data
Converted Data(2)
T0051-01
(1)
In the DSD mode, DSDL is also controlled like DSDR.
(2)
The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On Reset and RST Control
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AUDIO DATA INTERFACE
The PCM1804 interfaces the audio system through BCK/DSDL (pin 16), LRCK/DSDBCK (pin 17), and
DATA/DSDR (pin 15). The PCM1804 needs RST = low when in the interface mode and/or the data format are
changed.
INTERFACE MODE
The PCM1804 supports master mode and slave mode as interface modes, which are selected by S/M (pin 8) as
shown in Table 4. In master mode, the PCM1804 provides the timing of the serial audio data communications
between the PCM1804 and the digital audio processor or external circuit. While in slave mode, the PCM1804
receives the timing for data transfer from an external controller. Slave mode is not available for DSD.
Table 4. Interface Mode
S/M
MODE
Low
Master mode
High
Slave mode
DATA FORMAT
The PCM1804 supports four audio data formats in both master and slave modes, and these data formats are
selected by FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5.
Table 5. Data Format
FMT1
FMT0
MASTER
SLAVE
Low
Low
PCM, left-justified, 24-bit
FORMAT
Yes
Yes
Low
High
PCM, I2S, 24-bit
Yes
Yes
High
Low
PCM, standard, 24-bit
Yes
Yes
High
High
DSD
Yes
–
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INTERFACE TIMING FOR PCM
Figure 36 through Figure 38 illustrate the interface timing for PCM.
(1) Left-Justified Data Format; L-Channel = High, R-Channel = Low
1/fS
LRCK
L-Channel
R-Channel
BCK
DATA
1 2 3
22 23 24
1 2 3
22 23 24
1 2
(2) I2S Data Format; L-Channel = Low, R-Channel = High
1/fS
L-Channel
LRCK
R-Channel
BCK
1 2 3
DATA
22 23 24
1 2 3
22 23 24
1 2
(3) Standard Data Format; L-Channel = High, R-Channel = Low
1/fS
L-Channel
LRCK
R-Channel
BCK
DATA
22 23 24
1 2 3
22 23 24
1 2 3
22 23 24
T0009-03
NOTE: LRCK and BCK work as outputs in master mode and as inputs in slave mode.
Figure 36. Audio Data Format for PCM
22
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t(LRCP)
0.5 VDD
LRCK
tw(BCKL)
t(CKLR)
tw(BCKH)
0.5 VDD
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DATA
T0018-03
PARAMETERS
MIN
TYP
MAX
UNIT
(3)
t(BCKP)
BCK period
tw(BCKH)
BCK pulse duration, HIGH
32
1/(64 fS)
ns
tw(BCKL)
BCK pulse duration, LOW
32
ns
t(CKLR)
Delay time, BCK falling edge to LRCK valid
–5
t(LRCP)
LRCK period
t(CKDO)
Delay time, BCK falling edge to DATA valid
t(LRDO)
Delay time, LRCK edge to DATA valid
tr
Rising time of all signals(1)(2)
tf
Falling time of all signals(1)(2)
15
ns
–5
15
ns
–5
15
ns
10
ns
10
ns
1/fS
(1)
Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.
(2)
Load capacitance of all signals is 10 pF.
(3)
t(BCKP) is fixed at 1/(64 fS) in case of master mode.
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
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t(LRCP)
1.4 V
LRCK
tw(BCKL)
tw(BCKH)
t(LRSU)
t(LRHD)
1.4 V
BCK
t(CKDO)
t(BCKP)
t(LRDO)
0.5 VDD
DATA
T0017-03
PARAMETERS
MIN
TYP
1/(64 fS)
MAX
UNIT
t(BCKP)
BCK period
tw(BCKH)
BCK pulse duration, HIGH
32
1/(48 fS)
ns
tw(BCKL)
BCK pulse duration, LOW
32
ns
t(LRSU)
LRCK setup time to BCK rising edge
12
ns
t(LRHD)
LRCK hold time to BCK rising edge
12
t(LRCP)
LRCK period
t(CKDO)
Delay time, BCK falling edge to DATA valid
5
25
ns
t(LRDO)
Delay time, LRCK edge to DATA valid
5
25
ns
tr
Rising time of all signals(1)(2)
10
ns
tf
Falling time of all signals(1)(2)
10
ns
ns
1/fS
(1)
Rising and falling times are measured from 10% to 90% of IN/OUT signals swing.
(2)
Load capacitance of DATA/DSDR signal is 10 pF.
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
INTERFACE TIMING FOR DSD
Figure 39 and Figure 40 illustrate the interface timing for DSD.
DSDBCK
DSDL
Dn−3
Dn−2
Dn−1
Dn
Dn+1
Dn+2
Dn+3
DSDR
Dn−3
Dn−2
Dn−1
Dn
Dn+1
Dn+2
Dn+3
T0052−01
Figure 39. Audio Data Format
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tw(BCKH)
tw(BCKL)
t(CKDO)
DSDBCK
0.5 VDD
t(BCKP)
DSDL
DSDR
0.5 VDD
T0053−01
PARAMETERS
MIN
TYP
MAX
UNIT
t(BCKP)
DSDBCK period
354
ns
tw(BCKH)
DSDBCK pulse duration, HIGH
177
ns
tw(BCKL)
DSDBCK pulse duration, LOW
177
ns
t(CKDO)
Delay time DSDBCK falling edge to DSDL, DSDR valid
15
ns
tr
Rising time of all signals(1)(2)
10
ns
tf
Falling time of all signals(1)(2)
10
ns
–5
(1)
Rising and falling times are measured from 10% to 90% of IN/OUT signal swing.
(2)
Load capacitance of DSDBCK/DSDL/DSDR signal is 10 pF.
Figure 40. Audio Data Interface Timing for DSD (Master Mode Only)
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM FOR PCM
In slave mode, the PCM1804 operates under LRCK synchronized with the system clock SCKI. The PCM1804
does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of
LRCK and SCKI.
If the relationship between LRCK and SCKI changes more than ±6 BCK during one sample period due to LRCK
or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into BPZ code until
resynchronization between LRCK and SCKI is completed.
In case of changes less than ±5 BCK, resynchronization does not occur and the previously described digital
output control and discontinuity do not occur.
Figure 41 illustrates ADC digital output for loss of synchronization and resynchronization. During undefined data,
the PCM1804 may generate some noise in the audio signal. Also, the transitions of normal to undefined data and
undefined or zero data to normal cause a discontinuity of data on the digital output. This can generate noise in
the audio signal. In master mode, synchronization loss never occurs.
HIGH-PASS FILTER (HPF) BYPASS CONTROL FOR PCM
The built-in function for dc component rejection can be bypassed by BYPAS (pin 12) control. In bypass mode,
the dc component of the input analog signal and the internal dc offset are also converted and output in the digital
output data.
HPF Bypass Control
BYPAS PIN
HPF MODE
Low
Normal (high-pass) mode
High
Bypass (through) mode
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OVERFLOW FLAG FOR PCM
The PCM1804 has two overflow flag pins, OVFR (pin 20) and OVFL (pin 21). The pins go to high as soon as the
analog input goes across the full-scale range. The high level is held for 1.016 s at maximum, and returns to low if
the analog input does not go across the full-scale range for the period.
Synchronization Lost
State of Synchronization
Synchronous
Resynchronization
Asynchronous
Synchronous
1/fS
DATA(1)
Undefined
Data
Normal Data
90/fS
Zero Data
Converted Data(2)
T0020-06
(1)
Applies only for slave mode; the loss of synchronization never occurs in master mode.
(2)
The HPF transient response appears initially.
Figure 41. ADC Digital Output for Loss of Synchronization and Resynchronization
26
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PCM1804
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
TYPICAL CIRCUIT CONNECTION DIAGRAM
Figure 42 illustrates a typical circuit connection diagram in the PCM data format operation.
PCM1804
C1
+ 1
VREFL
VREFR
2
C3
AGNDL
AGNDR
VCOML
VCOMR
VINL+
VINR+
VINL−
VINR−
FMT0
AGND
FMT1
VCC
+ 3
4
+
L-Channel In
5
−
6
Format [1:0]
8
9
Control
10
Oversampling
Ratio [2:0]
11
12
13
3.3 V
S/M
OVFL
OSR0
OVFR
OSR1
RST
OSR2
SCKI
BYPAS
HPF Bypass
DGND
LRCK/DSDBCK
BCK/DSDL
C5
+ 14
27
C4
26 +
25
+
R-Channel In
24
−
23
7
Master/Slave
C2
28 +
C6
22
5V
+
21
20
Overflow
19
Reset
18
System Clock
17
L/R Clock
16
Audio Data
Processor
Data Clock
15
VDD
DATA/DSDR
Data Out
S0058-01
A.
C1, C2, C5, and C6: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum, depending on layout and power supply
B.
C3, C4: Bypass capacitor, 0.1-μF tantalum, depending on layout and power supply
Figure 42. Typical Circuit Connection Diagram for PCM
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PCM1804
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
Figure 43 illustrates a typical circuit connection diagram in the DSD data format operation.
PCM1804
C1
+ 1
VREFL
VREFR
2
AGNDL
C3
AGNDR
+ 3
VCOML
VCOMR
VINL+
VINR+
VINL−
VINR−
FMT0
AGND
FMT1
VCC
4
+
L-Channel In
5
−
6
Format [1:0]
8
9
Control
10
Oversampling
Ratio [2:0]
11
12
HPF Bypass
13
3.3 V
S/M
OVFL
OSR0
OVFR
OSR1
RST
OSR2
SCKI
BYPAS
DGND
LRCK/DSDBCK
BCK/DSDL
C5
+ 14
27
C4
26 +
25
+
R-Channel In
24
−
23
7
Master/Slave
C2
28 +
C6
22
5V
+
21
Overflow
20
19
Reset
18
System Clock
17
Data Clock
16
Audio Data
Processor
L-Channel Data Out
15
VDD
DATA/DSDR
R-Channel Data Out
S0058-02
A.
C1, C2, C5, and C6: Bypass capacitors, 0.1-μF ceramic and 10-μF tantalum, depending on layout and power supply
B.
C3 and C4: Bypass capacitors, 0.1-μF tantalum, depending on layout and power supply
Figure 43. Typical Circuit Connection Diagram for DSD
28
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PCM1804
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
VCC, VDD Pins
The digital and analog power supply lines to the PCM1804 should be bypassed to the corresponding ground pins
with 0.1-μF ceramic and 10-μF tantalum capacitors placed as close to the pins as possible to maximize the
dynamic performance of the ADC. Although the PCM1804 has two power lines to maximize the potential of
dynamic performance, using one common power supply is recommended to avoid unexpected power-supply
trouble like latch-up or power-supply sequence.
VIN Pins
Use of 0.01-μF film capacitors between VINL+ and VINL– and between VINR+ and VINR– is strongly
recommended to remove higher-frequency noise from the delta-sigma input section.
VREFX, VCOMX Inputs
Use 0.1-μF ceramic and 10-μF tantalum capacitors between VREFL, VREFR, and corresponding AGNDx, to ensure
low-source impedance at ADC references. Use 0.1-μF tantalum capacitors between VCOML, VCOMR and
corresponding AGNDx to ensure low source impedance of common voltage. These capacitors should be located
as close as possible to the VREFL, VREFR, VCOML, and VCOMR pins to reduce dynamic errors on references and
common voltage. The dc voltage level of these pins is 2.5 V.
DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK Pins
The DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins in master mode have large load drive capability.
Locating the buffer near the PCM1804 and minimizing the load capacitance, minimizes the digital-analog
crosstalk and maximizes the dynamic performance of the ADC.
System Clock
The quality of the system clock can influence dynamic performance, as the PCM1804 operates based on a
system clock. Therefore, it might be necessary to consider the system clock duty, jitter, and the time difference
between system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode.
Reset Control
If capacitors larger than 10 μF are used on VREFL and VREFR, an external reset control with a delay time
corresponding to the VREFL and VREFR response is required. Also, it works as a power-down control.
APPLICATION CIRCUIT FOR SINGLE-ENDED INPUT
An application diagram for a single-ended input circuit is shown in Figure 44. The maximum signal input voltage
and differential gain of this circuit is designed as Vinmax = 8.28 Vpp, Ad = 0.3. Differential gain (Ad) is given by
R3/R1(R4/R2) in a circuit configured as a normal inverted-gain amplifier. Resistor R5(R6) in the feedback loop
gives low-impedance drive operation and noise filtering for the analog input of the PCM1804. The circuit
technique using R5(R6) is recommended.
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PCM1804
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SLES022C – DECEMBER 2001 – REVISED OCTOBER 2007
R3 = 1 kΩ
C(1)
4.7 kΩ
4.7 kΩ
Analog In
_
10 µF
+
+
PCM1804
R1 = 3.3 kΩ
R5 = 47 Ω
_
VIN−
+
OPA2134 1/2
OPA2134 1/2
VCOM
0.01 µF
R4 = 1 kΩ
0.1 µF
C(1)
10 µF
R2 = 3.3 kΩ
R6 = 47 Ω
_
+
+
VIN+
OPA2134 1/2
S0059-01
(1)
A capacitor value of 1800 pF is recommended, unless an input signal greater than –6 dBFS at 100 kHz or higher is
applied in the DSD mode. In that case, 3300 pF is recommended.
Figure 44. Application Circuit for Single-Ended Input Circuit (PCM)
VIN+
∆Σ Modulator
VIN−
_
BGR
VCOM
VREF
+
_
+
S0060-01
Figure 45. Equivalent Circuit of Internal Reference (VCOM, VREF)
30
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCM1804DB
ACTIVE
SSOP
DB
28
47
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-10 to 70
PCM1804
Samples
PCM1804DBG4
ACTIVE
SSOP
DB
28
47
RoHS & Green
Call TI
Level-1-260C-UNLIM
-10 to 70
PCM1804
Samples
PCM1804DBR
ACTIVE
SSOP
DB
28
2000
RoHS & Green
Call TI | NIPDAU
Level-1-260C-UNLIM
-10 to 70
PCM1804
Samples
PCM1804DBRG4
ACTIVE
SSOP
DB
28
2000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-10 to 70
PCM1804
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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