PCM1807PWG4

          PCM1807 SLES147 – SEPTEMBER 2005 Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D Converter FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 Vp-p Oversampling Decimation Filter: – Oversampling Frequency: ×64 – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.91 Hz (48 kHz) High Performance: – THD+N: –93 dB (Typical) – SNR: 99 dB (Typical) – Dynamic Range: 99 dB (Typical) PCM Audio Interface With SPI Control: – Master/Slave Mode Selectable – Data Formats: 24-Bit Left-Justified, 24-Bit I2S Multiple Functions with SPI Control: – Power Down – Mute with Fade-Out and Fade-In – Polarity Control Analog Antialias LPF Included Sampling Rate: 16–96 kHz System Clock: 256 fS, 384 fS, 512 fS Dual Power Supplies: – 5-V for Analog – 3.3-V for Digital Package: 14-Pin TSSOP DVD Recorder Digital TV AV Amplifier/Receiver MD Player CD Recorder Multitrack Receiver Electric Musical Instrument DESCRIPTION The PCM1807 is high-performance, low-cost, single-chip stereo analog-to-digital converter with single-ended analog voltage input. The PCM1807 uses a delta-sigma modulator with 64-times oversampling and includes a digital decimation filter and high-pass filter that removes the dc component of the input signal. For various applications, the PCM1807 supports master and slave mode and two data formats in serial audio interface. The PCM1807 has many functions which are controlled through SPI serial-control port: power down, fade-in and fade-out, polarity control, etc. The PCM1807 is suitable for wide variety of cost-sensitive consumer applications where good performance and operation with a 5-V analog supply and 3.3-V digital supply is required. The PCM1807 is fabricated using a highly advanced CMOS process and is available in a small, 14-pin TSSOP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PCM1807 Analog supply voltage, VCC –0.3 V to 6.5 V Digital supply voltage, VDD –0.3 V to 4 V Ground voltage differences, AGND, DGND ±0.1 V Digital input voltage, LRCK, BCK, DOUT –0.3 V to (VDD + 0.3 V) < 4 V Digital input voltage, MD, MC, MS, SCKI –0.3 V to 6.5 V Analog input voltage, VINL, VINR, VREF –0.3 V to (VCC + 0.3 V) < 6.5 V ±10 mA Input current (any pins except supplies) Ambient temperature under bias, TA –40°C to 125°C Storage temperature, Tstg –55°C to 150°C Junction temperature, TJ 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (reflow, peak) (1) 260°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) Analog supply voltage, VCC Digital supply voltage, VDD Analog input voltage, full scale (–0 dB) MIN NOM MAX 4.5 5 5.5 2.7 3.3 3.6 VCC = 5 V 3 Digital input logic family Digital input clock frequency, system clock Digital input clock frequency, sampling clock 2 V V Vp-p TTL compatible 4.096 49.152 MHz 16 96 kHz 20 pF 85 °C Digital output load capacitance Operating free-air temperature, TA UNIT –40 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 24 UNIT Bits DATA FORMAT I2S, left-justified Audio data interface format Audio data bit length 24 Audio data format fS Sampling frequency System clock frequency Bits MSB-first, 2s complement 16 48 96 256 fS 4.096 12.288 24.576 384 fS 6.144 18.432 36.864 512 fS 8.192 24.576 49.152 kHz MHz INPUT LOGIC VIH (1) 2 VDD VIL (1) 0 0.8 2 5.5 VIH (2) (3) Input logic level VIL (2) (3) 0 IIH (2) IIL (2) IIH (1) (3) Input logic current IIL (1) (3) 0.8 VIN = VDD ±10 VIN = 0 V ±10 VIN = VDD VDC 65 100 µA ±10 VIN = 0 V OUTPUT LOGIC VOH (4) VOL (4) Output logic level IOUT = –4 mA 2.8 IOUT = 4 mA 0.5 VDC DC ACCURACY Gain mismatch, channel-to-channel ±1 ±3 % of FSR Gain error ±3 ±6 % of FSR –93 –87 DYNAMIC PERFORMANCE (5) VIN = –0.5 dB, fS = 48 kHz THD+N Total harmonic distortion + noise VIN = –0.5 dB, fS = 96 kHz S/N Signal-to-noise ratio Channel separation –87 VIN = –60 dB, fS = 48 kHz VIN = –60 dB, fS = 96 kHz Dynamic range (6) –37 (6) fS = 48 kHz, A-weighted fS = 96 kHz, A-weighted fS = 96 kHz, A-weighted fS = 48 kHz fS = 96 kHz –39 95 (6) fS = 48 kHz, A-weighted 99 101 95 (6) 99 101 93 (6) dB 97 91 dB dB dB ANALOG INPUT (1) (2) (3) (4) (5) (6) Input voltage 0.6 VCC Center voltage (VREF) 0.5 VCC Vp-p V Input impedance 60 kΩ Antialiasing filter frequency response –3 dB 1.3 MHz Pins 7, 8: LRCK, BCK (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, in slave mode) Pin 6: SCKI (Schmitt-trigger input, 5-V tolerant) Pins 10–12: MD, MC, MS (Schmitt-trigger input, with 50-kΩ typical pulldown resistor, 5-V tolerant) Pins 7–9: LRCK, BCK (in master mode), DOUT Analog performance specifications are tested using a System Two™ audio measurement system by Audio Precision™ with 400-Hz HPF and 20-kHz LPF in RMS mode. fS = 96 kHz, system clock = 256 fS. 3 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Stop band 0.583 fS ±0.05 Pass-band ripple Stop-band attenuation –65 Delay time dB dB 17.4/fS HPF frequency response –3 dB 0.019 fS/1000 POWER SUPPLY REQUIREMENTS VCC VDD Voltage range ICC Powered down Supply current (7) IDD 4.5 5 5.5 2.7 3.3 3.6 8.6 11 mA 8 mA (8) fS = 96 kHz 5.9 (9) Powered down 10.2 (8) Operatng, fS = 96 kHz Powered down mA µA 80 Operatng, fS = 48 kHz Power dissipation µA 1 fS = 48 kHz 62 (9) 81 77 (8) VDC mW µW 270 TEMPERATURE RANGE TA Operation temperature θJA Thermal resistance (7) (8) (9) 4 Minimum load on LRCK (pin 7), BCK (pin 8), DOUT (pin 9) By setting PDWN or SRST bit through serial control port. Halt SCKI, BCK, LRCK. fS = 96 kHz, system clock = 256 fS. –40 85 170 °C °C/W PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 PIN ASSIGNMENTS PW PACKAGE (TOP VIEW) VREF AGND VCC VDD DGND SCKI LRCK 1 2 3 4 5 6 7 VINR VINL MS MC MD DOUT BCK 14 13 12 11 10 9 8 P0032-01 TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION PIN AGND 2 – Analog GND BCK 8 I/O DGND 5 – Digital GND DOUT 9 O Audio data digital output LRCK 7 I/O Audio data latch enable input/output Audio data bit clock input/output (1) (1) (2) MC 11 I Mode control clock input MD 10 I Mode control data input MS 12 I Mode control select input SCKI 6 I System clock input; 256 fS, 384 fS or 512 fS (3) VCC 3 – Analog power supply, 5-V VDD 4 – Digital power supply, 3.3-V VINL 13 I Analog input, L-channel VINR 14 I Analog input, R-channel VREF 1 – Reference voltage decoupling (= 0.5 VCC) (1) (2) (3) (2) (2) Schmitt-trigger input with internal pulldown (50-kΩ, typical) Schmitt-trigger input with internal pulldown (50-kΩ, typical), 5-V tolerant Schmitt-trigger input, 5-V tolerant 5 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 Functional Block Diagram Antialias LPF VINL VREF Delta-Sigma Modulator BCK ×1/64 Decimation Filter with High-Pass Filter Reference Antialias LPF VINR DOUT MS Mode/ Format Control MC Delta-Sigma Modulator MD Clock and Timing Control Power Supply VCC LRCK Serial Interface AGND DGND SCKI VDD B0004-08 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DECIMATION FILTER FREQUENCY RESPONSE OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 50 0 −10 0 −20 Amplitude − dB Amplitude − dB −30 −50 −100 −40 −50 −60 −70 −150 −80 −90 −200 0 8 16 24 Normalized Frequency [× fS] Figure 1. 6 32 G001 −100 0.00 0.25 0.50 0.75 Normalized Frequency [× fS] Figure 2. 1.00 G002 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DECIMATION FILTER FREQUENCY RESPONSE (Continued) PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 –4.13 dB at 0.5 fS −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency [× fS] −10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 0.6 Normalized Frequency [× fS] G003 Figure 3. G004 Figure 4. HIGH-PASS FILTER FREQUENCY RESPONSE HPF STOP-BAND CHARACTERISTICS HPF PASS-BAND CHARACTERISTICS 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 Normalized Frequency [× fS/1000] Figure 5. 0.4 G005 0 1 2 3 Normalized Frequency [× fS/1000] 4 G006 Figure 6. 7 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs TEMPERATURE −87 105 −88 104 −89 103 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − dB THD+N vs TEMPERATURE −90 −91 −92 −93 −94 −95 −96 −97 −50 −25 0 25 50 75 100 99 SNR 97 −25 0 25 50 75 TA − Free-Air Temperature − °C G007 Figure 7. Figure 8. THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE −87 105 −88 104 −89 103 −90 −91 −92 −93 −94 −95 −96 −97 4.25 Dynamic Range 98 95 −50 100 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − dB 101 96 TA − Free-Air Temperature − °C 100 G008 102 101 100 Dynamic Range 99 SNR 98 97 96 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V Figure 9. 8 102 5.50 5.75 G009 95 4.25 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V Figure 10. 5.50 5.75 G010 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs fSAMPLE CONDITION −87 105 −88 104 −89 103 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − dB THD+N vs fSAMPLE CONDITION −90 −91 −92 −93 −94 −95 Dynamic Range SNR 102 101 100 99 98 97 (1) System (1) System Clock = 384 fS (2) System Clock = 512 f S (3) System Clock = 256 f S −96 −97 Clock = 384 fS System Clock = 512 fS (3) System Clock = 256 f S (2) 96 95 44.1(1) 48(2) 96(3) fSAMPLE Condition − kHz 44.1(1) 48(2) 96(3) fSAMPLE Condition − kHz G011 Figure 11. Figure 12. OUTPUT SPECTRUM (–0.5 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192) G012 OUTPUT SPECTRUM 0 0 Input Level = −60 dB Data Points = 8192 −20 −20 −40 −40 Amplitude − dB Amplitude − dB Input Level = −0.5 dB Data Points = 8192 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 f − Frequency − kHz G013 Figure 13. 0 5 10 15 20 f − Frequency − kHz G014 Figure 14. 9 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. OUTPUT SPECTRUM (Continued) THD+N − Total Harmonic Distortion + Noise − dB THD+N vs SIGNAL LEVEL 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G015 Figure 15. SUPPLY CURRENT SUPPLY CURRENT vs fSAMPLE CONDITION 15 ICC and IDD − Supply Current − mA ICC IDD 10 5 (1) System Clock = 384 fS System Clock = 512 fS (3) System Clock = 256 f S (2) 0 44.1(1) 48(2) 96(3) fSAMPLE Condition − kHz G016 Figure 16. 10 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SYSTEM CLOCK The PCM1807 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 6). The PCM1807 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode. In master mode, the system clock frequency must be controlled through the serial control port, which uses MD (pin 10), MC (pin 11), and MS (pin 12). The system clock is divided down automatically to generate frequencies of 128 fS and 64 fS, which are used to operate the digital filter and the delta-sigma modulator, respectively. Table 1 shows some typical relationships between sampling frequency and system clock frequency, and Figure 17 shows system clock timing. Table 1. Sampling Frequency and System Clock Frequency SAMPLING FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (fSCLK) (MHz) 256 fS 384 fS 16 4.096 6.144 8.192 32 8.192 12.288 16.384 44.1 11.2896 16.9344 22.5792 48 12.288 18.432 24.576 64 16.384 24.576 32.768 88.2 22.5792 33.8688 45.1584 96 24.576 36.864 49.152 tw(SCKH) 512 fS tw(SCKL) SCKI 2V SCKI 0.8 V T0005B07 SYMBOL PARAMETER MIN MAX UNIT tw(SCKH) System clock pulse duration, HIGH 8 ns tw(SCKL) System clock pulse duration, LOW 8 ns Figure 17. System Clock Timing FADE-IN AND FADE-OUT FUNCTIONS The PCM1807 has fade-in and fade-out functions on DOUT (pin 9) to avoid pop noise, and the functions come into operation in some cases as described in several following sections. The level changes from 0 dB to mute or mute to 0 dB are performed using calculated pseudo S-shaped characteristics with zero-cross detection. Because of the zero-cross detection, the time needed for the fade in and fade out depends on the analog input frequency (fin). It takes 48/fin until processing is completed. If there is no zero cross during 8192/fS, DOUT is faded in or out by force during 48/fS (TIME OUT). Figure 18 illustrates the fade-in and fade-out operation processing. 11 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 Fade-Out Start Fade-In Complete Fade-In Start DOUT (Contents) Fade-Out Complete BPZ 48/fin or 48/fS 48/fin or 48/fS T0080-01 Figure 18. Fade-In and Fade-Out Operations POWER ON The PCM1807 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts after VDD > 2.2 V (typical), the PCM1807 stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset state is released and the time of 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the data corresponding to the analog input signal is obtained. Figure 19 illustrates the power-on timing and the digital output. VDD 2.6 V 2.2 V 1.8 V Reset Reset Release Internal Reset Operation 1024 System Clocks 8960/fS System Clock DOUT Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) 48/fin or 48/fS T0014-09 Figure 19. Power-On Timing 12 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 CLOCK-HALT RESET FUNCTIONS The PCM1807 has a reset function, which is triggered by halting SCKI (pin 6) in both master and slave modes. The function is available anytime after power on. Reset and power down are performed automatically 4 µs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1807 stays in the reset and power-down mode, and DOUT is forced to zero. Also, all registers except the mode control registers are reset once. If minimization of power dissipation is required, the PDWN bit must be set to HIGH prior to halting SCKI through the serial control port as described in the SPI Serial Control Port for Mode Control section. SCKI must be supplied to release the reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024 SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset timing. To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI, SCKI should be masked until the synchronization is formed again, taking care of glitch and jitter. See the typical circuit connection diagram, Figure 31 To avoid ADC performance degradation, the clock-halt reset also should be asserted when fS, SCKI, MD[1:0], FMT bits, etc., are changed on the fly. SCKI Halt SCKI Resume Fixed to Low or High SCKI t(CKR) Reset: t(RST) Clock-Halt Reset Internal Reset DOUT Reset Release: t(REL) Operation Operation Normal Data Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) Normal Data 48/fin or 48/fS T0081-01 SYMBOL PARAMETER MIN MAX UNIT µs t(CKR) Delay time from SCKI halt to internal reset 4 t(RST) Delay time from SCKI resume to reset release 1024 SCKI µs t(REL) Delay time from reset release to DOUT output 8960/fS µs Figure 20. Clock-Halt Reset Timing 13 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SERIAL AUDIO DATA INTERFACE The PCM1807 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9). INTERFACE MODE The PCM1807 supports master mode and slave mode as interface modes, which are selected by MD1 and MD0. MD1 and MD0 are controlled through the serial control port as shown in Table 2. In master mode, the PCM1807 provides the timing of serial audio data communications between the PCM1807 and the digital audio processor or external circuit. While in slave mode, the PCM1807 receives the timing for data transfer from an external controller. Table 2. Interface Modes MD1 MD0 INTERFACE MODE 0 0 Slave mode (256 fS, 384 fS, 512 fS autodetection) (default) 0 1 Master mode (512 fS) 1 0 Master mode (384 fS) 1 1 Master mode (256 fS) Master mode In master mode, BCK and LRCK work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1807. The frequency of BCK is fixed at 64 BCK/frame. Slave mode In slave mode, BCK and LRCK work as input pins. The PCM1807 accepts 64 BCK/frame or 48 BCK/frame format (only for a 384 fS system clock), not 32 BCK/frame format. DATA FORMAT The PCM1807 supports two audio data formats in both master and slave modes. The data formats are selected by FMT, which is controlled through the serial control port as shown in Table 3. Figure 21 illustrates the data formats in slave mode and master mode. Table 3. Data Format FORMAT NO. 14 FMT FORMAT 0 0 I2S, 1 1 Left-justified, 24-bit 24-bit (default) PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 FORMAT 0: FMT = 0 24-Bit, MSB-First, I2S Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB FORMAT 1: FMT = 1 24-Bit, MSB-First, Left-Justified Left-Channel LRCK Right-Channel BCK DOUT 1 2 MSB 3 22 23 24 LSB 1 2 MSB 3 22 23 24 1 LSB T0016-14 Figure 21. Audio Data Format (LRCK and BCK Work as Inputs in Slave Mode and as Outputs in Master Mode) 15 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 INTERFACE TIMING Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively. t(LRCP) 1.4 V LRCK t(BCKL) t(BCKH) t(LRSU) t(LRHD) 1.4 V BCK t(BCKP) t(CKDO) t(LRDO) 0.5 VDD DOUT T0017-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) t(BCKL) t(LRSU) MIN TYP MAX UNIT 1/(64 fS) ns BCK pulse duration, HIGH 1.5 × tSCKI ns BCK pulse duration, LOW 1.5 × tSCKI ns LRCK setup time to BCK rising edge 50 ns t(LRHD) LRCK hold time to BCK rising edge 10 ns t(LRCP) LRCK period 10 t(CKDO) Delay time, BCK falling edge to DOUT valid –10 40 ns t(LRDO) Delay time, LRCK edge to DOUT valid –10 40 ns µs NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of DOUT is 20 pF. tSCKI is the SCKI period. Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs) 16 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(BCKP) t(CKDO) t(LRDO) 0.5 VDD DOUT T0018-02 MIN TYP MAX UNIT t(BCKP) SYMBOL BCK period PARAMETER 150 1/(64 fS) 1000 ns t(BCKH) BCK pulse duration, HIGH 65 600 ns t(BCKL) BCK pulse duration, LOW 65 600 ns t(CKLR) Delay time, BCK falling edge to LRCK valid –10 20 ns t(LRCP) LRCK period 10 65 µs t(CKDO) Delay time, BCK falling edge to DOUT valid –10 20 ns t(LRDO) Delay time, LRCK edge to DOUT valid –10 20 ns 1/fS NOTE: Timing measurement reference level is 0.5 VDD. Load capacitance of all signals is 20 pF. Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs) 1.4 V SCKI t(SCKBCK) t(SCKBCK) 0.5 VDD BCK T0074-01 SYMBOL t(SCKBCK) PARAMETER Delay time, SCKI rising edge to BCK edge MIN 5 TYP MAX UNIT 30 ns NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This timing is applied when SCKI frequency is less than 25 MHz. Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output) 17 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1807 operates under LRCK, synchronized with system clock SCKI. The PCM1807 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is established. In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does not occur and the previously described digital output control and discontinuity do not occur. Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, the PCM1807 can generate some noise in the audio signal. Also, the transition of normal data to undefined data creates a discontinuity in the digital output data, which can generate some noise in audio signal. The digital output is valid after resynchronization completes and the time of 32/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the operation stops and DOUT is forced to zero data immediately. The fade-in operation resumes from mute after the time of 32/fS following resynchronization. It is recommended to set the PDWN bit to HIGH once through the serial control port to get stable analog performance when the sampling rate, interface mode, or data format is changed. Resynchronization Resynchronization Synchronization Lost State of Synchronization Synchronous Asynchronous 1/fS DOUT Normal Data Synchronization Lost Synchronous Asynchronous Synchronous 32/fS Undefined Data Zero Data Normal Data Zero Data Normal Data Fade-In Complete Fade-In Start DOUT BPZ (Contents) Fade-In Restart Normal Data 32/fS 48/fin or 48/fS 48/fin or 48/fS T0082-01 Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization 18 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 FUNCTION CONTROL The PCM1807 has the following functions which can be controlled through the serial control port. When the LRCK (fS), SCKI, MD[1:0], or FMT bit is changed on the fly, a clock-halt reset or an immediate reset by PDWN or SRST via the serial control port is recommended to obtain stable analog performance. MUTE The MUTE bit controls fade-in and fade-out operation for DOUT. When the MUTE bit is set from 0 to 1, the fade-out operation provides step-down digital attenuation to prevent a pop noise. When the MUTE bit is set from 1 to 0, the fade-in operation provides a step-up digital gain to prevent a pop noise. The digital output of DOUT behaves as shown in Figure 18. Table 4. Mute On/Off Control MUTE MUTE CONTROL 0 Normal operation (default) 1 Mute on POLARITY CONTROL By setting PREV = 1, the PCM1807 inverts the data on DOUT relative to that of the analog signal on VINL/VINR (pin 13/pin 14). Because the inversion occurs immediately after the PREV bit changes, pop noise can be generated at the change. It is recommended that MUTE or PDWN be asserted before using PREV. Table 5. Polarity Control PREV POLARITY CONTROL 0 Normal operation (default) 1 Invert MODE CONTROL REGISTER RESET The MRST bit is used to reset the mode control register to the default setting. Table 6. Mode Control Register Reset MRST MODE CONTROL REGISTER RESET 0 Set default value 1 Normal operation (default) 19 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 POWER DOWN The PDWN bit controls the operation of the PCM1807. During power-down mode, both supply current for the analog section and clock signal for the digital section are shut down, and DOUT is forced to zero. Also, all registers except the mode control registers are reset once. The PCM1807 minimizes power dissipation during the power-down mode. When the PCM1807 takes power down or power up, fade-out or fade-in which is shown in Figure 18 is asserted, respectively. The system clock must be input until the fade-out process completes and prior to PDWN deassertion. The digital output is valid after the reset state is released and the time of 1024 SCKI + 8960/fS has elapsed. Because the fade-in operation is processed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. Figure 26 illustrates DOUT behavior on the power-down and power-up sequence by PDWN. PDWN SCKI Reset: t(RST) Reset Release: t(REL) Internal Reset Operation DOUT Normal Data Zero Data Normal Data Fade-In Complete Fade-Out Start Fade-Out Complete Fade-In Start Normal Data DOUT BPZ (Contents) 48/fin or 48/fS 48/fin or 48/fS T0083-01 SYMBOL PARAMETER MIN MAX UNIT t(RST) Delay time from SCKI resume to reset release 1024 SCKI µs t(REL) Delay time from reset release to DOUT output 8960/fS µs Figure 26. Power Up/Power Down Sequence by PDWN Table 7. Power-Down Control PDWN 20 POWER DOWN 0 Normal operation (default) 1 Power-down mode PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SYSTEM RESET The SRST bit controls the entire ADC operation except fade-out. DOUT is forced to zero immediately and the PCM1807 goes into power-down state. Also, all registers except the mode control register are reset once. The PCM1807 minimizes power dissipation during the power-down state. When the PCM1807 powers up, the digital output is valid after the reset state is released and the time of 1024 SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. Figure 27 illustrates DOUT behavior during the power-down and power-up sequences by SRST. SRST SCKI Reset: t(RST) Reset Release: t(REL) Internal Reset DOUT Normal Data Zero Data Normal Data Fade-In Complete Fade-In Start Normal Data DOUT BPZ (Contents) 48/fin or 48/fS T0084-01 MAX UNIT t(RST) SYMBOL Delay time from SCKI resume to reset release PARAMETER MIN 1024 SCKI µs t(REL) Delay time from reset release to DOUT output 8960/fS µs Figure 27. Power-Up/Power-Down Sequence by SRST Table 8. System Reset Control SRST SYSTEM RESET 0 System reset 1 Normal operation (default) 21 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SPI SERIAL CONTROL PORT FOR MODE CONTROL The user-programmable built-in functions of the PCM1807 can be controlled through the serial control port with SPI format. All operations for the serial control port use 16-bit data words. Figure 28 shows the control data word format. The most-significant bit must be set to 0. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operations. The least-significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 29 shows the functional timing diagram for writing to the serial control port. MS (pin 12) is held at a logic-1 state until a register is to be written. To start the register write cycle, MS is set to logic-0. Sixteen clocks are then provided on MC (pin 11), corresponding to the 16 bits of the control data word on MD (pin 10). After the 16th clock cycle has completed, the data is latched into the indexed-mode control register in the write operation. To write subsequent data, MS must be set to 1 once. LSB MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 Register Index (or Address) D3 D2 D1 D0 Register Data R0001-01 Figure 28. Control Data Word Format for MD MS MC MD X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X 0 IDX6 T0048-03 Figure 29. Serial Control Format 22 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 CONTROL INTERFACE TIMING REQUIREMENTS Figure 30 illustrates a detailed timing diagram for the serial control port. These timing parameters are critical for proper control port operation. t(MHH) MS 1.4 V t(MSS) t(MCL) t(MCH) t(MSH) MC 1.4 V t(MCY) LSB MD 1.4 V t(MDS) t(MDH) T0013-06 SYMBOL PARAMETER MIN MAX UNIT t(MCY) MC pulse cycle time 100 ns t(MCL) MC low-level time 40 ns t(MCH) MC high-level time 40 ns t(MHH) MS high-level time tMCY ns t(MSS) MS falling edge to MC rising edge 15 ns t(MSH) MS hold time (1) 15 ns t(MDH) MD hold time 15 ns t(MDS) MD setup time 15 ns (1) MC rising edge to MS rising edge for the MC pulse corresponding to the LSB of MD Figure 30. Control Interface Timing 23 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 MODE CONTROL REGISTER The user-programmable mode control functions and the mode control register bit map are shown in Table 9 and Table 10. Table 9. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER BIT(S) Mode control register reset Normal operation 49 MRST System reset Normal operation 49 SRST Audio interface mode control Slave mode 49 MD[1:0] Audio interface format control I2S, 24-bit 49 FMT Power-down control Normal operation 49 PDWN DOUT data polarity selection Normal operation 49 PREV DOUT data mute control Normal operation 49 MUTE Table 10. Mode Control Register Bit Map IDX (B14–B8) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 31h 49 0 0 1 1 0 0 0 1 MRST SRST MD1 MD0 FMT PDWN PREV MUTE 24 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 31 is typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog inputs, VINL and VINR. If the performance of these filters is not adequate for an application, appropriate external antialiasing filters are needed. A passive RC filter (100 Ω and 0.01 µF to 1 kΩ and 1000 pF) generally is used. PCM1807 C5(3) C4(2) 4 µs (min) 5V 3.3 V Mask PLL170x X1(4) C3(2) + + (5) + 1 VREF 2 AGND 3 VINR 14 VINL 13 VCC MS 12 4 VDD MC 11 5 DGND MD 10 6 SCKI DOUT 9 7 LRCK BCK 8 + C1(1) + C2(1) R-ch IN L-ch IN MCU DSP or Audio Processor S0113-01 (1) C1, C2: A 1-µF electrolytic capacitor gives 2.7 Hz (τ = 1 µF × 60 kΩ) cutoff frequency for the input HPF in normal operation and requires a power-on settling time with a 60-ms time constant in the power-on initialization period. (2) C3, C4: Bypass capacitors, 0.1-µF ceramic and 10-µF electrolytic, depending on layout and power supply (3) C5: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended. (4) X1: X1 masks the system clock input when using the clock-halt reset function with external control. (5) Optional external antialiasing filter could be required, depending on the application. Figure 31. Typical Circuit Connection Diagram BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD PINS The digital and analog power supply lines to the PCM1807 should be bypassed to the corresponding ground pins with both 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC. AGND, DGND PINS To maximize the dynamic performance of the PCM1807, the analog and digital grounds are not internally connected. These grounds should have low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the PCM1807 package to reduce potential noise problems. VINL, VINR PINS VINL and VINR are single-ended inputs. The antialias low-pass filters are integrated on these inputs to remove the noise outside the audio band. If the performance of these filters is not adequate for an application, appropriate external antialiasing filters are required. A passive RC filter (100 Ω and 0.01 µF to 1 kΩ and 1000 pF) is generally used. 25 PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 APPLICATION INFORMATION (continued) VREF PIN To ensure low source impedance of the ADC references, 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF pin to reduce dynamic errors on the ADC references. DOUT PIN The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the PCM1807 and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and maximize the dynamic performance of the ADC. SYSTEM CLOCK The quality of the system clock can influence dynamic performance, as the PCM1807 operates based on a system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference between system clock transition and BCK or LRCK transition in slave mode. 26 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PCM1807PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1807 PCM1807PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1807 PCM1807PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCM1807 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of