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PCM2702

PCM2702

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

  • 描述:

    PCM2702 - 16-Bit Stereo DIGITAL-TO-ANALOG CONVERTER with Interface - Burr-Brown Corporation

  • 数据手册
  • 价格&库存
PCM2702 数据手册
® PCM 270 2 PCM2702 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit Stereo DIGITAL-TO-ANALOG CONVERTER with Interface FEATURES q INTEGRATED USB INTERFACE: Full-Speed Transceiver Supports 12Mbps Data Transfer. Fully Compliant with the USB 1.0 Specification. Adaptive Mode for Isochronous Transfer. Self-Powered Device. q ACCEPTS 16-BIT STEREO AND MONO USB AUDIO DATA STREAMS. q ANALOG PERFORMANCE (VCC = 5V): Dynamic Range: 100dB (typ at 16-bit) SNR: 105dB (typ) THD+N: 0.002% (typ at 16-bit) Full-Scale Output: 3.1Vp-p q 8X OVERSAMPLING DIGITAL FILTER: Passband: 0.454fS Stopband: 0.546fS Passband Ripple: ±0.002dB Stopband Attenuation: –82dB q SAMPLING RATE (FS): 32kHz, 44.1kHz, 48kHz q ON-CHIP CLOCK GENERATOR WITH SINGLE 12MHz CLOCK SOURCE q MULTI-FUNCTIONS: Digital Attenuator: 0dB to –64dB, 1dB/step Soft Mute Zero Flag Suspend Flag Playback Flag q DUAL POWER SUPPLIES: +5V for Analog portion +3.3V for Digital portion q PACKAGE: SSOP-28 APPLICATIONS q q q q STAND-ALONE USB AUDIO SPEAKERS CRT/LCD INTEGRATED USB AUDIO SPEAKERS USB AUDIO AMPLIFIERS OTHER USB AUDIO APPLICATIONS DESCRIPTION The PCM2702 is a single chip digital-to-analog converter offering two D/A output channels and an integrated USB 1.0 compliant interface controller. The newly developed SpAct™ (Sampling Period Adaptive Controlled Tracking) system recovers a stable, lowjitter clock for internal PLL and DAC operation from the USB interface audio data. The PCM2702 is based upon Burr-Brown’s Enhanced Multi-level Delta-Sigma Modulator, an 8x oversampling digital interpolation filter, and an analog output low-pass filter. The PCM2702 can accept a 48kHz, 44.1kHz and 32kHz sampling rates, using either 16-bit stereo or monaural audio data. Digital attenuation and softmute features are included, and are controlled via USB audio class request. Patents Pending. SpAct™ is a trademark of Burr-Brown Corporation. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 2000 Burr-Brown Corporation 1 PDS-1584A Printed in U.S.A. PCM2702 May, 2000 SPECIFICATIONS At TA = +25°C, VCC = VCCL = VCCR = VCCP = 5.0V, VDD = VDDC = 3.3V, fS = 44.1MHz, signal frequency = 1kHz and 16-bit data, unless otherwise specified. PCM2702E PARAMETER RESOLUTION HOST INTERFACE DIGITAL FORMAT Audio Data Format Audio Data Bit Length Audio Data Channel Sampling Frequency (fS) DIGITAL INPUT/OUTPUT Input Logic Level VIH(1) VIL(1) VIH(2) VIL(2) IIH(1) IIL(1) IIH(2) IIL(2) VOH(3) VOL(3) 2.0 0.8 0.7 VDD VIN = VDD VIN = 0V VIN = VDD VIN = 0V IOH = –1mA IOL = +1mA +65 0.7 VDD +100 ±10 ±10 ±10 0.5 0.002 1.2 100 105 103 ±1.0 ±1.0 ±30 62% of VCC 50% of VCC 5 0.454fS 0.490fS 0.546fS Stopband = 0.546fS Stopband = 0.567fS –75 –82 34/fS at 20kHz ≠0.02 +3.3 +5.0 22 18 165 +3.6 +5.5 30 25 225 70 +125 100 11 ±0.002 dB dB dB s dB VDC VDC mA mA mW °C °C °C/W 0.005 CONDITIONS MIN TYP 16 Supports USB revision 1.0, Full Speed USB ISOCHRONOUS OUT 16 1, 2 32, 44.1, 48 VDC VDC VDC VDC µA µA µA µA VDC VDC % % dB dB dB % of FSR % of FSR mV Vp-p VDC kΩ MAX UNITS Bits Input Logic Current Output Logic Level DYNAMIC THD+N at VOUT = 0dB THD+N at VOUT = –60dB Dynamic Range SIgnal-to-Noise Ratio Channel Seperation PERFORMANCE(4) 2.8 EIAJ, A-Weighted EIAJ, A-Weighted 96 100 98 DC ACCURACY Gain Error Gain Mismatch, Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Passband Passband Stopband Passband Ripple Stopband Attenuation Stopband Attenuation Delay Time ANALOG FILTER PERFORMANCE Frequency Response VOUT = 0.5 VCC at BPZ Full-Scale(–0dB) AC-Load ±0.002dB –3dB ±3.0 ±3.0 ±60 POWER SUPPLY REQUIREMENTS Voltage Range VDD, VDDC +3.0 VCC, VCCL, VCCR, VCCP +4.5 Supply Current IDD VDD = VDDC = 3.3V ICC VCC = VCCL = VCCR = VCCP = 5.0V Power Dissipation VDD = VDDC = 3.3V, and VCC = VCCL = VCCR = VCCP = 5.0V TEMPERATURE RANGE Operation Temperature Storage Temperature Thermal Resistance, θJA 0 –55 SSOP-28 NOTES: (1) Pins 8, 13, 14, 15, 16: VBUS, TEST3 TEST2 TEST1, TEST0. (2) Pin1: XTI. (3) Pins 10, 11, 12, 28: PLYBCK, SSPND, ZERO, XTO. (4) The dynamic performance is based upon ideal host signal quality, and may vary according to the system. Dynamic performance specifications are tested using a Shibasoku #725 THD Meter with 400Hz HPF, 30kHz LPF, Average Mode, and 20kHz Bandwidth limiting. The load connected to the analog output is 5kΩ, or larger, via AC coupling. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM2702 2 Top View SSOP PIN 1 2 3 4 5 6 7 8 NAME XTI VDDC TYPE IN — DESCRIPTIONS Crystal Oscillator Input.(1) Digital Power Supply for Clock Generator, +3.3V. Digital Ground for Clock Generator. Digital Power Supply, +3.3V. Digital Ground. USB Differential Input/Output Plus. USB Differential Input/Output Minus. USB Bus Power (this pin NEVER consumes USB bus power).(2) Digital Ground for USB Transceiver. Playback flag, active LOW (LOW: playback, HIGH: idle). Suspend flag, active LOW (LOW: suspend, HIGH: operational). Zero flag (LOW: Normal, HIGH: ZERO.) Test pin 3. Connect to digital ground.(2) Test pin 2. Connect to digital ground.(2) Test pin 1. Connect to digital ground.(2) Test pin 0. Connect to digital ground.(2) Analog Supply for R-channel, +5V. Analog Ground for R-channel. Analog Output for R-channel. Analog Ground. DC Common-Mode Voltage for DAC. Analog Supply, +5V. Analog Output for L-channel. Analog Ground for L-channel. Analog Supply for L-channel, +5V. Analog Ground for PLL. Analog Supply for PLL, +5V. Crystal Oscillator Output. XTI VDDC DGNDC VDD DGND D+ D– VBUS DGNDU 1 2 3 4 5 6 7 PCM2702 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XTO VCCP AGNDP VCCL AGNDL VOUTL VCC VCOM AGND VOUTR AGNDR VCCR TEST0 TEST1 DGNDC — VDD — DGND — D+ IN/OUT D– IN/OUT VBUS IN — OUT OUT OUT IN IN IN IN — — OUT — — — OUT — — — — OUT 9 DGNDU 10 PLYBCK 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SSPND ZERO TEST3 TEST2 TEST1 TEST0 VCCR AGNDR VOUTR AGND VCOM VCC VOUTL AGNDL VCCL AGNDP VCCP XTO PLYBCK 10 SSPND 11 ZERO 12 TEST3 13 TEST2 14 NOTES: (1) 3.3 V tolerant. (2) Schmitt trigger input with internal pull-down, 5V tolerant. ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage(2) .............................................................................................................. +6.5V Supply Voltage(3) .............................................................................................................. +4.0V Supply Voltage Differences(4) .................................................................................. ±0.1V Supply Voltage Differences(5) .................................................................................. ±0.1V Ground Voltage Differences(6) ................................................................................. ±0.1V Digital Input Voltage(7) ................................................................. –0.3V to VDD + 0.3V Digital Input Voltage(8) ................................................................................ –0.3V to 6.5V Analog Input Voltage ................................................ –0.3V to VCC + 0.3V Input Current (any pins except supplies) ....................................... ±10mA Operating Temperature .................................................. –25°C to +85°C Storage Temperature ..................................................... –55°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 5s) ................................................. +260°C Package Temperature (IR reflow, peak, 10s) ............................... +235°C NOTES: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. (2) VCC, VCCL, VCCR, VDDP. (3) VDD, VDDC. (4) Among VCC, VCCL, VCCR, VCCP. (5) Among VDD, VDDC. (6) Among AGND, AGNDL, AGNDR, AGNDP, DGND, DGNDC, and DGNDU. (7) XTI, D+, D–, PLYBCK, SSPND, ZERO, XTO. (8) VBUS, TEST#, TEST2, TEST1, TEST0. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER 324 SPECIFIED TEMPERATURE RANGE 0°C to +70°C PACKAGE MARKING PCM2702E ORDERING NUMBER(1) PCM2702E PCM2702E/2K TRANSPORT MEDIA Rails Tape and Reel PRODUCT PCM2702E PACKAGE SSOP-28 " " " " " NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM2702E/2K” will get a single 2000-piece Tape and Reel. ® 3 PCM2702 BLOCK DIAGRAM PLYBCK AGNDL D+ D– VBUS DGNDU mclk USB I/F USB Packet Data FIFO wrclk Audio Data 8x Oversampling Digital Filter MultiLevel DeltaSigma Modulator VCCR VCCL AGNDR SSPND ZERO DAC Low-Pass Filter VOUTL VCOM DAC Low-Pass Filter VOUTR rdclk System Clock VDDC DGNDC USB Clock Generator SpAct™ Audio Clock Generator Crystal OSC Power Supply XTI XTO VDDP DGNDP VCC AGND VDD DGND ® PCM2702 4 TYPICAL PERFORMANCE CURVES All specifications at TA = +25°C, VCC = VCCL = VCCR = VCCP = 5.0V, VDD = VDDC = 3.3V, fS = 44.1MHz, signal frequency = 1kHz and 16-bit data, unless otherwise specified. DIGITAL FILTER PERFORMANCE FREQUENCY RESPONSE 0 –20 –40 –60 PASSBAND RIPPLE 0.003 0.002 0.001 (dB) (dB) –80 –100 –120 –140 –160 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (x fS) 0 –0.001 –0.002 –0.003 0 0.1 0.2 0.3 0.4 0.5 Frequency (x fS) ANALOG FILTER PERFORMANCE ANALOG FILTER PERFORMANCE (100MHz-10Hz) 10 0 –10 –20 –30 –40 –50 –60 100 1k 10k 100k 1M 10M Frequency (Hz) 1 0 –1 –2 –3 –4 –5 –6 100 1k 10k Frequency (Hz) 100k 1M ANALOG FILTER PERFORMANCE (100MHz-1MHz) Response (dB) Response (dB) ® 5 PCM2702 TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25°C, VCC = VCCL = VCCR = VCCP = 5.0V, VDD = VDDC = 3.3V, fS = 44.1MHz, signal frequency = 1kHz and 16-bit data, unless otherwise specified. ANALOG DYNAMIC PERFORMANCE THD+N (0dB) vs TA 0.003 106 DYNAMIC RANGE vs TA 104 Dynamic Range (dB) THD+N (0dB) (%) 102 0.002 100 98 0.001 –10 0 10 20 30 40 50 60 70 80 96 –10 0 10 20 30 40 50 60 70 80 TA (°C) TA (°C) SOUND-TO-NOISE RATIO vs TA 110 108 CHANNEL SEPARATION vs TA 106 Channel Separation (dB) 0 10 20 30 40 50 60 70 80 108 106 SNR (dB) 104 104 102 102 100 100 –10 98 –10 0 10 20 30 40 50 60 70 80 TA (°C) TA (°C) THD+N (0dB) vs VCC 0.003 106 DYNAMIC RANGE vs VCC 104 Dynamic Range (dB) THD+N (0dB) (%) 102 0.002 100 98 0.001 4.25 4.5 4.75 5.0 VCC (V) 5.25 5.5 5.75 96 4.25 4.5 4.75 5.0 VCC (V) 5.25 5.5 5.75 ® PCM2702 6 TYPICAL PERFORMANCE CURVES (Cont.) All specifications at TA = +25°C, VCC = VCCL = VCCR = VCCP = 5.0V, VDD = VDDC = 3.3V, fS = 44.1MHz, signal frequency = 1kHz and 16-bit data, unless otherwise specified. SOUND-TO-NOISE RATIO vs VCC 110 108 CHANNEL SEPEARATION vs VCC 106 Channel Separation (dB) 108 106 SNR (dB) 104 104 102 102 100 100 4.25 4.5 4.75 5.0 VCC (V) 5.25 5.5 5.75 98 4.25 4.5 4.75 5.0 VCC (V) 5.25 5.5 5.75 ® 7 PCM2702 THEORY OF OPERATION USB INTERFACE The description of the USB interface complies with Universal Serial Bus specification Rev. 1.0. Control and audio data are both transferred to the PCM2702 via D+ (pin 6) and D– (pin 7). All data to/from the PCM2702 are transferred at full-speed. VBUS (pin 8) and DGNDU (pin 9) are also connected to the USB bus. VBUS (pin 8) never consumes USB bus power, it is used only for detecting the connection of the USB bus. The following information is provided in the device descriptor. The Input Terminal is defined as “USB stream” (terminal type 0x0101). The Input Terminal can accept 2-channel audio streams comprised of left and right channel data. The Output Terminal is defined as a “speaker” (terminal type 0x0301). The Feature Unit supports the following sound control features. • Volume Control • Mute Control The built-in digital volume controller can be manipulated by an audio class specific request from 0.0dB to –64.0dB in steps of 1.0dB. Each channel can be set independently. The master volume control is also supported. The built-in digital mute controller can be manipulated by an audio class specific request. A master mute-control request is acceptable. A request to an individual channel will be stalled and ignored. Interface #1 has three alternative settings. Alternative setting #0 is the Zero Bandwidth setting. Alternative setting #1 is the 16-Bit Stereo setting, and is an operational setting. Alternative setting #2 is the 16-Bit Monaural setting, and is also an operational setting. The PCM2702 has the following two endpoints. • Control Endpoint (EP #0) • Isochronous Audio Data Stream Endpoint (EP #2) The Control Endpoint is a default endpoint and is used to control all functions of the PCM2702 by the standard USB request and the USB audio class specific request. The Isochronous Audio Data Stream Endpoint is an audio sink endpoint, which receives the PCM audio data, and accepts the adaptive transfer mode. USB Revision Device Class Device Subclass Device Protocol Max Packet Size for Endpoint 0 Vendor ID Device ID Release 1.0 0x00 (device defined interface level) 0x00 (not specified) 0x00 (not specified) 8 byte 0x08BB 0x2702 1.0 TABLE I. Device Definition. DEVICE CONFIGURATION Figure 1 illustrates USB audio function topology. The PCM2702 has two interfaces. Each interface is constructed by some alternative setting. Interface #0 has one alternative setting. Alternative setting #0 describes the standard audio control interface. The audio control interface is constructed by a terminal. The PCM2702 has the following three terminals. • Input Terminal (IT) • Output Terminal (OT) • Feature Unit (FU) Endpoint #0 Default Endpoint FU Endpoint #2 Audio Streaming Interface (IF #1) IT TID1 UID3 Standard Audio Control Interface (IF #0) PCM2702 OT TID2 Analog Out NOTE: IT = Input Terminal (Terminal ID #1); OT = Output Terminal (Terminal ID #2); FU = Feature Unit (Unit ID #3). FIGURE 1. USB Audio Function Topology. ® PCM2702 8 CLOCK AND RESET The PCM2702 requires a 12MHz (±500ppm) clock for USB and audio functions, which may be generated by an on-chip crystal oscillator with external 12MHz crystal resonator, or supplied by an external clock applied at XTI (pin1). The 12MHz crystal resonator must be connected to XTI (pin 1) and XTO (pin 28), along with a 1MΩ resistor and two small capacitors (value is dependent upon the specified load capacitance of the crystal resonator). If an external clock is used, the clock must be supplied at XTI, and XTO must be left open. The clock signal applied at XTI must be +3.3V logic level, as this input is not +5V tolerant. Figures 2 and 3 illustrate the circuit connections required for crystal and external clock options. The PCM2702 includes an internal power-on reset circuit, which automatically initializes digital logic when VDD exceeds 2.0V typical (range: 1.6V to 2.4V). Initialization requires approximately 350µs for completion. The VDD supply must rise to 2.0V within 10ms for proper power-on sequence operation. INTERFACE SEQUENCE Power-on, Attach, and Playback Sequence The PCM2702 is ready for setup when the reset sequence has finished and the USB bus is connected. After connection is established, the PCM2702 is ready to accept USB audio data. While waiting for audio data (idle state), the analog outputs are set to bipolar zero (BPZ) and the zero flag, ZERO (pin 12), is set to HIGH. When receiving the audio data, the PCM2702 stores the first audio packet, which contains 1ms of audio data, into an internal storage buffer. The PCM2702 starts playing the audio data upon detection of the Start of Frame (SOF) packet. See Figures 4 and 5 for the normal operation sequence. 1 XTI 12MHz External Clock 1 XTI XTAL 12MHz 1MΩ 28 XTO Must Be Left Open 28 XTO FIGURE 2. 12MHz Crystal Resonator Connection. FIGURE 3. External 12MHz Clock Input Connection. ® 9 PCM2702 10ms VDD 0V VBUS 2.0V (1.6 to 2.4V) 1st SOF D+/D– SOF PLYBCK 1ms 1st Audio Data 2nd Audio Data SOF SOF SOF SSPND 23ms (1024/fS) ZERO VOUTL VOUTR 350µs Internal Reset Device Setup 1ms Ready for Setup Attach (connect to USB bus) Ready for Playback FIGURE 4. Connecting the PCM2702 to the USB Bus After Power-On. 10ms VDD 0V VBUS 2.0V (1.6 to 2.4V) 1st SOF D+/D– SOF PLYBCK 1ms 1st Audio Data 2nd Audio Data SOF SOF SOF SSPND 23ms (1024/fS) ZERO VOUTL VOUTR 350µs Internal Reset Ready for Setup Attach (connect to USB bus) Device Setup 1ms Ready for Playback FIGURE 5. Connecting the PCM2702 to the USB Bus Prior to Power-On. ® PCM2702 10 Play, Stop, and Detach sequence When host finishes or aborts audio playback, the PCM2702 will stop playing after the last transmitted audio data has been received. Figure 6 shows the operation sequence for play, stop, and detach. PLYBCK, SSPND, AND ZERO FLAG PLYBCK, SSPND, and Zero flag in Figures 4, 5, and 6 are defined as follows. PLYBCK—while PCM audio input data is playing back, PLYBCK (pin 10) is switched LOW. SSPND—upon detection of a suspend state on the USB port, SSPND (pin 11) is switched LOW. ZERO—if the PCM audio input data is continuously zero for 1024 sampling periods (1/fS), ZERO (pin12) is switched to HIGH. TEST PINS The PCM2702 has four test pins—TEST0 (pin 16), TEST1 (pin 15), TEST2 (pin 14), and TEST3 (pin 13)—which are used solely for testing at the factory. These pins must be connected to a digital ground for proper operation. VBUS Audio Data D+/D– SOF PLYBCK SOF Audio Data Last Audio Data SOF SOF SOF SOF SSPND ZERO VOUTL VOUTR 1ms 23ms (1024/fS) 4ms Detach FIGURE 6. Play, Stop, and Detach. X1 12MHz C1 C2 R4 1 +3.3V C3 2 3 4 C5 R2 R3 USB Series “B” Connector 5 6 7 8 9 10 11 12 13 14 XTI VDDC DGNDC VDD DGND D+ D– PCM2702 VBUS DGNDU PLYBCK SSPND ZERO TEST3 TEST2 XTO VCCP AGNDP VCCL AGNDL VOUTL VCC VCOM AGND VOUTR AGNDR VCCR TEST0 TEST1 28 27 C4 26 25 C6 24 23 22 21 20 19 18 C8 17 16 15 POST LPF R-Channel C9 + POST LPF L-Channel +5V C7 NOTE: C1, C2: 10pF to 33pF (depending on Crystal Resonator); C3 ,C4: 0.1µF 1-100µF; C5 to C8: 0.1µF Ceramic each and two 1µF to 100µF for 5V and 3.3V; C9: 10µF; R1: 1.5kΩ; R2, R3: 22Ω; R4: 1MΩ; X1: Crystal Resonator (fundamental mode, parallel resonant). FIGURE 7. Typical Connection Diagram. ® 11 PCM2702
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