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PCM3168A
Burr-Brown Audio
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
PCM3168A 24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec With Differential Input/Output
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
Car Audio External Amplifiers
Car Audio AVN Applications
Home Theaters
AV Receivers
3 Description
The PCM3168A device is a high-performance, singlechip, 24-bit, 6-in/8-out, audio coder and decoder
(codecs) with single-ended and differential-selectable
analog inputs and differential outputs.
Device Information(1)
PART NUMBER
PCM3168A
PACKAGE
BODY SIZE (NOM)
HTQFP (64)
10.00 mm x 10.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application Diagram
DSP
6 Channel
Differential
Analog Audio
Source
Input
Filters
PCM3168A
I2C
•
24-Bit ΔΣ ADC and DAC
Six-ChanneL ADC:
– High Performance: Differential and SingleEnded, fS = 48 kHz
– THD+N: –93 dB (Differential and SingleEnded)
– SNR: 107 dB (Differential),
104 dB (Single-Ended)
– Dynamic Range: 107 dB (Differential),
104 dB (Single-Ended)
– Sampling Rate: 8 kHz to 96 kHz
– System Clock: 256 fS, 384 fS, 512 fS, 768 fS
– Differential Voltage Input: 2 VRMS
– Single-Ended Voltage Input: 1 VRMS
– Decimation Filter:
– Passband Ripple: ±0.035 dB
– Stop Band Attenuation: –75 dB
– On-Chip, Highpass Filter:
0.96 Hz at fS = 48 kHz
– Overflow Flag
Eight-Channel DAC:
– High Performance: Differential, fS = 48 kHz
– THD+N: –94 dB
– SNR: 112 dB
– Dynamic Range: 112 dB
– Sampling Rate: 8 kHz to 192 kHz
– System Clock: 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS
– Differential Voltage Output: 8 VPP
– Analog Lowpass Filter Included
– 4x/8x Oversampling Digital Filter:
– Passband Ripple: ±0.0018 dB
– Stop Band Attenuation: –75 dB
– Zero Flag
Flexible Mode Control:
– Four-Wire SPI™, Two-Wire I2C™ Compatible
Serial Control Interface or Hardware Control
Multi Functions Through SPI or I2C I/F:
– Audio I/F Mode and Format Select for ADC
and DAC
– Digital Attenuation and Soft Mute for ADC and
DAC
– Digital De-Emphasis: 32, 44.1, and 48 kHz for
DAC
Multi Functions Through H/W Control:
– Audio I/F Mode/Format Select
– Digital De-Emphasis Filter: 44.1 kHz for DAC
External Reset Pin:
– ADC/DAC Simultaneous
Audio Interface Mode:
– ADC/DAC Independent Master and Slave
Audio Data Format:
– ADC/DAC Independent I2S™, Left-Justified,
Right-Justified, DSP, TDM
Power Supplies: 5 V for Analog and 3.3 V for
Digital
Package: HTQFP-64
Operating Temperature Range:
– Consumer Grade: –40°C to 85°C
– Automotive Audio Grade: –40°C to 105°C
OVF/ZERO
•
•
1
•
TDM
1 Features
x4
TAS5424
C-Q1
x4
x4
TAS5424
C-Q1
x4
Output
Filters
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM3168A
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Absolute Maximum Ratings ..................................... 7
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Electrical Characteristics........................................... 9
Timing Requirements: System Clock...................... 12
Timing Requirements: Power-On Reset ................. 13
Timing Requirements: Audio Interface for LeftJustified, Right-Justified, and I2S (Slave Mode) ...... 13
8.9 Timing Requirements: Audio Interface for LeftJustified, Right-Justified, and I2S (Master Mode) .... 13
8.10 Timing Requirements: Audio Interface for DSP and
TDM (Slave Mode)................................................... 14
8.11 Timing Requirements: Audio Interface for DSP and
TDM (Master Mode)................................................. 14
8.12 Timing Requirements: DAC Outputs and ADC
Outputs..................................................................... 14
8.13 Timing Requirements: Four-Wire Serial Control
Interface ................................................................... 15
8.14 Timing Requirements: SCL and SDA Control
Interface ................................................................... 15
8.15 Typical Characteristics .......................................... 19
9
Detailed Description ............................................ 24
9.1
9.2
9.3
9.4
9.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Register Maps .........................................................
24
24
25
31
36
10 Application and Implementation........................ 51
10.1 Application Information.......................................... 51
10.2 Typical Application ................................................ 51
10.3 System Examples ................................................. 53
11 Power Supply Recommendations ..................... 54
12 Layout................................................................... 55
12.1 Layout Guidelines ................................................. 55
12.2 Layout Example .................................................... 57
13 Device and Documentation Support ................. 58
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
58
58
58
58
58
58
14 Mechanical, Packaging, and Orderable
Information ........................................................... 58
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2008) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section. .............................................................. 1
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5 Description (continued)
The six-channel, 24-bit analog-to-digital converter (ADC) employs a delta-sigma (ΔΣ) modulator and supports
8-kHz to 96-kHz sampling rates and a 16-bit/24-bit width digital audio output word on the audio interface.
The eight-channel, 24-bit digital-to-analog converter (DAC) employs a ΔΣ modulator and supports 8-kHz to
192-kHz sampling rates and a 16-bit/24-bit width digital audio input word on the audio interface. Each audio
interface supports I2S, left-justified, right-justified, and DSP formats with 16-bit/24-bit word width. In addition, the
PCM3168A device supports the time-division-multiplexed (TDM) format.
The PCM3168A device can be controlled through a four-wire, SPI-compatible interface, or two-wire, I2Ccompatible serial interface in software, which provides access to all functions including digital attenuation, soft
mute, de-emphasis, and so forth. Also, hardware control mode provides a subset of user-programmable
functions through four control pins. The PCM3168A device is available in a 12-mm × 12-mm (10-mm × 10-mm
body) HTQFP-64 PowerPAD™ package.
6 Device Comparison Table
PART
ADCs
DACs
CONTROL
2
AUTOMOTIVE GRADE
PCM3168A
6
8
SPI, I C
No
PCM3168A-Q1
6
8
SPI, I2C
Yes
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PCM3168A
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
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7 Pin Configuration and Functions
VIN6+
VIN6-
VIN5+
VIN5-
VREFAD2
AREFAD1
VIN4+
VIN4-
VIN3+
VIN3-
VIN2+
VIN2-
VIN1+
VIN1-
AGNDAD1
VCCAD1
PAP Package
64-Pin HTQFP With PowerPAD
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCOMAD
1
48
MODE
AGNDAD2
2
47
DGND1
VCCAD2
3
46
VDD1
RST
4
45
MS/ADR0/MD0
OVF
5
44
MDO/ADR1/MD1
LRCKAD
6
43
MDI/SDA/DEMP
BCKAD
7
42
MC/SCL/FMT
DOUT1
8
41
SCKI
DOUT2
9
40
DIN4
PCM3168A
PCM3168A-Q1
PowerPAD
(Connected to Analog Ground)
4
VCCDA1
14
35
LRCKDA
VCOMDA
15
34
VCCDA2
AGNDDA1
16
33
AGNDDA2
17
18
19
20
21
22
23
24
25
26
27
28
29
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30
31
32
VOUT1-
BCKDA
VOUT1+
36
VOUT2-
13
VOUT2+
ZERO
VOUT3-
DIN1
VOUT3+
37
VOUT4-
12
VOUT4+
VDD2
VOUT5-
DIN2
VOUT5+
38
VOUT6-
11
VOUT6+
DGND2
VOUT7-
DIN3
VOUT7+
39
VOUT8-
10
VOUT8+
DOUT3
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SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
Pin Functions
PIN
NO.
NAME
I/O
PULLDOWN
5-V
TOLERANT
DESCRIPTION
1
VCOMAD
—
No
No
ADC analog common voltage decoupling
2
AGNDAD2
—
No
No
Analog ground 2 for ADC
3
VCCAD2
—
No
No
ADC analog power supply 2, 5 V
4
RST
I
Yes
Yes
Reset and power-down control input with active low
5
OVF
O
No
No
Overflow flag output for ADC
6
LRCKAD
I/O
Yes
No
Audio data word clock input/output for ADC
7
BCKAD
I/O
Yes
No
Audio data bit clock input/output for ADC
8
DOUT1
O
No
No
Audio data digital output for ADC1 and ADC2
9
DOUT2
O
No
No
Audio data digital output for ADC3 and ADC4
10
DOUT3
O
No
No
Audio data digital output for ADC5 and ADC6
11
DGND2
—
No
No
Digital ground 2
12
VDD2
—
No
No
Digital power supply 2, 3.3 V
13
ZERO
O
No
No
Zero detect flag output for DAC
14
VCCDA1
—
No
No
DAC analog power supply 1, 5 V
15
VCOMDA
—
No
No
DAC voltage common decoupling
16
AGNDDA1
—
No
No
Analog ground 1 for DAC
17
VOUT8+
O
No
No
Positive analog output from DAC8
18
VOUT8–
O
No
No
Negative analog output from DAC8
19
VOUT7+
O
No
No
Positive analog output from DAC7
20
VOUT7–
O
No
No
Negative analog output from DAC7
21
VOUT6+
O
No
No
Positive analog output from DAC6
22
VOUT6–
O
No
No
Negative analog output from DAC6
23
VOUT5+
O
No
No
Positive analog output from DAC5
24
VOUT5–
O
No
No
Negative analog output from DAC5
25
VOUT4+
O
No
No
Positive analog output from DAC4
26
VOUT4–
O
No
No
Negative analog output from DAC4
27
VOUT3+
O
No
No
Positive analog output from DAC3
28
VOUT3–
O
No
No
Negative analog output from DAC3
29
VOUT2+
O
No
No
Positive analog output from DAC2
30
VOUT2–
O
No
No
Negative analog output from DAC2
31
VOUT1+
O
No
No
Positive analog output from DAC1
32
VOUT1–
O
No
No
Negative analog output from DAC1
33
AGNDDA2
—
No
No
Analog ground 2 for DAC
34
VCCDA2
—
No
No
DAC analog power supply 2, 5 V
35
LRCKDA
I/O
Yes
No
Audio data word clock input/output for DAC
36
BCKDA
I/O
Yes
No
Audio data bit clock input/output for DAC
37
DIN1
I
No
No
Audio data input for DAC1 and DAC2
38
DIN2
I
No
No
Audio data input for DAC3 and DAC4
39
DIN3
I
No
No
Audio data input for DAC5 and DAC6
40
DIN4
I
No
No
Audio data Input for DAC7 and DAC8
41
SCKI
I
No
Yes
System clock input
42
MC/SCL/FMT
I
No
Yes
Clock for SPI, clock for I2C, format select for hardware control
mode
43
MDI/SDA/DEMP
I/O
No
Yes
Input data for SPI, data for I2C (1), de-emphasis control for hardware
control mode
(1)
Open-drain configuration in I2C.
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Pin Functions (continued)
PIN
NO.
NAME
I/O
PULLDOWN
5-V
TOLERANT
DESCRIPTION
44
MDO/ADR1/MD1
I/O
No
No
Output data for SPI (2), address select 1 for I2C, mode select 1 for
hardware control mode
45
MS/ADR0/MD0
I
Yes
Yes
Chip select for SPI, address select 0 for I2C, mode select 0 for
hardware control mode
46
VDD1
—
No
No
Digital power supply 1, 3.3 V
47
DGND1
—
No
No
Digital ground 1
48
MODE
I
No
No
Control port mode selection. Tied to VDD: SPI, pull-up: H/W singleended input, pull-down: H/W and differential input, tied to DGND:
I2C
49
VCCAD1
—
No
No
ADC analog power supply 1, 5 V
50
AGNDAD1
—
No
No
Analog ground 1 for ADC
51
VIN1–
I
No
No
Negative analog input to ADC1
52
VIN1+
I
No
No
Positive analog input to ADC1
53
VIN2–
I
No
No
Negative analog input to ADC2
54
VIN2+
I
No
No
Positive analog input to ADC2
55
VIN3–
I
No
No
Negative analog input to ADC3
56
VIN3+
I
No
No
Positive analog input to ADC3
57
VIN4–
I
No
No
Negative analog input to ADC4
58
VIN4+
I
No
No
Positive analog input to ADC4
59
VREFAD1
—
No
No
ADC analog reference voltage 1 decoupling
60
VREFAD2
—
No
No
ADC analog reference voltage 2 decoupling
61
VIN5–
I
No
No
Negative analog input to ADC5
62
VIN5+
I
No
No
Positive analog input to ADC5
63
VIN6–
I
No
No
Negative analog input to ADC6
64
VIN6+
I
No
No
Positive analog input to ADC6
(2)
6
3-state (Hi-Z) operation in SPI.
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SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted). (1)
Supply voltage
Ground voltage differences
Supply voltage differences
Digital input voltage
Analog input voltage
MIN
MAX
VCCAD1
–0.3
6.5
VCCAD2
–0.3
6.5
VCCDA1
–0.3
6.5
VCCDA2
–0.3
6.5
VDD1
–0.3
4
VDD2
–0.3
4
AGNDAD1
–0.1
0.1
AGNDAD2
–0.1
0.1
AGNDDA1
–0.1
0.1
AGNDDA2
–0.1
0.1
DGND1
–0.1
0.1
DGND2
–0.1
0.1
VCCAD1
–0.1
0.1
VCCAD2
–0.1
0.1
VCCDA1
–0.1
0.1
VCCDA2
–0.1
0.1
VDD1
–0.1
0.1
VDD2
–0.1
0.1
RST
–0.3
6.5
MS
–0.3
6.5
MC
–0.3
6.5
MDI
–0.3
6.5
SCK
–0.3
6.5
BCKAD/DA
–0.3
(VDD + 0.3) < +4.0
LRCKAD/DA
–0.3
(VDD + 0.3) < +4.0
DIN1/2/3/4
–0.3
(VDD + 0.3) < +4.0
DOUT1/2/3
–0.3
(VDD + 0.3) < +4.0
MODE
–0.3
(VDD + 0.3) < +4.0
OVF
–0.3
(VDD + 0.3) < +4.0
ZERO
–0.3
(VDD + 0.3) < +4.0
MDO
–0.3
(VDD + 0.3) < +4.0
VIN1-6±
–0.3
(VCC + 0.3) < +6.5
VCOMAD/DA
–0.3
(VCC + 0.3) < +6.5
VOUT1-8±
–0.3
(VCC + 0.3) < +6.5
VREFAD1/2
–0.3
(VCC + 0.3) < +6.5
UNIT
V
V
V
V
V
Input current (all pins except supplies)
–10
10
mA
Ambient temperature range (under bias)
–40
125
°C
Junction temperature
150
°C
Lead temperature (soldering, 5s)
260
°C
Package temperature (IR reflow, peak)
260
°C
150
°C
Storage temperature, Tstg
(1)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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8.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
UNIT
VCC
Analog supply voltage
4.5
5.0
5.5
V
VDD
Digital supply voltage
3.0
3.3
3.6
V
Digital Interface
LVTTL compatible
Sampling frequency, LRCKAD/LRCKDA (1)
Digital input clock frequency
VI
Analog input level
VO
Analog output voltage
System clock frequency, SCKI
96/192 (1)
8
2.048
36.864
kHz
MHz
Single-ended
1
VRMS
Differential
2
VRMS
8
VPP
Differential
To AC-coupled GND
5
kΩ
To DC-coupled GND
15
kΩ
VOLR
Analog output load resistance
VOLC
Analog output load capacitance
50
pF
DOLC
Digital output load capacitance
20
pF
TA
Operating free-air
temperature
85
°C
(1)
PCM3168A Consumer grade
–40
25
192 kHz is supported only for DAC.
8.4 Thermal Information
PCM3168A
THERMAL METRIC (1)
PAP (HTQFP)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
26.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
7.7
°C/W
RθJB
Junction-to-board thermal resistance
8.9
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
8.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.2
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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8.5 Electrical Characteristics
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DATA FORMAT
I2S, LJ, RJ, DSP, TDM
Audio data interface format
Audio data word length
16, 24
Audio data format
fS
Sampling frequency, ADC
fS
Sampling frequency, DAC
System clock frequency
Bits
MSB first, twos complement
128 fS, 192 fS, 256 fS,
384 fS, 512 fS, 768 fS
8
48
96
kHz
8
48
192
kHz
2.048
36.864
MHz
2
VDD
INPUT LOGIC
VIH (1) (2)
VIL (1) (2)
VIH (3) (4)
VIL (3) (4)
IIH (2) (3)
IIL (2) (3)
IIH (1) (4)
IIL (1) (4)
Input logic level
0.8
2
Input logic level
Input logic level
Input logic level
5.5
0.8
VIN = VDD
±10
VIN = 0 V
±10
VIN = VDD
65
VIN = 0 V
VDC
VDC
μA
100
μA
±10
OUTPUT LOGIC
VOH (5)
VOL (5) (6)
Output logic level
IOUT = –4 mA
2.4
IOUT = 4 mA
0.4
VDC
REFERENCE INPUT/OUTPUT
VREFAD1 output voltage
VCCAD1
V
VREFAD2 output voltage
AGNDAD1
V
VCOMAD output voltage
0.5 × VCCAD1
VCOMAD output impedance
V
10
Allowable VCOMAD output
source/sink current
kΩ
μA
1
VCOMDA output voltage
0.5 × VCCDA1
VCOMDA output impedance
V
7.5
Allowable VCOMDA output
source/sink current
kΩ
μA
1
ADC CHARACTERISTICS
Resolution
Full-scale input voltage
16
24
Bits
VIN = 0 dB, Single-ended
0.2 × VCCAD1
VRMS
VIN = 0 dB, Differential
0.4 × VCCAD1
VRMS
Center voltage
0.5 × VCCAD1
V
Input impedance
45
kΩ
Common-mode rejection ratio
80
dB
DC ACCURACY
(1)
(2)
(3)
(4)
(5)
(6)
Gain mismatch channel-to-channel
Full-scale input, VIN
±2.0
±6
% of FSR
Gain error
Full-scale input, VIN
±2.0
±6
% of FSR
Bipolar zero error
Highpass filter bypass, VIN
±1.0
% of FSR
BCKAD, BCKDA, LRCKAD, and LRCKDA (in slave mode, Schmitt trigger input with 50-kΩ typical internal pulldown resistor).
DIN1/2/3/4 and MDO/ADR1/MD1. (Except SPI mode, Schmitt trigger input).
SCKI, MDI/SDA/DEMP, and MC/SCL/FMT (Schmitt trigger input, 5-V tolerant).
RST and MS/ADR0/MD0 (Schmitt trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant).
BCKAD, BCKDA, LRCKAD, and LRCKDA (in master mode), DOUT1/2/3, ZERO, OVF, and MDO/ADR1/MD1 (in SPI mode).
SDA (in I2C mode, open-drain low output).
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Electrical Characteristics (continued)
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fS = 48 kHz, Differential
–93
–87
fS = 96 kHz, Differential
–93
fS = 48 kHz, Single-ended
–93
fS = 96 kHz, Single-ended
–93
UNIT
DYNAMIC PERFORMANCE (7) (8)
THD+N, VIN = –1 dB
fS = 48 kHz, A-weighted,
differential
Dynamic range
100
107
fS = 48 kHz, A-weighted,
single-ended
104
fS = 96 kHz, A-weighted,
single-ended
104
dB
100
107
fS = 96 kHz, A-weighted,
differential
107
fS = 48 kHz, A-weighted,
single-ended
104
fS = 96 kHz, A-weighted,
single-ended
104
dB
fS = 48 kHz, Differential
Channel separation
(between one channel and others)
107
fS = 96 kHz, A-weighted,
differential
fS = 48 kHz, A-weighted,
differential
S/N ratio
dB
98
104
fS = 96 kHz, Differential
104
fS = 48 kHz, Single-ended
101
fS = 96 kHz, Single-ended
101
dB
DIGITAL FILTER PERFORMANCE
Passband (single)
0.454 × fS
Hz
Passband (dual)
0.454 × fS
Hz
Stop band (single)
0.555 × fS
Stop band (dual)
Hz
0.597 × fS
Passband ripple
< 0.454 × fS, 0.454 × fS
Stop band attenuation
> 0.555 × fS, 0.597 × fS
Hz
±0.035
dB
–75
dB
Group delay time (single)
27 / fS
sec
Group delay time (dual)
17 / fS
sec
0.02 × fS / 1000
Hz
24
Bits
Highpass filter frequency response
–3 dB
DAC CHARACTERISTICS
Resolution
16
DC ACCURACY
(7)
(8)
10
Gain mismatch channel-to-channel
±2.0
±6
% of FSR
Gain error
±2.0
±6
% of FSR
Bipolar zero error
±1.0
% of FSR
In differential mode at VINx± pin, fIN = 1 kHz, using Audio Precision System II, RMS mode with 20-kHz lowpass filter and 400-Hz
highpass filter.
fS = 48 kHz : SCKI = 512 fS (single), fS = 96 kHz : SCKI = 256 fS (dual), fS = 192 kHz : SCKI = 128 fS (quad).
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Electrical Characteristics (continued)
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fS = 48 kHz
–94
–88
fS = 96 kHz
–94
fS = 192 kHz
–94
UNIT
DYNAMIC PERFORMANCE (9) (10)
THD+N, VOUT = 0 dB
fS = 48 kHz, EIAJ, Aweighted
Dynamic range
105
S/N ratio
112
fS = 192 kHz, EIAJ, Aweighted
112
105
112
fS = 192 kHz, EIAJ, Aweighted
112
102
dB
112
fS = 96 kHz, EIAJ, Aweighted
fS = 48 kHz
Channel separation
(between one channel and others)
112
fS = 96 kHz, EIAJ, Aweighted
fS = 48 kHz, EIAJ, Aweighted
dB
dB
108
fS = 96 kHz
108
fS = 192 kHz
108
dB
ANALOG OUTPUT
Output voltage
Differential
Center voltage
Load impedance
Lowpass filter frequency response
DIGITAL FILTER PERFORMANCE (12)
(11)
5
To DC-coupled GND (11)
15
To AC-coupled GND
1.6 × VCCDA1
VPP
0.5 × VCCDA1
V
kΩ
f = 20 kHz
–0.04
f = 44 kHz
–0.18
dB
Slow roll-off
Passband (single, dual)
0.454 × fS
Hz
Passband (quad)
0.432 × fS
Hz
Stop band (single, dual)
0.546 × fS
Stop band (quad)
0.569 × fS
Passband ripple
≤ 0.454 × fS
Stop band attenuation
> 0.546 × fS, 0.569 × fS
DIGITAL FILTER PERFORMANCE
Hz
Hz
±0.0018
–75
dB
dB
Slow roll-off
Passband
0.328 × fS
Stop band
0.673 × fS
Passband ripple
< 0.328 × fS
Stop band attenuation
> 0.673 × fS
Hz
Hz
±0.0013
–75
dB
dB
(9)
In differential mode at VOUTx± pin, fOUT = 1 kHz, using Audio Precision System II, RMS mode with 20-kHz lowpass filter and 400-Hz
highpass filter.
(10) fS = 48 kHz : SCKI = 512 fS (single), fS = 96 kHz : SCKI = 256 fS (dual), fS = 192 kHz : SCKI = 128 fS (quad).
(11) Allowable minimum input resistance of differential to single-ended converter with D to S Gain = G is calculated as (1 + 2G)/(1 + G) × 5k
for AC-coupled and (1+ 0.9G)/(1 + G) × 15k for DC-coupled connection, refer to Figure 61 and Figure 62 of the Application Information
section.
(12) Exclude single and dual at 128 fS, 192 fS system clock and quad at 256 fS to 768 fS system clock, and specifications for quad, single,
and dual are respectively applied in reverse for them.
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Electrical Characteristics (continued)
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL FILTER PERFORMANCE (12)
Group delay time (single, dual)
28/fS
sec
Group delay time (quad)
19/fS
sec
De-emphasis error
±0.1
dB
POWER-SUPPLY REQUIREMENTS
VCCxx1/2
VDD1/2
4.5
5.0
5.5
3.0
3.3
3.6
fS = 48 kHz/ADC, fS = 48
kHz/DAC
162
210
fS = 96 kHz/ADC, fS = 192
kHz/DAC
162
mA
Full power-down (13)
300
μA
fS = 48 kHz/ADC, fS = 48
kHz/DAC
106
fS = 96 kHz/ADC, fS = 192
kHz/DAC
127
mA
50
μA
Voltage range
ICC
Supply current
IDD
Full power-down
Power dissipation
(13)
fS = 48 kHz/ADC, fS = 48
kHz/DAC
1160
fS = 96 kHz/ADC, fS = 192
kHz/DAC
1230
fS = 48 kHz/ADC, Powerdown/DAC
660
Power-down/ADC, fS = 48
kHz/DAC
633
Full power-down (13)
1.67
130
VDC
mA
mA
1480
mW
TEMPERATURE RANGE
θJA
Operating temperature
PCM3168A Consumer
grade
Thermal resistance
HTQFP-64
–40
85
21
°C
°C/W
(13) Halt SCKI, BCKAD, BCKDA, LRCKAD, and LRCKDA.
8.6 Timing Requirements: System Clock
Refer to Figure 1.
MIN
MAX
UNIT
tSCY
System clock pulse cycle time
27
ns
tSCH
System clock pulse width high
10
ns
tSCL
System clock pulse width low
10
ns
tDTY
System clock pulse duty cycle
12
40%
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8.7 Timing Requirements: Power-On Reset
Refer to Figure 2.
SINGLE
DUAL
QUAD
UNIT
tDACDLY1
DAC delay time internal reset release to
VOUT start
3600
7200
14400
Period of LRCKDA
tDACDLY2
DAC fade-in/fade-out time
2048
4096
8192
Period of LRCKDA
tADCDLY1
ADC delay time internal reset release to
DOUT start
4800
9600
N/A
Period of LRCKAD
tADCDLY2
ADC fade-in/fade-out time
2048
4096
N/A
Period of LRCKAD
8.8 Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Slave
Mode) (1)
Refer to Figure 3.
MIN
NOM
MAX
UNIT
tBCY
BCKAD/DA cycle time
75
ns
tBCH
BCKAD/DA pulse width high
35
ns
tBCL
BCKAD/DA pulse width low
35
ns
tLRS
LRCKAD/DA setup time to BCKAD/DA rising edge
10
ns
tLRH
LRCKAD/DA hold time to BCKAD/DA rising edge
10
ns
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
ns
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
(1)
0
30
ns
Load capacitance of output is 20 pF.
8.9 Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I2S (Master
Mode) (1)
Refer to Figure 4.
MIN
TYP
MAX
tBCY
BCKAD/DA cycle time
tBCH
BCKAD/DA pulse width high
0.4 × tBCY
0.5 × tBCY
0.6 × tBCY
tBCL
BCKAD/DA pulse width low
0.4 × tBCY
0.5 × tBCY
0.6 × tBCY
tLRD
LRCKAD/DA delay time from BCKAD/DA falling edge
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
(1)
UNIT
1 / (64 × fS)
–10
–10
20
ns
ns
ns
20
ns
Load capacitance of output is 20 pF.
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8.10 Timing Requirements: Audio Interface for DSP and TDM (Slave Mode) (1)
Refer to Figure 5.
MIN
tBCY
tBCH
tBCL
tLRW
TYP
MAX
UNIT
BCKAD cycle time
75
ns
BCKDA cycle time
40
ns
BCKAD pulse width high
35
ns
BCKDA pulse width high
15
ns
BCKAD pulse width low
35
ns
BCKDA pulse width low
15
ns
LRCKAD/DA pulse width high (DSP format)
tBCY
LRCKAD/DA pulse width high (TDM format)
tBCY
1 / fS – tBCY
tLRS
LRCKAD/DA setup time to BCKAD/DA rising edge
10
ns
tLRH
LRCKAD/DA hold time to BCKAD/DA rising edge
10
ns
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
(1)
ns
0
30
ns
Load capacitance of output is 20 pF.
8.11 Timing Requirements: Audio Interface for DSP and TDM (Master Mode) (1)
Refer to Figure 6.
MIN
BCKAD/DA cycle time (DSP format)
tBCY
TYP
MAX
BCKAD/DA cycle time (TDM format, single rate)
1 / (256 × fS)
BCKAD/DA cycle time (TDM format, dual rate)
1 / (128 × fS)
tBCH
BCKAD/DA pulse width high
0.4 × tBCY
0.5 × tBCY
0.6 × tBCY
tBCL
BCKAD/DA pulse width low
0.4 × tBCY
0.5 × tBCY
0.6 × tBCY
tLRW
LRCKAD/DA pulse width high (DSP format)
tBCY
LRCKAD/DA pulse width high (TDM format)
1 / (2 × fS)
tLRD
LRCKAD/DA delay time from BCKAD/DA falling edge
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
(1)
UNIT
1 / (64 × fS)
–10
20
ns
ns
ns
–10
20
ns
Load capacitance of output is 20 pF.
8.12 Timing Requirements: DAC Outputs and ADC Outputs
Refer to Figure 7.
SINGLE
DUAL
QUAD
UNIT
tDACDLY3
DAC delay synchronization detect to normal data
38
38
29
Period of
LRCKDA
tADCDLY3
ADC delay synchronization detect to normal data
60
60
N/A
Period of
LRCKAD
14
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8.13 Timing Requirements: Four-Wire Serial Control Interface (1)
Refer to Figure 8.
MIN
MAX
UNIT
tMCY
MC pulse cycle time
100
ns
tMCL
MC low-level time
40
ns
tMCH
MC high-level time
40
ns
tMHH
MS high-level time
tMCY
ns
tMSS
MS falling edge to MC rising edge
30
ns
tMSH
MS rising edge from MC rising edge for LSB
15
ns
tMDH
MDI hold time
15
ns
tMDS
MDI setup time
15
tMDD
MDO enable or delay time from MC falling edge
0
30
ns
tMDR
MDO disable time from MS rising edge
0
30
ns
(1)
ns
These timing parameters are critical for proper control port operation.
8.14 Timing Requirements: SCL and SDA Control Interface
Refer to Figure 9.
STANDARD MODE
MIN
FAST MODE
MAX
MIN
MAX
100
UNIT
fSCL
SCL clock frequency
tBUF
Bus free time between STOP and START condition
4.7
1.3
μs
tLOW
Low period of the SCL clock
4.7
1.3
μs
tHI
High period of the SCL clock
4.0
0.6
μs
tS-SU
Setup time for START/Repeated START condition
4.7
0.6
μs
tS-HD
Hold time for START/Repeated START condition
4.0
0.6
μs
tD-SU
Data setup time
250
100
tD-HD
Data hold time
0
400
kHz
ns
3450
0
900
ns
300
ns
tSCL-R
Rise time of SCL signal
1000
20 + (0.1 ×
CB)
tSCL-F
Fall time of SCL signal
1000
20 + (0.1 ×
CB)
300
ns
tSDA-R
Rise time of SDA signal
1000
20 + (0.1 ×
CB)
300
ns
tSDA-F
Fall time of SDA signal
1000
20 + (0.1 ×
CB)
300
ns
tP-SU
Setup time for STOP condition
tGW
Allowable glitch width
N/A
50
CB
Capacitive load for SDA and SCL line
400
100
VNH
Noise margin at high level for each connected device
(including hysteresis)
0.2 × VDD
0.2 × VDD
V
VNL
Noise margin at low level for each connected device
(including hysteresis)
0.1 × VDD
0.1 × VDD
V
VHYS
Hysteresis of Schmitt-trigger input
N/A
0.05 × VDD
V
4.0
μs
0.6
pF
tSCH
High
2.0 V
System Clock
(SCKI)
0.8 V
Low
tSCY
tSCL
Figure 1. System Clock Timing Requirements
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(VDD = 3.3 V, typ)
VDD
(VDD = 2.2 V, typ)
0V
SCKI,
BCKAD/DA,
LRCKAD/DA
Synchronous Clocks
RST
3846 ´ SCKI
Normal Operation
Internal Reset
tDACDLY2
tDACDLY1
VOUT1± to
VOUT8±
0.5 ´ VCC
VCOMDA
(0.5 ´ VCCDA1)
tADCDLY2
tADCDLY1
DOUT1/2/3
Fade-In
ZERO
Figure 2. Power-On Reset Timing Requirements
tBCH
tBCL
BCKAD/DA
(Input)
1.4 V
tBCY
tLRH
tLRS
LRCKAD/DA
(Input)
1.4 V
tDOD
DOUT1/2/3
0.5 ´ VDD
tDIS
tDIH
DIN1/2/3/4
1.4 V
Figure 3. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I 2S Data Formats
(Slave Mode)
16
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tBCH
tBCL
BCKAD/DA
(Output)
0.5 ´ VDD
tLRD
tBCY
tLRW
LRCKAD/DA
(Output)
0.5 ´ VDD
tDOD
DOUT1/2/3
0.5 ´ VDD
tDIS
tDIH
DIN1/2/3/4
1.4 V
Figure 4. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I 2S Data Formats
(Master Mode)
tBCL
tBCH
BCKAD/DA
(Input)
1.4 V
tBCY
tLRH
tLRS
LRCKAD/DA
(Input)
1.4 V
tLRW
tDOD
DOUT1/2/3
0.5 ´ VDD
tDIS
tDIH
DIN1/2/3/4
1.4 V
Figure 5. Audio Interface Timing Requirements for DSP and TDM Data Formats (Slave Mode)
tBCH
tBCL
BCKAD/DA
(Output)
0.5 ´ VDD
tLRD
tBCY
LRCKAD/DA
(Output)
tLRW
0.5 ´ VDD
tDOD
DOUT1/2/3
0.5 ´ VDD
tDIS
tDIH
DIN1/2/3/4
1.4 V
Figure 6. Audio Interface Timing Requirements for DSP and TDM Data Formats (Master Mode)
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State of
Synchronization
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Asynchronous
Synchronous
Synchronous
Within 1/fS
tDACDLY3
Undefined Data
DAC
VOUTX±
VCOMDA
(0.5VCCDA1)
Normal
Normal
tADCDLY3
Undefined Data
ADC
DOUTX
Normal
Normal
ZERO
Figure 7. DAC Outputs and ADC Outputs for Loss of Synchronization
tMHH
MS
1.4 V
tMCH
tMSS
tMCL
tMSH
MC
1.4 V
tMDS
MSB (R/W)
MDI
tMCY
tMDH
LSB (D0)
MSB (D7)
ADR0
1.4 V
tMDD
Hi-Z
MDO
tMDR
tMDD
MSB (D7)
LSB (D0)
Hi-Z
0.5 ´ VDD
(1) These timing parameters are critical for proper control port operation.
Figure 8. Four-Wire Serial Control Interface Timing
Repeated
START
START
tBUF
STOP
tD-HD
tD-SU
tSDA-R
tP-SU
SDA
tSCL-R
tSDA-F
tS-HD
tLOW
SCL
tSCL-F
tS-HD
tHI
tS-SU
Figure 9. SCL and SDA Control Interface Timing
18
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8.15 Typical Characteristics
8.15.1
ADC Digital Filter
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
0
0.20
-20
0.15
0.10
-60
Amplitude (dB)
Amplitude (dB)
-40
-80
-100
-120
-140
0.05
0
-0.05
-0.10
-160
-0.15
-180
-0.20
-200
0
2
4
8
6
0
0.1
Normalized Frequency (fS)
Figure 10. Frequency Response (Single Rate)
0
0.20
-20
0.15
0.5
0.4
0.10
-60
Amplitude (dB)
Amplitude (dB)
0.3
Figure 11. Frequency Response Passband (Single Rate)
-40
-80
-100
-120
-140
0.05
0
-0.05
-0.10
-160
-0.15
-180
-0.20
-200
0
1
2
4
3
0
0.1
Normalized Frequency (fS)
0.2
0.3
0.5
0.4
Normalized Frequency (fS)
Figure 12. Frequency Response (Dual Rate)
Figure 13. Frequency Response Passband (Dual Rate)
0
0
-5
-0.05
-10
-0.10
Amplitude (dB)
Amplitude (dB)
0.2
Normalized Frequency (fS)
-15
-20
-25
-0.15
-0.20
-0.25
-30
-0.30
-35
-0.35
-40
-0.40
0
0.0002
0.0004
0.0006
0.0008
0.0010
0
Normalized Frequency (fS)
0.002
0.004
0.006
0.008
0.010
Normalized Frequency (fS)
Figure 14. HPF Frequency Response
Figure 15. HPF Frequency Response Passband
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8.15.2 DAC Digital Filter
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
0
0.010
Sharp
Slow
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
-20
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
1
2
-0.010
4
3
0
0.1
Normalized Frequency (fS)
Figure 16. Frequency Response (Single Rate)
0.5
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
0.4
0.010
Sharp
Slow
-20
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
1
2
-0.010
4
3
0
0.1
Normalized Frequency (fS)
0.2
0.3
0.4
0.5
Normalized Frequency (fS)
Figure 18. Frequency Response (Dual Rate)
Figure 19. Frequency Response Passband (Dual Rate)
0.010
0
Sharp
Slow
-20
Sharp
Slow
0.008
0.006
-40
Amplitude (dB)
Amplitude (dB)
0.3
Figure 17. Frequency Response Passband (Single Rate)
0
-60
-80
0.004
0.002
0
-0.002
-0.004
-100
-0.006
-120
-0.008
-140
0
0.5
1.0
2.0
1.5
-0.010
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (fS)
Normalized Frequency (fS)
Figure 20. Frequency Response (Quad Rate)
20
0.2
Normalized Frequency (fS)
Figure 21. Frequency Response Passband (Quad Rate)
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DAC Digital Filter (continued)
0
0
-1
-1
-2
-2
-3
-3
Amplitude (dB)
Amplitude (dB)
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
-4
-5
-6
-4
-5
-6
-7
-7
-8
-8
-9
-9
-10
-10
0
4
2
6
10
8
12
14
16
18
20
22
0
4
2
6
10
8
12
14
16
18
20
Frequency (kHz)
Frequency (kHz)
Figure 22. De-Emphasis Characteristic (FS = 48 kHz)
Figure 23. De-Emphasis Characteristic (FS = 44 kHz)
0
0
-1
-10
-3
Amplitude (dB)
Amplitude (dB)
-2
-4
-5
-6
-20
-30
-7
-8
-40
-9
-10
0
2
4
6
8
10
-50
12
14
1k
10k
1M
100k
10M
Frequency (kHz)
Frequency (Hz)
Figure 24. De-Emphasis Characteristic (FS = 32 kHz)
Figure 25. Analog Filter Characteristic
8.15.3 ADC Performance
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
112
Dynamic Range and SNR (dB)
-88
THD+N (dB)
-90
-92
-94
-96
-98
110
SNR
108
Dynamic Range
106
104
102
100
-100
-50
-25
0
25
50
75
100
125
-50
Temperature (°C)
-25
0
25
50
75
100
125
Temperature (°C)
Figure 26. THD+N At –1 dB vs Temperature
Figure 27. Dynamic Range and SNR vs Temperature
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ADC Performance (continued)
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
112
Dynamic Range and SNR (dB)
-88
THD+N (dB)
-90
-92
-94
-96
-98
-100
4.50
4.75
5.25
5.00
110
SNR
108
Dynamic Range
106
104
102
100
4.50
5.50
4.75
5.25
5.00
5.50
Supply Voltage (V)
Supply Voltage (V)
Figure 28. THD+N At –1 dB vs Supply Voltage
Figure 29. Dynamic Range and SNR vs Supply Voltage
8.15.4 DAC Performance
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
116
Dynamic Range and SNR (dB)
-90
THD+N (dB)
-92
-94
-96
-98
-100
114
Dynamic Range
112
SNR
110
108
106
104
-102
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
Figure 30. THD+N vs Temperature
Dynamic Range and SNR (dB)
THD+N (dB)
75
100
125
116
-92
-94
-96
-98
-100
22
50
Figure 31. Dynamic Range and SNR vs Temperature
-90
-102
4.50
25
Temperature (°C)
4.75
5.00
5.25
5.50
114
Dynamic Range
112
SNR
110
108
106
104
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Figure 32. THD+N vs Supply Voltage
Figure 33. Dynamic Range and SNR vs Supply Voltage
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8.15.5 Output Spectrum
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
20
15
10
0
5
Frequency (kHz)
10
15
20
Frequency (kHz)
Figure 34. ADC Output Spectrum (–60 dB, N = 32768)
Figure 35. DAC Output Spectrum (–60 dB, N = 32768)
8.15.6 Power-Supply
At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit
data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.
200
ICC
IDD
Power-Supply Current (mA)
180
160
140
120
100
80
60
40
20
0
Operation
DAC Off
ADC Off
Clock Off
Power-Save Condition
Figure 36. Power-Supply Current vs Power-Save Condition
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9 Detailed Description
9.1 Overview
The PCM3168A device is a high-performance, multi-channel codec targeted for automotive audio applications,
such as external amplifiers, as well as home multi-channel audio applications (for example, home theaters and
A/V receivers). The PCM3168A device consists of six-channel analog-to-digital converters (ADCs) and eightchannel digital-to-analog converters (DACs). The ADC input is selectable between single-ended and differential
inputs. The DAC output type is fixed with a differential configuration. The PCM3168A device supports 24-bit
linear PCM input and output data in standard audio formats (left-justified, right-justified, and I2S), DSP and TDM
formats, and various sample frequencies from 8 kHz to 192 kHz (the ADC configuration supports only up to
96 kHz). The TDM format is useful to save interface bus line numbers for multi-channel audio data
communication between the codec and digital audio processor. The PCM3168A device offers three modes for
device control: two-wire I2C software, four-wire SPI software, and hardware modes.
VIN1+
BCKDA
LRCKDA
DIN4
DIN3
DIN2
DIN1
SCKI
DOUT3
DOUT2
DOUT1
BCKAD
LRCKAD
9.2 Functional Block Diagram
VOUT1+
Audio Serial Interface and Clock Control
ADC
DAC
VIN1-
VOUT1-
VIN2+
VOUT2+
DAC
ADC
VIN2-
VOUT2-
VIN3+
VOUT3+
DAC
ADC
VIN3-
VOUT3-
VIN4+
VOUT4+
ADC
Digital
Filter
and
Volume
Digital
Filter
and
Volume
VIN4VIN5+
ADC
DAC
VOUT4VOUT5+
DAC
VIN5-
VOUT5-
VIN6+
VOUT6+
DAC
ADC
VIN6-
VOUT6VOUT7+
DAC
VDD1
VDD2
DGND1
DGND2
VOUT7VOUT8+
DAC
VOUT8-
24
Mode Control Port
2
ZERO
MC/SCL/FMT
MDI/SDA/DEMP
MDO/ADR1/MD1
MS/ADR0/MD0
MODE
RST
(SPI/I C)
OVF
VCOMDA
VCOMAD
VREFAD2
Common and
Reference
VREFAD1
VCCAD1/2
VCCDA1/2
AGNDAD1/2
AGNDDA1/2
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9.3 Feature Description
9.3.1 Analog Inputs
The PCM3168A device includes six ADCs, each with individual pairs of differential voltage input pins, as shown
in Table 1. Additionally, the PCM3168A device has the capability of single-ended inputs. The full-scale input
voltage is (0.2 × VCCAD1) VRMS at the single-ended input mode and (0.4 × VCCAD1) VRMS at the differential
input mode. The input mode is selected by the MODE pin in hardware control mode or by register settings in the
software control mode. In single-ended mode, VINx+ pins are used and VINx– pins must be terminated with
AGNDAD1/2 through a capacitor or terminated with VCOMAD.
Table 1. Pin Assignments in Differential and Single-Ended Input Modes
CHANNEL
DIFFERENTIAL INPUT MODE
SINGLE-ENDED INPUT MODE
1 (ADC1)
VIN1+, VIN1–
VIN1+
2 (ADC2)
VIN2+, VIN2–
VIN2+
3 (ADC3)
VIN3+, VIN3–
VIN3+
4 (ADC4)
VIN4+, VIN4–
VIN4+
5 (ADC5)
VIN5+, VIN5–
VIN5+
6 (ADC6)
VIN6+, VIN6–
VIN6+
9.3.2 Analog Outputs
The The PCM3168A device includes eight DACs, each with individual pairs of differential voltage inputs pins, as
shown in Table 2. The full-scale output voltage is (1.6 × VCCDA1) VPP in differential mode. DC-coupled loads are
allowed in addition to ac-coupled loads if the load resistance conforms to the specification.
Table 2. Pin Assignments for Differential Output
CHANNEL
DIFFERENTIAL OUTPUT
1 (DAC1)
VOUT1+, VOUT1–
2 (DAC2)
VOUT2+, VOUT2–
3 (DAC3)
VOUT3+, VOUT3–
4 (DAC4)
VOUT4+, VOUT4–
5 (DAC5)
VOUT5+, VOUT5–
6 (DAC6)
VOUT6+, VOUT6–
7 (DAC7)
VOUT7+, VOUT7–
8 (DAC8)
VOUT8+, VOUT8–
9.3.3 Voltage References
The PCM3168A device includes two internal references for the six-channel ADCs; these references correspond
to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog ground via
decoupling capacitors. In addition, the PCM3168A device includes two pins for common-mode voltage output
(VCOMDA for DACs and VCOMAD for ADCs). These pins should be also connected with an analog ground via
decoupling capacitors. Furthermore, both common pins can be used to bias external high-impedance circuits, if
they are required.
9.3.4 System Clock Input
The PCM3168A device requires an external system clock input applied at the SCKI input for ADC and DAC
operation. The system clock operates at an integer multiple of the sampling frequency, or fS. The multiples
supported in ADC operation include 256 fS, 384 fS, 512 fS, and 768 fS; the multiples supported in DAC operation
include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS. Details for these system clock multiples are shown in
Table 3. Figure 1 shows the SCKI timing requirements.
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Table 3. System Clock Frequencies for Common Audio Sampling Rates
SAMPLING
FREQUENCY
DEFAULT
SAMPLING
MODE
SYSTEM CLOCK FREQUENCY (MHz)
fS (kHz)
Single rate
128 fS
(1)
(2)
(1)
256 fS
384 fS
512 fS
(2)
768 fS
8
N/A
N/A
2.0480
3.0720
4.0960
6.1440
2.0480 (1)
3.0720 (1)
4.0960
6.1440 (2)
8.1920
12.2880
32
4.0960 (1)
6.1440 (1)
8.1920
12.2880 (2)
16.3840
24.5760
(1)
(1)
(2)
11.2896
16.9344
22.5792
33.8688
48
5.6488
6.1440 (1)
9.2160 (1)
12.2880
18.4320 (2)
24.5760
36.8640
88.2
11.2896 (1)
16.9344 (1)
22.5792
33.8688
N/A
N/A
(1)
(1)
96
Quad rate (1)
192 fS
16
44.1
Dual rate
(1)
12.2880
8.4672
24.5760
36.8640
N/A
N/A
176.4 (1)
22.5792 (1)
18.4320
33.8688 (1)
N/A
N/A
N/A
N/A
192 (1)
24.5760 (1)
36.8640 (1)
N/A
N/A
N/A
N/A
Supported only by DAC operation
Requires 50% duty cycle for stable ADC performance.
9.3.5 Sampling Mode
The PCM3168A device supports two sampling modes (single rate and dual rate) in ADC operation, and three
sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the ADC and DAC
operate at an oversampling frequency of x128 (except when SCKI = 128 fS and 192 fS). This mode is supported
for sampling frequencies less than 50 kHz. In dual rate mode, the ADC and DAC operate at an oversampling
frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the
DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to
the ratio of system clock frequency and sampling frequency by default (for example, single rate for 512 fS and
768 fS, dual rate for 256 fS and 384 fS, and quad rate for 128 fS and 192 fS), but manual selection is also possible
for specified combinations through the serial mode control resistor.
Table 4 and Figure 37 show the relation between the oversampling rate (OSR) of the ΔΣ modulator, noise-free
shaped bandwidth, and each sampling mode setting for ADC operation. Table 5 and Figure 38 describe the
relation between the oversampling rate of the digital filter and ΔΣ modulator, noise-free shaped bandwidth, and
each sampling mode setting for DAC operation.
Table 4. ADC Modulator OSR and Noise-Free Shaped Bandwidth for Each Sampling Mode
SAMPLING MODE
REGISTER SETTING
Auto
Single
Dual
NOISE-FREE SHAPED BANDWIDTH (kHz)
SYSTEM CLOCK RATE (fS)
MODULATOR OSR
fS = 48 kHz
fS = 96 kHz
512, 768
40
N/A
256, 384
20
40
x64
512, 768
40
N/A
x128
256, 384
40
N/A
x128
256, 384
20
40
x64
x128
Table 5. DAC Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth
for Each Sampling Mode
SAMPLING MODE
REGISTER SETTING
Auto
SYSTEM CLOCK
RATE (fS)
NOISE-FREE SHAPED
BANDWIDTH
DIGITAL FILTER OSR
MODULATOR OSR
N/A
x8
x128
N/A
x8
x64
40
x4
x32
fS = 48
kHz
fS = 96
kHz
fS = 192
kHz
512, 768
40
N/A
256, 384
20
40
10
20
128, 192
(1) (2)
(1)
(2)
Supported only by DAC operation.
Quad mode filter characteristic is applied.
26
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Table 5. DAC Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth
for Each Sampling Mode (continued)
SAMPLING MODE
REGISTER SETTING
NOISE-FREE SHAPED
BANDWIDTH
SYSTEM CLOCK
RATE (fS)
Single
Quad
MODULATOR OSR
N/A
x8
x128
N/A
x8
x128
fS = 96
kHz
fS = 192
kHz
512, 768
40
N/A
256, 384
40
N/A
128, 192
Dual
DIGITAL FILTER OSR
fS = 48
kHz
(1) (2)
20
N/A
N/A
x4
x64
256, 384
20
40
N/A
x8
x64
128, 192 (1) (2)
20
40
N/A
x4
x64
(1) (2)
10
20
40
x4
x32
128, 192
spacer
0
-60
-40
-80
-100
-120
-80
-100
-120
-140
-160
-160
-180
-180
0
0.5
1.0
2.0
1.5
DF_Single
DF_Dual
DF_Quad
-60
-140
-200
DSM_Single
DSM_Dual
DSM_Quad
-20
Amplitude (dB)
-40
Amplitude (dB)
0
DSM_Single
DSM_Dual
DF_Single
DF_Dual
-20
-200
0
Normalized Frequency (fS)
0.5
1.0
1.5
2.0
Normalized Frequency (fS)
Figure 37. ADC ΔΣ Modulator and Digital Filter
Characteristic
Figure 38. DAC ΔΣ Modulator and Digital Filter
Characteristic
9.3.6 Reset Operation
The PCM3168A device has both an internal power-on reset circuit and an external reset circuit. The sequences
for both reset circuits are illustrated in Figure 2, Timing Requirements: Power-On Reset, and Figure 39. Figure 2
and Timing Requirements: Power-On Reset describe the timing chart at the internal power-on reset. Initialization
is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after
3846 SCKI clock cycles from power-on if RST is kept high and SCKI is provided. VOUT from the DACs are
forced to the VCOMDA level initially (0.5 × VCCDA1) and settles at a specified level according to the rising VCC.
If synchronization among SCKI, BCKAD/DA, and LRCKAD/DA is maintained, VOUT starts to output with a fadein sequence after tDACDLY1 from the internal reset release; VOUT then provides an output that corresponds to DIN
after (3846 SCKI + tDACDLY1 + tDACDLY2) from power-on. Meanwhile, DOUT from the ADCs begins to output with a
fade-in sequence after tADCDLY1 from the internal reset release; DOUT then provides output corresponding to VIN
after (3846 SCKI + tADCDLY1 + tADCDLY2) from power-on. If the synchronization is not held, the internal reset is not
released and both operating modes are maintained at reset and power-down states; after the synchronization
forms again, both the DAC and ADC return to normal operation with the above sequences.
Figure 39 illustrates a timing chart at the external reset. RST accepts an external forced reset by RST = low, and
provides a device reset and power-down state that makes the lowest power dissipation state available in the
PCM3168A device. If RST goes from high to low under synchronization among SCKI, BCKAD/DA, and
LRCKAD/DA, the internal reset is asserted, all registers and memory are reset, and finally the PCM3168A device
enters into an all power-down state. At the same time, VOUT is immediately forced into the AGNDDA1 level and
DOUT becomes 0. To begin normal operation again, toggle RST high; the same power-up sequence as poweron reset shown in Figure 2 is performed.
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The PCM3168A device does not require particular power-on sequences for VCC and VDD; it allows VDD on and
then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings, however,
simultaneous power-on is recommended for avoiding unexpected responses on VOUTx and DOUTx. Figure 2
illustrates the response for VCC on with VDD on.
(VDD = 3.3 V, typ)
VDD
SCKI,
BCKAD/DA,
LRCKAD/DA
0V
Synchronous Clocks
Synchronous Clocks
100 ns (min)
RST
3846 ´ SCKI
Internal Reset
Normal Operation
Normal Operation
Power-Down
tDACDLY2
tDACDLY1
VOUT1± to
VOUT8±
0.5 ´ VCC
tADCDLY1
DOUT1/2/3
tADCDLY2
Fade-In
ZERO
Figure 39. External Reset Timing Requirements
9.3.7 Highpass Filter (HPF)
The PCM3168A device includes a highpass filter (HPF) for all ADC channels in order to remove the DC
component of the digitized input signal. The filter is located at the output of the digital decimation filter. The –3-dB
corner frequency for the HPF scales with the output sampling rate, where f–3 dB = 0.020 × fS/1000. When
fS = 48 kHz, f–3 dB is 0.96 Hz. The HPF function can be disabled (bypassed) by the BYP bits in two channels.
9.3.8 Overflow Flag
The PCM3168A device includes an overflow flag output for all ADC channels. As soon as any of the six-channel
ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. The overflow flag
is held high for 1024 LRCKAD clock cycles. In parallel, overflow flag information is stored in the OVF bits of the
mode control register, and the OVF bit is held until the mode control register is read. The overflow flag polarity
can be changed by the OVFP bit. The OVF pin also indicates internal reset completion by transmitting a 4096
SCKI width pulse.
9.3.9 Zero Flag
The PCM3168A device includes a zero flag output for all DAC channels. When all of the eight-channel DACs
digital inputs have continued as zero data for 1024 LRCKDA clock cycles, the zero flag is forced high on ZERO.
In parallel, zero flag information is stored in the ZERO bits according to channel. The zero flag polarity can be
changed by the ZREV bit. Also, the zero flag function can be selected by the AZRO bits. AND or OR logic for
stereo, six channels, and eight channels can be selected.
9.3.10 Four-Wire (SPI) Serial Control
The PCM3168A device includes an SPI-compatible serial port that operates asynchronously with the audio serial
interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and
MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output
to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is
the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.
28
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9.3.11 Control Data Word Format
All single write/read operations through the serial control port use 16-bit data words. Figure 40 shows the control
data word format. The first bit is for read/write controls; 0 indicates a write operation and 1 indicates a read
operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the
write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written
to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0].
MSB
R/W
LSB
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
D7
D6
D5
Register Address
D3
D4
D2
D1
D0
Register Data
Figure 40. Control Data Word Format for MDI
9.3.12 Register Write Operation
Figure 41 shows the functional timing diagram for single write operations on the serial control port. MS is held at
a high state until a register must be written. To start the register write cycle, MS is set to a low state. 16 clocks
are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle
has been completed, MS is set high to latch the data into the indexed mode control register.
Also, the PCM3168A device supports multiple write operations in addition to single write operations, which can
be performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and
register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation can be
accomplished by setting MS to a high state.
MS
MC
MDI
X
(1)
'0'
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
D7
D6
D5
D3
D4
D2
D1
D0
X
X
R/W ADR6
(1) X = Don't care
Figure 41. Register Write Operation
9.3.13 Register Read Operation
Figure 42 shows the functional timing diagram for single read operations on the serial control port. MS is held at
a high state until a register must be read. To start the register read cycle, MS is set to a low state. 16 clocks are
then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight
bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for
the next write or read operation. MDO remains in a high impedance state except during the eight MC clock
periods of the actual data transfer.
MS
MC
MDI
MDO
(1)
X
'1'
Don't Care (X)
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Hi-Z
D7
D6
D5
D4
D3
D2
R/W ADR6
D1
D0
Hi-Z
(1) X = Don't care
Figure 42. Register Read Operation
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9.3.14 Two-Wire (I2C) Serial Control
The PCM3168A device supports an I2C-compatible serial bus and data transmission protocol for fast mode
configured as a slave device. This protocol is explained in the I2C specification, version 2.0.
The PCM3168A device has a 7-bit slave address, as shown in Figure 43. The first five bits are the most
significant bits (MSB) of the slave address and are factory-preset to 10001. The next two bits of the address byte
are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four PCM3168A
device can be connected on the same bus at any one time. Each device responds when it receives its own slave
address.
MSB
LSB
0
1
0
0
1
ADR0
ADR1
R/W
Figure 43. Slave Address
9.3.15 Packet Protocol
A master device must control the packet protocol, which consists of the start condition, slave address with the
read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop
condition. The PCM3168A device supports both slave receiver and transmitter functions. Details about DATA for
both write and read operations are described in Figure 44.
SDA
SCL
1 to 7
St
Slave Address
8
9
(1)
R/W
ACK
1 to 8
(2)
DATA
(3)
9
1 to 8
9
9
ACK
DATA
ACK
ACK
Sp
Start
Condition
Stop
Condition
(1) R/W: Read operation if 1; write operation otherwise.
(2) ACK: Acknowledgement of a byte if 0, not Acknowledgement of a byite if 1.
(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.
Figure 44. DATA Operation
9.3.16 Write Operation
The PCM3168A device supports a receiver function. A master device can write to any PCM3168A device register
using single or multiple accesses. The master sends a PCM3168A device slave address with a write bit, a
register address, and the data. If multiple access is required, the address is that of the starting register, followed
by the data to be transferred. When the data are received properly, the index register is incremented by one
automatically. When the index register reaches 0x5E, the next value is 0x40. When undefined registers are
accessed, the PCM3168A device does not send an acknowledgment. Figure 45 illustrates a diagram of the write
operation. The register address and write data are in 8-bit, MSB-first format.
Transmitter
M
M
Data Type
St
Slave Address
M
S
M
S
M
S
M
S
S
M
W
ACK
Reg Address
ACK
Write Data 1
ACK
Write Data 2
ACK
ACK
Sp
(1) M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.
Figure 45. Framework for Write Operation
9.3.17 Read Operation
A master device can read the registers from 0x40 to 0x5E of the PCM3168A device. The value of the register
address is stored in an indirect index register in advance. The master sends the PCM3168A slave address with a
read bit after storing the register address. Then the PCM3168A device transfers the data of the register with
address that is in the indirect index register. Figure 46 shows a diagram of the read operation.
30
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Transmitter
M
M
M
S
M
S
M
M
M
S
S
M
M
Data Type
St
Slave Address
W
ACK
Reg Address
ACK
Sr
Slave Address
R
ACK
Read Data
NACK
Sp
(1) M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,
NACK = Not acknowledge, and Sp = Stop condition.
NOTE: The slave address after the repeated start condition must be the same as the previous address.
Figure 46. Framework for Read Operation
9.4 Device Functional Modes
9.4.1 Mode Control
The PCM3168A device includes four-way mode control selectable by MODE pin, as shown in Table 6. The pullup and pull-down resistors must be 220 kΩ ±5%. This mode control selection is sampled only when the internal
reset is released by a power-on reset or by a low-to-high transition of the external reset (RST pin); a system
clock is also required.
Table 6. Mode Control Selection
MODE
Tied to DGND
Tied to DGND through pull-down resistor
Tied to VDD through pull-up resistor
Tied to VDD
MODE CONTROL INTERFACE
Two-wire (I2C) serial control, selectable analog input configuration
H/W (hardware control), differential analog input
H/W (hardware control), single-ended analog input
Four-wire (SPI) serial control, selectable analog input configuration
From the mode control selection described in Table 6, the functions of four pins are changed, as shown in
Table 7.
Table 7. Pin Functions
PIN ASSIGNMENTS
PIN
SPI
I2C
H/W
MD0
MS/ADR0/MD0
MS
ADR0
MDO/ADR1/MD1
MDO
ADR1
MD1
MDI/SDA/DEMP
MDI
SDA
DEMP
MC/SCL/FMT
MC
SCL
FMT
Both serial controls are available while RST = high and after internal reset completion, which is indicated as a
negative transition (high ≥ low) of a 4096 × SCKI width pulse on the OVF pin.
9.4.2 Hardware Control Mode Configuration
The data format is selected by the MC/SCL/FMT pin between I2S format and I2S mode in TDM format, as shown
in Table 8.
Table 8. Data Format Selection
FMT
MODE CONTROL INTERFACE
I2S audio data format
Low
High
2
I S mode, TDM audio data format (supported only for SCKI = 128 fS, 256 fS, or 512 fS)
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The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in
hardware control mode, as shown in Table 9. The software mode provides full selections of 32 kHz, 44.1 kHz,
and 48 kHz.
Table 9. Hardware Control Mode
DEMP (DE-EMPHASIS FILTER ENABLE)
DESCRIPTION
Low
44.1 kHz, de-emphasis disabled
High
44.1 kHz, de-emphasis enabled
The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The
selectable multiple of the master mode audio interface is limited between 256 fS, 384 fS, and 512 fS; the
selectable sampling mode is limited as shown in Table 10. The software mode provides full selections.
Table 10. Selectable Sampling Mode
DESCRIPTION
MD1
MD0
INTERFACE MODE
ADC
Low
Low
(1)
(2)
Low
High
Slave
(1)
Master, 512 fS
SAMPLING MODE
DAC
ADC
Slave
Slave
(1)
Single rate
Auto (2)
(1)
Dual rate
Auto (2)
Dual rate
Auto (2)
High
Low
Master, 384 fS
Slave
High
High
Master, 256 fS
Slave (1)
Auto
(2)
DAC
(1)
Auto (2)
The multiples between system clock and sampling frequency are automatically detected; 256 fS, 384 fS, 512 fS, and 768 fS are
acceptable for ADC operation, and 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS are acceptable for DAC operation.
The sampling mode is automatically set as single rate for 512 fS and 768 fS, dual rate for 256 fS and 384 fS, and quad rate for 128 fS and
198 fS, according to the detected multiples between the system clock and sampling clock.
9.4.3 Audio Serial Port Operation
The PCM3168A device audio serial port consists of 11 signals: BCKDA, BCKAD, LRCKDA, LRCKAD, DIN1,
DIN2, DIN3, DIN4, DOUT1, DOUT2, and DOUT3. The PCM3168A device also supports audio-interface mode,
slave mode, and master mode. The BCKAD/DA is a bit clock input at the slave mode and an output at the
master mode. The LRCKAD/DA is a left/right word clock or frame synchronization clock input at slave mode and
output at master mode. The DIN1/2/3/4 are the audio data inputs for the DAC. The DOUT1/2/3 are the audio
data outputs from the ADC. BCKAD, LRCKAD and DOUT1/2/3 are used for the ADC, and BCKDA, LRCKDA and
DIN1/2/3/4 are used for the DAC.
9.4.4 Audio Data Interface Formats and Timing
The PCM3168A device supports eight audio data interface formats for the ADC and DAC separately in both
master and slave modes: 24-bit I2S, 24-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit leftjustified mode DSP, 24-bit I2S mode DSP, 24-bit left-justified mode TDM, and 24-bit I2S mode TDM format. The
PCM3168A device also supports two audio data interface formats for the DAC and slave mode: 24-bit leftjustified mode high-speed TDM and 24-bit I2S mode high-speed TDM format. In the case of I2S, left-justified, and
right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported, but 48 BCKs are
limited in slave mode and 32 BCKs are limited in slave mode 16-bit right-justified only. In the case of TDM data
format in single rate, BCKAD/DA, LRCKAD/DA, DOUT1, and DIN1 are used. In the case of TDM data format in
dual rate, BCKAD/DA, LRCKAD/DA, DOUT1/2, and DIN1/2 are used. In the case of high-speed TDM format in
dual rate, BCKDA, LRCKDA, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCKDA,
LRCKDA, and DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 fS,
256 fS, 128 fS, and fBCK ≤ fSCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode
and registers 65 and 81 in software control mode. All data must be in binary twos complement, MSB first.
Figure 47 through Figure 53 show 10 audio interface data formats. Table 11 summarizes the applicable formats
and describes the relationships among them and the respective restrictions with mode control.
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Table 11. Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions
CONTROL
MODE
FORMAT
I/F MODE
I2S/Left-Justified
Master/Slave
I2S/ Left-Justified
TDM
High-Speed I2S/LeftJustified TDM
Slave and
DAC Only (3)
I2S
Hardware
control
(1)
(2)
(3)
Master
(ADC), Slave
I2S TDM
BCK RATE (xfS)
64, 48 (slave)
24, 16
I2S/Left-Justified
DSP
SCKI RATE (xfS)
24
Right-Justified
Software
control
MAX LRCK
FREQUENCY (fS)
DATA BITS
96 kHz (ADC)
192 kHz (DAC)
APPLICABLE PINS
(1)
64, 48 (slave) (1),
32 (slave, 16 bit) (1)
256 to 768 (ADC)
128 to 768 (DAC)
24
DOUT1/2/3
DIN1/2/3/4
64
24
48 kHz
256, 512
256
DOUT1, DIN1
24
96 kHz
128 (DAC) (2), 256
128
DOUT1/2, DIN1/2
24
96 kHz
256
256
DIN1
24
192 kHz
128
128
DIN1/2
24
96 kHz (ADC)
192 kHz (DAC)
256 to 768 (ADC)
128 to 768 (DAC)
64, 48 (slave) (1)
DOUT1/2/3
DIN1/2/3/4
24
48 kHz
512
256
DOUT1, DIN1
24
96 kHz
256
128
DOUT1/2, DIN1/2
BCK = 48 fS, 32 fS is supported only in slave mode; BCK = 32 fS is supported only for 16-bit data length.
SCKI = 128 fS is supported only for DAC.
High-Speed I2S/Left-Justified TDM format is supported only for DAC operation in slave mode.
Ch 1 (Dx1) or Ch 3 (Dx2)
Ch 5 (Dx3) or Ch 7 (DIN4)
LRCKAD/DA
Ch 2 (Dx1) or Ch 4 (Dx2)
Ch 6 (Dx3) or Ch 8 (DIN4)
BCKAD/DA
DIN1/2/3/4
23 22 21
2
1 0
DOUT1/2/3
23 22 21
LSB
MSB
23 22 21
2
1 0
MSB
2
1 0
2
1 0
MSB
LSB
23 22 21
LSB
LSB
MSB
Figure 47. Audio Data Format: 24-Bit I2S
LRCKAD/DA
Ch 2 (Dx1) or Ch 4 (Dx2)
Ch 6 (Dx3) or Ch 8 (DIN4)
Ch 1 (Dx1) or Ch 3 (Dx2)
Ch 5 (Dx3) or Ch 7 (DIN4)
BCKAD/DA
DIN1/2/3/4
23 22 21
2
DOUT1/2/3
1 0
23 22 21
LSB
MSB
23 22 21
2
MSB
2
1 0
2
23 22 21
MSB
LSB
23
1 0
LSB
MSB
23
1 0
LSB
Figure 48. Audio Data Format: 24-Bit Left-Justified
Ch 2 (Dx1) or Ch 4 (Cx2)
Ch 6 (Dx3) or Ch 8 (DIN4)
Ch 1 (Dx1) or Ch 3 (Cx2)
Ch 5 (Dx3) or Ch 7 (DIN4)
LRCKAD/DA
BCKAD/DA
DIN1/2/3/4
0
23 22 21
2
1
MSB
DOUT1/2/3
0
23 22 21
MSB
0
LSB
2
1
0
LSB
23 22 21
2
1
MSB
0
LSB
23 22 21
2
MSB
1
0
LSB
Figure 49. Audio Data Format: 24-Bit Right-Justified
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LRCKAD/DA
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Ch 2 (Dx1) or Ch 4 (Dx2)
Ch 6 (Dx3) or Ch 8 (DIN4)
Ch 1 (Dx1) or Ch 3 (Dx2)
Ch 5 (Dx3) or Ch 7 (DIN4)
BCKAD/DA
DIN1/2/3/4
15 14 13
0
2
1 0
MSB
DOUT1/2/3
15 14 13
0
15 14 13
LSB
2
1 0
MSB
2
1 0
2
1 0
MSB
LSB
15 14 13
LSB
MSB
LSB
Figure 50. Audio Data Format: 16-Bit Right-Justified
1/fS (64 BCKs)
Ch 1 (Dx1) or Ch 3 (Dx2)
(Ch 5 (Dx3) or Ch 7 (DIN4)
LRCKAD/DA
Ch 2 (Dx1) or Ch 4 (Dx2)
(Ch 6 (Dx3) or Ch 8 (DIN4)
BCKAD/DA
Left-Justified Mode
DIN1/2/3/4
DOUT1/2/3
23 22 21
2
1
0
2
1
23 22 21
2
1
0
2
1
23 22 21
2
I S Mode
DIN1/2/3/4
DOUT1/2/3
23 22 21
0
23 22 21
0
23 22
Figure 51. Audio Data Format: 24-Bit DSP Format
1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)
LRCKAD/DA
(Master)
LRCKAD/DA
(Slave)
BCKAD/DA
Left-Justified Mode
DIN1, DOUT1
(Single)
2
I S Mode
DIN1, DOUT1
(Single)
Left-Justified Mode
DIN1/2, DOUT1/2
(Dual)
23 22
23 22
23 22
23 22
0
23 22
Ch 2
32 BCKs
0
23 22
1 0
23 22
1 0
0
23 22
Ch 3
32 BCKs
0
23 22
23 22
Ch 1/Ch 5
32 BCKs
2
I S Mode
DIN1/2, DOUT1/2
(Dual)
0
Ch 1
32 BCKs
0
23 22
Ch 4
32 BCKs
0
23 22
1 0
0
23 22
1 0
23 22
0
23 22
Ch 6
32 BCKs
0
23 22
Ch 2/Ch 6
32 BCKs
23 22
0
Ch 5
32 BCKs
23 22
1 0
0
23 22
23 22
Ch 3/Ch 7
32 BCKs
23 22
1 0
0
23 22
Ch 7
32 BCKs
0
23 22
Ch 8
32 BCKs
0
23 22
1 0
0
23 22
23 22
Ch 4/Ch 8
32 BCKs
23 22
1 0
23 22
Figure 52. Audio Data Format: 24-Bit TDM Format (SCKI = 128 fS, 256 fS, and 512 fS Only)
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1/fS (256 BCKs at Dual Rate, 128 BCKs at Quad Rate)
LRCKDA
(Slave)
BCKDA
Left-Justified Mode
DIN1
(Dual)
2
I S Mode
DIN1
(Dual)
Left-Justified Mode
DIN1/2
(Quad)
23 22
23 22
Ch 1
32 BCKs
23 22
23 22
0
23 22
Ch 2
32 BCKs
0
23 22
23 22
0
23 22
Ch 3
32 BCKs
0
1 0
23 22
23 22
Ch 1/Ch 5
32 BCKs
2
I S Mode
DIN1/2
(Quad)
0
1 0
0
23 22
Ch 4
32 BCKs
0
23 22
1 0
1 0
23 22
Ch 5
32 BCKs
0
23 22
0
23 22
Ch 6
32 BCKs
0
23 22
Ch 2/Ch 6
32 BCKs
23 22
0
23 22
1 0
1 0
23 22
Ch 7
32 BCKs
0
23 22
0
23 22
Ch 8
32 BCKs
0
23 22
Ch 3/Ch 7
32 BCKs
23 22
0
23 22
1 0
0
23 22
23 22
Ch 4/Ch 8
32 BCKs
23 22
1 0
23 22
Figure 53. Audio Data Format: 24-Bit High-Speed TDM Format
(SCKI = 128 fS, 256 fS, DAC, and Slave Mode Only)
9.4.5 Synchronization With the Digital Audio System
The PCM3168A device operates under the system clock (SCKI) and the audio sampling rate (LRCKAD/DA).
Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode. The PCM3168A device does
not need a specific phase relationship between the audio interface clocks (LRCKAD/DA, BCKAD/DA) and the
system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCKAD/DA,
BCKAD/DA, and SCKI.
If the relationship between SCKI and LRCKDA changes more than ±2 BCKDA clocks because of jitter, sampling
frequency change, and so forth, the DAC internal operation halts within 1 / fS, and the analog output is forced into
VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then
tDACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than ±2 BCKADs because of
jitter, sampling frequency change, and so forth, the ADC internal operation halts within 1 / fS, and the digital
output is forced into a 0 code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and
then tADCDLY3 passes. In the event the change is less than ±2 BCKAD/DAs, re-synchronization does not occur,
and this analog/digital output control and discontinuity do not occur.
Figure 7 shows the DAC analog output and ADC digital output for loss of synchronization. During undefined data
periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and
undefined (or zero) data to normal data creates a discontinuity of data on the analog and digital outputs, which
then may generate some noise in the audio signal.
Both ADC outputs (DOUTx) and DAC outputs (VOUTx) hold the previous state if the system clock halts, but the
asynchronous and re-synchronization processes would occur after the system clock resumes. Figure 7 shows
DAC outputs and ADC outputs for loss of synchronization.
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9.5 Register Maps
Table 12. Register Map
ADDRESS
36
DATA
DAC
HEX
B7
B6
B5
B4
B3
B2
B1
B0
64
40
MRST
SRST
—
—
—
—
SRDA1
SRDA0
65
41
PSMDA
MSDA2
MSDA1
MSDA0
FMTDA3
FMTDA2
FMTDA1
FMTDA0
66
42
OPEDA3
OPEDA2
OPEDA1
OPEDA0
FLT3
FLT2
FLT1
FLT0
67
43
REVDA8
REVDA7
REVDA6
REVDA5
REVDA4
REVDA3
REVDA2
REVDA1
68
44
MUTDA8
MUTDA7
MUTDA6
MUTDA5
MUTDA4
MUTDA3
MUTDA2
MUTDA1
69
45
ZERO8
ZERO7
ZERO6
ZERO5
ZERO4
ZERO3
ZERO2
ZERO1
70
46
ATMDDA
ATSPDA
DEMP1
DEMP0
AZRO2
AZRO1
AZRO0
ZREV
71
47
ATDA07
ATDA06
ATDA05
ATDA04
ATDA03
ATDA02
ATDA01
ATDA00
72
48
ATDA17
ATDA16
ATDA15
ATDA14
ATDA13
ATDA12
ATDA11
ATDA10
73
49
ATDA27
ATDA26
ATDA25
ATDA24
ATDA23
ATDA22
ATDA21
ATDA20
74
4A
ATDA37
ATDA36
ATDA35
ATDA34
ATDA33
ATDA32
ATDA31
ATDA30
75
4B
ATDA47
ATDA46
ATDA45
ATDA44
ATDA43
ATDA42
ATDA41
ATDA40
76
4C
ATDA57
ATDA56
ATDA55
ATDA54
ATDA53
ATDA52
ATDA51
ATDA50
77
4D
ATDA67
ATDA66
ATDA65
ATDA64
ATDA63
ATDA62
ATDA61
ATDA60
78
4E
ATDA77
ATDA76
ATDA75
ATDA74
ATDA73
ATDA72
ATDA71
ATDA70
79
4F
ATDA87
ATDA86
ATDA85
ATDA84
ATDA83
ATDA82
ATDA81
ATDA80
80
50
—
—
—
—
—
—
SRAD1
SRAD0
81
51
—
MSAD2
MSAD1
MSAD0
—
FMTAD2
FMTAD1
FMTAD0
82
52
—
PSVAD2
PSVAD1
PSVAD0
—
BYP2
BYP1
BYP0
83
53
—
—
SEAD6
SEAD5
SEAD4
SEAD3
SEAD2
SEAD1
84
54
—
—
REVAD6
REVAD5
REVAD4
REVAD3
REVAD2
REVAD1
85
55
—
—
MUTAD6
MUTAD5
MUTAD4
MUTAD3
MUTAD2
MUTAD1
86
56
—
—
OVF6
OVF5
OVF4
OVF3
OVF2
OVF1
87
57
ATMDAD
ATSPAD
—
—
—
—
—
OVFP
88
58
ATAD07
ATAD06
ATAD05
ATAD04
ATAD03
ATAD02
ATAD01
ATAD00
89
59
ATAD17
ATAD16
ATAD15
ATAD14
ATAD13
ATAD12
ATAD11
ATAD10
90
5A
ATAD27
ATAD26
ATAD25
ATAD24
ATAD23
ATAD22
ATAD21
ATAD20
91
5B
ATAD37
ATAD36
ATAD35
ATAD34
ATAD33
ATAD32
ATAD31
ATAD30
92
5C
ATAD47
ATAD46
ATAD45
ATAD44
ATAD43
ATAD42
ATAD41
ATAD40
93
5D
ATAD57
ATAD56
ATAD55
ATAD54
ATAD53
ATAD52
ATAD51
ATAD50
94
5E
ATAD67
ATAD66
ATAD65
ATAD64
ATAD63
ATAD62
ATAD61
ATAD60
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9.5.1 Control Register Definitions (Software Mode Only)
The PCM3168A device has many user-programmable functions that are accessed through control registers, and
is programmed through the SPI or I2C serial control port. Table 13 shows the available mode control functions
along with reset default conditions and associated register address. Table 12 lists the register map.
Table 13. User-Programmable Mode Control Functions
RESET DEFAULT
REGISTER
LABEL
Mode control register reset for ADC and DAC operation
FUNCTION
Normal operation
64
MRST
System reset for ADC and DAC operation
Normal operation
64
SRST
Auto
64
SRDA[1:0]
DAC power-save mode selection
Power save
65
PSMDA
DAC master/slave mode selection
Slave
65
MSDA[2:0]
I2S
65
FMTDA[3:0]
Normal operation
66
OPEDA[3:0]
Sharp roll-off
66
FLT[3:0]
Normal
67
REVDA[8:1]
DAC soft mute control
Mute disabled
68
MUTDA[8:1]
DAC zero flag
Not detected
69
ZERO[8:1]
DAC digital attenuation mode
Channel independent
70
ATMDDA
DAC digital attenuation speed
N × 2048/fS
70
ATSPDA
Disabled
70
DEMP[1:0]
DAC zero flag function selection
Independent
70
AZRO[2:0]
DAC zero flag polarity selection
High for detection
70
ZREV
0 dB, no attenuation
71–79
ATDAx[7:0]
ADC sampling mode selection
Auto
80
SRAD[1:0]
ADC master/slave mode selection
Slave
81
MSAD[2:0]
I2S
81
FMTAD[2:0]
ADC power-save control
Normal operation
82
PSVAD[2:0]
ADC HPF bypass control
Normal output, HPF enabled
82
BYP[2:0]
Differential
83
SEAD[6:1]
Normal
84
REVAD[6:1]
ADC soft mute control
Mute disabled
85
MUTAD[6:1]
ADC overflow flag
Not detected
86
OVF[6:1]
Channel independent
87
ATMDAD
ATSPAD
DAC sampling mode selection
DAC audio interface format selection
DAC operation control
DAC digital filter roll-off control
DAC output phase selection
DAC digital de-emphasis function control
DAC digital attenuation level shifting
ADC audio interface format selection
ADC input configuration control
ADC input phase selection
ADC digital attenuation mode
ADC digital attenuation speed
N × 2048/fS
87
ADC overflow flag polarity selection
High for detection
87
OVFP
ADC digital attenuation level setting
0 dB, no gain or attenuation
88–94
ATADx[7:0]
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9.5.2 Register Definitions
Table 14. Register: Reset Control
DEC
64
MRST
HEX
40
B7
MRST
B6
SRST
B5
—
B4
—
B3
—
B2
—
B1
SRDA1
B0
SRDA0
Mode control register reset for the ADC and DAC
This bit sets the mode control register reset to the default value. Pop-noise may be generated. Returning the MRST bit to
1 is unneccesary, because it is automatically set to 1 after the mode control register is reset.
Default value = 1.
MRST
SRST
Mode control register reset
0
Set default value
1
Normal operation (default)
System reset for the ADC and DAC
This bit controls system reset, the relation between system clock and sampling clock re-synchronization, and ADC
operation and DAC operation restart. The mode control register is not reset and the PCM3168A device does not go into a
power-down state. The fade-in sequence is supported in the resume process, but pop-noise may be generated. Returning
the SRST bit to 1 is unneccesary; it is automatically set to 1 after triggering a system reset.
Default value = 1.
SRST
SRDA[1:0]
System reset
0
Resynchronization
1
Normal operation (default)
DAC Sampling mode select
These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is automatically set according
to multiples between the system clock and sampling clock, single rate for 512 fS and 768 fS, dual rate for 256 fS or 384 fS,
and quad rate for 128 fS and 192 fS.
Default value = 00.
SRDA
38
DAC Sampling mode select
00
Auto (default)
01
Single rate
10
Dual rate
11
Quad rate
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Table 15. Register: DAC Control 1
DEC
65
PSMDA
HEX
41
B7
PSMDA
B6
MSDA2
B5
MSDA1
B4
MSDA0
B3
FMTDA3
B2
FMTDA2
B1
FMTDA1
B0
FMTDA0
DAC Power-save mode select
This bit selects the power-save mode for the OPEDA[3:0] function. OPEDA[3:0] is the control of power-save mode and
normal operation for PSMDA = 0, or OPEDA[3:0] works as the control of DAC disable (not power-save mode) and normal
operation for PSMDA = 1.
Default value: 0.
PSMDA
MSDA[2:0]
DAC Power-save mode select
0
Power-save enable mode (default)
1
Power-save disable mode
DAC Master/slave mode select
These bits control the audio interface mode for DAC operation.
Default value: 000 (slave mode).
MSDA
FMTDA[3:0]
DAC Master/slave mode select
000
Slave mode (default)
001
Master mode, 768 fS
010
Master mode, 512 fS
011
Master mode, 384 fS
100
Master mode, 256 fS
101
Master mode, 192 fS
110
Master mode, 128 fS
111
Reserved
DAC Audio interface format select
These bits control the audio interface format for DAC operation. Details of the format, and any related restrictions with the
system clock and master/slave mode, are described in Audio Data Interface Formats and Timing.
Default value: 0000 (24-bit I2S format).
FMTDA
DAC Audio interface format select
0000
24-bit I2S format (default)
0001
24-bit left-justified format
0010
24-bit right-justified format
0011
16-bit right-justified format
0100
24-bit I2S mode DSP format
0101
24-bit left-justified mode DSP format
0110
24-bit I2S mode TDM format
0111
24-bit left-justified mode TDM format
1000
24-bit high-speed I2S mode TDM format
1001
24-bit high-speed left-justified mode TDM format
101x
Reserved
11xx
Reserved
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Table 16. Register: DAC Control 2
DEC
66
OPEDA[3:0]
HEX
42
B7
OPEDA3
B6
OPEDA2
B5
OPEDA1
B4
OPEDA0
B3
FLT3
B2
FLT2
B1
FLT1
B0
FLT0
DAC Operation control
These bits control the DAC operation mode. In operation disable mode, the DAC output is cut off from DIN with a fade-out
sequence, and the internal DAC data is reset. DAC output is forced into VCOMDA if PSMDA = 1, or DAC output is forced
into AGNDDA and goes into a power-down state if PSMDA = 0. For normal operating mode, a fade-in sequence is
applied on the DAC output in resume process. The serial mode control is effective during operation disable mode. A wait
time greater than tDACDLY2 is required for the status change because of power-save control turning on/off.
Default value: 0000.
FLT[3:0]
OPEDA
DAC Operation control
xxx0
DAC1/2 normal operation
xxx1
DAC1/2 operation disable with or without power save
xx0x
DAC3/4 normal operation
xx1x
DAC3/4 operation disable with or without power save
x0xx
DAC5/6 normal operation
x1xx
DAC5/6 operation disable with or without power save
0xxx
DAC7/8 normal operation
1xxx
DAC7/8 operation disable with or without power save
DAC Digital filter roll-off control
The FLT[3:0] bits allow users to select the digital filter roll-off that is best suited to their applications. Sharp and Slow filter
roll-off selections are available. The filter responses for these selections are shown in Typical Characteristics.
Default value: 0000.
40
FLT
DAC Digital filter roll-off control
xxx0
DAC1/2 sharp roll-off
xxx1
DAC1/2 slow roll-off
xx0x
DAC3/4 sharp roll-off
xx1x
DAC3/4 slow roll-off
x0xx
DAC5/6 sharp roll-off
x1xx
DAC5/6 slow roll-off
0xxx
DAC7/8 sharp roll-off
1xxx
DAC7/8 slow roll-off
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Table 17. Register: DAC Output Phase
DEC
67
REVDA[8:1]
HEX
43
B7
REVDA8
B6
REVDA7
B5
REVDA6
B4
REVDA5
B3
REVDA4
B2
REVDA3
B1
REVDA2
B0
REVDA1
DAC Output phase select
The REVDA[8:1] bits are used to control the phase of DAC analog signal outputs.
Default value: 0000 0000.
REVDA
DAC Output phase select3
xxxx xxx0
DAC1 normal output
xxxx xxx1
DAC1 inverted output
xxxx xx0x
DAC2 normal output
xxxx xx1x
DAC2 inverted output
xxxx x0xx
DAC3 normal output
xxxx x1xx
DAC3 inverted output
xxxx 0xxx
DAC4 normal output
xxxx 1xxx
DAC4 inverted output
xxx0 xxxx
DAC5 normal output
xxx1 xxxx
DAC5 inverted output
xx0x xxxx
DAC6 normal output
xx1x xxxx
DAC6 inverted output
x0xx xxxx
DAC7 normal output
x1xx xxxx
DAC7 inverted output
0xxx xxxx
DAC8 normal output
1xxx xxxx
DAC8 inverted output
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Table 18. Register: DAC Soft Mute Control
DEC
68
MUTDA[8:1]
HEX
44
B7
MUTDA8
B6
MUTDA7
B5
MUTDA6
B4
MUTDA5
B3
MUTDA4
B2
MUTDA3
B1
MUTDA2
B0
MUTDA1
DAC Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUT. The Soft Mute
function is incorporated into the digital attenuators.
When Mute is disabled (MUTDA[8:1] = 0), the attenuator and DAC operate normally. When Mute is enabled by setting
MUTDA[8:1] = 1, the digital attenuator for the corresponding output decreases from the current setting to infinite
attenuation with an s-curve response and time set by ATSPDA.
By setting MUTDA[8:1] = 0, the attenuator increases to the last attenuation level with s-curve response in the same
manner as it is for decreasing levels. This configuration provides pop and zipper noise-free muting of the DAC output.
The Soft Mute control uses the same digital attenuation level resource setting as the DAC. Mute control has priority over
the digital attenuation level setting.
Default value: 0000 0000.
MUTDA
42
DAC Soft Mute control
xxxx xxx0
DAC1 Mute disabled
xxxx xxx1
DAC1 Mute enabled
xxxx xx0x
DAC2 Mute disabled
xxxx xx1x
DAC2 Mute enabled
xxxx x0xx
DAC3 Mute disabled
xxxx x1xx
DAC3 Mute enabled
xxxx 0xxx
DAC4 Mute disabled
xxxx 1xxx
DAC4 Mute enabled
xxx0 xxxx
DAC5 Mute disabled
xxx1 xxxx
DAC5 Mute enabled
xx0x xxxx
DAC6 Mute disabled
xx1x xxxx
DAC6 Mute enabled
x0xx xxxx
DAC7 Mute disabled
x1xx xxxx
DAC7 Mute enabled
0xxx xxxx
DAC8 Mute disabled
1xxx xxxx
DAC8 Mute enabled
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Table 19. Register: DAC Zero Flag
DEC
69
ZERO[8:1]
HEX
45
B7
ZERO8
B6
ZERO7
B5
ZERO6
B4
ZERO5
B3
ZERO4
B2
ZERO3
B1
ZERO2
B0
ZERO1
DAC Zero flag (read-only)
These bits indicate the present status of the zero detect circuit for each DAC channel; these bits are read-only.
ZERO
DAC Zero flag
xxxx xxx0
DAC1 zero input not detected
xxxx xxx1
DAC1 zero input detected
xxxx xx0x
DAC2 zero input not detected
xxxx xx1x
DAC2 zero input detected
xxxx x0xx
DAC3 zero input not detected
xxxx x1xx
DAC3 zero input detected
xxxx 0xxx
DAC4 zero input not detected
xxxx 1xxx
DAC4 zero input detected
xxx0 xxxx
DAC5 zero input not detected
xxx1 xxxx
DAC5 zero input detected
xx0x xxxx
DAC6 zero input not detected
xx1x xxxx
DAC6 zero input detected
x0xx xxxx
DAC7 zero input not detected
x1xx xxxx
DAC7 zero input detected
0xxx xxxx
DAC8 zero input not detected
1xxx xxxx
DAC8 zero input detected
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Table 20. Register: DAC Control 3
DEC
70
ATMDDA
HEX
46
B7
ATMDDA
B6
ATSPDA
B5
DEMP1
B4
DEMP0
B3
AZRO2
B2
AZRO1
B1
AZRO0
B0
ZREV
DAC Attenuation mode
This bit controls the DAC attenuation mode. ATDA1[7:0] to ATDA8[7:0] are simply used for ATMDDA = 0, and
ATDA0[7:0] + ATDA1[7:0] to ATDA0[7:0] + ATDA8[7:0] in decibel number are used for ATMDDA = 1.
Default value: 0.
ATMDDA
ATSPDA
DAC Attenuation mode
0
Each channel with independent data (default)
1
All channels with preset (independent) data + master (common) data in decibel number
DAC Attenuation speed
This bit controls the DAC attenuation speed. N × 2048/fS for ATSPDA = 0 and N × 4096/fS for ATSPDA = 1. N is
automatically selected according to the DAC sampling mode, SRDA, N = 1 for single rate, N = 2 for dual rate, and N = 4
for quad rate.
Default value: 0.
ATSPDA
DEMP[1:0]
DAC Attenuation speed
0
N × 2048/fS (default)
1
N × 4096/fS
DAC Digital de-emphasis function/sampling rate control
These bits are used to control the enable/disable and sampling frequency of the digital de-emphasis function.
Default value: 00.
DEMP
AZRO[2:0]
DAC Digital de-emphasis function/sampling rate control
00
Disable (default)
01
48 kHz enable
10
44.1 kHz enable
11
32 kHz enable
DAC Zero flag function select
The AZRO[2:0] bits are used to select the function of the zero flag pin.
Default value: 000.
AZRO
ZREV
DAC Zero flag function select
000
DAC1/2/3/4/5/6/7/8 (8 channel) zero input detect with AND logic (default)
001
DAC1/2/3/4/5/6/7/8 (8 channel) zero input detect with OR logic
010
DAC1/2/3/4/5/6 (6 channel) zero input detect with AND logic
011
DAC1/2/3/4/5/6 (6 channel) zero input detect with OR logic
100
DAC7/8 (2 channel) zero input detect with AND logic
101
DAC7/8 (2 channel) zero input detect with OR logic
11x
Reserved
DAC Zero flag polarity select
This bit controls the polarity of the zero flag pin.
Default value: 0.
ZREV
44
DAC Zero flag polarity select
0
High for zero detect (default)
1
Low for zero detect
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Table 21. Register: DAC Attenuation
DEC
71
72
73
74
75
76
77
78
79
ATDAx[7:0]
HEX
47
48
49
4A
4B
4C
4D
4E
4F
B7
ATDA07
ATDA17
ATDA27
ATDA37
ATDA47
ATDA57
ATDA67
ATDA77
ATDA87
B6
ATDA06
ATDA16
ATDA26
ATDA36
ATDA46
ATDA56
ATDA66
ATDA76
ATDA86
B5
ATDA05
ATDA15
ATDA25
ATDA35
ATDA45
ATDA55
ATDA65
ATDA75
ATDA85
B4
ATDA04
ATDA14
ATDA24
ATDA34
ATDA44
ATDA54
ATDA64
ATDA74
ATDA84
B3
ATDA03
ATDA13
ATDA23
ATDA33
ATDA43
ATDA53
ATDA63
ATDA73
ATDA83
B2
ATDA02
ATDA12
ATDA22
ATDA32
ATDA42
ATDA52
ATDA62
ATDA72
ATDA82
B1
ATDA01
ATDA11
ATDA21
ATDA31
ATDA41
ATDA51
ATDA61
ATDA71
ATDA81
B0
ATDA00
ATDA10
ATDA20
ATDA30
ATDA40
ATDA50
ATDA60
ATDA70
ATDA80
DAC Digital attenuation level setting
Where x = 0 and 1 to 8, corresponding to the DAC channel, DACx (x = 1 to 8).
Each DAC channel (VOUTx) has a digital attenuator function. The attenuation level can be set from 0 dB to –100 dB in
0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target
value is performed by incrementing or decrementing with s-curve responses and a time set by ATSPDA. While an
attenuation level change sequence is in progress, new processing of the attenuation level change for new commands are
ignored; any new commands are overwritten into the command buffer. The last command for the attenuation level change
is performed after the present attenuation level change sequence is finished.
The attenuation level for each channel can be set individually using the following formula; the table below shows
attenuation levels for various settings.
Attenuation level (dB) = 0.5 × (ATDAx[7:0]DEC – 255), where ATDAx[7:0]DEC = 0 through 255 for ATDAx[7:0]DEC = 0
through 54, attenuation is set to infinite attenuation (Mute).
ATDA0[7:0] are used to control all channels at the same time with attenuation data of ATDA0[7:0] + ATDAx[7:0] in decibel
number, when ATMDDA is set to 1. This scheme provides preset and master volume operation.
Default value: 1111 1111.
Decimal value
Attenuation level setting
1111 1111
ATDAx
255
0 dB, no attenuation (default)
1111 1110
254
–0.5 dB
1111 1101
253
–1.0 dB
...
...
1000 0001
129
–63.0 dB
1000 0000
128
–63.5 dB
0111 1111
...
127
–64 dB
...
...
...
0011 1000
56
–99.5 dB
0011 0111
55
–100 dB
0011 0110
54
Mute
...
...
...
0000 0000
0
Mute
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Table 22. Register: ADC Sampling Mode
DEC
80
SRAD[1:0]
HEX
50
B7
—
B6
—
B5
—
B4
—
B3
—
B2
—
B1
SRAD1
B0
SRAD0
ADC Sampling mode select
These bits control the sampling mode of ADC operation. In Auto mode, the sampling mode is automatically set according
to multiples between system clock and sampling clock, single rate for 512 fS and 768 fS, and dual rate for 256 fS and 384
fS.
Default value: 00.
SRAD
ADC Sampling mode select
00
Auto (default)
01
Single rate
10
Dual rate
11
Reserved
Table 23. Register: ADC Control 1
DEC
81
MSAD[2:0]
HEX
51
B7
—
B6
MSAD2
B5
MSAD1
B4
MSAD0
B3
—
B2
FMTAD2
B1
FMTAD1
B0
FMTAD0
ADC Master/slave mode select
These bits control the audio interface mode for ADC operation.
Default value: 000 (slave mode).
MSAD
FMTAD[2:0]
ADC Master/slave mode select
000
Slave mode (default)
001
Master mode, 768 fS
010
Master mode, 512 fS
011
Master mode, 384 fS
100
Master mode, 256 fS
101
Reserved
110
Reserved
111
Reserved
ADC Audio interface format select
These bits control the audio interface format for ADC operation. The format details and restrictions related to the system
clock and master/slave mode are described in Audio Data Interface Formats and Timing.
Default value: 000 (24-bit I2S format).
FMTAD
46
ADC Audio interface format select
000
24-bit I2S format (default)
001
24-bit left-justified format
010
24-bit right-justified format
011
16-bit right-justified format
100
24-bit I2S mode DSP format
101
24-bit left-justified mode DSP format
110
24-bit I2S mode TDM format
111
24-bit left-justified mode TDM format
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Table 24. Register: ADC Control 2
DEC
82
PSVAD[2:0]
HEX
52
B7
—
B6
PSVAD2
B5
PSVAD1
B4
PSVAD0
B3
—
B2
BYP2
B1
BYP1
B0
BYP0
ADC Power-save control
These bits control the ADC power-save mode. In power-save mode, DOUT is forced into ZERO with a fade-out
sequence, the internal ADC data are reset, and the ADC goes into a power-down state. For power-save mode release, a
fade-in sequence is applied on DOUT in resume process. The serial mode control is enabled during this mode. Wait
times greater than tADCDLY2 are required for the status change because of the power-save control turning on/off.
Default value: 000.
BYP[2:0]
PSVAD
ADC Power-save control
xx0
ADC1/2 normal operation
xx1
ADC1/2 power-save mode
x0x
ADC3/4 normal operation
x1x
ADC3/4 power-save mode
0xx
ADC5/6 normal operation
1xx
ADC5/6 power-save mode
ADC HPF bypass control
These bits control the HPF function and dc components of the input signal; internal dc offset is converted in bypass
mode.
Default value: 000.
BYP
ADC HPF bypass control
xx0
ADC1/2 normal output, HPF enabled
xx1
ADC1/2 bypassed output, HPF disabled
x0x
ADC3/4 normal output, HPF enabled
x1x
ADC3/4 bypassed output, HPF disabled
0xx
ADC5/6 normal output, HPF enabled
1xx
ADC5/6 bypassed output, HPF disabled
Table 25. Register: ADC Input Configuration
DEC
83
SEAD[6:1]
HEX
53
B7
—
B6
—
B5
SEAD6
B4
SEAD5
B3
SEAD4
B2
SEAD3
B1
SEAD2
B0
SEAD1
ADC Input configuration control
These bits control the input configuration of each ADC channel, differential or single-ended.
Default value: 00 0000 (all ADC channels have differential inputs).
SEAD
ADC Input configuration
xx xxx0
ADC1 differential input
xx xxx1
ADC1 single-ended input
xx xx0x
ADC2 differential input
xx xx1x
ADC2 single-ended input
xx x0xx
ADC3 differential input
xx x1xx
ADC3 single-ended input
xx 0xxx
ADC4 differential input
xx 1xxx
ADC4 single-ended input
x0 xxxx
ADC5 differential input
x1 xxxx
ADC5 single-ended input
0x xxxx
ADC6 differential input
1x xxxx
ADC6 single-ended input
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Table 26. Register: ADC Input Phase
DEC
84
REVAD[6:1]
HEX
54
B7
—
B6
—
B5
REVAD6
B4
REVAD5
B3
REVAD4
B2
REVAD3
B1
REVAD2
B0
REVAD1
B2
MUTAD3
B1
MUTAD2
B0
MUTAD1
ADC Input phase select
These bits are used to control the phase of analog signal inputs.
Default value: 00 0000.
REVAD
ADC Input phase select
xx xxx0
ADC1 normal input
xx xxx1
ADC1 inverted input
xx xx0x
ADC2 normal input
xx xx1x
ADC2 inverted input
xx x0xx
ADC3 normal input
xx x1xx
ADC3 inverted input
xx 0xxx
ADC4 normal input
xx 1xxx
ADC4 inverted input
x0 xxxx
ADC5 normal input
x1 xxxx
ADC5 inverted input
0x xxxx
ADC6 normal input
1x xxxx
ADC6 inverted input
Table 27. Register: ADC Soft Mute
DEC
85
MUTAD[6:1]
HEX
55
B7
—
B6
—
B5
MUTAD6
B4
MUTAD5
B3
MUTAD4
ADC Soft Mute control
These bits are used to enable or disable the Soft Mute function for the corresponding ADC outputs, DOUT. The Soft Mute
function is incorporated into the digital attenuators.
When Mute is disabled (MUTAD[6:1] = 0), the attenuator and ADC operate normally. When Mute is enabled by setting
MUTAD[6:1] = 1, the digital attenuator for the corresponding output decreases from the current setting to infinite
attenuation with an s-curve responses and time set by ATSPAD.
By setting MUTAD[6:1] = 0, the attenuator increases to the last attenuation level with the s-curve response in same
manner as for decreasing levels. This provides pop and zipper noise-free muting for the ADC input.
The Soft Mute control uses the same digital attenuation level resource setting as the ADC. Mute control has priority over
the digital attenuation level setting.
Default value: 00 0000.
48
MUTAD
ADC Soft Mute control
xx xxx0
ADC1 Mute disabled
xx xxx1
ADC1 Mute enabled
xx xx0x
ADC2 Mute disabled
xx xx1x
ADC2 Mute enabled
xx x0xx
ADC3 Mute disabled
xx x1xx
ADC3 Mute enabled
xx 0xxx
ADC4 Mute disabled
xx 1xxx
ADC4 Mute enabled
x0 xxxx
ADC5 Mute disabled
x1 xxxx
ADC5 Mute enabled
0x xxxx
ADC6 Mute disabled
1x xxxx
ADC6 Mute enabled
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Table 28. Register: ADC Overflow Flag
DEC
86
OVF[6:1]
HEX
56
B7
—
B6
—
B5
OVF6
B4
OVF5
B3
OVF4
B2
OVF3
B1
OVF2
B0
OVF1
ADC Overflow flag (read-only)
These bits indicate the status information of an overflow detect circuit for each ADC channel; these bits are read only. 1
means an overflow has been detected in the past, and reading this register resets all OVF bits.
OVF
ADC Overflow flag
xx xxx0
ADC1 overflow input not detected
xx xxx1
ADC1 overflow input detected
xx xx0x
ADC2 overflow input not detected
xx xx1x
ADC2 overflow input detected
xx x0xx
ADC3 overflow input not detected
xx x1xx
ADC3 overflow input detected
xx 0xxx
ADC4 overflow input not detected
xx 1xx3x
ADC4 overflow input detected
x0 xxxx
ADC5 overflow input not detected
x1 xxxx
ADC5 overflow input detected
0x xxxx
ADC6 overflow input not detected
1x xxxx
ADC6 overflow input detected
Table 29. Register: ADC Control 3
DEC
87
ATMDAD
HEX
57
B7
ATMDAD
B6
ATSPAD
B5
—
B4
—
B3
—
B2
—
B1
—
B0
OVFP
ADC Attenuation mode
This bit controls the ADC attenuation mode. ATAD1[7:0] to ATAD6[7:0] are simply used for ATMDAD = 0, and
ATAD0[7:0] + ATAD1[7:0] to ATAD0[7:0] + ATAD6[7:0] in decibel number are used for ATMDAD = 1.
Default value: 0.
ATMDAD
ATSPAD
ADC Attenuation mode
0
Each channel with independent data (default)
1
All channels with preset (independent) data + master (common) data in decibel number
ADC Attenuation speed
This bit controls the ADC attenuation Speed, N × 2048/fS for ATSPAD = 0 and N × 4096/fS for ATSPAD = 1. N is
automatically selected according to the ADC sampling mode, SRAD: N = 1 for single and N = 2 for dual rate.
Default value: 0.
ATSPAD
OVFP
ADC Attenuation speed
0
N × 2048/fS (default)
1
N × 4096/fS
ADC Overflow flag polarity select
This bit controls the polarity of the overflow flag pin.
Default value: 0.
OVFP
ADC Overflow flag polarity select
0
High for overflow detect (default)
1
Low for overflow detect
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Table 30. Register: ADC Attenuation
DEC
88
89
90
91
92
93
94
ATADx[7:0]
HEX
58
59
5A
5B
5C
5D
5E
B7
ATAD07
ATAD17
ATAD27
ATAD37
ATAD47
ATAD57
ATAD67
B6
ATAD06
ATAD16
ATAD26
ATAD36
ATAD46
ATAD56
ATAD66
B5
ATAD05
ATAD15
ATAD25
ATAD35
ATAD45
ATAD55
ATAD65
B4
ATAD04
ATAD14
ATAD24
ATAD34
ATAD44
ATAD54
ATAD64
B3
ATAD03
ATAD13
ATAD23
ATAD33
ATAD43
ATAD53
ATAD63
B2
ATAD02
ATAD12
ATAD22
ATAD32
ATAD42
ATAD52
ATAD62
B1
ATAD01
ATAD11
ATAD21
ATAD31
ATAD41
ATAD51
ATAD61
B0
ATAD00
ATAD10
ATAD20
ATAD30
ATAD40
ATAD50
ATAD60
ADC Digital attenuation level setting
Where x = 0 and 1 to 6, corresponding to the ADC channel, ADCx (x = 1 to 6).
Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level can be set from 20 dB to –100
dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to
target value is performed by increment or decrement with s-curve response and time set by ATSPAD. While the
attenuation level change sequence is in progress, new processing of an attenuation level change for a new command is
ignored; the new command is overwritten into the command buffer. The last command for an attenuation level change is
performed after the present attenuation level change sequence is finished.
The attenuation level for each channel can be set individually using the following formula, and the above table shows
attenuation levels for various settings.
Attenuation level (dB) = 0.5 × (ATADx[7:0]DEC – 215), where ATADx[7:0]DEC = 0 through 255 for ATADx[7:0]DEC = 0
through 14, attenuation is set to infinite attenuation (Mute).
ATAD0[7:0] is used to control all channels at the same time with attenuation data of ATAD0[7:0] + ATADx[7:0] in decibel
number, though maximum level is limited within +20 dB, when ATMDAD is set to 1. This scheme provides preset and
master volume operation.
Default value: 1101 0111.
Decimal value
Attenuation level setting
1111 1111
ATADx
255
20.0 dB
1111 1110
254
19.5 dB
1111 1101
253
19.0 dB
...
...
1101 1000
216
0.5 dB
1101 0111
215
0 dB, no attenuation (default)
1101 0110
214
–0.5 dB
...
...
...
0001 0000
16
–99.5 dB
0000 1111
15
–100.0 dB
0000 1110
14
Mute
...
...
...
0000 0000
0
Mute
...
50
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
A typical circuit connection for six-channel analog in and eight-channel analog out is shown in Figure 54.
10.2 Typical Application
Digital Audio Processor
5V
0V
C3
C8
+
C4
+
C11
C9
+
+
C10
BCKDA
LRCKDA
DIN4
DIN3
DIN2
DIN1
SCKI
DOUT3
DOUT2
DOUT1
R12
VOUT1-
VIN2-
VOUT2+
VIN3+
VOUT2-
VIN3-
VOUT3+
VIN4+
VOUT3-
VIN4-
VOUT4+
VIN5+
VOUT4-
VIN5-
VOUT5+
VIN6+
VOUT5-
PCM3168A
PCM3168A-Q1
VOUT6-
DGND1
VOUT7+
VDD2
VOUT7-
DGND2
VOUT8+
VCCAD1
VOUT8-
AGNDA1
VCCDA1
VCCAD2
AGNDDA1
AGNDAD2
VREFAD1
VREFAD2
Termination
Analog Output
LPF and Buffer
Analog Output
LPF and Buffer
Analog Output
LPF and Buffer
Analog Output
LPF and Buffer
VOUT6+
VDD1
VCOMAD
Analog Output
LPF and Buffer
VCCDA2
AGNDDA2
VCOMDA
Analog Output
LPF and Buffer
Analog Output
LPF and Buffer
Analog Output
LPF and Buffer
C5
C6
C12
+
ZERO
C2
R11
VOUT1+
VIN6C1
C7
R10
VIN2+
OVF
0V
+
R9
VIN1-
MODE
3.3 V
R8
MC/SCL/FMT
Analog Input
R7
MDI/SDA/DEMP
Analog Input
R6
MDO/ADR1/MD1
Analog Input
R5
MS/ADR0/MD0
Analog Input
R4
RST
Analog Input
R3
BCKAD
VIN1+
Analog Input
R2
LRCKAD
R1
Control MCU
C1 through C6 are 1-μF ceramic capacitors dependent on power-supply quality. C7 and C8 are 10-μF electrolytic capacitors dependent on
power-supply quality. C9 and C10 are 10-μF electrolytic capacitors. C11 and C12 are 10-μF electrolytic capacitors. R1 through R12 are 22-Ω to
100-Ω resistors.
Figure 54. Example Board Layout
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Typical Application (continued)
10.2.1 Design Requirements
For this design example, use the parameters listed in Table 31.
Table 31. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Audio input
PCM audio, differential analog
audio
Audio output
PCM audio, differential analog
audio
Control
I2C, SPI
10.2.2 Detailed Design Procedure
10.2.2.1 Analog Input and Output
It is recommended that input and output filters be used to condition the inputs and outputs. Input filters can be
used to convert a single ended signal into a differential signal while also attenuating out of band noise. Another
use of an input filter for the ADC it to reduce a 2-VRMS signal to a 1-VRMS input, which is the limit of the ADC
input. Output filters can be used to go from differential to single ended, while reducing a differential signal that is
8 VPP to a 2-VRMS signal. The output filter can also attenuate out of band noise.
10.2.2.2 PCM Interface
The PCM3168A has the capability of inputting 8 PCM channels over 4 data pins in normal PCM mode, or can
operate in TDM mode to take in 8 channels on one data pin. The PCM3168A can also output up to 6 PCM
channels over 3 data pins, or over 1 pin in TDM mode.
0
0
-20
-20
-40
-40
Amplitude (dB)
Amplitude (dB)
10.2.3 Application Curves
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
10
20
15
0
Frequency (kHz)
10
15
20
Frequency (kHz)
–1 dB, N = 32768
0 dB, N = 32768
Figure 55. ADC Output Spectrum
52
5
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Figure 56. DAC Output Spectrum
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10.3 System Examples
10.3.1 Typical Circuit Connections
Termination for mode control: Any one of the circuits shown in Figure 57 must be applied according to the
necessary mode or configuration. Resistor value must be 220-kΩ, ±5% tolerant. The PowerPAD must be tied to
the ground plane with enough electrical and thermal conductivity; see the example board layout in Figure 54.
3.3 V
48
3.3 V
48
48
48
(1)
(2)
0V
0V
(3)
(4)
Figure 57. Typical Circuit Connections
Typical interface circuits for analog input and analog output are shown in Figure 58 through Figure 62.
R2
1.5 kW
R2
470 pF
C1
22 pF
1.5 kW
R1
R3
R3
VIN(1 VRMS)
VIN+
(1 VRMS)
4.7 kW
R2
R2
C2
470 pF
C1
10 mF 4.7 kW
+
Analog Input
(2 VRMS)
R2
R1
R3
C2
VIN+
(1 VRMS)
C1
0.1 mF
Analog Input
(2 VRMS)
10 mF
R1
+
VCOMAD
R3
VIN(1 VRMS)
VCOMAD
0.1 mF
Amplifier is an NE5532A x2 or OPA2134 x2; R1 = 1.5-kΩ resistor;
R2 = 750-Ω resistor; R3 = 47-Ω resistor; C1 = 3300-pF capacitor; C2
= 0.01-μF capacitor; Gain = 1; f–3 dB = 45 kHz.
Amplifier is an NE5532A x1 or OPA2134 x1; R1 = 3-kΩ resistor; R2
= 1.5-kΩ resistor; R3 = 47-Ω resistor; C1 = 2200-pF capacitor; C2 =
0.01-μF capacitor; Gain = 1; f–3 dB = 48 kHz.
Figure 58. Single-Ended to Differential Buffer and
Anti-Aliasing LPF For Differential ADC Input
Figure 59. Single-Ended to Differential Buffer and
Anti-Aliasing LPF For Differential ADC Input
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System Examples (continued)
R2
R2
C2
C1
10 mF
R1
R3
VOUT+
(4 VPP)
10 mF
R1
R3
47W
C1
+
C2
VIN+
(1 VRMS)
VOUT(4 VPP)
+
+
Analog Input
(2 VRMS)
10 mF
Analog Output
(2 VRMS)
R3
R1
R2
VIN-
C2
C2
0.1 mF
VCOMAD
Amplifier is an NE5532A x1 or OPA2134 x1; R1 = 3-kΩ resistor; R2
= 1.5-kΩ resistor; R3 = 47-Ω resistor; C1 = 2200-pF capacitor; C2 =
0.022-μF capacitor; Gain = 0.5; f–3 dB = 48 kHz.
Figure 60. Buffer and Anti-Aliasing LPF for SingleEnded ADC Input
R2
47W
C1
R1
1 mF
+
VOUT+
(4 VPP)
Analog Input+
(1 VRMS)
R3
1 mF
R1
VIN(1 VRMS)
+
VOUT(4 VPP)
Figure 61. Post-LPF and Differential to SingleEnded Buffer for DAC Output (AC-Coupled)
Analog Input(1 VRMS)
C2
R1
Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 7.5-kΩ
resistor; R2 = 5.6-kΩ resistor; R3 = 360-Ω resistor; C1 = 3300-pF
capacitor; C2 = 680-pF capacitor; Gain = 0.747; f–3 dB = 53 kHz.
R1
C1
VIN+
(1 VRMS)
Analog Output
(2 VRMS)
R3
R2
C2
Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R1 = 15-kΩ resistor;
R2 = 11-kΩ resistor; R3 = 820-Ω resistor; C1 = 1500-pF capacitor; C2
= 330-pF capacitor; Gain = 0.733; f–3 dB = 54 kHz.
Figure 62. Post-LPF and Differential to SingleEnded Buffer for DAC Output (DC-Coupled)
Figure 63. Basic Differential Input Circuit With AntiAliasing LPF for Differential ADC Input
11 Power Supply Recommendations
The PCM3168A requires a 5-V and 3.3-V nominal supply rail. The 3.3-V supply rail is needed for VDD1 and
VDD2. The 5-V supply rail is needed for VCCAD1, VCCAD2, VCCDA1, and VCCDA2. The decoupling capacitors
for the power supplies should be placed close to the device terminals.
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12 Layout
12.1 Layout Guidelines
12.1.1 Power-Supply Pins (VCCAD1/2, VCCDA1/2, and VDD1/2)
The digital and analog power-supply pins of the PCM3168A device should be bypassed to the corresponding
ground pins with 1-μF ceramic capacitors placed as close to the pins as possible. Each power-supply line (VCC
and VDD) to the PCM3168A device should be bypassed to the corresponding ground pins with 10-μF electrolytic
capacitors to maximize the dynamic performance of the ADC and DAC.
Although the PCM3168A device has two power lines to maximize the potential of dynamic performance, using
one common source (for instance, a 5-V power supply for VCC and a 3.3-V power supply for VDD generated from
one common source) is recommended to avoid unexpected power-supply trouble such as latch-up or incorrect
power-supply conditions. Also, simultaneous power-on/off of VCC and VDD is recommended to avoid unexpected
transient responses in outputs, though the power-supply sequence of VCC and VDD is not specified in the
operation and absolute maximum ratings point of view.
12.1.2 Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2)
To maximize the dynamic performance of the PCM3168A device, the analog and digital grounds are not
connected internally. These pins should have very low impedances to avoid digital noise and signal components
feeding back into the analog ground. All ground pins should be connected directly to each other under the part,
and the device should be connected to the analog ground of the application, as with acceptable analog layout
practices; this layout reduces the potential of noise problems.
12.1.3 VIN1±, VIN2±, VIN3±, VIN4±, VIN5±, and VIN6± Pins
In case of direct interface to VINx±, 1-μF electrolytic capacitors are recommended because the ac-coupling
capacitor (which gives a 2-Hz HPF corner frequency and 47-Ω and 0.1-μF to 470-Ω and 0.001-μF differential
LPF) is recommended as the anti-aliasing filter that gives a 160-kHz LPF corner frequency. If signal source
impedance is not enough (too low) or input line length to the VINx± is not enough (too short), insertion of an
analog front-end buffer (see Figure 58 to Figure 60) is recommended to maximize the dynamic performance. The
voltage coefficient of the capacitor for an anti-aliasing filter should be considered to maximize the THD
performance. A film-type capacitor is recommended; if a ceramic capacitor is used, a relatively higher voltage
type is recommended.
There are three ways to terminate any unused input pins. First, terminate these pins to AGNDAD with 0.001-μF
to 1-μF capacitors. This termination is applied on unused pins whose channels are configured in single-ended
mode. The second form of termination is to connect the positive (+) pin and negative (–) pins together and
terminating these to AGNDAD with 0.001-μF to 1-μF capacitors. This option applies to unused pins with channels
that are configured in differential mode. The last termination method is to terminate the pins directly to VCOMAD;
this option can be applied on unused pins with unused channels combined into two channels that are then
configured in power-save mode.
12.1.4 VCOMAD and VCOMDA Pins
10-μF electrolytic capacitors are recommended between VCOMAD and AGNDAD, and VCOMDA and AGNDDA
to ensure a low source impedance of ADC and DAC common voltages. These capacitors should be located as
close to each pin as possible to reduce dynamic errors on the ADC and DAC common voltages.
12.1.5 VREFAD1/2 Pins
10-μF electrolytic capacitors are recommended between VREFAD1/2 and AGNDAD to ensure low source
impedances of ADC references. These capacitors should be located as close to each pin as possible to reduce
dynamic errors on ADC references.
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Layout Guidelines (continued)
12.1.6 VOUT1±, VOU2±, VOUT3±, VOUT4±, VOUT5±, VOUT6±, VOUT7±, and VOUT8± Pins
The differential to single-ended buffer with post LPF can be directly connected (without capacitors) to these
output pins (see Figure 62), thereby minimizing the use of coupling capacitors for the 2-VRMS outputs. The op
amp and resistors must be determined with consideration of degrading some performance through this
differential to single-ended and LPF buffer; there is about 1.5-dB degradation seen in the examples of Figure 61
and Figure 62.
12.1.7 MODE Pin
This pin is a logic input with quad-state input capability. The MODE pin is high when connected to VDD, low when
connected to DGND, and pulled up or pulled down through an external resistor and for the two mid-states in
order to distinguish the four input states. The pull-up or pull-down resistor must be 220 kΩ, ±5% in tolerance.
Note that the state of the MODE pin is only sampled by a power-on or a low-to-high transition of the RST pin.
12.1.8 RST Pin
When the MODE pin setting changes to change the operating mode, the new mode setting does not take effect
immediately; a RST pin toggle is required to make the new mode setting valid, and for the new mode to take
effect.
12.1.9 OVF Pin
The OVF pin has two functions. It is primarily the flag for ADC overflow occurrence detection. It is also used to
indicate that the internal reset sequence is complete and that the device is ready to enter serial mode control.
12.1.10 System Clock and Audio Interface Clocks
The quality of SCKI may influence dynamic performance, because the PCM3168A device (both the ADC and
DAC) operates based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise and fall time of
the system clock.
In slave mode, the PCM3168A device does not require a specific timing relationship between BCKAD/LRCKAD
and SCKI, and BCKDA/LRCKDA and SCKI; however, there is a possibility of performance degradation with a
certain timing relationship between them. In that case, specific timing relationship control might resolve this
performance degradation.
In master mode, there is a possibility of performance degradation because of heavy loads on BCKAD/LRCKAD,
BCKDA/LRCKDA, and DOUT1/2/3. It is recommended to load these pins as lightly as possible. Note that all
output clocks and signals go low; they do not go into a high-impedance state during power-save mode.
12.1.11 PowerPAD
The PowerPAD of the PCM3168A device is internally connected to the substrate of the silicon. It should be
connected to the ground plane with sufficient low conductance in electrical and thermal; see Figure 54. The
PowerPAD size is 7.25 mm x 7.00 mm (0.725 cm × 0.7 cm).
12.1.12 External Mute Control
For power-down ON/OFF control without the pop-noise that is generated by a DC level change on the DAC
output, the external mute control is generally required. Use of the following control sequence is recommended:
external mute ON, codec power-down ON, SCKI stop and resume if necessary, codec power-down OFF, and
external mute OFF control.
56
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12.2 Layout Example
It is recommended to place a top layer ground pour for
shielding around PCM3168 and connect to lower main PCB
ground plane by multiple vias
Resistors on PCM audio interfaces are for
reducing reflections of high frequency
signals if needed. These resistors should
be between 22 Q v 100 Q
Analog Inputs
+5V
10 F
+ +
Analog Inputs
10 F
10 F
55
54
VIN5-
VREFAD2
AREFAD1
VIN4+
VIN4-
VIN3+
VIN3-
VIN2+
1
VCOMAD
2
AGNDAD2
3
VCCAD2
4
53
52
51
50
49
VCCAD1
56
AGNDAD1
57
VIN1-
58
VIN2-
59
VIN1+
60
See Mode Pin in Layout
Guidelines for configuration
MODE
48
DGND1
47
VDD1
46
RST
MS,ADR0,MD0
45
5
OVF
MDO,ADR1,MD1
44
6
LRCKAD
MDI,SDA,DEMP
43
1 F
10 F
+5V
PCM Audio
Output
Interface
1 F
7
BCKAD
MC,SCL,FMT
42
8
DOUT1
SCKI
41
9
DOUT2
DIN4
40
10
DOUT3
DIN3
39
11
DGND2
DIN2
38
12
VDD2
DIN1
37
13
ZERO
BCKDA
36
14
VCCDA1
LRCKDA
35
15
VCOMDA
VCCDA2
34
PCM3168
+3.3V
+5V
10 F
+3.3V
Serial and
Hardware
Control
Interface
PCM Audio
Input
Interface
1 F
10 F
1 F
24
VOUT1+
23
25
26
27
28
29
30
31
AGNDDA2
VOUT1-
22
VOUT2-
21
VOUT2+
VOUT5-
20
VOUT3-
VOUT5+
19
VOUT3+
VOUT6-
18
VOUT4+
VOUT6+
17
VOUT4-
VOUT7-
16
VOUT7+
10 F
AGNDDA1
VOUT8-
+
VOUT8+
10 F
61
VIN6-
+
62
VIN5+
10 F
63
VIN6+
1 F
64
33
+5V
1 F
10 F
32
Analog Outputs
Top Layer Ground Pour and PowerPad
Top Layer Signal Traces
Pad to top layer ground pour
Figure 64. PCM3168A Board Layout
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Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: PCM3168A
57
PCM3168A
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
www.ti.com
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation, refer to the following:
• PCM3168PAP IBIS Model Analog & Mixed-Signal (SLAC203)
• PurePath™ Console Motherboard User's Guide (SLOU366)
13.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
PowerPAD is a trademark of Texas Instruments Incorporated.
SPI is a trademark of Motorola.
I2C, I2S are trademarks of NXP Semiconductors.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
58
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Copyright © 2008–2016, Texas Instruments Incorporated
Product Folder Links: PCM3168A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM3168APAP
ACTIVE
HTQFP
PAP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
PCM3168A
PCM3168APAPR
ACTIVE
HTQFP
PAP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
PCM3168A
PCM3168APAPRG4
ACTIVE
HTQFP
PAP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
PCM3168A
PCM3168ATPAPQ1
ACTIVE
HTQFP
PAP
64
160
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
PCM3168AQ1
PCM3168ATPAPRQ1
ACTIVE
HTQFP
PAP
64
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
PCM3168AQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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