SBAS290B − JULY 2003 − SEPTEMBER 2004
High-Performance 24-Bit, 216kHz Sampling
Stereo Audio Analog-to-Digital Converter
FEATURES
D Two High-Performance Delta-Sigma
D
D
D
D
D
D
D
D
D
Analog-to-Digital Converters
− 24-Bit Linear PCM or 1-Bit Direct Stream
Digital (DSD) Output Data
− Supports PCM Output Sampling Rates up
to 216kHz
− Supports 64fS and 128fS DSD Output Data
Rates
Dynamic Performance: PCM Output
− Dynamic Range (VIN = −60dBFS,
fIN = 1kHz, A-Weighted): 118dB
− THD+N (VIN = −0.5dB, fIN = 1kHz): −105dB
Dynamic Performance: DSD Output, 64fS
− Dynamic Range (A-Weighted): 115dB
− THD+N (VIN = −0.5dB, fIN = 1kHz): −102dB
Audio Serial Port
− 24-Bit Linear PCM Output Data
− Master or Slave Mode Operation
− Supports Left-Justified, Right-Justified,
and I2SE Data Formats
Additional PCM Output Features:
− Linear-Phase Digital Decimation Filter
− Digital High-Pass Filter for DC Removal
− Clipping Flag Output for Each Channel
Power Supplies: +5V Analog and +3.3V Digital
Power Dissipation:
− fS = 48kHz: 308mW typical
− fS = 96kHz: 338mW typical
− fS = 192kHz: 318mW typical
Power-Down Mode
Available in a SSOP-28 Package
Pin- and Function-Compatible with the
PCM1804
APPLICATIONS
D Digital Recorders and Mixing Desks
D Digital Audio Effects Processors
D Broadcast Studio Equipment
D Surround-Sound Encoders
D High-End A/V Receivers
DESCRIPTION
The PCM4202 is a high-performance, stereo audio
analog-to-digital (A/D) converter designed for professional
and broadcast audio applications. The PCM4202
architecture utilizes a 1-bit delta-sigma modulator per
channel, incorporating a novel density modulated dither
scheme for improved dynamic performance.
The PCM4202 supports 24-bit linear PCM output data,
with sampling frequencies up to 216kHz. The PCM4202
can also be configured to output either 64x or 128x
oversampled, 1-bit direct stream digital (DSD) data for
each channel. Support for PCM and DSD output formats
makes the PCM4202 suitable for a variety of digital audio
recording and processing applications.
The PCM4202 includes a flexible audio serial port interface, which supports standard audio data formats. Audio
data format selection, sampling mode configuration, and
high-pass filter functions are all programmed using dedicated control pins.
The PCM4202 operates from a +5V analog power supply
and a +3.3V digital power supply. The digital I/O pins are
compatible with +3.3V logic families. The PCM4202 is
available in a small SSOP-28 package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2S is a registered trademark of Royal Philips Electronics B.V., The Netherlands. All other trademarks are the property of their respective owners.
Copyright 2003−2004, Texas Instruments Incorporated
! " #$
% $ %
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SBAS290B − JULY 2003 − SEPTEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PCM4202
UNIT
VCC
VDD
+6.0
V
Supply voltage
+3.6
V
Ground voltage differences
(any AGND to DGND)
±0.1
V
Digital input voltage
FMT0, FMT1, S/M, FS0, FS1, FS2, SCKI,
RST, HPFD, BCK, LRCK
−0.3 to (VDD + 0.3)
V
Analog input voltage
VINL+, VINL−, VINR+, VINR−
−0.3 to (VCC + 0.3)
V
±10mA
V
−10 to +70
°C
Input current (any pin except supplies)
Operating temperature range
Storage temperature range, TSTG
−65 to +150
°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this
datasheet.
PIN ASSIGNMENT
VREFL
1
28
VREFR
AGNDL
2
27
AGNDR
VCOML
3
26
VCOMR
VINL+
4
25
VINR+
VINL−
5
24
VINR−
FMT0
6
23
AGND
FMT1
7
22
VCC
PCM4202
2
S/M
8
21
CLIPL
FS0
9
20
CLIPR
FS1
10
19
RST
FS2
11
18
SCKI
HPFD
12
17
LRCK or DSDBCK
DGND
13
16
BCK or DSDL
VDD
14
15
DATA or DSDR
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SBAS290B − JULY 2003 − SEPTEMBER 2004
Terminal Functions
TERMINAL
PIN NO.
NAME
I/O
1
Output
Left Channel Voltage Reference
2
VREFL
AGNDL
DESCRIPTION
Ground
Left Channel Reference Ground
3
VCOML
Output
Left Channel DC Common-mode Voltage, +2.5V Typical
4
VINL+
Input
Left Channel Non-inverting Analog Input
5
VINL−
Input
Left Channel Inverting Analog Input
6
FMT0
Input
Audio Data Format Selection
7
FMT1
Input
Audio Data Format Selection
8
S/M
Input
Audio Serial Port Slave/Master Mode Selection (0 = Master, 1 = Slave)
9
FS0
Input
Sampling Mode Selection
10
FS1
Input
Sampling Mode Selection
11
FS2
Input
Sampling Mode Selection
12
HPFD
Input
High-pass Filter Disable (Active High)
13
DGND
Ground
Digital Ground
14
VDD
Power
Digital Power Supply, +3.3V
15
DATA
or DSDR
Output
Audio Serial Port Left and Right Channel PCM Data
or Right Channel DSD Data
16
BCK
or DSDL
I/O
Audio Serial Port Bit (or Data) Clock
or Left Channel DSD Data Output
17
LRCK
or DSDBCK
I/O
Audio Serial Port Left/Right (or Word) Clock
or DSD Data Clock Output
18
SCKI
Input
System Clock
19
RST
Input
Reset/Power-down (Active Low with internal pull-up)
20
CLIPR
Output
Right Channel Clipping Flag (Active High)
21
CLIPL
Output
Left Channel Clipping Flag (Active High)
22
VCC
Power
Analog Power Supply, +5V
23
AGND
Ground
Analog Ground
24
VINR−
Input
Right Channel Inverting Analog Input
25
VINR+
Input
Right Channel Non-inverting Analog Input
26
VCOMR
Output
Right Channel DC Common-mode Voltage, +2.5V Typical
27
AGNDR
Ground
Right Channel Reference Ground
28
VREFR
Output
Right Channel Voltage Reference
3
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
PCM4202
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
MAX
24
UNITS
Bits
AUDIO DATA FORMAT
Linear PCM interface formats
I2S, Left or Right Justified
Two’s complement, MSB first data
Linear PCM word length
24
Bits
Direct Stream Digital (DSD) output
1
Bit
DIGITAL CHARACTERISTICS
Input logic level
Output logic level
Input current
Input current(1)
VIH
0.7 x VDD
VDD
V
VIL
0
0.3 x VDD
V
VOH
IOH = −2mA
VOL
IOL = +2mA
0.2 x VDD
V
IIH
VIN = VDD
+10
µA
IIL
VIN = 0V
−10
µA
IIH
VIN = VDD
+25
µA
IIL
fS
−25
µA
8
54
kHz
Dual rate
54
108
kHz
Quad rate
108
216
kHz
55
%
System clock duty cycle
System clock frequency(2)
V
VIN = 0V
Single rate
Sampling frequency(2)
0.8 x VDD
45
50
Single rate, SCKI = 256fS
2.048
13.824
MHz
Single rate, SCKI = 384fS
3.072
20.736
MHz
Single rate, SCKI = 512fS
4.096
27.648
MHz
Single rate, SCKI = 768fS
6.144
38.4
MHz
Dual rate, SCKI = 256fS
13.824
27.648
MHz
Dual rate, SCKI = 384fS
20.736
38.4
MHz
Quad rate, SCKI = 128fS
13.824
27.648
MHz
Quad rate, SCKI = 192fS
20.736
38.4
MHz
ANALOG OUTPUTS
Input voltage, full-scale
6.0
VPP
Input impedance
Differential input
3
kΩ
Common-mode rejection
85
dB
DC PERFORMANCE
±4
% of FSR
Gain error
±4
% of FSR
Gain mismatch channel-to-channel
±3
% of FSR
Output offset error
HPFD = 1
(1) Applies to the RST input, pin 19.
(2) Single, Dual, and Quad Rate sampling modes are described within this data sheet.
(3) Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The
measurement bandwidth is limited by using the Audio Precision 22Hz high-pass filter in combination with the Audio Precision 20kHz, fS/2, or
a user-defined 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination
with the previously mentioned filters.
4
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
PCM4202
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
−105
−95
dB
DYNAMIC PERFORMANCE(3)
fS = 48kHz, Single Rate
Total harmonic distortion + noise
BW = 20Hz to 20kHz
THD+N
Dynamic range
VIN = −0.5dBFS, fIN = 1kHz
VIN = −60dBFS, fIN = 1kHz, A-Weighted
Dynamic range, no weighting
118
dB
116
dB
120
dB
VIN = −0.5dBFS, fIN = 1kHz
−105
dB
VIN = −60dBFS, fIN = 1kHz, A-Weighted
118
dB
VIN = −60dBFS, fIN = 1kHz
112
dB
120
dB
−103
dB
VIN = 0VRMS, A-Weighted
117
dB
VIN = 0VRMS
108
dB
120
dB
−102
dB
Channel separation
100
fS = 96kHz, Dual Rate
Total harmonic distortion + noise
BW = 20Hz to 40kHz
THD+N
Dynamic range
Dynamic range, no weighting
Channel separation
fS = 192kHz, Quad Rate
Total harmonic distortion + noise
BW = 20Hz to 40kHz
THD+N
Dynamic range
Dynamic range, no weighting
VIN = −0.5dBFS, fIN = 1kHz
Channel separation
DSD Output, 64fS Rate
Total harmonic distortion + noise
DSDBCK = 2.8224MHz
THD+N
Dynamic range
VIN = −0.5dBFS, fIN = 1kHz
VIN = −60dBFS, fIN = 1kHz, A-Weighted
115
dB
120
dB
VIN = −0.5dBFS, fIN = 1kHz
−105
dB
VIN = −60dBFS, fIN = 1kHz, A-Weighted
118
dB
120
dB
Channel separation
DSD Output, 128fS Rate
Total harmonic distortion + noise
Dynamic range
Channel separation
112
VIN = −60dBFS, fIN = 1kHz
DSDBCK = 5.6448MHz
THD+N
(1) Applies to the RST input, pin 19.
(2) Single, Dual, and Quad Rate sampling modes are described within this data sheet.
(3) Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The
measurement bandwidth is limited by using the Audio Precision 22Hz high-pass filter in combination with the Audio Precision 20kHz, fS/2, or
a user-defined 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination
with the previously mentioned filters.
5
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise
noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode.
PCM4202
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL DECIMATION FILTER
Passband edge
Single and Dual Rate
0.453fS
Hz
Passband ripple
Single and Dual Rate
±0.005
dB
Passband edge
Single and Dual Rate
0.547fS
Hz
Stop band attenuation
Single and Dual Rate
−100
dB
Group delay
Single and Dual Rate
37/fS
sec
Passband edge (−0.005dB)
Quad Rate
0.375fS
Hz
−3dB cutoff frequency
Quad Rate
0.490fS
Hz
Passband ripple
Quad Rate
Passband edge
Quad Rate
0.770fS
Stop band attenuation
Quad Rate
−135
Group delay
Quad Rate
±0.005
dB
Hz
dB
9.5/fS
sec
fS/48000
Hz
DIGITAL HIGH PASS FILTER
Frequency response (−3dB)
POWER SUPPLY
Voltage range
VCC
+4.75
+5.0
+5.25
VDC
+3.0
+3.3
+3.6
VDC
fS = 48kHz, Single Rate
55
65
mA
fS = 96kHz, Dual Rate
55
65
mA
fS = 192kHz, Quad Rate
55
65
mA
fS = 48kHz, Single Rate
10
12
mA
fS = 96kHz, Dual Rate
19
25
mA
fS = 192kHz, Quad Rate
13
15
mA
VDD
Operating supply current
VCC = +5V, VDD = +3.3V
IDD
Power-down mode current
Total power dissipation
VCC = +5V, VDD = +3.3V
VCC = +5V, VDD = +3.3V, RST = 0
ICC
Clocks applied
10
mA
IDD
Clocks applied
2
mA
VCC = +5V, VDD = +3.3V
fS = 48kHz, Single Rate
308
365
mW
fS = 96kHz, Dual Rate
338
408
mW
fS = 192kHz, Quad Rate
318
375
mW
(1) Applies to the RST input, pin 19.
(2) Single, Dual, and Quad Rate sampling modes are described within this data sheet.
(3) Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. The
measurement bandwidth is limited by using the Audio Precision 22Hz high-pass filter in combination with the Audio Precision 20kHz, fS/2, or
a user-defined 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination
with the previously mentioned filters.
6
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SBAS290B − JULY 2003 − SEPTEMBER 2004
TYPICAL CHARACTERISTICS
At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
OVERALL CHARACTERISTICS
SINGLE RATE FILTER
STOP BAND ATTENUATION CHARACTERISTICS
SINGLE RATE FILTER
50
0
Normalized Frequency (fS )
Amplitude (dB)
fS = 48 kHz
−50
−100
−150
−200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
4.0
fS = 48 kHz
0
TRANSIENT BAND CHARACTERISTICS
SINGLE RATE FILTER
0
0.02
fS = 48kHz
−1
fS = 48kHz
−2
Amplitude (dB)
0
Amplitude (dB)
1
0.75
Normalized Frequency (f S)
PASSBAND RIPPLE CHARACTERISTICS
SINGLE RATE FILTER
−0.02
−0.04
−0.06
−3
−4
−5
−6
−7
−8
−0.08
−9
−10
0.45
−0.1
0
0.2
0.1
0.4
0.3
0.6
0.5
0.47
Normalized Frequency (fS)
fS = 96kHz
Amplitude (dB)
0
−50
−100
−150
−200
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Normalized Frequency (fS )
0.51
0.53
0.55
STOP BAND ATTENUATION CHARACTERISTICS
DUAL RATE FILTER
50
0
0.49
Normalized Frequency (fS)
OVERALL CHARACTERISTICS
DUAL RATE FILTER
Amplitude (dB)
0.5
0.25
Normalized Frequency (f S)
1.6
1.8
2.0
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
fS = 96kHz
0
0.5
0.75
0.25
Normalized Frequency (f S)
1
7
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SBAS290B − JULY 2003 − SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
TRANSIENT BAND CHARACTERISTICS
DUAL RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
DUAL RATE FILTER
0
0.02
−2
Amplitude (dB)
0
Amplitude (dB)
f S = 96kHz
−1
fS = 96kHz
−0.02
−0.04
−0.06
−3
−4
−5
−6
−7
−8
−0.08
−9
−10
0.45
−0.1
0
0.2
0.1
0.4
0.3
0.6
0.5
0.47
0.49
OVERALL CHARACTERISTICS
QUAD RATE FILTER
fS = 192kHz
Amplitude (dB)
Amplitude (dB)
0
−50
−100
−150
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
1
0
0.5
0.75
0.25
Normalized Frequency (f S)
1
TRANSIENT BAND CHARACTERISTICS
QUAD RATE FILTER
PASSBAND RIPPLE CHARACTERISTICS
QUAD RATE FILTER
0
0.02
−1
fS = 192kHz
0
fS = 192kHz
−2
Amplitude (dB)
Amplitude (dB)
0.55
fS = 192kHz
Normalized Frequency (fS)
−0.02
−0.04
−0.06
−3.90dB at 0.5f S
−3
−4
−5
−6
−7
−8
−0.08
−9
−0.1
0
0.1
0.2
0.3
0.4
Normalized Frequency (fS )
8
0.53
STOP BAND ATTENUATION CHARACTERISTICS
QUAD RATE FILTER
50
−200
0.51
Normalized Frequency (fS)
Normalized Frequency (fS )
0.5
0.6
−10
0.45
0.47
0.49
0.51
Normalized Frequency (fS)
0.53
0.55
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SBAS290B − JULY 2003 − SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
HIGH PASS FILTER
PASSBAND CHARACTERISTICS
5
0.02
−20
0
Amplitude (dB)
Amplitude (dB)
HIGH PASS FILTER
STOP BAND CHARACTERISTICS
−40
−60
−80
−0.06
−0.1
0
0.1
0.2
0.3
0.4
0
0.5
1
1.5
2
2.5
3
Normalized Frequency (fS/1000)
Normalized Frequency (fS /1000)
FFT PLOT
(fS = 48kHz, fIN = 997Hz at −20dB)
FFT PLOT
(fS = 48kHz, fIN = 997Hz at −60dB)
0
0
−20
−20
−40
−40
−60
−60
−80
Amplitude (dB)
Amplitude (dB)
−0.04
−0.08
−100
−100
−120
−140
−160
3.5
4
10k
20k
−80
−100
−120
−140
−160
−180
−180
20
100
1k
10k
20k
20
100
1k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
(fS = 48kHz, No Input [Idle])
FFT PLOT
(fS = 96kHz, fIN = 997Hz at −20dB)
0
0
−20
−20
−40
−40
−60
−60
−80
−80
Amplitude (dB)
Amplitude (dB)
−0.02
−100
−120
−140
−160
−100
−120
−140
−160
−180
−180
20
100
1k
Frequency (Hz)
10k
20k
20
100
1k
10k
40k
Frequency (Hz)
9
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SBAS290B − JULY 2003 − SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
FFT PLOT
(fS = 96kHz, No Input [Idle])
0
0
−20
−20
−40
−40
−60
−60
−80
−80
Amplitude (dB)
Amplitude (dB)
FFT PLOT
(fS = 96kHz, fIN = 997Hz at −60dB)
−100
−120
−140
−160
100
1k
10k
40k
20
100
1k
10k
Frequency (Hz)
Frequency (Hz)
FFT PLOT
(fS = 192kHz, fIN = 997Hz at −20dB)
FFT PLOT
(fS = 192kHz, fIN = 997Hz at −60dB)
0
0
−20
−20
−40
−40
−60
−60
−80
Amplitude (dB)
Amplitude (dB)
−140
−180
20
−100
−120
−140
−160
40k
−80
−100
−120
−140
−160
−180
−180
20
100
1k
10k
100k
20
10k
100k
FFT PLOT
(fS = 192kHz, No Input [Idle])
THD+N vs AMPLITUDE
(fS = 48kHz, f IN = 1kHz, BW = 10Hz to 20kHz)
−40
−60
THD+N (dB)
−80
−100
−120
−140
−160
−180
100
1k
Frequency (Hz)
0
20
100
Frequency (Hz)
−20
Amplitude (dB)
−120
−160
−180
1k
Frequency (Hz)
10
−100
10k
100k
−90
−92
−94
−96
−98
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
−140
−120
−100
−80
−60
Input Amplitude (dB)
−40
−20
0
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SBAS290B − JULY 2003 − SEPTEMBER 2004
TYPICAL CHARACTERISTICS (continued)
At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted.
THD+N (dB)
−90
−92
−94
−96
−98
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
100
1k
10k
20k
−120
−100
−80
−60
−40
−20
Input Amplitude (dB)
THD+N vs FREQUENCY
(fS = 96kHz, Input Amplitude = −0.5dB,
BW = 10Hz to 40kHz)
THD+N vs AMPLITUDE
(fS = 192kHz, f IN = 1kHz, BW = 10Hz to 40kHz)
−90
−92
−94
−96
−98
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
20
−90
−92
−94
−96
−98
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
−140
THD+N vs AMPLITUDE
(fS = 96kHz, fIN = 1kHz, BW = 10Hz to 40kHz)
Input Frequency (Hz)
THD+N (dB)
THD+N (dB)
20
100
1k
10k
40k
−90
−92
−94
−96
−98
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
−140
−120
−100
−80
−60
−40
−20
0
0
Input Amplitude (dB)
Input Frequency (Hz)
THD+N vs FREQUENCY
(fS = 192kHz, Input Amplitude = −0.5dB,
BW = 10Hz to 40kHz)
THD+N (dB)
THD+N (dB)
THD+N vs FREQUENCY
(f S = 48kHz, Input Amplitude = −0.5dB,
BW = 10Hz to 20kHz)
−90
−92
−94
−96
−98
−100
−102
−104
−106
−108
−110
−112
−114
−116
−118
−120
20
100
1k
10k
80k
Input Frequency (Hz)
11
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SBAS290B − JULY 2003 − SEPTEMBER 2004
PRODUCT OVERVIEW
The PCM4202 is a high-performance, stereo audio
analog-to-digital (A/D) converter designed for use in
professional and broadcast audio applications. The
PCM4202 features 24-bit linear PCM or 1-bit Direct
Stream Digital (DSD) data output capability for both
channels. Sampling rates up to 216kHz are supported for
PCM output formats, while 64x or 128x oversampled 1-bit
data is supported for DSD output mode. Native support for
both PCM and DSD data formats makes the PCM4202
ideal for use in a wide variety of audio recording and
processing applications.
The PCM4202 features 1-bit delta-sigma modulators
employing density modulated dither for improved dynamic
performance. Differential voltage inputs are utilized for the
modulators, providing excellent common-mode rejection.
On-chip voltage references are provided for the
VINR+
VINR−
Delta−Sigma
Modulator
Decimation
Filter
modulators, in addition to generating DC common-mode
bias voltage outputs for use with external input circuitry.
Linear phase digital decimation filtering is provided for the
24-bit PCM data outputs, with a minimum stop band
attenuation of −100dB for all sampling modes.
The PCM output mode features clipping flag outputs for
each channel, as well as a digital high-pass filter for DC
removal. The PCM4202 may be configured using
dedicated input pins for sampling mode and audio data
format selection, high-pass filter enable/disable, and
reset/power-down operation.
A +5V power supply is required for the analog section of
the device, while a +3.3V power supply is required for the
digital circuitry. Figure 1 shows the functional block
diagram for the PCM4202.
LRCK
or DSDBCK
HPF
BCK
or DSDL
VCOMR
AGNDR
VREFR
VREFL
AGNDL
DATA
or DSDR
Voltage
Reference
Audio
Serial
Port
Voltage
Reference
CLIPR
CLIPL
VCOML
S/M
FMT0
VINL−
VINL+
Delta−Sigma
Modulator
Decimation
Filter
FMT1
HPF
HPFD
FS0
Reset
Logic
Power
Clock
Control
FS1
FS2
SCKI
RST
VCC
AGND
VDD
DGND
Figure 1. PCM4202 Functional Block Diagram
12
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SBAS290B − JULY 2003 − SEPTEMBER 2004
ANALOG INPUTS
The PCM4202 includes two channels of A/D conversion,
each with its own pair of differential voltage input pins. The
VINL+ (pin 4) and VINL− (pin 5) inputs correspond to Left
channel input, while VINR+ (pin 25) and VINR− (pin 24)
correspond to the Right channel input. The average input
impedance of each input pin is 3kΩ.
Each analog input pair accepts a full-scale input voltage of
approximately 6.0VPP differential, which corresponds to a
2.12VRMS or +8.75dBu input swing. The analog input
should not swing below analog ground or above the VCC
power supply by more than 300mV. Refer to the
Applications Information section of this datasheet for an
example input buffer circuit.
VOLTAGE REFERENCES AND COMMON MODE
BIAS VOLTAGE OUTPUTS
The PCM4202 includes two on-chip voltage references,
one each for the Left and Right channels. The VREFL (pin
1) and VREFR (pin 28) outputs correspond to high
reference outputs for Left and Right channels,
respectively. De-coupling capacitors are connected
between each of these pins and the corresponding
reference ground pin, either AGNDL (pin 2) for the VREFL
output or AGNDR (pin 27) for the VREFR output. It is
recommended to have at least a 0.1µF X7R ceramic chip
capacitor connected in parallel with a 33µF low ESR
tantalum chip capacitor for de-coupling purposes. The
VREFL and VREFR outputs should not be utilized to bias
external circuitry, because they are not buffered. Use the
VCOML (pin 3) and VCOMR (pin 26) outputs to bias external
circuitry, as described in the following paragraphs.
Refer to the Applications Information section of this
datasheet for the recommended voltage reference pin
connections.
The PCM4202 analog inputs are internally biased to
approximately VCC/2. This bias voltage is referred to as the
common mode voltage, and is output at VCOML (pin 3) and
VCOMR (pin 26), corresponding to the Left and Right
channels, respectively. These outputs provide a level
shifting voltage for biasing external input buffer circuitry.
Although the VCOML and VCOMR outputs are internally
buffered, the output current is limited to a few hundred µA.
It is recommended to connect these pins to external nodes
with greater than 1MΩ impedance, or to buffer the outputs
with a voltage follower circuit when driving multiple
external or low impedance nodes.
Refer to the Applications Information section of this
datasheet for an example input buffer circuit that utilizes
the common-mode bias voltage outputs.
SYSTEM CLOCK INPUT
The PCM4202 requires an external system clock, from
which the modulator oversampling and digital sub-system
clocks are derived. The system clock is applied at the
SCKI input (pin 18). The frequency of the system clock is
dependent upon the desired PCM output sampling
frequency or DSD data rate, along with the sampling mode
selection. Table 1 shows the corresponding system clock
frequencies for common output sampling and data rates,
along with the corresponding sampling modes. Timing
requirements for the system clock are shown in Figure 2.
Table 1. System Clock Frequencies for Common Output Sampling and Data Rates
SYSTEM CLOCK FREQUENCY (MHz)
SAMPLING FREQUENCY, fS
(kHz)
128fS
192fS
Single Rate
32
n/a
n/a
8.192
12.288
16.384
24.576
Single Rate
44.1
n/a
n/a
11.2896
16.9344
22.5792
33.8688
Single Rate
48
n/a
n/a
12.288
18.432
24.576
36.864
Dual Rate
88.2
n/a
n/a
22.5792
33.8688
n/a
n/a
Dual Rate
96
n/a
n/a
24.576
36.864
n/a
n/a
Quad Rate
176.4
22.5792
33.8688
n/a
n/a
n/a
n/a
Quad Rate
192
24.576
36.864
n/a
n/a
n/a
n/a
DSD Output
128fS Data (Single Rate)
n/a
n/a
11.2896
16.9344
22.5792
33.8688
DSD Output
64fS Data (Dual Rate)
n/a
n/a
11.2896
16.9344
n/a
n/a
SAMPLING MODE
256fS
384fS
512fS
768fS
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SBAS290B − JULY 2003 − SEPTEMBER 2004
t SCKIH
SCKI
t SCKI
t SCKIL
PARAMETER
DESCRIPTION
MIN
t SCKI
System Clock Period
26
ns
t SCKIH
System Clock High Pulse Time
12
ns
t SCKIL
System Clock Low Pulse Time
12
ns
MAX
UNITS
Figure 2. System Clock Timing Requirements
SAMPLING MODES
The PCM4202 may be operated in one of three PCM
sampling modes, or at one of two DSD output data rates.
The PCM sampling modes are referred to as Single Rate,
Dual Rate, and Quad Rate.
Single Rate mode is utilized for sampling rates up to
54kHz. The delta-sigma modulator oversamples the
analog input signal by a rate equal to 128 times the desired
output sampling rate.
Dual Rate mode is utilized for sampling rates higher than
54kHz and up to 108kHz. The delta-sigma modulator
oversamples the analog input signal by a rate equal to 64
times the desired output sampling rate.
Quad Rate mode is utilized for sampling frequencies
higher than 108kHz and up to 216kHz. The delta-sigma
modulator oversamples the analog input signal by a rate
equal to 32 times the desired output sampling rate.
For DSD output data, the user may select either 64fS or
128fS oversampled data rates, where fS is the base
sampling rate, which is 44.1kHz for Super Audio CD
(SACD) applications. The 64fS data rate is analogous to
the Dual Rate PCM sampling mode, where the analog
input signal is oversampled by a rate equal to 64 times the
base sampling rate. The 128fS data rate corresponds to
the Single Rate PCM sampling mode, where the analog
input signal is oversampled by a rate equal to 128 times the
base sampling rate.
Table 1 indicates the sampling mode utilized for common
system clock and sampling rate combinations. The FS0
(pin 9), FS1 (pin 10), and FS2 (pin 11) inputs are utilized
to select the sampling mode for the PCM4202. If the state
of the sampling mode pins is changed any time after
power-up reset initialization, the user should issue an
external forced reset to re-initialize the PCM4202. Table 2,
14
Table 3, and Table 4 indicate the sampling mode
selections for PCM Master and Slave mode operation, as
well as the DSD Output mode.
Table 2. Sampling Mode Selection for PCM
Master Mode Operation
FS2
FS1
FS0
SAMPLING MODE WITH
SYSTEM CLOCK RATE
0
0
0
Single Rate with fSCKI = 768fS
0
0
1
Single Rate with fSCKI = 512fS
0
1
0
Single Rate with fSCKI = 384fS
0
1
1
Single Rate with fSCKI = 256fS
1
0
0
Dual Rate with fSCKI = 384fS
1
0
1
1
1
0
Dual Rate with fSCKI = 256fS
Quad Rate with fSCKI = 192fS
1
1
1
Quad Rate with fSCKI = 128fS
Table 3. Sampling Mode Selection for PCM Slave
Mode Operation
FS2
FS1
FS0
SAMPLING MODE
0
0
0
Single Rate with Clock Auto-Detection
0
0
1
Dual Rate with Clock Auto-Detection
0
1
0
Quad Rate with Clock Auto-Detection
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
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SBAS290B − JULY 2003 − SEPTEMBER 2004
Table 4. Sampling Mode Selection for DSD
Output Mode Operation
FS2
FS1
FS0
SAMPLING MODE
0
0
0
0
0
1
128fS DSD Output Rate with fSCKI = 768fS
128fS DSD Output Rate with fSCKI = 512fS
0
1
0
0
1
1
1
0
0
1
0
1
64fS DSD Output Rate with fSCKI = 384fS
64fS DSD Output Rate with fSCKI = 256fS
1
1
0
Reserved
1
1
1
Reserved
In Slave mode, the PCM bit and left/right clocks (BCK and
LRCK) are configured as input pins. DSD data formats are
not supported in Slave mode. Slave mode supports
commonly used PCM audio data formats, including Left
Justified, Right Justified, and Philips I2S.
In Master mode, the PCM bit and left/right clocks (BCK and
LRCK respectively) are configured as output pins, and are
derived from the system clock input (SCKI). Alternatively,
the DSD output data may be provided at the port output.
128fS DSD Output Rate with fSCKI = 384fS
128fS DSD Output Rate with fSCKI = 256fS
Table 5 shows the available data format selections.
Figure 3 and Figure 4 illustrate the PCM and DSD data
formats.
Table 5. Audio Data Format Selection
AUDIO DATA FORMATS
As mentioned previously, the PCM4202 supports 24-bit
linear PCM output data, as well as 1-bit DSD output data.
The available data formats are dependent upon whether
the PCM4202 is configured in Slave or Master mode. The
S/M (pin 8), FMT0 (pin 6), and FMT1 (pin 7) inputs are
utilized to select either Slave or Master mode and the
corresponding audio data format.
FMT1
FMT0
AUDIO DATA FORMAT
0
0
24-bit Left Justified
0
1
24-bit I2S
1
0
24-bit Right Justified
1
1
1-bit DSD (Master Mode Only)
Right Channel
Left Channel
LRCKI
BCKI
DATA
MSB
LSB
MSB
LSB
(a) Left Justified Data Format
LRCKI
BCKI
DATA
MSB
LSB
MSB
LSB
(b) Right Justified Data Format
LRCKI
BCKI
DATA
MSB
LSB
MSB
LSB
(c) I2S Data Format
1/fS
Figure 3. PCM Data Formats: Left Justified, Right Justified, and Philips I2S
15
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SBAS290B − JULY 2003 − SEPTEMBER 2004
In Slave mode, the BCK and LRCK signals are inputs, with
the clocks being generated by a master timing source,
such as a DSP serial port, PLL clock synthesizer, or a
crystal oscillator/divider circuit. The BCK rate is typically
equal to 128fS in Single Rate sampling mode, and 64fS in
Dual or Quad Rate sampling modes. Although other BCK
clock rates are possible, they are not recommended as a
result if potential clock phase sensitivity issues, which can
degrade the dynamic performance of the PCM4202. The
LRCK clock must be operated at fS, the output sampling
rate.
DSDBCK
DSDL
DSDR
DN−3 DN−2 DN−1 DN DN+1 DN+2 DN+3 DN+4
Figure 4. DSD Output Data Format
AUDIO SERIAL PORT OPERATION
This section provides additional details regarding the
PCM4202 audio serial port, utilized for 24-bit linear PCM
or 1-bit DSD output data. PCM output operation will be
described in this section, while DSD output mode
operation will be described in the following section.
Figure 5 illustrates the typical audio serial port
connections between a PCM4202 and an audio signal
processor when using the PCM output data formats.
Figure 6 illustrates the audio serial port timing for both the
Master and Slave modes of operation.
For PCM data formats, the serial port is comprised of three
signals: BCK (pin 16), LRCK (pin 17), and DATA (pin 15).
The BCK signal functions as the data (or bit) clock for the
serial audio data. The LRCK is the left/right word clock for
the audio serial port. The LRCK and BCK clocks must be
synchronous. The DATA signal is the serial audio data
output, with data being clocked out on the falling edge of
the BCK signal. DATA carries audio data for both the Left
and Right channels.
DSP
PCM4202
FSX
LRCK
CLKR
BCK
DR
DATA
SCKI
As mentioned in the Audio Data Format section of this
datasheet, the audio serial port can operate in Master or
Slave mode. In Master mode, the BCK and LRCK clock
signals are outputs, derived from the system clock input,
SCKI. The BCK clock is fixed at 128fS for Single Rate
sampling mode, and at 64fS for Dual or Quad Rate
sampling modes. The LRCK clock operates at fS, the
output sampling rate (that is, 48kHz, 96kHz, etc.).
System Clock
Figure 5. Typical Audio Serial Port Connections
for Left Justified, Right Justified, and I2S Data
Formats
tLRCKHL
tLRCKHL
tLRCKHL
LRCK
BCK
tBCKP
tBCKHL
DATA
tBCKDO
PARAMETER
DESCRIPTIO N
MIN
MAX
UNITS
tLRCKP
LRCK Period
5
µs
tLRCKHL
LRCK High/Low Time
2.25
µs
tBCKP
BCK Period
78
ns
tBCKHL
BCK High/Low Time
35
tBCKDO
SDOUT Data Output Delay from BCK Falling Edge
ns
10
ns
Figure 6. Master and Slave Mode Audio Serial Port Timing: Left Justified, Right Justified, and Philips I2S
16
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SBAS290B − JULY 2003 − SEPTEMBER 2004
DSD OUTPUT MODE OPERATION
The output port DSD mode operation consists of a single
DSD data clock signal, DSDBCK (pin 17), along with two
synchronous DSD data lines, DSDR (pin 15) and DSDL
(pin 16). The data lines correspond to Right and Left
channels, respectively. The DSD output rate is determined
by the sampling mode settings for the device, discussed
in the Sampling Modes section of this datasheet.
filter can be enabled or disabled for both the Left and Right
channels using the HPFD input (pin 12). Driving the HPFD
input low enables the high-pass filter. Driving the HPFD
input high disables the high-pass filter.
The −3dB corner frequency for the high-pass filter scales
with the output sampling rate, where f−3dB = fS/48000,
where fS is the output sampling rate.
For DSD output data, the serial port is configured in Master
mode, with the DSDBCK derived from the system clock
input, SCKI. The DSDBCK is equivalent to the
oversampling clock supplied to the delta-sigma
modulators. The DSD data outputs, DSDR through DSDL,
are synchronous to the DSDBCK. The clock and data lines
are then connected to a data capture or processing device.
CLIPPING FLAGS
Figure 7 illustrates the DSD port timing for both the DSD
output mode.
A clipping flag is forced high as soon as the digital output
of the decimation filter exceeds the full-scale range for the
corresponding channel. The clipping flag output is held
high for a maximum of (256 x N) / fS seconds, where N =
128 for Single Rate sampling mode, 256 for Dual Rate
sampling mode, and 512 for Quad Rate sampling mode.
If the decimation filter output does not exceed the full-scale
range during the initial hold period, the output returns to a
low state upon termination of the hold period.
HIGH-PASS FILTER
A digital high-pass filter is available for removing the DC
component of the digitized input signal. The filter is located
at the output of the digital decimation filter, and is available
only when using PCM output data formats. The high-pass
The PCM4202 includes a clipping flag output for each
channel. The outputs are designated CLIPL (pin 21) and
CLIPR (pin 20), corresponding to the Left and Right
channels, respectively. The clipping flags are only
available when using PCM output data formats.
DSDBCK
t DCKP
t DCKHL
DSDL
DSDR
t DCKDO
D ES C R IPT IO N
M IN
tDCKP
LRCK pulse width
156
tDCKP
LRCK active edge to BCK sampling edge delay
70
tDCKP
Data setup time
P A R A M E T ER
MAX
U N ITS
ns
ns
10
ns
Figure 7. DSD Data Port Timing
17
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SBAS290B − JULY 2003 − SEPTEMBER 2004
RESET OPERATION
The PCM4202 includes two reset functions: power-on and
externally controlled. This section describes the operation
of each of these functions.
On power-up, the internal reset signal is forced low, forcing
the PCM4202 into a reset state. The power-on reset circuit
monitors the VDD (pin 14) and VCC (pin 22) power supplies.
When the VDD supply exceeds +2.0V (±400mV) and the
VCC supply exceeds +4.0V (±400mV), the internal reset
signal is forced high. The PCM4202 then waits for the
system clock input (SCKI) to become active. Once the
system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. During the
initialization sequence, the ADC output data pins are
forced low. Once the initialization sequence is completed,
the PCM4202 output is enabled. Figure 8 shows the
power-on reset sequence timing.
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST input (pin 19). The RST input is active low, and
requires a minimum low pulse width of 40ns. The
low-to-high transition of the applied reset signal forces an
initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 9 illustrates
the reset sequence initiated when using the RST input.
Figure 10 shows the state of the audio data outputs for the
PCM4202 before, during and after the reset operations.
~ 4.0V
VCC
0V
VDD
~ 2.0V
0V
Internal
Reset
1024 System Clock Periods
Required for Initialization
0V
SCKI
0V
System Clock
Indeterminate
or Inactive
Figure 8. Power-On Reset Sequence
18
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SBAS290B − JULY 2003 − SEPTEMBER 2004
t
RSTL
> 40ns
RST
0V
1024 System Clock Periods
Required for Initialization
Internal
Reset
0V
SCKI
0V
Figure 9. External Reset Sequence
Internal
Reset
Output
Data Pins
HI
LO
Valid Output Data
Outputs are Forced Low
Outputs are Forced Low
for 1024 SCKI Periods
Valid Output Data
Initialization
Period
Figure 10. ADC Digital Output State for Reset Operations
19
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SBAS290B − JULY 2003 − SEPTEMBER 2004
POWER-DOWN OPERATION
The PCM4202 can be forced to a power-down state by
applying a low level to the RST input (pin 19) for a minimum
of 65,536 system clock cycles. In power-down mode, all
internal clocks are stopped, and output data pins are
forced low. The system clock may then be removed to
conserve additional power. Before exiting power-down
mode, the system and audio clocks should be restarted.
Once the clocks are active, the RST input may be driven
high, which initiates a reset initialization sequence.
Figure 11 illustrates the state of the output data pins during
before, during, and upon exiting the power-down state.
APPLICATIONS INFORMATION
A typical connection diagram for the PCM4202 is shown
in Figure 12. Capacitors for power supply and reference
bypassing are shown with recommended values. Bypass
capacitors should be located as close as possible to the
power supply and reference pins of the PCM4202. Due to
its small size, the 0.1µF capacitor can be located on the
component (top) side of the board, while the larger 33µF
capacitor can be located on the solder (bottom) side of the
board.
A single ground plane is utilized for the analog and digital
ground connections. This approach ensures a low
impedance connection between the analog and digital
ground pins. The +5V analog and +3.3V digital power
connections are provided from separate supplies.
Figure 13 illustrates an example input buffer circuit,
designed for balanced differential input signals. This circuit
is utilized on the PCM4202EVM evaluation board. The
2.7nF and 100pF capacitors shown at the output of the
buffer should be located as close as possible to the analog
input pins of the PCM4202. The buffer shown in Figure 13
can be easily made to function as a single ended to
differential converter by simply grounding the (−) input
terminal of the buffer circuit.
The input impedance for the VCOMIN pin of the OPA1632
is relatively low and will load down the VCOML or VCOMR
outputs from the PCM4202. A voltage follower circuit is
required to buffer these outputs, with a typical circuit
configuration shown in Figure 14. An OPA227 is utilized as
the buffer for the PCM4202EVM evaluation board.
However, alternative op amps with comparable
performance may be substituted.
HI
RST
LO
Output
Data Pins
Valid Output Data
Outputs are
Forced Low
65,536
SCKI Periods
Outputs are
Forced Low
Enter
Power−Down
State
Outputs are
Forced Low
1024
SCKI Periods
Required for
Initialization
Figure 11. ADC Digital Output State for Power-Down Operations
20
Valid Output Data
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SBAS290B − JULY 2003 − SEPTEMBER 2004
33µF
33µF
+
+
0.1µF
1
2
0.1µF
Input Buffer
3
4
Left Channel
Analog Input
5
6
7
8
From
Logic, µP,
or
Hardwired
Connection
9
10
11
12
13
0.1µF
14
VREFL
VREFR
AGNDL
AGNDR
VCOML
VCOMR
VINL+
VINR+
VINL−
VINR−
FMT0
AGND
FMT1
PCM4202
VCC
S/M
CLIPL
FS0
CLIPR
FS1
RST
FS2
SCKI
HPFD
LRCK or DSDBCK
DGND
BCK or DSDL
VDD
DATA or DSDR
28
0.1µF
27
26
0.1µF
25
Right Channel
Analog Input
24
23
+5V
22
0.1µF
21
20
19
18
+
33µF
To Clipping
Indicators
To A/D or System Reset
To Audio System Clock
17
16
15
Digital Audio
Transmitter or
Processor
33µF
+
+3.3V
Figure 12. Typical Connection Diagram
21
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SBAS290B − JULY 2003 − SEPTEMBER 2004
270Ω
1nF
−15V
10µF
+
0.01µF
6
7
(+)
Differential
Analog Input
(−)
1kΩ
8
EN
5
OPA1632
1kΩ
1
VOCM
40.2Ω
100pF
To VIN−
40.2Ω
2.7nF
To VIN+
4
100pF
2
3
1kΩ
0.01µF
0.1µF
10µF
+
+15V
1nF
270Ω
Figure 13. Example Input Buffer Circuit
OPA227
or equivalent
PCM4202
VCOML
or
VCOMR
0.1µF
To
Buffered VCOM
in Figure 13.
Figure 14. Example Buffer Circuit for VCOML and VCOMR
22
From
Buffered VCOM
in Figure 14.
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SBAS290B − JULY 2003 − SEPTEMBER 2004
COMPATIBILITY WITH THE PCM1804
D When operating in Master mode with Single Rate
sampling selected, the audio serial port bit clock
(BCK) is equal to 64fS for the PCM1804, while the
BCK rate is equal to 128fS for the PCM4202.
Although the PCM4202 and PCM1804 are pin- and
function-compatible, there are a few differences between
the two devices that the designer should be aware of.
These differences are noted here for clarity.
D The following pins on the PCM4202 and PCM1804
D The full-scale input of the PCM4202 is 6.0VPP
have different names, but they perform the same
functions.
differential, while it is 5.0VPP for the PCM1804. This
is a result of the PCM4202 having an internal +3.0V
voltage reference, and the PCM1804 having an
internal +2.5V voltage reference.
D The PCM1804 includes +5V tolerant digital inputs.
The PCM4202 does not include these because the
digital inputs are designed for interfacing to +3.3V
logic.
D The reset pin (RST) pin of the PCM4202 has an
internal pull-up resistor. For the PCM1804, this pin
has an internal pull-down resistor.
TERMINAL
NUMBER
PCM4202
TERMINAL NAME
PCM1804
TERMINAL NAME
9
FS0
OSR0
10
FS1
OSR1
11
FS2
OSR2
12
HPFD
BYPAS
20
CLIPR
OVFR
21
CLIPL
OVFL
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM4202DB
ACTIVE
SSOP
DB
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4202
PCM4202DBR
ACTIVE
SSOP
DB
28
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4202
PCM4202DBT
ACTIVE
SSOP
DB
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4202
PCM4202DBTG4
ACTIVE
SSOP
DB
28
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-10 to 70
PCM4202
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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