PCM4204PAPR

$% SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004
    
          !" # FEATURES D Four High-Performance Delta-Sigma D D D D D D D D D Analog-to-Digital Converters − 24-Bit Linear PCM or 1-Bit Direct Stream Digital (DSD) Output Data − Supports PCM Output Sampling Rates up to 216kHz − Supports 64fS and 128fS DSD Output Data Rates Dynamic Performance: PCM Output − Dynamic Range: 118dB − THD+N: −105dB Dynamic Performance: DSD Output − Dynamic Range: 115dB − THD+N: −103dB Audio Serial Port − 24-Bit Linear PCM Output Data − Master or Slave Mode Operation − Supports Left-Justified, Right-Justified, I2S, and TDM Data Formats DSD Data Port − Supports DSD Output or Input for All Four Channels Simultaneously − Input Mode Provides 1-Bit DSD to 24-Bit PCM Data Format Conversion Additional PCM Output Features − Linear-Phase Digital Decimation Filter − Digital High-Pass Filter for DC Removal − Clipping Flag Output for Each Channel Power Supplies: +5V Analog and +3.3V Digital Power Dissipation: − fS = 48kHz: 600mW typical − fS = 96kHz: 640mW typical − fS = 192kHz: 615mW typical Power-Down Mode Available in a Thermally-Enhanced HTQFP-64 Package APPLICATIONS D Digital Recorders and Mixing Desks D Digital Audio Effects Processors D Broadcast Studio Equipment D Surround Sound Encoders D High-End A/V Receivers DESCRIPTION The PCM4204 is a high-performance, four-channel analog-to-digital (A/D) converter designed for professional and broadcast audio applications. The PCM4204 architecture utilizes a 1-bit delta-sigma modulator per channel incorporating a novel density modulated dither scheme for improved dynamic performance. The PCM4204 supports 24-bit linear PCM output data, with sampling frequencies up to 216kHz. The PCM4204 can also be configured to output either 64x or 128x oversampled, 1-bit direct stream digital (DSD) data for each channel. In addition, the PCM4204 supports a DSD input mode, allowing 1-bit DSD to 24-bit PCM data format conversion utilizing the on-chip digital decimation filter. These features make the PCM4204 suitable for a variety of digital audio recording and processing applications. The PCM4204 includes a flexible audio serial port interface, which supports standard PCM audio data formats, as well as time division multiplexed (TDM) PCM data formats. Multiple format support allows the system designer to choose the interface format that best suits the end application. Audio data format selection, sampling mode configuration, and high-pass filter functions are all programmed using dedicated control pins. The PCM4204 operates from a +5V analog power supply and a +3.3V digital power supply. The digital I/O pins are compatible with +3.3V logic families. The PCM4204 is available in a thermally-enhanced HTQFP-64 PowerPAD package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright  2004, Texas Instruments Incorporated &'!()*'+ !)   ,   , - .  ,    ,  ,   , )/, * , , ,  0 1.    ,,   ,  ,,1   ,   ,. www.ti.com $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM4204 UNIT VCC1, VCC2 VDD1, VDD2, VDD3 +6.0 V Supply voltage +3.6 V Ground voltage differences (any AGND to DGND or BGND) ±0.1 V Digital input voltage FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, SCKI, RST, HPFD, SUB, BCK, LRCK, DSDCLK, DSD1, DSD2, DSD3, DSD4, TEST −0.3 to (VDD + 0.3) V Analog input voltage VIN1−4+, VIN1−4− −0.3 to (VCC + 0.3) V Input current (any pin except supplies) Operating temperature range ±10mA V −10 to +70 °C Storage temperature range, TSTG −65 to +150 °C (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet. 2 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS Unless otherwise noted, all characteristics specified with TA = +25°C, VCC = +5V, VDD = +3.3V, system clock (SCKI) is 512fS for Single Rate Sampling, 256fS for Dual Rate Sampling, or 128fS for Quad Rate Sampling. The device is operated in Master mode for all dynamic performance measurements. PCM4204 PARAMETER TEST CONDITIONS MIN RESOLUTION TYP MAX 24 UNIT Bits DATA FORMAT Left and Right Justified, I2S, TDM Audio Data Formats (PCM) Audio Data Word Length (PCM) 24 Binary Data Format (PCM) Bits Two’s Complement Binary, MSB First DSD Output Format and Word Length Bits 1-Bit Data DIGITAL INPUT/OUTPUT Input Logic Level Output Logic Level Input Leakage Current(1) Input Leakage Current(2) VIH VIL VOH VOL IOH = −2mA IOH = +2mA 0.7 x VDD 0 VDD 0.3 x VDD V 0.8 x VDD 0 VDD 0.2 x VDD V IIH VIN = VDD +1 +10 µA IIL VIN = 0V −1 −10 µA IIH VIN = VDD +35 +100 µA IIL VIN = 0V −35 −100 µA CLOCK FREQUENCIES System Clock Frequency, fSCKI Single Rate Sampling Mode Dual Rate Sampling Mode 6.144 12.8 38.4 38.4 MHz MHz Quad Rate Sampling Mode 12.8 38.4 MHz Sampling Frequency, fS Single Rate Sampling Mode Dual Rate Sampling Mode Quad Rate Sampling Mode 24 54 108 54 108 216 kHz kHz kHz ANALOG INPUTS Full Scale Input Voltage Average Input Impedance Common-mode Rejection Differential Input 6.0 3 85 VPP kΩ dB +2.5 200 V µA DC SPECIFICATIONS VCOM12, VCOM34 Output Voltage VCOM12, VCOM34 Output Current (1) Applies to the FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, HPFD, BCK, LRCK, SUB, DSDCLK, DSD1, DSD2, DSD3, DSD4, and SCKI pins. (2) Applies to the TEST and RST pins. (3) Typical performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter in combination with either a 20kHz low-pass filter for fS = 48kHz or a 40kHz low-pass filter for fS = 96kHz and 192kHz. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting filters already mentioned. The measurements are made with the RMS detector selected. (4) A 256fS system clock is used at final production test for fS = 48kHz measurements. (5) Typical DSD performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter in combination with a 20kHz low-pass filter. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting filter already mentioned. The measurements are made with the RMS detector selected. The 1-bit DSD data is converted to 24-bit linear PCM data for measurement using a PCM4204 configured for DSD input mode. 3 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, all characteristics specified with TA = +25°C, VCC = +5V, VDD = +3.3V, system clock (SCKI) is 512fS for Single Rate Sampling, 256fS for Dual Rate Sampling, or 128fS for Quad Rate Sampling. The device is operated in Master mode for all dynamic performance measurements. PCM4204 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT −96 112 105 −105 −56 118 120 dB dB dB dB DYNAMIC PERFORMANCE (PCM Output)(3) fS = 48kHz(4) THD+N VIN = −0.5dBFS, fIN = 1kHz VIN = −60dBFS, fIN = 1kHz VIN = −60dBFS, fIN = 1kHz, A-weighted Dynamic Range Channel Separation fS = 96kHz THD+N Dynamic Range Channel Separation fS = 192kHz THD+N Dynamic Range VIN = −0.5dBFS, fIN = 1kHz, BW = 20Hz to 40kHz VIN = −60dBFS, fIN = 1kHz, BW = 20Hz to 40kHz VIN = −60dBFS, fIN = 1kHz, A-weighted −103 −52 118 120 dB dB dB dB VIN = −0.5dBFS, fIN = 1kHz, BW = 20Hz to 40kHz VIN = 0V, Unweighted, BW = 20Hz to 40kHz VIN = 0V, A-weighted −103 108 117 120 dB dB dB dB DSDBCK = 2.8224MHz, BW = 20Hz to 20kHz VIN = −0.5dBFS, fIN = 1kHz VIN = −60dBFS, fIN = 1kHz VIN = −60dBFS, fIN = 1kHz, A-weighted −103 −52 115 dB dB dB DSDBCK = 5.6448MHz, BW = 20Hz to 20kHz VIN = −0.5dBFS, fIN = 1kHz VIN = −60dBFS, fIN = 1kHz VIN = −60dBFS, fIN = 1kHz, A-weighted −105 −56 118 dB dB dB Channel Separation DYNAMIC PERFORMANCE (DSD Output)(5) 64fS Output Rate THD+N Dynamic Range 128fS Output Rate THD+N Dynamic Range DIGITAL DECIMATION FILTER Single and Dual Rate Sampling Modes Passband Edge Passband Ripple Stop Band Edge Stop Band Attenuation Group Delay −0.005dB 0.453fS ±0.005 0.547fS −100 37/fS Hz dB Hz dB sec (1) Applies to the FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, HPFD, BCK, LRCK, SUB, DSDCLK, DSD1, DSD2, DSD3, DSD4, and SCKI pins. (2) Applies to the TEST and RST pins. (3) Typical performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter in combination with either a 20kHz low-pass filter for fS = 48kHz or a 40kHz low-pass filter for fS = 96kHz and 192kHz. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting filters already mentioned. The measurements are made with the RMS detector selected. (4) A 256fS system clock is used at final production test for fS = 48kHz measurements. (5) Typical DSD performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter in combination with a 20kHz low-pass filter. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting filter already mentioned. The measurements are made with the RMS detector selected. The 1-bit DSD data is converted to 24-bit linear PCM data for measurement using a PCM4204 configured for DSD input mode. 4 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, all characteristics specified with TA = +25°C, VCC = +5V, VDD = +3.3V, system clock (SCKI) is 512fS for Single Rate Sampling, 256fS for Dual Rate Sampling, or 128fS for Quad Rate Sampling. The device is operated in Master mode for all dynamic performance measurements. PCM4204 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.375fS 0.490fS ±0.005 9.5/fS Hz Hz dB Hz dB sec fS/48000 Hz DIGITAL DECIMATION FILTER (continued) Quad Rate Sampling Mode Passband Edge −0.005dB −3dB Passband Ripple Stop Band Edge Stop Band Attenuation Group Delay 0.770fS −135 DIGITAL HIGH PASS FILTER Frequency Response (−3dB) POWER SUPPLY Voltage Range VCC1, VCC2 VDD1, VDD2, VDD3 Power Down Supply Current ICC1 + ICC2 IDD1 + IDD2 + IDD3 Quiescent Current ICC1 + ICC2 IDD1 + IDD2 + IDD3 Total Power Dissipation +4.75 +3.0 +5.0 +3.3 +5.25 +3.6 VDC VDC 10 2 mA mA VCC = +5V, VDD = +3.3V, RST = Low VCC = +5.0V fS = 48kHz(4) fS = 96kHz fS = 192kHz 108 108 108 130 130 130 mA mA mA VDD = +3.3V fS = 48kHz(4) fS = 96kHz fS = 192kHz 18 30 23 23 44 26 mA mA mA VCC = +5V, VDD = +3.3V fS = 48kHz(4) fS = 96kHz fS = 192kHz 600 640 615 726 795 736 mW mW mW (1) Applies to the FMT0, FMT1, FMT2, S/M, FS0, FS1, FS2, HPFD, BCK, LRCK, SUB, DSDCLK, DSD1, DSD2, DSD3, DSD4, and SCKI pins. (2) Applies to the TEST and RST pins. (3) Typical performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter in combination with either a 20kHz low-pass filter for fS = 48kHz or a 40kHz low-pass filter for fS = 96kHz and 192kHz. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting filters already mentioned. The measurements are made with the RMS detector selected. (4) A 256fS system clock is used at final production test for fS = 48kHz measurements. (5) Typical DSD performance is measured using an Audio Precision System Two Cascade or Cascade Plus test system. The measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter in combination with a 20kHz low-pass filter. All A-weighted measurements are performed using the A-weighting filter in combination with the band limiting filter already mentioned. The measurements are made with the RMS detector selected. The 1-bit DSD data is converted to 24-bit linear PCM data for measurement using a PCM4204 configured for DSD input mode. 5 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 61 60 59 58 55 54 53 52 51 50 VREF34+ VREF34− AGND3 VCOM34 NC 56 VIN3− 57 VIN3+ VIN2− VIN2+ NC VCOM12 AGND4 62 NC 63 NC 64 VREF12− VREF12+ PIN ASSIGNMENT 49 VIN1− 1 48 VIN4+ VIN1+ 2 47 VIN4− NC 3 46 NC NC 4 45 NC VCC1 5 44 VCC2 AGND1 6 43 AGND2 BGND1 7 42 BGND4 DGND1 8 VDD1 9 40 VDD3 RST 10 39 SUB 41 DGND3 PCM4204 TEST 11 38 HPFD FS0 12 37 CLIP4 FS1 13 36 CLIP3 FS2 14 35 CLIP2 SCKI 15 34 CLIP1 6 27 28 29 30 31 32 SDOUT2 DGND2 26 SDOUT1 NC 25 LRCK FMT2 24 BCK FMT1 23 DSD4 22 DSD3 21 DSD2 20 DSD1 19 DSDCLK 18 VDD2 17 FMT0 33 BGND3 S/M BGND2 16 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 Terminal Functions TERMINAL PIN NO. NAME I/O 1 Input Channel 1 Analog Input, Inverting 2 VIN1− VIN1+ DESCRIPTION Input Channel 1 Analog Input, Non-inverting 3 NC — No Internal Connection No Internal Connection 4 NC — 5 VCC1 Power Analog Supply, +5V Nominal 6 AGND1 Ground Analog Ground 7 BGND1 Ground Substrate Ground 8 DGND1 Ground Digital Ground 9 VDD1 Power Digital Supply, +3.3V Nominal 10 RST Input Reset/Power Down (Active Low with internal pull-up to VDD1) 11 TEST Input Test Pin (Active High with internal pull-down to DGND) 12 FS0 Input Sampling Mode 13 FS1 Input Sampling Mode 14 FS2 Input Sampling Mode 15 SCKI Input System Clock 16 BGND2 Ground 17 S/M Input Audio Serial Port Slave/Master Mode (0 = Master, 1 = Slave) 18 FMT0 Input Audio Data Format 19 FMT1 Input Audio Data Format 20 FMT2 Input Audio Data Format 21 NC — 22 DGND2 Ground Digital Ground 23 VDD2 Power Digital Supply, +3.3V Nominal 24 DSDCLK I/O DSD Data Clock 25 DSD1 I/O Channel 1 DSD Data 26 DSD2 I/O Channel 2 DSD Data 27 DSD3 I/O Channel 3 DSD Data 28 DSD4 I/O Channel 4 DSD Data 29 BCK I/O Audio Serial Port Bit Clock Audio Serial Port Left/Right (or Word) Clock Substrate Ground No Internal Connection 30 LRCK I/O 31 SDOUT1 Output PCM Data for Channels 1 and 2(1) 32 SDOUT2 Output PCM Data for Channels 3 and 4(1) 33 BGND3 Ground Substrate Ground 34 CLIP1 Output Channel 1 Clipping Flag (Active High) 35 CLIP2 Output Channel 2 Clipping Flag (Active High) 36 CLIP3 Output Channel 3 Clipping Flag (Active High) 37 CLIP4 Output Channel 4 Clipping Flag (Active High) 38 HPFD Input High-Pass Filter Disable (Active High) TDM Sub-Frame Assignment (0 = SF 0, 1 = SF 1) 39 SUB Input 40 VDD3 Power Digital Supply, +3.3V Nominal (1) For TDM formats, SDOUT1 carries data for all four channels, while SDOUT2 is driven low. 7 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 Terminal Functions (continued) TERMINAL PIN NO. NAME I/O 41 DGND3 Ground Digital Ground DESCRIPTION 42 BGND4 Ground Substrate Ground 43 AGND2 Ground Analog Ground 44 VCC2 Power Analog Supply, +5V Nominal 45 NC — No Internal Connection No Internal Connection 46 NC — 47 VIN4− Input Channel 4 Analog Input, Inverting 48 VIN4+ Input Channel 4 Analog Input, Non-inverting 49 VREF34+ Output Voltage Reference De-Coupling for Channels 3 and 4 50 VREF34− Output Reference Ground for Channels 3 and 4, connect to AGND 51 AGND3 Output Analog Ground 52 VCOM34 Output Common-mode Voltage for Channels 3 and 4, +2.5V Nominal 53 NC — 54 VIN3− Input Channel 3 Analog Input, Inverting 55 VIN3+ Input Channel 3 Analog Input, Non-inverting 56 NC — No Internal Connection 57 NC — No Internal Connection 58 VIN2− Input Channel 2 Analog Input, Inverting 59 VIN2+ Input Channel 2 analog Input, Non-inverting 60 NC — 61 VCOM12 Output Common-mode Voltage for Channels 1 and 2, +2.5V Nominal 62 AGND4 Ground Analog Ground 63 VREF12− Output Reference Ground for Channels 1 and 2, connect to AGND 64 No Internal Connection No Internal Connection VREF12+ Output Voltage Reference De-Coupling for Channels 1 and 2 (1) For TDM formats, SDOUT1 carries data for all four channels, while SDOUT2 is driven low. 8 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted. OVERALL CHARACTERISTICS SINGLE RATE FILTER STOP BAND ATTENUATION CHARACTERISTICS SINGLE RATE FILTER 50 0 Normalized Frequency (fS ) Amplitude (dB) fS = 48 kHz −50 −100 −150 −200 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 4.0 fS = 48 kHz 0 TRANSIENT BAND CHARACTERISTICS SINGLE RATE FILTER 0 0.02 fS = 48kHz −1 fS = 48kHz −2 Amplitude (dB) 0 Amplitude (dB) 1 0.75 Normalized Frequency (f S) PASSBAND RIPPLE CHARACTERISTICS SINGLE RATE FILTER −0.02 −0.04 −0.06 −3 −4 −5 −6 −7 −8 −0.08 −9 −10 0.45 −0.1 0 0.2 0.1 0.4 0.3 0.6 0.5 0.47 Normalized Frequency (fS) fS = 96kHz Amplitude (dB) 0 −50 −100 −150 −200 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Normalized Frequency (fS ) 0.51 0.53 0.55 STOP BAND ATTENUATION CHARACTERISTICS DUAL RATE FILTER 50 0 0.49 Normalized Frequency (fS) OVERALL CHARACTERISTICS DUAL RATE FILTER Amplitude (dB) 0.5 0.25 Normalized Frequency (f S) 1.6 1.8 2.0 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 fS = 96kHz 0 0.5 0.75 0.25 Normalized Frequency (f S) 1 9 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted. TRANSIENT BAND CHARACTERISTICS DUAL RATE FILTER PASSBAND RIPPLE CHARACTERISTICS DUAL RATE FILTER 0 0.02 −2 Amplitude (dB) 0 Amplitude (dB) f S = 96kHz −1 fS = 96kHz −0.02 −0.04 −0.06 −3 −4 −5 −6 −7 −8 −0.08 −9 −10 0.45 −0.1 0 0.2 0.1 0.4 0.3 0.6 0.5 0.47 0.49 OVERALL CHARACTERISTICS QUAD RATE FILTER fS = 192kHz Amplitude (dB) Amplitude (dB) 0 −50 −100 −150 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 1 0 0.5 0.75 0.25 Normalized Frequency (f S) 1 TRANSIENT BAND CHARACTERISTICS QUAD RATE FILTER PASSBAND RIPPLE CHARACTERISTICS QUAD RATE FILTER 0 0.02 −1 fS = 192kHz 0 fS = 192kHz −2 Amplitude (dB) Amplitude (dB) 0.55 fS = 192kHz Normalized Frequency (fS) −0.02 −0.04 −0.06 −3.90dB at 0.5f S −3 −4 −5 −6 −7 −8 −0.08 −9 −0.1 0 0.1 0.2 0.3 0.4 Normalized Frequency (fS ) 10 0.53 STOP BAND ATTENUATION CHARACTERISTICS QUAD RATE FILTER 50 −200 0.51 Normalized Frequency (fS) Normalized Frequency (fS ) 0.5 0.6 −10 0.45 0.47 0.49 0.51 Normalized Frequency (fS) 0.53 0.55 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted. HIGH PASS FILTER PASSBAND CHARACTERISTICS 5 0.02 −20 0 Amplitude (dB) Amplitude (dB) HIGH PASS FILTER STOP BAND CHARACTERISTICS −40 −60 −80 −0.06 −0.1 0 0.1 0.2 0.3 0.4 0 0.5 1 1.5 2 2.5 3 Normalized Frequency (fS/1000) Normalized Frequency (fS /1000) FFT PLOT (fS = 48kHz, fIN = 997Hz at −20dB) FFT PLOT (fS = 48kHz, fIN = 997Hz at −60dB) 0 0 −20 −20 −40 −40 −60 −60 −80 Amplitude (dB) Amplitude (dB) −0.04 −0.08 −100 −100 −120 −140 −160 3.5 4 10k 20k −80 −100 −120 −140 −160 −180 −180 20 100 1k 10k 20k 20 100 1k Frequency (Hz) Frequency (Hz) FFT PLOT (fS = 48kHz, No Input [Idle]) FFT PLOT (fS = 96kHz, fIN = 997Hz at −20dB) 0 0 −20 −20 −40 −40 −60 −60 −80 −80 Amplitude (dB) Amplitude (dB) −0.02 −100 −120 −140 −100 −120 −140 −160 −160 −180 −180 20 100 1k Frequency (Hz) 10k 20k 20 100 1k 10k 40k Frequency (Hz) 11 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted. FFT PLOT (fS = 96kHz, No Input [Idle]) 0 0 −20 −20 −40 −40 −60 −60 −80 −80 Amplitude (dB) Amplitude (dB) FFT PLOT (fS = 96kHz, fIN = 997Hz at −60dB) −100 −120 −140 −160 −120 −140 −160 −180 −180 20 100 1k 10k 40k 20 100 1k Frequency (Hz) FFT PLOT (fS = 192kHz, fIN = 997Hz at −20dB) FFT PLOT (fS = 192kHz, fIN = 997Hz at −60dB) 0 0 −20 −20 −40 −40 −60 −60 −80 −100 −120 −140 −160 −80 −100 −120 −140 −180 20 100 1k 10k 100k 20 100 1k Frequency (Hz) 0 −20 −40 −60 THD+N (dB) −80 −100 −120 −140 −160 −180 20 100 1k Frequency (Hz) 10k 100k Frequency (Hz) FFT PLOT (f S = 192kHz, No Input [Idle]) Amplitude (dB) 40k −160 −180 12 10k Frequency (Hz) Amplitude (dB) Amplitude (dB) −100 10k 100k −90 −92 −94 −96 −98 −100 −102 −104 −106 −108 −110 −112 −114 −116 −118 −120 −140 THD+N vs AMPLITUDE (f S = 48kHz, fIN = 1kHz, BW = 20Hz to 20kHz) −120 −100 −80 −60 Input Amplitude (dB) −40 −20 0 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 20Hz to 20kHz, unless otherwise noted. −90 −92 −94 −96 −98 −100 −102 −104 −106 −108 −110 −112 −114 −116 −118 −120 THD+N (dB) THD+N (dB) THD+N vs FREQUENCY (f S = 48kHz, Input Amplitude = −1dB, BW = 20Hz to 20kHz) 20 100 1k 10k 20k −100 −80 −60 −40 −20 Input Amplitude (dB) THD+N vs FREQUENCY (fS = 96kHz, Input Amplitude = −1dB, BW = 20Hz to 40kHz) THD+N vs AMPLITUDE (fS = 192kHz, fIN = 1kHz, BW = 20Hz to 40kHz) −75 −80 −85 THD+N (dB) −90 −95 −100 −105 −110 −115 −120 100 1k 10k 40k −90 −92 −94 −96 −98 −100 −102 −104 −106 −108 −110 −112 −114 −116 −118 −120 −140 −120 Input Frequency (Hz) −100 −80 −60 −40 −20 0 0 Input Amplitude (dB) THD+N vs FREQUENCY (fS = 192kHz, Input Amplitude = −1dB, BW = 20Hz to 40kHz) −70 −75 −80 −85 −90 THD+N (dB) THD+N (dB) −120 Input Frequency (Hz) −70 20 −90 −92 −94 −96 −98 −100 −102 −104 −106 −108 −110 −112 −114 −116 −118 −120 −140 THD+N vs AMPLITUDE (fS = 96kHz, fIN = 1kHz, BW = 20Hz to 40kHz) −95 −100 −105 −110 −115 −120 20 100 1k 10k 80k Input Frequency (Hz) 13 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 PRODUCT OVERVIEW The PCM4204 is a high-performance, four-channel audio analog-to-digital (A/D) converter designed for use in professional and broadcast audio applications. The PCM4204 features 24-bit linear PCM data outputs, as well as 1-bit Direct Stream Digital (DSD) data output and input capability for all four channels. Sampling rates up to 216kHz are supported for PCM output formats, while 64x or 128x oversampled 1-bit data is supported for DSD modes. Native support for both PCM and DSD data formats makes the PCM4204 ideal for use in a wide variety of audio recording and processing applications. The PCM4204 features 1-bit delta sigma modulators employing density modulated dither for improved dynamic performance. Differential voltage inputs are utilized for the modulators, providing excellent common-mode rejection. VIN1+ VIN1− Delta−Sigma Modulator On-chip voltage references are provided for the modulators, in addition to generating DC common-mode bias voltage outputs for use with external input circuitry. Linear phase digital decimation filtering is provided for the 24-bit PCM output, with a minimum stop band attenuation of −100dB for all sampling modes. The PCM output mode features clipping flag outputs for each of the four channels, as well as a digital high-pass filter for DC removal. The PCM4204 may be configured using dedicated input pins for sampling mode and audio data format selection, high-pass filter enable/disable, and reset/power-down operation. A +5V power supply is required for the analog section of the device, while a +3.3V power supply is required for the digital circuitry. Figure 1 shows the functional block diagram for the PCM4204. Digital Decimation and High Pass Filters Audio Serial Port LRCK BCK SDOUT1 SDOUT2 DSD Data Port DSD1 DSD2 DSD3 DSD4 DSDCLK VREF12+ VREF12− AGND4 Reference VCOM12 VIN2+ VIN2− VIN3+ VIN3− Control and Status FS0 FS1 FS2 S/M FMT0 FMT1 FMT2 HPFD SUB RST CLIP1 CLIP2 CLIP3 CLIP4 System Clock and Timing SCKI Delta−Sigma Modulator Delta−Sigma Modulator To/From Other Blocks VREF34+ VREF34− Reference AGND3 VCOM34 To Other Blocks VIN4+ VIN4− Delta−Sigma Modulator VCC1 AGND1 VCC2 AGND2 BGND1 BGND2 BGND3 BGND4 VDD1 DGND1 VDD2 DGND2 VDD3 DGND3 Power and Ground Figure 1. PCM4204 Functional Block Diagram 14 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 ANALOG INPUTS The PCM4204 includes four channels of A/D conversion, each with its own pair of differential voltage input pins. The VIN1− (pin 1) and VIN1+ (pin 2) analog inputs correspond to Channel 1. The VIN2− (pin 58) and VIN2+ (pin 59) analog inputs correspond to Channel 2. The VIN3− (pin 54) and VIN3+ (pin 55) analog inputs correspond to Channel 3. The VIN4− (pin 47) and VIN4+ (pin 48) analog inputs correspond to Channel 4. The average input impedance of each input pin is 3.0kΩ. Each analog input pair accepts a full-scale input voltage of approximately 6.0VPP differential. The analog input should not swing below analog ground or above the VCC1 (pin 5) or VCC2 (pin 44) power supplies by more than 300mV. Schottky diodes may be used to clamp these pins to a safe input range, or the input buffer circuitry may be designed in a manner to ensure that the input swing does not exceed the absolute maximum ratings of the PCM4204. Refer to the Applications Information section of this datasheet for an example input buffer circuit. recommended to have at least a 0.1µF X7R ceramic chip capacitor connected in parallel with a 33µF low ESR capacitor (tantalum, multilayer ceramic, or aluminum electrolytic) for de-coupling purposes. Refer to the Applications Information section of this datasheet for the recommended voltage reference pin connections. The VREF12+ and VREF34+ outputs should not be utilized to bias external circuitry, as they are not buffered. Use the VCOM12 (pin 16) and VCOM34 (pin 52) outputs to bias external circuitry. Although the VCOML and VCOMR outputs are internally buffered, the output current is limited to a few hundred µA. It is recommended to connect these pins to external nodes with greater than 1MΩ impedance, or to buffer the outputs with a voltage follower circuit when driving multiple external nodes. Refer to the Applications Information section of this datasheet for an example input buffer circuit that utilizes the common-mode bias voltage outputs. SYSTEM CLOCK INPUT VOLTAGE REFERENCES AND COMMON MODE BIAS VOLTAGE OUTPUTS The PCM4204 includes two on-chip voltage references, one for Channels 1 and 2 and another for Channels 3 and 4. The VREF12− (pin 63) and VREF12+ (pin 64) outputs correspond to low and high reference outputs for Channels 1 and 2. The VREF34− (pin 50) and VREF34+ (pin 49) outputs correspond to low and high reference outputs for Channels 3 and 4. De-coupling capacitors are connected between the high and low reference pins, and the low reference pin is then connected to an analog ground. It is The PCM4204 requires a system clock, from which the modulator oversampling and digital sub-system clocks are derived. The system clock is applied at the SCKI input (pin 15). The frequency of the system clock is dependent upon the desired PCM output sampling frequency or DSD data rate, along with the sampling mode selection. Table 1 shows the corresponding system clock frequencies for common output sampling and data rates, along with the corresponding sampling modes. Timing requirements for the system clock are shown in Figure 2. Table 1. System Clock Frequencies for Common Output Sampling and Data Rates SYSTEM CLOCK FREQUENCY (MHz) SAMPLING FREQUENCY, fS (kHz) 128fS 192fS Single Rate 32 n/a n/a 8.192 12.288 16.384 24.576 Single Rate 44.1 n/a n/a 11.2896 16.9344 22.5792 33.8688 Single Rate 48 n/a n/a 12.288 18.432 24.576 36.864 Dual Rate 88.2 n/a n/a 22.5792 33.8688 n/a n/a Dual Rate 96 n/a n/a 24.576 36.864 n/a n/a Quad Rate 176.4 22.5792 33.8688 n/a n/a n/a n/a Quad Rate 192 24.576 36.864 n/a n/a n/a n/a DSD Input/Output 128fS Data (Single Rate) n/a n/a 11.2896 16.9344 22.5792 33.8688 DSD Input/Output 64fS Data (Dual Rate) n/a n/a 11.2896 16.9344 n/a n/a SAMPLING MODE 256fS 384fS 512fS 768fS 15 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 t SCKIH SCKI t SCKI t SCKIL PARAMETER DESCRIPTION MIN t SCKI System Clock Period 26 ns t SCKIH System Clock High Pulse Time 12 ns t SCKIL System Clock Low Pulse Time 12 ns MAX UNITS Figure 2. System Clock Timing Requirements SAMPLING MODES The PCM4204 may be operated in one of three PCM sampling modes, or at one of two DSD output data rates. The PCM sampling modes are referred to as Single Rate, Dual Rate, and Quad Rate. of the sampling mode pins is changed any time after power-up reset initialization, the user should issue an external forced reset to re-initialize the PCM4204. Table 2, Table 3, Table 4, and Table 5 indicate the sampling mode selections for PCM Master and Slave mode operation, as well as the DSD Output and Input mode operation. Single Rate mode is utilized for sampling rates up to 54kHz. The delta-sigma modulator oversamples the analog input signal by a rate equal to 128 times the desired output sampling rate. Table 2. Sampling Mode Selection for PCM Master Mode Operation Dual Rate mode is utilized for sampling rates higher than 54kHz and up to 108kHz. The delta-sigma modulator oversamples the analog input signal by a rate equal to 64 times the desired output sampling rate. FS2 FS1 FS0 SAMPLING MODE WITH SYSTEM CLOCK RATE 0 0 0 Single Rate with fSCKI = 768fS 0 0 1 Single Rate with fSCKI = 512fS 0 1 0 Single Rate with fSCKI = 384fS Quad Rate mode is utilized for sampling frequencies higher than 108kHz and up to 216kHz. The delta-sigma modulator oversamples the analog input signal by a rate equal to 32 times the desired output sampling rate. 0 1 1 Single Rate with fSCKI = 256fS 1 0 0 Dual Rate with fSCKI = 384fS 1 0 1 Dual Rate with fSCKI = 256fS 1 1 0 Quad Rate with fSCKI = 192fS For DSD output data, the user may select either 64fS or 128fS oversampled data rates, where fS is the base sampling rate, which is 44.1kHz for Super Audio CD (SACD) applications. The 64fS data rate is analogous to the Dual Rate PCM sampling mode, where the analog input signal is oversampled by a rate equal to 64 times the base sampling rate. The 128fS data rate corresponds to the Single Rate PCM sampling mode, where the analog input signal is oversampled by a rate equal to 128 times the base sampling rate. For DSD input data, the rate of the data must be known in order to configure the digital decimation filter for either 1/64 or 1/128 operation. 1 1 1 Quad Rate with fSCKI = 128fS Table 1 indicates the sampling mode utilized for common system clock and sampling rate combinations. The FS0 (pin 12), FS1 (pin 13), and FS2 (pin 14) inputs are utilized to select the sampling mode for the PCM4204. If the state 16 Table 3. Sampling Mode Selection for PCM Slave Mode Operation FS2 FS1 FS0 SAMPLING MODE 0 0 0 Single Rate with Clock Auto-Detection 0 0 1 Dual Rate with Clock Auto-Detection 0 1 0 Quad Rate with Clock Auto-Detection 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 Table 4. Sampling Mode Selection for DSD Output Mode Operation 128fS DSD Output Rate with fSCKI = 384fS 128fS DSD Output Rate with fSCKI = 256fS In Master mode, the PCM bit and left/right clocks (BCK and LRCK respectively) are configured as output pins, and are derived from the system clock input (SCKI). For the DSD data and clock pins (DSD1, DSD2, DSD3, DSD4, and DSDCLK), they may be configured as either inputs or outputs, depending upon the DSD format selection. Table 7 summarizes the corresponding Master mode data format selections. 1 64fS DSD Output Rate with fSCKI = 384fS 64fS DSD Output Rate with fSCKI = 256fS Figure 3, Figure 4, and Figure 5 illustrate the PCM and DSD data formats supported by the PCM4204. 1 0 Reserved 1 1 Reserved FS2 FS1 FS0 SAMPLING MODE 0 0 0 0 0 1 128fS DSD Output Rate with fSCKI = 768fS 128fS DSD Output Rate with fSCKI = 512fS 0 1 0 0 1 1 1 0 0 1 0 1 1 Table 6. Slave Mode Audio Data Format Selection S/M FMT2 FMT1 FMT0 AUDIO DATA FORMAT Table 5. Sampling Mode Selection for DSD Input Mode Operation 1 0 0 0 24-bit Left-Justified 1 0 0 1 24-bit I2S FS2 FS1 FS0 SAMPLING MODE 1 0 1 0 24-bit Right-Justified 0 0 0 Reserved 1 0 1 1 0 0 1 TDM with No BCK Delay for Start of Frame 0 1 0 128fS DSD Output Rate with fSCKI = 512fS 128fS DSD Output Rate with fSCKI = 384fS 1 1 0 0 0 1 1 1 0 0 128fS DSD Output Rate with fSCKI = 256fS 64fS DSD Output Rate with fSCKI = 384fS TDM with One BCK Delay for Start of Frame 1 1 0 1 Reserved 1 0 1 1 1 1 0 Reserved 1 1 0 64fS DSD Output Rate with fSCKI = 256fS Reserved 1 1 1 1 Reserved 1 1 1 Reserved Table 7. Master Mode Audio Data Format Selection AUDIO DATA FORMATS As mentioned previously, the PCM4204 supports 24-bit linear PCM output data, as well as 1-bit DSD output data. The available data formats are dependent upon whether the PCM4204 is configured in Slave or Master mode. The S/M (pin 17), FMT0 (pin 18), FMT1 (pin 19), and FMT2 (pin 20) inputs are utilized to select either Slave or Master mode and the corresponding audio data format. S/M FMT2 FMT1 FMT0 AUDIO DATA FORMAT 0 0 0 0 24-bit Left-Justified 0 0 0 1 24-bit I2S 0 0 1 0 24-bit Right-Justified 0 0 1 1 DSD Output with PCM Output Disabled In Slave mode, the PCM bit and left/right word clocks (BCK and LRCK) are configured as input pins. DSD data formats are not supported in Slave mode. Slave mode supports commonly used PCM audio data formats, including LeftJustified, Right-Justified, and Philips I2S. Time division multiplexed (TDM) data formats are also supported, allowing up to two PCM4204 devices to be cascaded on a single audio serial bus. Table 6 summarizes the corresponding Slave mode data format selections. 0 1 0 0 DSD Input with 24−Bit RightJustified PCM Output 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 17 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 Ch. 2 (SDOUT1) or Ch. 4 (SDOUT2) Ch. 1 (SDOUT1) or Ch. 3 (SDOUT2) LRCKI BCKI SDOUT1 SDOUT2 MSB LSB MSB LSB (a) Left−Justified Data Format LRCKI BCKI SDOUT1 SDOUT2 MSB LSB MSB LSB (b) Right−Justified Data Format LRCKI BCKI SDOUT1 SDOUT2 MSB LSB MSB LSB (c) I 2S Data Format 1/fS Figure 3. PCM Data Formats: Left-Justified, Right-Justified, and Philips I2S 18 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 TDM Data Format − Long Frame (Single and Dual Rate Sampling Modes) LRCK No BCK Delay LRCK One BCK Delay SDOUT1 Supports 8 Channels, or two PCM4204 devices. Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Ch. 1 Ch. 2 Ch. 3 Ch. 4 Ch. 1 Ch. 2 Ch. 3 Ch. 4 Sub−Frame 0 (SUB = 0) Sub−Frame 1 (SUB = 1) One Frame BCK = 256fS TDM Data Format − Short Frame (All Sampling Modes) LRCK No BCK Delay LRCK One BCK Delay SDOUT1 Supports 4 Channels, or two PCM4204 devices. Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Ch. 1 Ch. 2 Ch. 3 Ch. 4 Ch. 1 Ch. 2 Ch. 3 Ch. 4 One Frame BCK = 128fS (the SUB pin is ignored when using a Short Frame) In the case of BCK = 256fS, each time slot is 32 bits long and contains the 24−bit audio data for the corresponding channel. The audio data is left−justified in the time slot, with the the least significant 8 bits of each time slot being don’t care bits. Audio data is always presented in two’s complement, MSB−first format. Figure 4. PCM Data Formats: Time Division Multiplexed (TDM) DSDCLK DSD1 DSD2 DSD3 DSD4 DN−3 DN−2 DN−1 DN DN+1 DN+2 DN+3 DN+4 Figure 5. DSD Input and Output Data Format AUDIO SERIAL PORT OPERATION This section provides additional details regarding the PCM4204 audio serial port, utilized for 24-bit linear PCM output data. The serial port is comprised of four signals: BCK (pin 29), LRCK (pin 30), SDOUT1 (pin 31), and SDOUT2 (pin 32). The BCK signal functions as the data (or bit) clock for the serial audio data. The LRCK is the left/right word or TDM frame synchronization clock for the audio serial port. The LRCK and BCK clocks must be synchronous. The SDOUT1 and SDOUT2 signals are the serial audio data outputs, with data being clocked out on the falling edge of the BCK clock. SDOUT1 carries data for Channels 1 and 2 when using Left-Justified, RightJustified, or I2S data formats. SDOUT1 carries data for all four channels when using TDM data formats. SDOUT2 carries data for Channels 3 and 4 when using LeftJustified, Right-Justified, or I2S data formats. SDOUT2 is forced low when using TDM data formats. As mentioned in the Audio Data Format section of this datasheet, the audio serial port can operate in Master or Slave mode. In Master mode, the BCK and LRCK clock signals are outputs, derived from the system clock input, SCKI. The BCK clock is fixed at 128fS for Single Rate sampling mode, and at 64fS for Dual or Quad Rate sampling modes. The LRCK clock operates at fS, the output sampling rate (that is, 48kHz, 96kHz, etc.). 19 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 In Slave mode, the BCK and LRCK signals are inputs, with the clocks being generated by a master timing source, such as a DSP serial port, PLL clock synthesizer, or a crystal oscillator/divider circuit. For Left Justified, Right Justified, and I2S data formats, the BCK rate is typically 128fS in Single Rate sampling mode, and 64fS in Dual or Quad Rate sampling modes. Although other BCK clock rates are possible, they are not recommended due to the potential for clock phase sensitivity issues, which may degrade the dynamic performance of the PCM4204. The LRCK clock operates at fS, the output sampling rate. In Slave mode, the TDM data formats support a BCK clock rate of 256fS for Long Frame operation, and 128fS for Short Frame operation. The length and rate of the TDM frame is auto−detected by the audio serial port. Long Frame operation is supported for Single and Dual rate sampling modes only. Short Frame operation is supported for all sampling modes. For the TDM data formats, the maximum BCK rate is 27.648MHz for either Long or Short Frame operation. The LRCK clock operates at fS, the output sampling rate. The minimum clock high time for the LRCK clock is one BCK clock period. The start of frame is referenced to the rising edge of the LRCK signal. Figure 6 illustrates the typical audio serial port connections between a PCM4204 and an audio signal processor when using Left-Justified, Right-Justified, and I2S data formats in either Slave or Master modes. DSP Sub-frame selection for Long Frame TDM operation is accomplished by using the SUB input (pin 39). When SUB = 0, the PCM4204 is assigned to sub-frame 0. The SDOUT1 pin will be driven during sub-frame 0 and tri-stated during sub-frame 1. When SUB = 1, the PCM4204 is assigned to sub-frame 1. The SDOUT1 pin will be driven during sub-frame 1 and tri-stated during sub-frame 0. For Short Frame TDM operation, the SUB pin is ignored, although driving or hardwiring the SUB pin low is an acceptable practice. Figure 7 shows two PCM4204 devices and an audio DSP in a typical TDM format application. PCM4204 FSR CLKR LRCK BCK DR0 SDOUT1 DR1 SDOUT2 SCKI System Clock Figure 8 and Figure 9 illustrate the PCM4204 audio serial port timing for both Master and Slave mode operation. Figure 6. Typical Audio Serial Port Connections for Left-Justified, Right-Justified, and Philips I2S Data Formats Device #1 (Sub−Frame 0) PCM4204 DSP FSR CLKR DR LRCK BCK SDOUT1 SUB SCKI Device #2 (Sub−Frame 1) PCM4204 LRCK BCK SDOUT1 SUB VCC System Clock Figure 7. TDM Connections for Two PCM4204 Devices and an Audio DSP 20 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 t LRCKP t LRCKHL t LRCKHL LRCK BCK t BCKP t BCKHL SDOUT1 SDOUT2 t BCKDO PA R A M E TER D ES C R IP T IO N M IN MAX U N IT S t LRCKP t LRCKHL LRCK Period LRCK High/Low Time 5 2.25 µs µs t BCKP t BCKHL BCK Period BCK High/Low Time SDOUT Data Output Delay from BCK Falling Edge 78 35 ns ns ns t BCKDO 10 Figure 8. Master and Slave Mode Audio Serial Port Timing: Left-Justified, Right-Justified, and Philips I2S One Frame 1/fS t LRCKPW LRCK BCK t BCKHL t BCKP SDOUT1 t BCKDO P A R A M ET E R M IN M AX U N IT S LRCK Period Width tBCKP 1/fS −tBCKP µs t BCKP BCK Period 39 t BCKHL BCK High/Low Time 17.5 t BCKDO SDOUT Data Output Delay from BCK Falling Edge t LRCKPW D E SC R IPTIO N ns ns 10 ns Figure 9. Slave Mode Audio Serial Port Timing: Time Division Multiplexed (TDM) Formats 21 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 DSD DATA PORT OPERATION HIGH-PASS FILTER The DSD data port consists of a single DSD data clock signal, DSDCLK (pin 24), along with four synchronous DSD data lines, DSD1 (pin 25), DSD2 (pin 26), DSD3 (pin 27), and DSD4 (pin 28). The data lines correspond to Channels 1 through 4, respectively. The DSD output or input data rate is determined by the sampling mode settings for the device, discussed in the Sampling Modes section of this datasheet. A digital high-pass filter is available for removing the DC component of the digitized input signal. The filter is located at the output of the digital decimation filter, and is available only when using PCM output data formats. The high-pass filter can be enabled or disabled for all four channels using the HPFD input (pin 38). Driving the HPFD input low enables the high-pass filter. Driving the HPFD input high disables the high-pass filter. For DSD output data, the serial port is configured in Master mode, with the DSDCLK derived from the system clock input, SCKI. The DSDCLK is equivalent to the oversampling clock supplied to the delta-sigma modulators. The DSD data outputs, DSD1 through DSD4, are synchronous to the DSDCLK. The clock and data lines are then connected to a data capture device for storage and processing. The −3dB corner frequency for the high-pass filter scales with the output sampling rate, where f−3dB = fS/48000, where fS is the output sampling rate. The DSD input mode, the data port is configured as an input port, with DSD clock and data lines driven from an external data source. The Audio Serial Port is configured in Master mode, with the LRCK and BCK clocks derived from the system clock input, SCKI. The PCM data format is set to 24-bit Right-Justified. The input data is processed by the digital decimation filter and output as PCM data at the audio serial port. Figure 10 illustrates the DSD port timing for both the DSD output and input modes. CLIPPING FLAGS The PCM4204 includes a clipping flag output for each channel. The outputs are designated CLIP1 (pin 34), CLIP2 (pin 35), CLIP3 (pin 36), and CLIP4 (pin 37), corresponding to Channels 1 through 4, respectively. A clipping flag is forced high as soon as the digital output of the decimation filter exceeds the full-scale range for the corresponding channel. The clipping flag output is held high for a maximum of (256 x N) / fS seconds, where N = 128 for Single Rate sampling mode, 256 for Dual Rate sampling mode, and 512 for Quad Rate sampling mode. If the decimation filter output does not exceed the full-scale range during the initial hold period, the output returns to a low state upon termination of the hold period. DSDCLK t DCKP t DCKHL DSD1 DSD2 Input DSD3 DSD4 t DS DSD1 DSD2 DSD3 DSD4 t DH Output t DCKDO PA R A M E TER D E SC R IP TIO N M IN t DCKP DSDCLK Cycle Time 156 tDCKHL DSDCLK High/Low Time 70 tDS Data Setup Time 10 tDH Data Hold Time 10 t DCKDO DSD Data Output Delay from DSDCLK Falling Figure 10. DSD Data Port Timing 22 MAX U N IT S ns ns 10 ns 10 ns 10 ns $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 RESET OPERATION The PCM4204 includes two reset functions: power-on and externally controlled. This section describes the operation of each of these functions. On power-up, the internal reset signal is forced low, forcing the PCM4204 into a reset state. The power-on reset circuit monitors the VDD1, VDD2, VDD3, VCC1, and VCC2 power supply. When the VDD supply exceeds +2.0V (±400mV) and VDD1 and VDD2 supply exceeds +4.0V (±400mV), the internal reset signal is forced high. The PCM4204 then waits for the system clock input (SCKI) to become active. Once the system clock has been detected, the initialization sequence begins. The initialization sequence requires 1024 system clock periods for completion. During the initialization sequence, the ADC output data pins are forced low. Once the initialization sequence is completed, the PCM4204 output is enabled. Figure 11 shows the power-on reset sequence timing. The user may force a reset initialization sequence at any time while the system clock input is active by utilizing the RST input (pin 10). The RST input is active low, and requires a minimum low pulse width of 40ns. The low-to-high transition of the applied reset signal forces an initialization sequence to begin. As in the case of the power-on reset, the initialization sequence requires 1024 system clock periods for completion. Figure 12 illustrates the reset sequence initiated when using the RST input. Figure 13 shows the state of the audio data outputs for the PCM4204 before, during and after the reset operations. ~ 4.0V VCC1 VCC2 0V VDD1 VDD2 VDD3 Internal Reset ~ 2.0V 0V 1024 System Clock Periods Required for Initialization 0V SCKI 0V System Clock Indeterminate or Inactive Figure 11. Power-On Reset Sequence 23 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 t RSTL > 40ns RST 0V 1024 System Clock Periods Required for Initialization Internal Reset 0V SCKI 0V Figure 12. External Reset Sequence Internal Reset Output Data Pins HI LO Valid Output Data Outputs are Forced Low Outputs are Forced Low for 1024 SCKI Periods Valid Output Data Initialization Period Figure 13. ADC Digital Output State for Reset Operations 24 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 POWER-DOWN OPERATION The PCM4204 can be forced to a power-down state by applying a low level to the RST input (pin 10) for a minimum of 65,536 system clock cycles. In power-down mode, all internal clocks are stopped, and output data pins are forced low. The system clock may then be removed to conserve additional power. Before exiting power-down mode, the system and audio clocks should be restarted. Once the clocks are active, the RST input may be driven high, which initiates a reset initialization sequence. Figure 14 illustrates the state of the output data pins before, during, and upon exiting the power-down state. APPLICATIONS INFORMATION A typical connection diagram for the PCM4204 is shown in Figure 15. Capacitors for power supply and reference bypassing are shown with recommended values. Bypass capacitors should be located as close as possible to the power supply and reference pins of the PCM4204. Due to its small size, the 0.1µF capacitor can be located on the component (top) side of the board, while the larger 33µF capacitor can be located on the solder (bottom) side of the board. A single ground plane is utilized for the analog and digital ground connections. This approach ensures a low impedance connection between the analog, digital, and substrate ground pins. The +5V analog and +3.3V digital power connections are provided from separate supplies. Figure 16 illustrates an example input buffer circuit, designed for balanced differential input signals. This circuit is utilized on the PCM4204EVM evaluation board. The 2.7nF and 100pF capacitors shown at the output of the buffer should be located as close as possible to the analog input pins of the PCM4204. The buffer shown in Figure 16 can be easily made to function as a single ended to differential converter by simply grounding the (−) input terminal of the buffer circuit. The input impedance for the VCOMIN pin of the OPA1632 is relatively low and will load down the VCOM12 or VCOM34 outputs from the PCM4204. A voltage follower circuit is required to buffer these outputs, with a typical circuit configuration shown in Figure 17. An OPA227 is utilized as the buffer for the PCM4204EVM evaluation board. However, alternative op amps with comparable performance may be substituted. HI RST LO Output Data Pins Valid Output Data Outputs are Forced Low 65,536 SCKI Periods Outputs are Forced Low Outputs are Forced Low Enter Power Down State 1024 SCKI Periods Required for Initialization Valid Output Data Figure 14. ADC Digital Output State for Power-Down Operations 25 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 100Ω 24 25 DSD Data Storage or Processing 26 27 28 DSDCLK DSD1 DSD2 DSD3 VIN1− DSD4 VIN1+ SCKI VREF12+ BCK VREF12− 1 100Ω 15 29 30 Master Clock PCM Audio to DSP, DIT, etc. 31 32 AGND4 LRCK VCOM12 11 12 13 14 17 18 CONTROL via Logic, µP, etc. 19 20 34 35 36 37 38 39 33µF 64 63 33µF + 0.1µF 0.1µF 62 61 SDOUT1 SDOUT2 VIN2+ 10 A1 2 RST VIN2− 59 A2 58 TEST FS0 VIN3+ FS1 VIN3− FS2 S/M VCOM34 FMT0 AGND3 FMT1 FMT2 PCM4204 VREF34− CLIP1 VREF34+ CLIP2 VIN4+ CLIP3 CLIP4 HPFD SUB VIN4− VCC1 AGND1 55 A3 54 52 51 0.1µF 50 49 48 A4 47 33µF + 5 6 0.1µF +3.3VD 9 0.1µF 8 VDD1 DGND1 VCC2 + AGND2 33µF 23 0.1µF 22 DGND2 + 33µF 40 0.1µF 41 VDD3 DGND3 + 16 33 42 43 0.1µF +5VA NC NC NC NC 7 33µF + 44 VDD2 NC BGND1 NC BGND2 NC BGND3 NC BGND4 NC 3 4 21 45 46 53 A1 through A4 are analog input buffers. Refer to Figure 16 for an example circuit. All capacitor values are in microfarads (µF). The 0.1µF caps are X7R ceramic chip type. The 33µF caps are Low ESR tantalum or X7R multi−layer ceramic chip type. 56 57 60 Figure 15. Typical Connection Diagram 26 0.1µF 33µF + Analog Inputs $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 270Ω 1nF −15V 10µF + 0.1µF 6 7 (+) Differential Analog Input (−) 1kΩ 8 5 EN OPA1632 1kΩ 1 To VIN− 40.2Ω VOCM 100pF 40.2Ω 2.7nF To VIN+ 4 100pF 2 3 1kΩ 0.01µF 0.1µF From Buffered VCOM in Figure 17. 10µF + +15V 1nF 270Ω Figure 16. Example Input Buffer Circuit OPA227 or equivalent PCM4204 VCOM12 or VCOM34 0.1µF To Buffered VCOM in Figure 16. Figure 17. Example Buffer Circuit for VCOM12 and VCOM34 27 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 PowerPAD THERMALLY ENHANCED PACKAGING The PowerPAD concept is implemented in standard epoxy resin package material. The integrated circuit is attached to the leadframe die pad using thermally conductive epoxy. The package is molded so that the leadframe die pad is exposed at a surface of the package. This provides an extremely low thermal resistance to the path between the IC junction and the exterior case. The external surface of the leadframe die pad is located on the PCB side of the package, allowing the die pad to be attached to the PCB IC Die using standard flow soldering techniques. This allows efficient attachment to the PCB and permits the board structure to be utilized as a heat sink for the package. Using a thermal pad identical in size to the die pad and vias connected to the PCB ground plane, the board designer can now implement power packaging without additional thermal hardware (for example, external heat sinks) or the need for specialized assembly instructions. Figure 18 illustrates a cross-section view of a PowerPAD package. Mold Compount (Epoxy) Wire Bond Wire Bond Leadframe Die Pad Exposed at Base of Package Die Attach Epoxy (thermally conductive) Leadframe Figure 18. Cross-Section View of a PowerPAD Thermally-Enhanced Package 28 $% www.ti.com SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 PowerPAD PCB LAYOUT CONSIDERATIONS FOR THE PCM4204 Figure 19 shows the recommended layer structure for thermal management when using a PowerPad package on a 4-layer printed circuit board design. Note that the thermal pad is placed on both the top and bottom sides of the board. The ground plane is utilized as the heat sink, while the power plane is thermally isolated from the thermal vias. Figure 20 shows the required thermal pad etch pattern for the 64-lead HTQFP package used for the PCM4204. Nine 13 mil (0.33 mm) thermal vias plated with 1 oz. copper are placed within the thermal pad area for the purpose of connecting the pad to the ground plane layer. The ground plane is utilized as a heatsink in this application. It is very important that the thermal via diameter be no larger than 13mils in order to avoid solder wicking during the reflow process. Solder wicking results in thermal voids that reduce heat dissipation efficiency and hampers heat flow away from the IC die. The via connections to the thermal pad and internal ground plane should be plated completely around the hole, as opposed to the typical web or spoke thermal relief connection. Plating entirely around the thermal via provides the most efficient thermal connection to the ground plane. ADDITIONAL PowerPAD PACKAGE INFORMATION Texas Instruments publishes the PowerPAD Thermally Enhanced Package Application Report (TI literature number SLMA002), available for download at www.ti.com, which provides a more detailed discussion of PowerPAD design and layout considerations. Before attempting a board layout with the PCM4204, it is recommended that the hardware engineer and/or layout designer be familiar with the information contained in this document. 9/20/2004 Package Thermal Pad Component Traces 13mils (0.33mm) Component (top) Side Thermal Via Ground Plane Power Plane Thermal Isolation (power plane only) Solder (bottom) Side Package Thermal Pad (bottom trace) Figure 19. Recommended PCB Structure for a 4−Layer Board 29 $% www.ti.com 118mils (3mm) 40mils (1mm) 40mils (1mm) SBAS327A − JUNE 2004 − REVISED SEPTEMBER 2004 Package Outline Thermal Pad 40mils (1mm) 40mils (1mm) 118mils (3mm) 316mils (8mm) Thermal Via 13mils (0.33mm) 316mils (8mm) Figure 20. Thermal Pad Etch and Via Pattern for the 64-Lead HTQFP Package 30 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PCM4204PAPR ACTIVE HTQFP PAP 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -10 to 70 PCM4204 PCM4204PAPRG4 ACTIVE HTQFP PAP 64 1500 RoHS & Green NIPDAU Level-3-260C-168 HR -10 to 70 PCM4204 PCM4204PAPT ACTIVE HTQFP PAP 64 250 RoHS & Green NIPDAU Level-3-260C-168 HR -10 to 70 PCM4204 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of