PCM5102PW

PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 2VRMS DirectPath™, 112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface Check for Samples: PCM5100, PCM5101, PCM5102 FEATURES 1 112 / 106 / 100dB Dynamic Range 112 / 106 / 100dB THD+N @ - 1dBFS –93 / –92 / –90dB Full Scale Output 2.1VRMS (GND center) Normal 8× Oversampling Digital Filter Latency: 20/fS Low Latency 8× Oversampling Digital Filter Latency: 3.5/fS Sampling Frequency 8kHz to 384kHz System Clock Multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz Current Segment DAC Current Segment DAC I/V Zero Data Detector SNR I/V DIN (i2s) PCM5102 / PCM5101 / PCM5100 Analog Mute • Typical Performance (3.3V Power Supply) Parameter Analog Mute • 32bit ∆Σ Modulator • 8x Interpolation Filter • • • Market-Leading Low Out-of-Band Noise Selectable Digital-Filter Latency and Performance No DC Blocking Capacitors Required Integrated Negative Charge Pump Internal Pop-Free Control For Sample-Rate Changes Or Clock Halts Intelligent Muting System; Soft Up or Down Ramp and Analog Mute For 120dB Mute SNR With Popless Operation. Integrated High-Performance Audio PLL With BCK Reference To Generate SCK Internally Small 20-pin TSSOP Package Audio Interface • • 23 LINE OUT Advanced Mute Control Clock Halt Detection PCM510x LRCK BCK Power Supply PLL Clock MCK UVP/Reset POR Ch. Pump CPVDD (3.3V) AVDD (3.3V) DVDD (3.3V) GND CAPP CAPM VNEG Figure 1. PCM510x Functional Block Diagram OTHER KEY FEATURES • • • • • 1 2 3 Accepts 16-, 24-, And 32-Bit Audio Data PCM Data Formats: I2S, Left-Justified Automatic Power-Save Mode When LRCK And BCK Are Deactivated. 3.3V Failsafe LVCMOS Digital Inputs Hardware Configuration • • Single Supply Operation: – 3.3V Analog, 3.3V Digital Integrated Power-On Reset Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two Cascade, Audio Precision are trademarks of Audio Precision. DirectPath is a trademark of Texas, Instruments, Inc.. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. APPLICATIONS • • • • A/V Receivers DVD, BD Players HDTV Receivers Applications Requiring 2VRMS Audio Output DESCRIPTION The PCM510x devices are a family of monolithic CMOS integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510x uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM510x provides 2.1VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers. The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1kΩ. By supporting loads down to 1kΩ, the PCM510x can essentially drive up to 10 products in parallel, such as an LCD TV, DVDR, AV Receivers and other devices. The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. Intelligent clock error and PowerSense under voltage protection utilizes a two level mute system for pop-free performance. Upon clock error or system power failure, the device digitally attenuates the data (or last known good data), then mutes the analog circuit Compared with existing DAC technology, the PCM510x family offers up to 20dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100kHz OBN measurements all the way to 3MHz) The PCM510x accepts industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384kHz are supported. Table 1. Differences Between PCM510x Devices Part Number Dynamic Range SNR THD PCM5102 112dB 112dB –93dB PCM5101 106dB 106dB –92dB PCM5100 100dB 100dB –90dB spacer 2 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION TERMINAL FUNCTIONS, PCM510x PCM510x (top view) Table 2. TERMINAL FUNCTIONS, PCM510x TERMINAL I/O DESCRIPTION 1 — Charge pump power supply, 3.3V 2 O Charge pump flying capacitor terminal for positive rail CPGND 3 — Charge pump ground CAPM 4 O Charge pump flying capacitor terminal for negative rail VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V OUTL 6 O Analog output from DAC left channel OUTR 7 O Analog output from DAC right channel AVDD 8 -— Analog power supply, 3.3V AGND 9 — Analog ground DEMP 10 I De-emphasis control for 44.1kHz sampling rate (1): Off (Low) / On (High) FLT 11 I Filter select : Normal latency (Low) / Low latency (High) SCK 12 I System clock input (1) BCK 13 I Audio data bit clock input (1) DIN 14 I Audio data input (1) LRCK 15 I Audio data word clock input (1) FMT 16 I Audio format selection : I2S (Low) / Left justified (High) XSMT 17 I Soft mute control (1): Soft mute (Low) / soft un-mute (High) LDOO 18 — Internal logic supply rail terminal for decoupling DGND 19 — Digital ground DVDD 20 — Digital power supply, 3.3V NAME NO. CPVDD CAPP (1) Failsafe LVCMOS Schmitt trigger input Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 3 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE Supply Voltage AVDD, CPVDD, DVDD UNIT –0.3 to 3.9 Digital Input Voltage –0.3 to 3.9 Analog Input Voltage –0.3 to 3.9 Operating Temperature Range –25 to 85 Storage Temperature Range –65 to 150 V °C THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP θJA Theta JA ψJT Psi JT 1.0 ψJB Psi JB 41.5 θJC Theta JC θJB Theta JB High K MAX UNIT 91.2 Top ºC/W 25.3 42.0 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS Resolution MIN TYP MAX 16 24 32 UNIT Bits 384 kHz Data Format (PCM Mode) fS (1) Audio data interface format I2S, left justified Audio data bit length 16, 24, 32-bit acceptable Audio data format MSB First, 2’s Complement Sampling frequency 8 System clock frequency 64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or 3072 fSCK, up to 50Mhz Digital Input/Output Logic Family: 3.3V LVCMOS compatible VIH VIL IIH IIL VOH VOL (1) 4 0.7×DVDD Input logic level Input logic current Output logic level 0.3×DVDD VIN = VDD 10 VIN = 0V –10 IOH = –4mA 0.8×DVDD IOL = 4mA 0.22×DVDD V µA V One sample time si defined as the reciprocal of the sampling frequency. 1tS = 1/fS Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Performance (PCM Mode) (2) (3) (Values shown for three devices PCM5102/PCM5101/PCM5100) THD+N at –1 dBFS (3) fS = 48kHz –93/–92/–90 fS = 96kHz –93/–92/–90 fS = 192kHz Dynamic range (3) Signal-to-noise ratio (3) EIAJ, A-weighted, fS = 48kHz –93/–92/–90 106/ 100/ 95 112/106/100 EIAJ, A-weighted, fS = 192kHz 112/106/100 EIAJ, A-weighted, fS = 48kHz 112/106/100 EIAJ, A-weighted, fS = 96kHz 112/106/100 EIAJ, A-weighted, fS = 48kHz EIAJ, A-weighted, fS = 96kHz fS = 48 kHz dB 112/106/100 113 123 123 EIAJ, A-weighted, fS = 192kHz Channel Separation 112/106/100 EIAJ, A-weighted, fS = 96kHz EIAJ, A-weighted, fS = 192kHz Signal to noise ratio with analog mute (3) (4) -83/ -82/ -80 123 100/ 95/ 90 109/103/97 fS = 96kHz 109/103/97 fS = 192kHz 109/103/97 Analog Output Output voltage 2.1 VRMS Gain error –6 ±2.0 6 Gain mismatch, channel-tochannel –6 ±2.0 6 –5 ±1.0 5 Bipolar zero error At bipolar zero Load impedance % of FSR % of FSR 1 mV kΩ Filter Characteristics–1: Normal Pass band 0.45fS Stop band 0.55fS Stop band attenuation –60 Pass-band ripple ±0.02 Delay time 20/fS dB s Filter Characteristics–2: Low Latency Pass band 0.47fS Stop band 0.55fS Stop band attenuation –52 Pass-band ripple ±0.0001 Delay time (2) (3) (4) 3.5/fS dB s Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode. Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter). Assert XSMT or both L-ch and R-ch PCM data are BPZ Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 5 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply Requirements DVDD Digital supply voltage 3.0 3.3 3.6 AVDD Analog supply voltage 3.0 3.3 3.6 CPVDD Charge-pump suply voltage 3.0 3.3 3.6 fS = 48kHz 7 12 fS = 96kHz 8 fS = 192kHz 9 fS = 48kHz 8 IDD IDD DVDD supply current at 3.3V DVDD supply current at 3.3V Target DVDD = 3.3V (5) (6) IDD DVDD supply current at 3.3V (7) ICC AVDD / CPVDD Supply Current (5) ICC ICC AVDD / CPVDD Supply Current (6) AVDD / CPVDD Supply Current (7) Power Dissipation, DVDD = 3.3V (5) Power Dissipation, DVDD = 3.3V (6) Power Dissipation, DVDD = 3.3V (7) (5) (6) (7) 6 fS = 96kHz 9 fS = 192kHz 10 mA 13 mA 0.5 0.8 fS = 48kHz 11 16 fS = 96kHz 11 fS = 192kHz 11 fS = 48kHz 22 fS = 96kHz 22 fS = 192kHz 22 fS = n/a 0.2 0.4 fS = 48kHz 59.4 92.4 fS = 96kHz 62.7 fS = 192kHz 66.0 fS = 48kHz 99.0 fS = 96kHz 102.3 fS = 192kHz 105.6 fS = n/a (Power Down Mode) 2.3 VDC mA mA 32 mA mA mW 148.5 mW 4.0 mW Input is Bipolar Zero data. Input is 1kHz -1dBFS data Power Down Mode Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PCM5100 THD+N vs Input Level PCM5101 THD+N vs Input Level 10 -10 -10 -30 -30 THD+N [dB] THD+N [dB] 10 -50 -50 -70 -70 -90 -90 -110 -100 -110 -80 -60 -40 Input Level [dBFS] -20 -100 0 -80 -60 -40 Input Level [dBFS] Figure 2. -20 0 Figure 3. PCM5102 THD+N vs Input Level 10 -10 THD+N [dB] -30 -50 -70 -90 -110 -100 -80 -60 -40 Input Level [dBFS] -20 0 Figure 4. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 7 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PCM5101 FFT Plot at BPZ With AMUTE -20 -40 -40 -60 -60 -80 -80 Amplitude [dB] Amplitude [dB] PCM5100 FFT Plot at BPZ With AMUTE -20 -100 -120 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 Frequency [kHz] 15 0 20 5 10 Frequency [kHz] Figure 5. 15 20 Figure 6. PCM5102 FFT Plot at BPZ With AMUTE -20 -40 -60 Amplitude [dB] -80 -100 -120 -140 -160 -180 0 5 10 Frequency [kHz] 15 20 Figure 7. 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PCM5101 FFT Plot at –60dB To 300kHz 0 -20 -20 -40 -40 -60 -60 Amplitude [dB] Amplitude [dB] PCM5100 FFT Plot at –60dB To 300kHz 0 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 200 Frequency [kHz] 250 0 300 50 100 150 200 Frequency [kHz] Figure 8. 250 300 Figure 9. PCM5102 FFT Plot at –60dB To 300kHz 0 -20 -40 Amplitude [dB] -60 -80 -100 -120 -140 -160 0 50 100 150 200 Frequency [kHz] 250 300 Figure 10. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 9 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INFORMATION Reset and System Clock Functions Power-On Reset Function The PCM510x includes a power-on reset function shown in Figure 11. With VDD > 2.8V, the power-on reset function is enabled. After the initialization period, the PCM510x is set to its default reset state. 3.3V 2.8V AVDD, DVDD, CPVDD Internal Reset Reset Removal Internal Reset 4 ms I2S Clocks SCK, BCK, LRCK Figure 11. Power-On Reset Timing, DVDD = 3.3V 10 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 System Clock Input The PCM510x requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 12) and supports up to 50MHz. The PCM510x system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies of 8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.4kHz -192kHz, and 384kHz with ±4% tolerance are supported. The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge Pump (NCP) automatically. Table 3 shows examples of system clock frequencies for common audio sampling rates. SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in software mode, available only in the PCM512x and PCM514x devices, by configuring various PLL and clockdivider registers. Software mode allows the device to become a clock master and drive the host serial port with LRCK and BCK, from a non-audio related clock; for example, using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK). Figure 12 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Table 3. System Master Clock Inputs for Audio Related Clocks System Clock Frequency (fSCK) (MHz) Sampling Frequency 64 fS 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1024 fS 1152 fS 1536 fS 2048 fS 3072 fS 8 kHz – (1) 1.0240 (2) 1.5360 (2) 2.0480 3.0720 4.0960 6.1440 8.1920 9.2160 12.2880 16.3840 24.5760 16 kHz – (1) 2.0480 (2) 3.0720 (2) 4.0960 6.1440 8.1920 12.2880 16.3840 18.4320 24.5760 36.8640 49.1520 32 kHz – (1) 4.0960 (2) 6.1440 (2) 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 49.1520 – (1) – (1) 44.1 kHz – (1) 5.6488 (2) 8.4672 (2) 11.2896 16.9344 22.5792 33.8688 45.1584 – (1) – (1) – (1) – (1) – (1) (2) (2) 49.1520 – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) 48 kHz 88.2 kHz 96 kHz 176.4 kHz 192 kHz 384 kHz (1) (2) 24.5760 6.1440 11.2896 (2) 12.2880 (2) 9.2160 12.2880 16.9344 22.5792 18.4320 22.5792 24.5760 33.8688 24.5760 45.1584 36.8640 49.1520 – 49.1520 (1) – (1) 18.4320 33.8688 36.8640 – (1) – (1) – (1) 24.5760 45.1584 49.1520 – (1) – (1) – (1) 36.8640 – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) – (1) This system clock rate is not supported for the given sampling frequency. This system clock rate is supported by PLL mode. tSCKH "H" 0.7*DVDD System Clock (SCK) 0.3*DVDD "L" tS CK L tSCY Figure 12. Timing Requirements for SCK Input Table 4. Timing Requirements for SCK Input Min Max Unit tSCY Parameters System clock pulse cycle time 20 1000 ns tSCKH System clock pulse width, High 9 ns tSCKL System clock pulse width, Low 9 ns Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 11 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com System Clock PLL Mode The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference. The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal SCK from the BCK reference. The PCM510x disables the internal PLL when an external SCK is supplied; specific BCK rates are required to generate an appropriate master clock. Table 5 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an internal SCK. Table 5. BCK Rates (MHz) by LRCK Sample Rate for PCM510x PLL Operation BCK (fS) Sample f (kHz) 32 64 8 - - 16 - 1.024 32 1.024 2.048 44.1 1.4112 2.8224 48 1.536 3.072 96 3.072 6.144 192 6.144 12.288 384 12.288 24.576 Audio Data Interface Audio Serial Interface The audio interface port is a 3-wire serial port, including LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM510x on the rising edge of BCK. LRCK is the serial audio left/right word clock. Table 6. PCM510x Audio Data Formats, Bit Depths and Clock Rates CONTROL MODE FORMAT DATA BITS Hardware Control I2S/LJ 32, 24, 20, 16 MAX LRCK FREQUENCY [fS] SCK RATE [x fS] BCK RATE [x fS] Up to 192kHz 128 – 3072 (≤50MHz) 64, 48, 32 384kHz 64, 128 64, 48, 32 The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase relation between LRCK and system clock. If the relationship between LRCK and system clock changes more than ±5 SCK, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and system clock is completed. If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and BCK is completed. 12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 PCM Audio Data Formats and Timing The PCM510x supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified. All formats require binary 2s complement, MSB-first audio data. Figure 13 shows a detailed timing diagram for the serial audio interface. LRCK 0. 5 * DVDD (Input) tBCH t BCL tLB BCK 0. 5 * DVDD (Input) tBCY tBL DATA 0. 5 * DVDD (Input) tDS tDH Figure 13. PCM510x Serial Audio Timing - Slave Table 7. Audio Interface Slave Timing Parameters Min Max Units tBCY BCK Pulse Cycle Time 40 ns tBCL BCK Pulse Width LOW 16 ns tBCH BCK Pulse Width HIGH 16 ns tBL BCK Rising Edge to LRCK Edge 8 ns tLB LRCK Edge to BCK Rising Edge 8 ns ns tDS DATA Set Up Time 8 tDH DATA Hold Time 8 fBCK BCK frequency @ DVDD=3.3V ns 24.576 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 MHz Submit Documentation Feedback 13 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com 1tS R-channel L-channel LRCK BCK Audio data word = 16-bit, BCK = 32, 48, 64fS 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB 2 23 Audio data word = 24-bit, BCK = 48, 64fS - , 1 2 2 24 1 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64fS 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB Left Justified Data Format; L-channel = HIGH, R-channel = LOW Figure 14. Left Justified Audio Data Format 1tS LRCK L- channel R- channel BCK Audio data word = 16-bit, BCK = 32, 48, 64fS 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB Audio data word = 24-bit, BCK = 48, 64fS 1 2 23 1 24 2 23 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64fS 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB 2 I S Data Format; L-channel = LOW, R-channel = HIGH Figure 15. I2S Audio Data Format 14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 Function Descriptions Interpolation Filter The PCM510x provides 2 types of interpolation filter. Users can select which filter to use by using the FLT pin (pin11) Table 8. Digital Interpolation Filter Options FLT Pin Description 0 FIR Normal x8/x4/x2/x1 Interpolation Filters 1 IIR Low Latency x8/x4/x2/x1 Interpolation Filters The Normal x8/x4/x2/x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sample time (tS) for sample rates from 8kHz to 384kHz. Table 9. Normal x8 Interpolation Filter Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typ) Filter Gain Stop Band 0.55fS ….. 7.455fS Filter Group Delay Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 4 −0.4 0 50 100 150 200 250 Samples 300 350 G023 G012 Figure 16. Normal x8 Interpolation Filter Frequency Response 400 Figure 17. Normal x8 Interpolation Filter Impulse Response Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 15 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.1 0.2 0.3 Frequency (x fS) 0.4 0.5 G034 Figure 18. Normal x8 Interpolation Filter Passband Ripple 16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 The Normal x4/x2/x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sample time (tS) for sample rates from 8kHz to 384kHz. Table 10. Normal x4 Interpolation Filter Parameter Condition Value (Typ) Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 7.455fS Filter Group Delay 0 Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 20 40 60 80 100 Samples 120 140 G009 Figure 19. Normal x4 Interpolation Filter Frequency Response 160 G020 Figure 20. Normal x4 Interpolation Filter Impulse Response 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.5 Frequency (x fS) 1.0 G031 Figure 21. Normal x4 Interpolation Filter Passband Ripple Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 17 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com Normal x2 / x1(bypass) Interpolation filter is programmed in 256 cycles in 1 sample time (tS) for sample rates from 8kHz to 384kHz. Table 11. Normal x2 Interpolation Filter Parameter Condition Value (Typ) Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 7.455fS Filter Group Delay 0 Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 10 20 30 40 50 60 Samples G006 Figure 22. Normal x2 Interpolation Filter Frequency Response 70 80 90 100 G017 Figure 23. Normal x2 Interpolation Filter Impulse Response 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.5 1.0 Frequency (x fS) 1.5 2.0 G028 Figure 24. Normal x2 Interpolation Filter Passband Ripple 18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 The low-latency x8 / x4 / x2 / x1(bypass) Interpolation filter is programmed in 256 cycles 1 sample time (tS) for sample rates from 8kHz to 384kHz. Table 12. Low latency x8 Interpolation Filter Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 7.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter Group Delay 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 4 −0.6 0 50 100 150 200 250 Samples 300 350 G011 Figure 25. Low latency x8 Interpolation Filter Frequency Response 400 G022 Figure 26. Low latency x8 Interpolation Filter Impulse Response 0.00010 0.00008 0.00006 Amplitude (dB) 0.00004 0.00002 0.00000 −0.00002 −0.00004 −0.00006 −0.00008 −0.00010 0.0 0.1 0.2 0.3 Frequency (x fS) 0.4 0.5 G033 Figure 27. Low latency x8 Interpolation Filter Passband Ripple Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 19 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com Table 13. Low latency x4 Interpolation Filter Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 3.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter Group Delay 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 4 −0.6 0 20 40 60 80 100 Samples G008 Figure 28. Low latency x4 Interpolation Filter Frequency Response 120 140 160 180 G019 Figure 29. Low latency x4 Interpolation Filter Impulse Response 0.0001 0.00008 0.00006 Amplitude (dB) 0.00004 0.00002 0 −0.00002 −0.00004 −0.00006 −0.00008 −0.0001 0.0 0.5 Frequency (x fS) 1.0 G030 Figure 30. Low latency x4 Interpolation Filter Passband Ripple 20 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 PCM5100, PCM5101, PCM5102 www.ti.com SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 Table 14. Low latency x2 Interpolation Filter Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 1.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter Group Delay space 0 1.0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 4 −0.4 0 10 20 30 40 50 60 Samples 70 80 90 G005 Figure 31. Low latency x2 Interpolation Filter Frequency Response 100 G016 Figure 32. Low latency x2 Interpolation Filter Impulse Response 0.0001 0.00008 0.00006 Amplitude (dB) 0.00004 0.00002 0 −0.00002 −0.00004 −0.00006 −0.00008 −0.0001 0.0 0.5 Frequency (x fS) 1.0 G030 Figure 33. Low latency x2 Interpolation Filter Passband Ripple Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: PCM5100 PCM5101 PCM5102 Submit Documentation Feedback 21 PCM5100, PCM5101, PCM5102 SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012 www.ti.com Zero Data Detect The PCM510x has a zero-data detect function. When the device detects continuous zero data, it enters a full analog mute condition. The PCM510x counts zero data over 1024LRCKs (21ms @ 48kHz) before setting analog mute. Power Save Mode When any kind of clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510x enters Stand-by mode automatically. The current-segment DAC and Line driver are also powered down. When BCK and LRCK halt to a low level for more than 1 second, the PCM510x enters Power down mode automatically. Power-down mode includes the negative charge pump and Bias/Reference circuit power-down in addition to stand-by. Whenever expected Audio clocks (SCK, BCK, LRCK) are applied to the PCM510x, the device starts its powerup sequence automatically. XSMT Pin (Soft Mute and Soft Un-Mute) For external digital control of the PCM510x, the XSMT pin must be driven by an external digital host with a specific/minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM510x requires tr/tf times of less than 20ns. In the majority of applications, this shouldn’t be a problem, however, traces with high capacitance may have issues. When the XSMT pin is shifted from high to low (3.3V to 0V), a soft digital attenuation ramp is started. –1dB attenuation will be applied every 1tS from 0dBFS to –∞. This attenuation takes 104 sample times. When the XSMT pin is shifted from low to high (0V to 3.3V), a soft digital “un-mute” is started. 1dB gain steps are applied every tS from –∞ to 0dBFS. This ramp-up takes 104 sample times. 0.9 * DVDD XSMT 0.1 * DVDD tr tf