PCM5102-Q1
Not Recommended For New Designs
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
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SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
2-VRMS DirectPath™, 112/106/100-dB Audio Stereo DAC With 32-Bit, 384-kHz PCM
Interface
Check for Samples: PCM5100-Q1 (Preliminary), PCM5101-Q1 (Preliminary), PCM5102-Q1
FEATURES
1
•
•
23
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 2: –40°C to
105°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
Market-Leading Low Out-of-Band Noise
Selectable Digital-Filter Latency and
Performance
No DC Blocking Capacitors Required
Integrated Negative Charge Pump
Internal Pop-Free Control For Sample-Rate
Changes or Clock Halts
Intelligent Muting System; Soft Up/Down Ramp
and Analog Mute For 120-dB Mute SNR With
Popless Operation.
Integrated High-Performance Audio PLL With
BCK Reference to Generate SCK Internally
Small 20-pin TSSOP Package
Typical Performance (3.3-V Power Supply)
Parameter
PCM5102-Q1 / PCM5101-Q1 /
PCM5100-Q1
SNR
112 / 106 / 100 dB
Dynamic range
112 / 106 / 100 dB
THD+N at –1 dBFS
Full-scale output
–93 / –92 / –90 dB
2.1VRMS (GND center)
Normal 8× oversampling digital-filter latency: 22 / fS
Low-latency 8× oversampling digital-filter latency: 3.5 / fS
Sampling frequency
8 kHz to 384 kHz
System clock multiples (fSCK): 64, 128, 192, 256, 384, 512,
768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
System Two Cascade, Audio Precision are trademarks of Audio Precision.
DirectPath is a trademark of Texas, Instruments, Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
PCM5102-Q1
Not Recommended For New Designs
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
ZeroData
Detector
Current
Segment
DAC
I/V
Analog
Mute
Current
Segment
DAC
I/V
Analog
Mute
32-Bit ΔΣ Modulator
Audio Interface
2
DIN (I S)
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8´ Interpolation Filter
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
LINE OUT
Advanced Mute Control
Clock Halt
Detection
PCM510x-Q1
PLL Clock
Power
Supply
LRCK
BCK
UVP/Reset
POR
Ch. Pump
VNEG
CAPM
CAPP
MCK
CPVDD (3.3 V)
AVDD (3.3 V)
DVDD (3.3 V)
GND
Figure 1. PCM510x-Q1 Functional Block Diagram
OTHER KEY FEATURES
•
•
•
•
•
•
•
Accepts 16-, 24-, and 32-Bit Audio Data
PCM Data Formats: I2S, Left-Justified
Automatic Power-Save Mode When LRCK And
BCK Are Deactivated
3.3-V Failsafe LVCMOS Digital Inputs
Hardware Configuration
Single-Supply Operation:
– 3.3-V Analog, 3.3-V Digital
Integrated Power-On Reset
APPLICATIONS
•
•
•
•
A/V Receivers
DVD, BD Players
HDTV Receivers
Applications Requiring 2-VRMS Audio Output
DESCRIPTION
The PCM510x-Q1 family is a series of monolithic
CMOS integrated circuits that include a stereo digitalto-analog converter and additional support circuitry in
a small TSSOP package. The PCM510x-Q1 uses the
latest generation of TI’s advanced segment-DAC
architecture
to
achieve
excellent
dynamic
performance and improved tolerance to clock jitter.
2
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The PCM510x-Q1 provides 2.1-VRMS groundcentered outputs, allowing designers to eliminate not
only dc blocking capacitors on the output, but also
external muting circuits traditionally associated with
single-supply line drivers.
The integrated line driver surpasses all other chargepump-based line drivers by supporting loads down to
1 kΩ. By supporting loads down to 1 kΩ, the
PCM510x-Q1 can essentially drive up to 10 products
in parallel (LCD TV, DVDR, AV receivers, and so on).
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock). This allows a three-wire I2S
connection, along with reduced system EMI.
Intelligent clock error and PowerSense undervoltage
protection uses a two-level mute system for pop-free
performance. On clock error or system power failure,
the device digitally attenuates the data (or last
known-good data), then mutes the analog circuit
Compared with existing DAC technology, the
PCM510x-Q1 offers up to 20-dB lower out-of-band
(OBN) noise, reducing EMI and aliasing in
downstream amplifiers/ADCs. (from traditional 100kHz OBN measurements all the way to 3 MHz)
The PCM510x-Q1 accepts industry-standard audio
data formats with 16- to 32-bit data and supports
sSample rates up to 384 kHz.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: PCM5100-Q1 (Preliminary) PCM5101-Q1 (Preliminary) PCM5102-Q1
PCM5102-Q1
Not Recommended For New Designs
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PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
Table 1. Ordering Information
Part Number
TA
Top-Side Symbol
PCM5100TPWRQ1 (Preview)
–40°C to 105°C
PCM5100Q
PCM5101TPWRQ1 (Preview)
–40°C to 105°C
PCM5101Q
PCM5102TPWRQ1
–40°C to 105°C
PCM5102Q
spacer
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
Supply voltage
AVDD, CPVDD, DVDD
UNIT
–0.3 to 3.9
Digital input voltage
–0.3 to 3.9
Analog input voltage
–0.3 to 3.9
Operating temperature range
–40 to 105
Storage temperature range
–65 to 150
Human-body model (HBM) AEC-Q100 Classification
Level H2
ESD rating
Charged-device model (CDM) AEC-Q100
Classification Level C3B
V
°C
2
kV
750
V
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
θJA
Theta JA
ψJT
Psi JT
1
ψJB
Psi JB
41.5
θJC
Theta JC
θJB
Theta JB
High K
MAX
UNIT
91.2
Top
ºC/W
25.3
42
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
3
3.3
3.6
VDC
3
3.3
3.6
VDC
3
VDC
Power-Supply Requirements
DVDD
Digital supply voltage
AVDD
Analog supply voltage
CPVDD
Charge-pump supply voltage
IDD
IDD
DVDD supply current at 3.3
V (1)
DVDD supply current at 3.3
V (2)
IDD
DVDD supply current at 3.3
V (3)
ICC
AVDD / CPVDD supply
current (1)
(1)
(2)
(3)
Target DVDD = 3.3 V
3.3
3.6
fS = 48 kHz
7
12
fS = 96 kHz
8
fS = 192 kHz
9
fS = 48 kHz
8
fS = 96 kHz
9
fS = 192 kHz
10
mA
13
mA
0.5
0.8
fS = 48 kHz
11
16
fS = 96 kHz
11
fS = 192 kHz
11
mA
mA
Input is bipolar-zero data.
Input is 1-kHz, –1-dBFS data.
Power-down mode
Copyright © 2012–2013, Texas Instruments Incorporated
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3
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
PCM5102-Q1
Not Recommended For New Designs
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
32
UNIT
Power-Supply Requirements
ICC
ICC
AVDD / CPVDD supply
current (2)
AVDD / CPVDD supply
current (3)
Power dissipation, DVDD = 3.3
V (1)
fS = 48 kHz
22
fS = 96 kHz
22
fS = 192 kHz
22
fS = N/A
0.2
0.4
fS = 48 kHz
59.4
92.4
fS = 96 kHz
62.7
fS = 192 kHz
Power dissipation, DVDD = 3.3
V (2)
Power dissipation, DVDD = 3.3
V (3)
4
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mA
mW
66
fS = 48 kHz
99
fS = 96 kHz
102.3
fS = 192 kHz
105.6
fS = N/A (power-down mode)
mA
2.3
148.5
mW
4
mW
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: PCM5100-Q1 (Preliminary) PCM5101-Q1 (Preliminary) PCM5102-Q1
PCM5102-Q1
Not Recommended For New Designs
www.ti.com
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
16
24
32
UNIT
Bits
384
kHz
Data Format (PCM Mode)
fS
Audio data interface format
I2S, left justified
Audio data bit length
16, 24, 32-bit acceptable
Audio data format
MSB-first, 2s complement
Sampling frequency
8
System clock frequency
64, 128, 192, 256, 384, 512, 768, 1024, 1152, 1536, 2048, or
3072
fSCK, up to 50 Mhz
Digital Input/Output
Logic family: 3.3-V LVCMOS compatible
VIH
VIL
IIH
IIL
VOH
VOL
0.7 × DVDD
Input logic level
Input logic current
Output logic level
V
0.3 × DVDD
VIN = VDD
10
VIN = 0 V
–10
IOH = –4 mA
µA
0.8 × DVDD
IOL = 4 mA
V
0.22 × DVDD
Dynamic Performance (PCM Mode) (1) (2) (Values shown for three devices PCM5102-Q1/PCM5101-Q1/PCM5100-Q1)
fS = 48 kHz
–93/–92/–90
THD+N at –1 dBFS (2)
fS = 96 kHz
–93/–92/–90
Dynamic range (2)
EIAJ, A-weighted, fS = 48 kHz
fS = 192 kHz
Signal-to-noise ratio (2)
Signal-to-noise ratio with
analog mute (2) (3)
Channel separation
–93/–92/–90
106/100/95
112/106/100
EIAJ, A-weighted, fS = 96 kHz
112/106/100
EIAJ, A-weighted, fS = 192
kHz
112/106/100
EIAJ, A-weighted, fS = 48 kHz
112/106/100
EIAJ, A-weighted, fS = 96 kHz
112/106/100
EIAJ, A-weighted, fS = 192
kHz
112/106/100
EIAJ, A-weighted, fS = 48 kHz
113
123
EIAJ, A-weighted, fS = 192
kHz
123
100/95/90
dB
123
EIAJ, A-weighted, fS = 96 kHz
fS = 48 kHz
–83/–82/–80
109/103/97
fS = 96 kHz
109/103/97
fS = 192 kHz
109/103/97
Analog Output
Output voltage
2.1
VRMS
Gain error
–6
±2
6
Gain mismatch, channel-tochannel
–6
±2
6
–5
±1
5
Bipolar-zero error
At bipolar zero
Load impedance
% of FSR
% of FSR
1
mV
kΩ
Filter Characteristics–1: Normal
(1)
(2)
(3)
Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF; dynamic range: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted signal-to-noise
ratio: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted channel separation: 20-Hz HPF, 20-kHz AES17 LPF; using the System Two
Cascade™ audio measurement system by Audio Precision™ in the rms mode to measure analog performance specifications.
Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see recommended output filter).
Both L-ch and R-ch are BPZ with XSMT de-asserted
Copyright © 2012–2013, Texas Instruments Incorporated
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5
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
PCM5102-Q1
Not Recommended For New Designs
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
Pass band
MAX
UNIT
0.45 fS
Stop band
0.55 fS
Stop-band attenuation
–60
Pass-band ripple
±0.02
Delay time
22 / fS
dB
s
Filter Characteristics–2: Low Latency
Pass band
0.47 fS
Stop band
0.55 fS
Stop-band attenuation
–52
Pass-band ripple
±0.0001
Delay time
3.5 / fS
dB
s
DEVICE INFORMATION
TERMINAL FUNCTIONS, PCM510x-Q1
PW Package
20 Pins
(Top View)
CPVDD
1
20
DVDD
CAPP
2
19
DGND
CPGND
3
18
LDOO
CAPM
4
17
XSMT
VNEG
5
16
FMT
OUTL
6
15
LRCK
OUTR
7
14
DIN
AVDD
8
13
BCK
AGND
9
12
SCK
DEMP
10
11
FLT
Table 2. PIN FUNCTIONS, PCM510x-Q1
PIN
DESCRIPTION
NO.
AGND
9
—
Analog ground
AVDD
8
-—
Analog power supply, 3.3 V
BCK
13
I
Audio-data bit-clock input (1)
CAPM
4
O
Charge-pump flying-capacitor terminal for negative rail
CAPP
2
O
Charge-pump flying-capacitor terminal for positive rail
CPGND
3
—
Charge-pump ground
CPVDD
1
—
DEMP
10
I
DGND
19
—
DIN
14
I
DVDD
20
—
FLT
11
I
Filter select : Normal latency (Low) or Low latency (High)
FMT
16
I
Audio format selection : I2S (Low) or Left-justified (High)
(1)
6
I/O
NAME
Charge-pump power supply, 3.3 V
De-emphasis control for 44.1-kHz sampling rate (1): Off (Low), On (High)
Digital ground
Audio-data input (1)
Digital power supply, 3.3 V
Failsafe LVCMOS Schmitt-trigger input
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PCM5102-Q1
Not Recommended For New Designs
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PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
Table 2. PIN FUNCTIONS, PCM510x-Q1 (continued)
PIN
I/O
DESCRIPTION
18
—
Internal-logic supply-rail terminal for decoupling
15
I
Audio-data word-clock input (1)
6
O
Analog output from DAC left channel
OUTR
7
O
Analog output from DAC right channel
SCK
12
I
System clock input (1)
VNEG
5
O
Negative charge-pump rail terminal for decoupling, –3.3 V
XSMT
17
I
Soft-mute control (1): Soft mute (Low), Soft un-mute (High)
NAME
NO.
LDOO
LRCK
OUTL
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7
PCM5102-Q1
Not Recommended For New Designs
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data unless
otherwise noted.
PCM5100-Q1 THD+N
versus
INPUT LEVEL
PCM5101-Q1 THD+N
versus
INPUT LEVEL
10
-10
-10
-30
-30
THD+N [dB]
THD+N [dB]
10
-50
-50
-70
-70
-90
-90
-110
-110
-100
-80
-60
-40
Input Level [dBFS]
-20
-100
0
-80
-60
-40
Input Level [dBFS]
Figure 2.
-20
0
Figure 3.
PCM5102-Q1 THD+N
versus
INPUT LEVEL
10
-10
THD+N [dB]
-30
-50
-70
-90
-110
-100
-80
-60
-40
Input Level [dBFS]
-20
0
Figure 4.
8
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PCM5102-Q1
Not Recommended For New Designs
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PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data unless
otherwise noted.
PCM5101-Q1 FFT PLOT AT BPZ WITH AMUTE
-20
-40
-40
-60
-60
-80
-80
Amplitude [dB]
Amplitude [dB]
PCM5100-Q1 FFT PLOT AT BPZ WITH AMUTE
-20
-100
-120
-100
-120
-140
-140
-160
-160
-180
-180
0
5
10
Frequency [kHz]
15
5
0
20
10
Frequency [kHz]
Figure 5.
15
20
Figure 6.
PCM5102-Q1 FFT PLOT AT BPZ WITH AMUTE
-20
-40
-60
Amplitude [dB]
-80
-100
-120
-140
-160
-180
0
5
10
Frequency [kHz]
15
20
Figure 7.
Copyright © 2012–2013, Texas Instruments Incorporated
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9
PCM5102-Q1
Not Recommended For New Designs
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS, and 24-bit data unless
otherwise noted.
PCM5101-Q1 FFT PLOT AT –60 dB TO 300 kHz
0
-20
-20
-40
-40
-60
-60
Amplitude [dB]
Amplitude [dB]
PCM5100-Q1 FFT PLOT AT –60 dB TO 300 kHz
0
-80
-100
-80
-100
-120
-120
-140
-140
-160
-160
0
50
100
150
200
Frequency [kHz]
250
0
300
50
100
150
200
Frequency [kHz]
Figure 8.
250
300
Figure 9.
PCM5102-Q1 FFT PLOT AT –60 dB TO 300 kHz
0
-20
-40
Amplitude [dB]
-60
-80
-100
-120
-140
-160
0
50
100
150
200
Frequency [kHz]
250
300
Figure 10.
10
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PCM5102-Q1
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PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
APPLICATION INFORMATION
Reset and System Clock Functions
Power-On Reset Function
The PCM510x-Q1 includes a power-on-reset function shown in Figure 11. Having VDD > 2.8 V enables the
power-on reset function. After the initialization period, the PCM510x-Q1 enters its default reset state.
3.3V
2.8V
AVDD, DVDD,
CPVDD
Internal Reset
Reset Removal
Internal Reset
4 ms
I2S Clocks
SCK, BCK, LRCK
Figure 11. Power-On Reset Timing, DVDD = 3.3 V
Copyright © 2012–2013, Texas Instruments Incorporated
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11
PCM5102-Q1
Not Recommended For New Designs
PCM5100-Q1 (Preliminary)
PCM5101-Q1 (Preliminary)
PCM5102-Q1
SLAS832C – MARCH 2012 – REVISED FEBRUARY 2013
www.ti.com
System-Clock Input
The PCM510x-Q1 requires a system clock for operating the digital interpolation filters and advanced segment
DAC modulators. The system clock, applied at the SCK input (pin 12), supports up to 50 MHz. The PCM510x-Q1
has a system-clock detection circuit that automatically senses the system-clock frequency. The device supports
common audio sampling frequencies of 8 kHz, 16 kHz, 32 kHz–44.1 kHz and 48 kHz, 88.2 kHz-96 kHz, 176.4
kHz-192 kHz, and 384 kHz with ±4% tolerance. The sampling-frequency detector sets the clock for the digital
filter, delta-sigma modulator (DSM), and the negative charge pump (NCP) automatically. Table 3 shows
examples of system clock frequencies for common audio sampling rates.
NOTE
The sampling frequency detector only detects six sampling-frequency options. Any
sampling frequency between the range of 32 kHz–44.1 kHz (or if it is 48 kHz) is one
option. The same case applies for the ranges from 88.2 kHz–96 kHz and 176.4 kHz–192
kHz.
The device supports SCK rates between 1 MHz and 50 MHz that are not common to standard audio clocks by
configuring various PLL and clock-divider registers. This allows the device to become a clock master and drive
the host serial port with LRCK and BCK, from a non-audio related clock (for example. using 12 MHz to generate
44.1 kHz (LRCK) and 2.8224 MHz (BCK)).
Figure 12 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise.
Table 3. System Master Clock Inputs for Audio-Related Clocks
System Clock Frequency (fSCK) (MHz)
Sampling
Frequency
64 fS
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1024 fS
1152 fS
1536 fS
2048 fS
3072 fS
8 kHz
– (1)
1.0240 (2)
1.5360 (2)
2.0480
3.0720
4.0960
6.1440
8.1920
9.2160
12.2880
16.3840
24.5760
16 kHz
– (1)
2.0480 (2)
3.0720 (2)
4.0960
6.1440
8.1920
12.2880
16.3840
18.4320
24.5760
36.8640
49.1520
32 kHz
–
(1)
4.0960
(2)
6.1440 (2)
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
49.1520
– (1)
– (1)
–
(1)
5.6488
(2)
(2)
11.2896
16.9344
22.5792
33.8688
45.1584
(1)
– (1)
44.1 kHz
8.4672
–
(1)
–
(1)
–
48 kHz
– (1)
6.1440 (2)
9.2160 (2)
12.2880
18.4320
24.5760
36.8640
49.1520
– (1)
– (1)
– (1)
– (1)
88.2 kHz
– (1)
11.2896 (2)
16.9344
22.5792
33.8688
45.1584
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
96 kHz
– (1)
12.2880 (2)
18.4320
24.5760
36.8640
49.1520
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
176.4 kHz
– (1)
22.5792
33.8688
45.1584
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
192 kHz
– (1)
24.5760
36.8640
49.1520
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
384 kHz
24.5760
49.1520
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
– (1)
(1)
(2)
The device does not support this system clock rate for the given sampling frequency.
PLL mode supports this system clock rate.
tSCKH
"H"
0.7*DVDD
System Clock
(SCK)
0.3*DVDD
"L"
tSCY
tS CK L
Figure 12. Timing Requirements for SCK Input
Table 4. Timing Requirements for SCK Input
Parameters
12
Min
Max
tSCY
System clock-pulse cycle time
20
1000
tSCKH
System clock-pulse duration, High
9
ns
tSCKL
System clock-pulse duration, Low
9
ns
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Unit
ns
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System Clock PLL Mode
The system clock PLL mode allows designers to use a simple three-wire I2S audio source when driving the DAC,
thereby reducing the need for a high-frequency SCK, making PCB layout easier, and reducing high-frequency
electromagnetic interference.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. In the PCM510x-Q1, supplying an external SCK disables the internal PLL; the
device requires specific BCK rates to generate an appropriate master clock. Table 5 describes the minimum and
maximum BCK per LRCK for the integrated PLL to generate an internal SCK automatically.
Table 5. BCK Rates (MHz) by LRCK Sample Rate for
PCM510x-Q1 PLL Operation
BCK (fS)
Sample f (kHz)
32
64
8
–
–
16
–
1.024
32
1.024
2.048
44.1
1.4112
2.8224
3.072
48
1.536
96
3.072
6.144
192
6.144
12.288
384
12.288
24.576
Audio Data Interface
Audio Serial Interface
The audio interface port is a three-wire serial port. It includes LRCK (pin 15), BCK (pin 13), and DIN (pin 14).
BCK is the serial audio bit clock, and it clocks the serial data present on DIN into the serial shift register of the
audio interface. Clocking of serial data into the PCM510x-Q1 occurs on the rising edge of BCK. LRCK is the
serial audio left/right word clock.
Table 6. PCM510x-Q1 Audio Data Formats, Bit Depths and Clock Rates
CONTROL MODE
FORMAT
DATA BITS
Hardware control
I2S or LJ
32, 24, 20, 16
MAX LRCK
FREQUENCY [fS]
SCK RATE [× fS]
BCK RATE [× fS]
Up to 192 kHz
128–3072 (≤50
MHz)
64, 48, 32
384 kHz
64, 128
64, 48, 32
The PCM510x-Q1 requires the synchronization of LRCK and system clock, but does not need a specific phase
relation between LRCK and system clock.
If the relationship between LRCK and system clock changes more than ±5 SCK, the device initializes internal
operation within one sample period and forces analog outputs to the bipolar-zero level until the completion of
resynchronization between LRCK and the system clock.
If the relationship between LRCK and BCK is invalid for more than 4 LRCK periods, the device initializes internal
operation within one sample period and forces analog outputs to the bipolar-zero level until the completion of
resynchronization between LRCK and BCK.
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PCM Audio Data Formats and Timing
The PCM510x-Q1 supports industry-standard audio data formats, including standard I2S and left-justified. Data
formats are selected using the FMT (pin 16), Low for I2S, and High for left-justified.
All formats require binary 2s-complement, MSB-first audio data. Figure 13 shows a detailed timing diagram for
the serial audio interface.
LRCK
0. 5 * DVDD
(Input)
tBCH
t BCL
tLB
BCK
0. 5 * DVDD
(Input)
tBCY
tBL
DATA
0. 5 * DVDD
(Input)
tDS
tDH
Figure 13. PCM510x-Q1 Serial Audio Timing - Slave
Table 7. Audio Interface Slave Timing
14
Parameters
Min
tBCY
BCK pulse cycle time
40
Max
Unit
ns
tBCL
BCK pulse duration, LOW
16
ns
tBCH
BCK pulse duration, HIGH
16
ns
tBL
BCK rising edge to LRCK edge
8
ns
tLB
LRCK edge to BCK rising edge
8
ns
ns
tDS
DATA setup time
8
tDH
DATA hold time
8
fBCK
BCK frequency at DVDD = 3.3 V
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ns
24.576
MHz
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1/fS
R-channel
L-channel
LRCK
BCK
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15
16
1
2
15
16
DATA
MSB
LSB
MSB
LSB
2
23
Audio data word = 24-bit, BCK = 48, 64fS
- ,
1
2
2
24
1
24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31
32
1
2
31
32
DATA
MSB
LSB
MSB
LSB
Left-justified data format; L-channel = HIGH, R-channel = LOW
Figure 14. Left-Justified Audio Data Format
1/fS
LRCK
L- channel
R- channel
BCK
Audio data word = 16-bit, BCK = 32, 48, 64fS
1
2
15
16
1
2
15
16
DATA
MSB
LSB
MSB
LSB
Audio data word = 24-bit, BCK = 48, 64fS
1
2
23
1
24
2
23
24
DATA
MSB
LSB
MSB
LSB
Audio data word = 32-bit, BCK = 64fS
1
2
31
32
1
2
31
32
DATA
MSB
LSB
MSB
LSB
2
I S Data Format; L-channel = LOW, R-channel = HIGH
Figure 15. I2S Audio Data Format
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Function Descriptions
Interpolation Filter
The PCM510x-Q1 provides two types of interpolation filter. Users can select which filter to use by using the FLT
pin (pin11).
Table 8. Digital Interpolation Filter Options
FLT Pin
Description
0
FIR normal ×8, ×4, ×2, and ×1 interpolation filters
1
IIR low-latency ×8, ×4, ×2, and ×1 interpolation filters
The normal ×8, ×4, ×2, or ×1 (bypass) interpolation filter is programmed in 256 cycles in 1 sampling frequency
(fS) for from 8 kHz to 384 kHz.
Table 9. Normal ×8 Interpolation Filter
Parameter
Condition
Filter-gain pass band
0–0.45 fS
Filter-gain stop band
0.55 fS–7.455 fS
Value (Typ)
Filter-group delay
Value (Max)
Unit
±0.02
dB
–60
dB
22 / fS
s
space
1.0
0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
4
−0.4
0
50
100
150
200
250
Samples
16
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350
400
G023
G012
Figure 16. Normal ×8 Interpolation-Filter Frequency
Response
300
Figure 17. Normal ×8 Interpolation-Filter Impulse
Response
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0.05
0.04
0.03
Amplitude (dB)
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.1
0.2
0.3
Frequency (x fS)
0.4
0.5
G034
Figure 18. Normal ×8 Interpolation-Filter Pass-Band Ripple
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The normal ×4, ×2, or ×1 (bypass) interpolation filter is programmed in 256 cycles in 1 sampling frequency (fS)
from 8 kHz to 384 kHz.
Table 10. Normal ×4 Interpolation Filter
Parameter
Condition
Filter-gain pass band
0–0.45 fS
Filter-gain stop band
0.55 fS–7.455 fS
Value (Typ)
Filter-group delay
Value (Max)
Unit
±0.02
dB
–60
dB
22 / fS
s
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
−0.4
4
0
20
40
60
80
100
Samples
G009
Figure 19. Normal ×4 Interpolation-Filter Frequency
Response
120
140
160
G020
Figure 20. Normal ×4 Interpolation-Filter Impulse
Response
0.05
0.04
0.03
Amplitude (dB)
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
Frequency (x fS)
1.0
G031
Figure 21. Normal ×4 Interpolation-Filter Pass-Band Ripple
18
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Normal ×2 or ×1 (bypass) interpolation filter is programmed in 256 cycles in 1 sampling frequency (fS) from 8 kHz
to 384 kHz.
Table 11. Normal ×2 Interpolation Filter
Parameter
Condition
Value (Typ)
Filter-gain pass band
0–0.45 fS
Filter-gain stop band
0.55 fS–7.455 fS
Filter-group delay
Value (Max)
Unit
±0.02
dB
–60
dB
22 / fS
s
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
−0.4
4
0
10
20
30
40
50
60
Samples
70
80
90
G006
Figure 22. Normal ×2 Interpolation-Filter Frequency
Response
100
G017
Figure 23. Normal ×2 Interpolation-Filter Impulse
Response
0.05
0.04
0.03
Amplitude (dB)
0.02
0.01
0.00
−0.01
−0.02
−0.03
−0.04
−0.05
0.0
0.5
1.0
Frequency (x fS)
1.5
2.0
G028
Figure 24. Normal ×2 Interpolation-Filter Pass-Band Ripple
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The low-latency ×8, ×4, ×2, or ×1 (bypass) interpolation filter is programmed in 256 cycles in 1 fS from 8 kHz to
384 kHz.
Table 12. Low-Latency ×8 Interpolation Filter
Parameter
Condition
Value (Typ)
Unit
Filter-gain pass band
0–0.45 fS
±0.0001
dB
Filter-gain stop band
0.55 fS–7.455 fS
–52
dB
3.5 / fS
s
Filter-group delay
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
0.0
−80
−0.2
−100
−0.4
−120
0
1
2
Frequency (x fS)
3
4
−0.6
0
50
100
150
200
250
Samples
G011
Figure 25. ×8 Interpolation-Filter Frequency
Response
300
350
400
G022
Figure 26. Low-Latency ×8 Interpolation-Filter
Impulse Response
0.00010
0.00008
0.00006
Amplitude (dB)
0.00004
0.00002
0.00000
−0.00002
−0.00004
−0.00006
−0.00008
−0.00010
0.0
0.1
0.2
0.3
Frequency (x fS)
0.4
0.5
G033
Figure 27. Low-Latency ×8 Interpolation-Filter Pass-Band Ripple
20
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Table 13. Low-Latency ×4 Interpolation Filter
Parameter
Condition
Value (Typ)
Unit
Filter-gain pass band
0–0.45 fS
±0.0001
dB
Filter-gain stop band
0.55 fS–3.455 fS
–52
dB
3.5 / fS
s
Filter-group delay
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
0.0
−80
−0.2
−100
−0.4
−120
0
1
2
Frequency (x fS)
3
4
−0.6
0
20
40
60
80
100
Samples
120
140
160
G008
Figure 28. Low-Latency ×4 Interpolation-Filter
Frequency Response
180
G019
Figure 29. Low-Latency ×4 Interpolation-Filter
Impulse Response
0.0001
0.00008
0.00006
Amplitude (dB)
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 30. Low latency ×4 Interpolation-Filter Pass-Band Ripple
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Table 14. Low-Latency ×2 Interpolation Filter
Parameter
Condition
Value (Typ)
Unit
Filter-gain pass band
0–0.45 fS
±0.0001
dB
Filter-gain stop band
0.55 fS–1.455 fS
–52
dB
3.5 / fS
s
Filter-group delay
space
0
1.0
0.8
−20
0.6
Amplitude (FFS)
Amplitude (dB)
−40
−60
0.4
0.2
−80
0.0
−100
−120
−0.2
0
1
2
Frequency (x fS)
3
4
−0.4
0
10
20
30
40
50
60
Samples
G005
Figure 31. Low-Latency ×2 Interpolation-Filter
Frequency Response
70
80
90
100
G016
Figure 32. Low-Latency ×2 Interpolation-Filter
Impulse Response
0.0001
0.00008
0.00006
Amplitude (dB)
0.00004
0.00002
0
−0.00002
−0.00004
−0.00006
−0.00008
−0.0001
0.0
0.5
Frequency (x fS)
1.0
G030
Figure 33. Low-Latency ×2 Interpolation-Filter Pass-Band Ripple
22
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Zero-Data Detect
The PCM510x-Q1 has a zero-data detect function. When the device detects continuous zero data, it enters a full
analog-mute condition.
The PCM510x-Q1 counts zero data over 1024 LRCKs (21 ms at 48 kHz) before setting analog mute.
Power-Save Mode
On detection of any kind of clock error (SCK, BCK, and LRCK) or clock halt, the PCM510x-Q1 enters standby
mode automatically and powers down the current-segment DAC and line driver.
When BCK and LRCK halt to a low level for more than 1 second, the PCM510x-Q1 enters the power-down mode
automatically. Power-down mode includes the negative charge pump and reference circuit power-down in
addition to standby.
On application of expected audio clocks (SCK, BCK, LRCK) to the PCM510x-Q1, the device starts its power-up
sequence automatically.
XSMT Pin (Soft Mute and Soft Un-Mute)
For external digital control of the PCM510x-Q1, an external digital host must drive the XSMT pin with a specific
minimum rise time (tr) and fall time (tf) for soft mute and soft un-mute. The PCM510x-Q1 requires tr and tf times
of less than 20 ns. In the majority of applications, this should not be a problem; however, traces with high
capacitance may have issues.
When shifting the XSMT pin from high to low (3.3 V to 0 V), a soft digital attenuation ramp starts. Gain steps of
–1 dB occur every 1 / fS from 0 dBFS to –∞. This takes 104 sample periods.
Shifting the XSMT pin from low to high (0 V to 3.3V) starts a soft digital un-mute. Gain steps of 1 dB occur every
1 / fS from –∞ to 0 dBFS. This takes 104 sample periods.
0.9 * DVDD
XSMT
0.1 * DVDD
tR
tF
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