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PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
PCM512x 2-VRMS DirectPath™, 112-dB and 106-dB Audio Stereo DACs
With 32-Bit, 384-kHz PCM Interface
1 Features
3 Description
•
The PCM512x devices are a family of monolithic
CMOS-integrated circuits that include a stereo digitalto-analog converter and additional support circuitry in
a small TSSOP package. The PCM512x uses the
latest generation of TI’s advanced segment-DAC
architecture
to
achieve
excellent
dynamic
performance and improved tolerance to clock jitter.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Register-Selectable Audio-Processing Functions
up to 48-kHz fS
– Dynamic Range Control (DRC)
– Equalization (EQ)
– Filtering
DAC Functionality to 384-kHz fS
Market-Leading Low Out-of-Band Noise
Selectable Digital-Filter Latency and Performance
No DC-Blocking Capacitors Required
Integrated Negative Charge Pump
Intelligent Muting System; Soft Up or Down Ramp
and Analog Mute for 120-dB Mute SNR
Integrated High-Performance Audio PLL With
BCK Reference to Generate SCK Internally
Accepts 16-, 20-, 24-, and 32-Bit Audio Data
PCM Data Formats: I2S, Left-Justified, RightJustified, TDM / DSP
SPI or I2C Control
Software or Hardware Configuration
Automatic Power-Save Mode When LRCK and
BCK are Deactivated
1.8-V or 3.3-V Failsafe LVCMOS Digital Inputs
Single Supply Operation:
– 3.3-V Analog, 1.8-V or 3.3-V Digital
Integrated Power-On Reset
Small28-Pin Package
Members of the PCM512x family integrate preset
audio processing functions with programmable
coefficients, allowing developers to change the
characteristics of the interpolation filter, speaker EQ,
dynamic range controls, and average volume control
in their products.
The PCM512x provides 2.1-VRMS ground-centered
outputs, allowing designers to eliminate DC-blocking
capacitors on the output, as well as external muting
circuits traditionally associated with single supply line
drivers.
The integrated line driver surpasses all other chargepump-based line drivers by supporting loads down to
1 kΩ. By supporting loads down to 1 kΩ, the
PCM512x can essentially drive up to 10 products in
parallel (LCD TV, DVDR, AV receivers, and so forth).
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock), allowing a 3-wire I2S connection, along
with reducing system EMI.
Device Information(1)
PART NUMBER
PCM5121
PACKAGE
TSSOP (28)
BODY SIZE (NOM)
9.7 mm × 4.4 mm
2 Applications
PCM5122
•
•
•
•
(1) For all available packages, see the package option addendum
at the end of the data sheet.
A/V Receivers
DVD, BD Players
HDTV Receivers
Applications Requiring 2-VRMS Audio Output
Simplified System Diagram
2
I S
PCM1863/5
BCK
LRCK
IN
AUX
DOUT
Audio
Processing
Blocks,
Filters
IN
MIC
2ch Single Ended
Current Segment DAC
PCM512x
Analog
Sensor
- Light Intensity
- Ultrasonic
- Battery Level
BT Module
MSP430
TPA3130
TPA6120A2
WiLAN chip
OUT
LINE
2ch Single Ended
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
1
1
1
2
4
5
7
Specifications......................................................... 7
6.1 Pin Functions ............................................................ 5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
8.5
9
Absolute Maximum Ratings ...................................... 7
ESD Ratings ............................................................ 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Timing Requirements: SCK Input ........................... 11
Timing Requirements: XSMT .................................. 11
Switching Characteristics ........................................ 11
Typical Characteristics ............................................ 12
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
14
14
14
51
57
Application and Implementation ........................ 58
9.2 Typical Application .................................................. 58
10 Power Supply Recommendations ..................... 60
10.1 Power Supply Distribution and Requirements ......
10.2 Recommended Powerdown Sequence.................
10.3 External Power Sense Undervoltage Protection
Mode ........................................................................
10.4 Power-On Reset Function.....................................
10.5 PCM512x Power Modes .......................................
60
60
62
64
65
11 Layout................................................................... 66
11.1 Layout Guidelines ................................................. 66
11.2 Layout Example .................................................... 66
12 Register Maps...................................................... 67
12.1 PCM512x Register Map ........................................ 67
13 Device and Documentation Support ............... 113
13.1
13.2
13.3
13.4
Development Support .........................................
Documentation Support ......................................
Related Links ......................................................
Receiving Notification of Documentation
Updates..................................................................
13.5 Community Resources........................................
13.6 Trademarks .........................................................
13.7 Electrostatic Discharge Caution ..........................
13.8 Glossary ..............................................................
113
113
113
113
113
113
113
113
14 Mechanical, Packaging, and Orderable
Information ......................................................... 114
9.1 Application Information............................................ 58
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2016) to Revision C
•
Page
Added bullet item with additional description for 3-wire mode operation to Design Requirements section ........................ 58
Changes from Revision A (September 2012) to Revision B
Page
•
Changed Accepts 16-, 24-, And 32-Bit Audio Data to Accepts 16-, 20-, 24-, And 32-Bit Audio Data ................................... 1
•
Deleted Internal Pop-Free Control For Sample-Rate Changes Or Clock Halts, .. With Popless Operation .......................... 1
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................... 1
•
Clarified Pin Functions table................................................................................................................................................... 5
•
Deleted redundant PLL specification in Recommended Operating Conditions .................................................................... 7
•
Deleted Intelligent clock error... and ...for pop-free performance in the Overview section. ................................................. 14
•
Added note on instruction cycle requirements. .................................................................................................................... 20
•
Added note on instruction cycles in Fixed Audio Processing Flow (Program 5).................................................................. 34
•
Changed Ouptut to Output ................................................................................................................................................... 42
•
Deleted VREF mode provides 2.1Vrms full-scale output at both AVDD levels...................................................................... 42
•
Clarified clock generation explanation in Reset and System Clock Functions..................................................................... 45
•
Clarified external SCK discussion in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)........... 47
•
Deleted The PCM512x disables the internal PLL when an external SCK is supplied. ........................................................ 47
2
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PCM5121, PCM5122
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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
Changes from Original (August 2012) to Revision A
•
Page
Changed the device status From: Preview To: Production ................................................................................................... 1
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: PCM5121 PCM5122
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PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
www.ti.com
5 Device Comparison
Table 1. Differences Between PCM512x Devices
PART NUMBER
DYNAMIC RANGE
SNR
THD
PCM5122A
112 dB
112 dB
–93 dB
PCM5121A
106 dB
106 dB
–92 dB
Table 2. Typical Performance (3.3-V Power Supply)
PARAMETER
PCM5122 / PCM5121
SNR
112 / 106 dB
Dynamic range
112 /106 dB
THD+N at –1 dBFS
–93/ –92 dB
Full-scale single-ended output
2.1 VRMS (GND center)
Normal 8× oversampling digital filter latency
20/fS
Low latency 8× oversampling digital filter latency
3.5/fS
Sampling frequency
8 kHz to 384 kHz
System clock multiples (fSCK): 64, 128, 192, 256, 384,
512, 768, 1024, 1152, 1536, 2048, 3072
4
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Up to 50 MHz
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: PCM5121 PCM5122
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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
6 Pin Configuration and Functions
RHB Package
I2C Mode
(MODE1 tied to DGND and MODE2
tied to DVDD)
Top View
RHB Package
Hardwired Mode
(MODE1 tied to DGND, MODE2 tied
to DGND)
Top View
RHB Package
SPI Mode
(MODE1 tied to DVDD)
Top View
1 CPVDD
DVDD 28
1 CPVDD
DVDD 28
1 CPVDD
DVDD 28
2 CAPP
DGND 27
2 CAPP
DGND 27
2 CAPP
DGND 27
3 CPGND
LDOO 26
3 CPGND
LDOO 26
3 CPGND
LDOO 26
4 CAPM
XSMT 25
4 CAPM
XSMT 25
4 CAPM
XSMT 25
5 VNEG
ADR1 24
5 VNEG
MISO 24
5 VNEG
FMT 24
6 OUTL
LRCK 23
6 OUTL
LRCK 23
6 OUTL
LRCK 23
7 OUTR
DIN 22
7 OUTR
DIN 22
7 OUTR
DIN 22
8 AVDD
BCK 21
8 AVDD
BCK 21
8 AVDD
BCK 21
9 AGND
SCK 20
9 AGND
SCK 20
9 AGND
SCK 20
10 VCOM
GPIO6 19
10 VCOM
GPIO6 19
10 DEMP
11 SDA
MODE2 18
11 MOSI
12 SCL
MODE1 17
12 MC
FLT 19
MS 18
11 ATT2
MODE2 18
MODE1 17
12 ATT1
MODE1 17
13 GPIO5
ADR2 16
13 GPIO5
GPIO2 16
13 ATT0
DOUT 16
14 GPIO4
GPIO3 15
14 GPIO4
GPIO3 15
14 MAST
AGNS 15
Table 3. Gain and Attenuation in Hardwired Mode
ATT PIN CONDITION (ATT2 : ATT1 : ATT0)
GAIN AND ATTENUATION LEVEL
(000)
0 dB
(001)
3 dB
(010)
6 dB
(011)
9 dB
(100)
12 dB
(101)
15 dB
(110)
–6 dB
(111)
–3 dB
I/O
DESCRIPTION
6.1 Pin Functions
PIN
NAME
MODE, NO.
I2C
SPI
HW
CPVDD
1
1
1
-
Charge pump power supply, 3.3 V
CAPP
2
2
2
O
Charge pump flying capacitor terminal for positive rail
CPGND
3
3
3
-
Charge pump ground
CAPM
4
4
4
O
Charge pump flying capacitor terminal for negative rail
VNEG
5
5
5
O
Negative charge pump rail terminal for decoupling, –3.3 V
OUTL
6
6
6
O
Analog output from DAC left channel
OUTR
7
7
7
O
Analog output from DAC right channel
AVDD
8
8
8
-
Analog power supply, 3.3 V
AGND
9
9
9
-
Analog ground
VCOM
10
10
–
O
VCOM output (optional mode selected by register; default setting is VREF
I2C, SPI mode.) When in VREF mode (default), this pin ties to GND. When in VCOM
mode, decoupling capacitor to GND is required.
DEMP
–
–
10
I
HW
DEMP: De-emphasis control for 44.1-kHz sampling rate: Off (Low) / On
(High)
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Pin Functions (continued)
PIN
MODE, NO.
NAME
I/O
I2C
SPI
HW
SDA
11
–
–
MOSI
–
11
–
ATT2
–
–
11
SCL
12
–
–
MC
–
12
–
I/O
I
I
DESCRIPTION
I2C
Data for I2C (1) (2)
SPI
Input data for SPI (2)
HW
Digital gain and attenuation control pin
I2C
Input clock for I2C (2)
SPI
Input clock for SPI (2)
Digital gain and attenuation control pin
ATT1
–
–
12
HW
GPIO5
13
13
–
I2C, SPI General purpose digital input and output port
ATT0
–
–
13
GPIO4
14
14
–
MAST
–
–
14
GPIO3
15
15
–
AGNS
–
–
15
ADR2
16
–
–
GPIO2
–
16
–
DOUT
–
–
16
I/O
HW
Digital gain and attenuation control pin
I2C, SPI General purpose digital input and output port
I/O
I/O
O
MODE1
17
17
17
MODE2
18
–
18
MS
–
18
–
I
GPIO6
19
19
–
I/O
(3)
2
HW
I S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low)
BCK/LRCK inputs
I2C, SPI General purpose digital input and output port
I/O
(3)
(3)
HW
Analog gain selector : 0-dB 2-VRMS output (Low), –6-dB 1-VRMS output
(High)
I2C
2nd LSB address select bit for I2C
SPI
General purpose digital input and output port
HW
General Purpose Output (Low level)
Mode control selection pin (2)
MODE1 = Low, MODE2 = Low : Hardwired mode
MODE1 = Low, MODE2 = High: I2C mode
MODE1 = High: SPI mode
I
I2C,
HW
MODE2
SPI
MS pin (chip select for SPI)
I2C, SPI General purpose digital input and output port
FLT
–
–
19
I
HW
SCK
20
20
20
I
System clock input (2)
BCK
21
21
21
I/O
DIN
22
22
22
I
LRCK
23
23
23
I/O
ADR1
24
–
–
MISO (GPIO1)
–
24
–
FMT
–
–
24
XSMT
25
25
25
I
Soft mute control Soft mute (2) (Low) / soft un-mute (High)
LDOO
26
26
26
-
Internal logic supply rail terminal for decoupling, 1.8 V
DGND
27
27
27
-
Digital ground
DVDD
28
28
28
-
Digital power supply, 3.3 V or 1.8 V
(1)
(2)
(3)
6
I/O
Filter select : Normal latency (Low) / Low latency (High)
Audio data bit clock input (slave) or output (master) (2)
Audio data input (2)
Audio data word clock input (slave) or output (master) (2)
I2C
LSB address select bit for I2C
SPI
Primary output data for SPI readback. Secondary; general purpose digital
input/output port controlled by register
HW
Audio format selection : I2S (Low) / Left justified (High)
Open-drain configuration in out mode.
Failsafe LVCMOS Schmitt trigger input.
Internal Pulldown
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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Digital input voltage
MIN
MAX
AVDD, CPVDD, DVDD
–0.3
3.9
LDO with DVDD at 1.8 V
–0.3
2.25
DVDD at 1.8 V
–0.3
2.25
DVDD at 3.3 V
–0.3
3.9
UNIT
V
V
Analog input voltage
–0.3
3.9
V
Operating junction temperature, TJ
–40
130
°C
Storage temperature, Tstg
–65
150
°C
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
AVDD
Analog power supply voltage
Referenced to AGND (1)
DVDD
Digital power supply voltage
Referenced to DGND (1)
CPVDD
Charge pump supply voltage
Referenced to CPGND (1)
MCLK
Master clock frequency
LOL, LOR
Stereo line output load resistance
CLOUT
Digital output load capacitance
TJ
Operating junction temperature
(1)
VCOM mode
MIN
NOM
MAX
3
3.3
3.46
VREF mode
3.2
3.3
3.46
1.8 V DVDD
1.65
1.8
1.95
3.3 V DVDD
3.1
3.3
3.46
3.1
3.3
3.46
UNIT
V
V
V
50
1
MHz
10
kΩ
10
–40
pF
130
°C
All grounds on board are tied together; they must not differ in voltage by more than 0.2-V maximum, for any combination of ground
signals.
7.4 Thermal Information
PCM512x
THERMAL METRIC
(1)
RHB (TSSOP)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
72.2
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
17.5
°C/W
RθJB
Junction-to-board thermal resistance
35.0
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
34.5
°C/W
(1)
For more information about trdational and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
16
24
32
UNIT
Bits
DIGITAL INPUT/OUTPUT
Logic Family: 3.3-V LVCMOS Compatible
VIH
Input logic level, high
0.7 × DVDD
V
VIL
Input logic level, low
0.3 × DVDD
V
IIH
Input logic current, high
VIN = VDD
10
µA
IIL
Input logic current, low
VIN = 0 V
–10
µA
VOH
Output logic level, high
IOH = –4 mA
VOL
Output logic level, low
IOL = 4 mA
0.8 × DVDD
V
0.22 × DVDD
V
Logic Family 1.8-V LVCMOS Compatible
VIH
Input logic level, high
VIL
Input logic level, low
IIH
Input logic current, high
IIL
0.7 × DVDD
V
0.3 × DVDD
V
VIN = VDD
10
µA
Input logic current, low
VIN = 0 V
–10
µA
VOH
Output logic level, high
IOH = –2 mA
VOL
Output logic level, low
IOL = 2 mA
0.8 × DVDD
V
0.22 × DVDD
V
DYNAMIC PERFORMANCE (PCM MODE) (1) (2)
THD+N at –1 dB (2)
fS = 48 kHz
–93
fS = 96 kHz
–93
fS = 192 kHz
–93
EIAJ, A-weighted, fS = 48 kHz
Dynamic range (2)
Signal-to-noise ratio
(2)
Signal-to-noise ratio with analog
mute (2) (3)
Channel separation
(1)
(2)
(3)
8
108
–83
dB
112
EIAJ, A-weighted, fS = 96 kHz
112
EIAJ, A-weighted, fS = 192 kHz
112
EIAJ, A-weighted, fS = 48 kHz
112
EIAJ, A-weighted, fS = 96 kHz
112
EIAJ, A-weighted, fS = 192 kHz
112
EIAJ, A-weighted, fS = 48 kHz
113
123
EIAJ, A-weighted, fS = 96 kHz
113
123
EIAJ, A-weighted, fS = 192 kHz
113
123
fS = 48 kHz
100 / 95
109 / 103
fS = 96 kHz
100 / 95
109 / 103
fS = 192 kHz
100 / 95
109 / 103
dB
dB
dB
dB
Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise
ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance
specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see Recommended Output Filter for the PCM512x).
Assert XSMT or both L-ch and R-ch PCM data are BPZ
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Electrical Characteristics (continued)
TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Gain error
–6
±2.0
6
% of FSR
Gain mismatch, channel-to-channel
–6
±0.5
6
% of FSR
ANALOG OUTPUT
Single-ended output voltage
2.1
Load impedance
VRMS
5
kΩ
FILTER CHARACTERISTICS–1: NORMAL (8x)
Pass band
0.45 × fS
Stop band
kHz
0.55 × fS
Stop band attenuation
kHz
–60
dB
Pass-band ripple
±0.02
Delay time
dB
20 × tS
s
FILTER CHARACTERISTICS–2: LOW LATENCY (8x)
Pass band
0.47 × fS
Stop band
kHz
0.55 × fS
Stop band attenuation
kHz
–52
dB
Pass-band ripple
±0.0001
Delay time
dB
3.5 × tS
s
FILTER CHARACTERISTICS–3: ASYMMETRIC FIR (8x)
Pass band
0.4 × fS
Stop band
kHz
0.72 × fS
Stop band attenuation
kHz
–52
dB
Pass-band ripple
±0.05
Delay time
dB
1.2 × tS
s
FILTER CHARACTERISTICS–4: HIGH-ATTENUATION (8x)
Pass band
0.45 × fS
Stop band
kHz
0.45 × fS
Stop band attenuation
kHz
–100
Pass-band ripple
dB
±0.0005
Delay time
dB
33.7 × tS
s
POWER SUPPLY REQUIREMENTS
DVDD
Digital supply voltage
Target DVDD = 1.8 V
1.65
1.8
1.95
VDC
DVDD
Digital supply voltage
Target DVDD = 3.3 V
3
3.3
3.6
VDC
AVDD
Analog supply voltage
3
3.3
3.6
VDC
CPVDD
Charge-pump supply voltage
3
3.3
3.6
VDC
IDD
IDD
IDD
(4)
DVDD supply current at 1.8 V
DVDD supply current at 1.8 V
DVDD supply current at 1.8 V
(4)
fS = 48 kHz, input is bipolar zero
data
11
fS = 96 kHz, input is bipolar zero
data
12
fS = 192 kHz, input is bipolar
zero data
14
fS = 48 kHz, input is 1 kHz – 1
dBFS data
11
fS = 96 kHz, input is 1 kHz – 1
dBFS data
12
fS = 192 kHz, input is 1 kHz – 1
dBFS data
14
fS = N/A, power-down mode
0.3
14
mA
14
mA
0.6
mA
Power-down mode, with LRCK, BCK, and SCK halted at low level.
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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
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Electrical Characteristics (continued)
TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data (unless otherwise noted).
PARAMETER
IDD
IDD
IDD
ICC
ICC
ICC
TEST CONDITIONS
DVDD supply current at 3.3 V
DVDD supply current at 3.3 V
DVDD supply current at 3.3 V (4)
AVDD + CPVDD supply current
AVDD + CPVDD supply current
AVDD + CPVDD supply current (4)
Power dissipation, DVDD = 1.8 V
Power dissipation, DVDD = 1.8 V
Power dissipation, DVDD = 1.8 V
(4)
Power dissipation, DVDD = 3.3 V
Power dissipation, DVDD = 3.3 V
Power dissipation, DVDD = 3.3 V (4)
10
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MIN
TYP
fS = 48 kHz, input is bipolar zero
data
12
fS = 96 kHz, input is bipolar zero
data
13
fS = 192 kHz, input is bipolar
zero data
15
fS = 48 kHz, input is 1 kHz – 1
dBFS data
12
fS = 96 kHz, input is 1 kHz – 1
dBFS data
13
fS = 192 kHz, input is 1 kHz – 1
dBFS data
15
fS = N/A, power-down mode
0.5
fS = 48 kHz, input is bipolar zero
data
11
fS = 96 kHz, input is bipolar zero
data
11
fS = 192 kHz, input is bipolar
zero data
11
fS = 48 kHz, input is 1 kHz – 1
dBFS data
24
fS = 96 kHz, input is 1 kHz – 1
dBFS data
24
fS = 192 kHz, input is 1 kHz – 1
dBFS data
24
fS = N/A, power-down mode
0.2
fS = 48 kHz, input is bipolar zero
data
59.4
fS = 96 kHz, input is bipolar zero
data
61.2
fS = 192 kHz, input is bipolar
zero data
64.8
fS = 48 kHz, input is 1 kHz – 1
dBFS data
99
fS = 96 kHz, input is 1 kHz – 1
dBFS data
100.8
fS = 192 kHz, input is 1 kHz – 1
dBFS data
104.4
fS = N/A, power-down mode
MAX
15
mA
15
mA
0.8
79.2
fS = 96 kHz, input is bipolar zero
data
82.5
fS = 192 kHz, input is bipolar
zero data
89.1
fS = 48 kHz, input is 1 kHz – 1
dBFS data
118.8
fS = 96 kHz, input is 1 kHz – 1
dBFS data
122.1
fS = 192 kHz, input is 1 kHz – 1
dBFS data
128.7
fS = N/A, power-down mode
2.3
mA
16
mA
32
mA
0.4
mA
78
mW
130.8
mW
1.2
fS = 48 kHz, input is bipolar zero
data
UNIT
mW
103
mW
155
mW
4
mW
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SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
7.6 Timing Requirements: SCK Input
Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low
phase jitter and noise.
MIN
tSCY
System clock pulse cycle time
tSCKH
System clock pulse width, high
tSCKL
System clock pulse width, low
NOM
20
DVDD = 1.8 V
8
DVDD = 3.3 V
9
DVDD = 1.8 V
8
DVDD = 3.3 V
9
MAX
UNIT
1000
ns
ns
ns
7.7 Timing Requirements: XSMT
MIN
NOM
MAX
UNIT
tr
Rise time
20
ns
tf
Fall time
20
ns
MAX
UNIT
7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
DATA FORMAT (PCM MODE)
Audio data interface format
I2S, left-justified, right-justified, and
TDM
Audio data bit length
16, 20, 24, 32-bit acceptable
Audio data format
MSB first, twos-complement
Sampling frequency (1)
fS
8
384
kHz
CLOCKS
64, 128, 192, 256, 384, 512, 768,
1024, 1152, 1536, 2048, or 3072
fSCK, up to 50 Mhz
System clock frequency
PLL input frequency
(1)
(2)
Clock divider uses fractional divide
D > 0, P=1
(2)
Clock divider uses integer divide
D = 0, P=1
6.7
20
MHz
1
20
MHz
One sample time is defined as the reciprocal of the sampling frequency. 1 × tS = 1 / fS
With the appropriate P coefficient setting, the PLL accepts up to 50 MHz. This clock is then divided to meet the ≤ 20-MHz requirement.
See PLL Calculation.
tSCKH
"H"
0.7*DVDD
System Clock
(SCK)
0.3*DVDD
"L"
tS CK L
tSCY
Figure 1. Timing Requirements for SCK Input
0.9 * DVDD
XSMT
0.1 * DVDD
tr