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PCM5242
SLASE12A – JULY 2014 – REVISED OCTOBER 2014
PCM5242 4.2-VRMS DirectPath™, 114-dB Audio Stereo Differential-Output DAC with 32-bit,
384-kHz PCM Interface
1 Features
3 Description
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•
•
•
•
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The PCM5242 is a monolithic CMOS integrated
circuit that includes a stereo digital-to-analog
converter and additional support circuitry in a small
QFN package. The PCM5242 uses the latest
generation
of
TI’s
advanced
segment-DAC
architecture
to
achieve
excellent
dynamic
performance and improved tolerance to clock jitter.
1
•
•
•
•
•
•
•
•
•
•
Differential DirectPath™ Ground Biased Outputs
Market-Leading Low Out-of-Band Noise
Selectable Digital-Filter Latency and Performance
No DC Blocking Capacitors Required
Integrated Negative Charge Pump
Intelligent Muting System; Soft Up or Down Ramp
and Analog Mute for 120dB Mute SNR
Integrated High-Performance Audio PLL With
BCK Reference to Generate SCK Internally
Accepts 16-, 24-, and 32-Bit Audio Data
PCM Data Formats: I2S, Left-Justified, RightJustified, TDM
SPI or I2C Control
Software or Hardware Configuration
Automatic Power-Save Mode When LRCK And
BCK Are Deactivated
1.8V or 3.3V Failsafe LVCMOS Digital Inputs
Single Supply Operation:
– 3.3V Analog, 1.8V or 3.3V Digital
Integrated Power-On Reset
Small 32-terminal QFN Package
The PCM5242 integrates a fully programmable
miniDSP core, allowing developers to integrate filters,
dynamic range controls, custom interpolators and
other differentiating features to their products.
The PCM5242 provides 4.2VRMS ground-centered
differential outputs, allowing designers to eliminate
DC blocking capacitors on the output, as well as
external muting circuits traditionally associated with
single supply line drivers.
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock), allowing a 3-wire I2S connection and
reducing system EMI.
Device Information(1)
PART NAME
PCM5242
VQFN (32)
BODY SIZE (NOM)
5.00mm × 5.00mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
PACKAGE
HiFi Smartphone
A/V Receivers
DVD, BD Players
HDTV Receivers
4 Simplified System Diagram
2
I S
2ch Single Ended
PCM1863/5
DOUT
BCK
LRCK
IN
AUX
2ch Single Ended
Current Segment DAC
TPA3130
miniDSPs,
Filters
PCM5242
IN
MIC
TPA6120A2
Analog
Sensor
- Light Intensity
- Ultrasonic
- Battery Level
BT Module
MSP430
WiLAN chip
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM5242
SLASE12A – JULY 2014 – REVISED OCTOBER 2014
www.ti.com
32-bit ∆Σ Modulator
Interpolation Filter
Programmable
miniDSP
Zero Data
Detector
Differential
Line Outputs
Current
Segment
DAC
I/V
DOUT (I2S)
(through
any GPIO)
Digital
Volume
Control
Current
Segment
DAC
I/V
DIN (I2S)
Audio Interface
Simplified Block Diagram
Advanced Mute Control
2
SPI/I C
Clock Halt
Detection
PCM5242
Program
RAM
GPIO
GPIO6/FLT
GPIO5/ATT0
GPIO4/MAST
GPIO3/AGNS
GPIO2/ADR2/DOUT
Power
Supply
CPVDD (3.3V)
AVDD (3.3V)
DVDD (1.8V or 3.3V)
GND
LRCK
BCK
MCK
PLL
Clock
UVP/
Reset
POR
UVP/XSMT
VCom
Charge
Pump
MOSI/SDA/ATT2
MS/MODE2
MODE1
MC/SCL/ATT1
MISO/ADR1/FMT
CAPP
CAPM
VNEG
Typical Performance (3.3V Power Supply)
Parameter
PCM5242
SNR
114dB
Dynamic Range
114dB
THD+N at - 1dBFS
–94dB
Full Scale Differential Output
4.2VRMS (GND center)
Normal 8× Oversampling Digital Filter Latency: 20tS
Low Latency 8× Oversampling Digital Filter Latency: 3.5tS
Sampling Frequency
8kHz to 384kHz
System Clock Multiples (fSCK): 64, 128, 192, 256, 384, 512, 768, 1024,
1152, 1536, 2048, 3072; up to 50 MHz
2
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SLASE12A – JULY 2014 – REVISED OCTOBER 2014
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified System Diagram ..................................
Revision History.....................................................
Pin Configuration and Functions .........................
1
1
1
1
3
4
6.1 Control Mode Effect On Pin Assignments ................ 4
6.2 Pin Assignments ....................................................... 4
7
Specifications......................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
Absolute Maximum Ratings ...................................... 7
Handling Ratings....................................................... 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Switching Characteristics ........................................ 11
Timing Requirements: SCK Input ........................... 11
Timing Requirements: PCM Audio Data ................. 12
Timing Requirements: XSMT .................................. 13
Typical Characteristics .......................................... 14
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
8.5
Overview .................................................................
Functional Block Diagram .......................................
Terminology ............................................................
Audio Data Interface ...............................................
XSMT Pin (Soft Mute / Soft Un-Mute) ...................
16
16
16
17
21
8.6
8.7
8.8
8.9
9
Audio Processing ....................................................
DAC and Differential Analog Outputs .....................
Reset and System Clock Functions ........................
Device Functional Modes........................................
22
44
47
54
Applications and Implementation ...................... 60
9.1 Application Information............................................ 60
9.2 Typical Application .................................................. 60
10 Power Supply Recommendations ..................... 62
10.1 Power Supply Distribution and Requirements ...... 62
10.2 Recommended Powerdown Sequence................. 63
10.3 External Power Sense Undervoltage Protection
mode (supported only when DVDD = 3.3V) ........... 65
10.4 Power-On Reset Function..................................... 66
10.5 PCM5242 Power Modes ....................................... 68
11 Layout................................................................... 71
11.1 Layout Guidelines ................................................. 71
12 Programming and Registers Reference............ 72
12.1 Coefficient Data Formats ...................................... 72
12.2 Power Down and Reset Behavior ......................... 72
12.3 PCM5242 Register Map........................................ 73
13 Device and Documentation Support ............... 120
13.1 Community Resources........................................ 120
13.2 Trademarks ......................................................... 120
13.3 Electrostatic Discharge Caution .......................... 120
14 Mechanical, Packaging, and Orderable
Information ......................................................... 120
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Initial (July 2014) to Revision A
Page
•
Changed From: A 4-page Product Preview To: A Production datasheet .............................................................................. 1
•
Changed Description text in the first paragraph From: "The PCM5242 devices are a family.." To: "The PCN5242 is a
monolithic.." ............................................................................................................................................................................ 1
•
Changed Description text in third paragraoh From: "The PCM5242 provides 2.1VRMS.." To: "The PCM5242 provides
4.2VRMS.. ................................................................................................................................................................................. 1
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PCM5242
SLASE12A – JULY 2014 – REVISED OCTOBER 2014
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6 Pin Configuration and Functions
6.1 Control Mode Effect On Pin Assignments
The PCM5242 supports control from I2C, SPI and Hardware Modes (referred to as HW mode). Selection of
modes is done using Mode1 and Mode2 pins. (See Table 1)
SPI Mode is selected by pulling MODE1 to DVDD.
I2C Mode is selected by pulling MODE1 to DGND and Mode2 to DVDD.
Hardware Control Mode is selected by pulling both MODE1 and MODE2 pins to DGND.
6.2 Pin Assignments
LDOO
2
23
MODE1
LDOO
2
DGND
3
22
ADR2
DGND
3
32
31
30
29
SCK
25
24
FLT
1
DIN
XSMT
BCK
MODE2
NC
25
24
NC
26
1
FMT
27
XSMT
LRCK
SCK
28
GPIO6
29
DIN
30
BCK
31
NC
32
NC
26
MISO
27
LRCK
SCK
28
GPIO6
29
DIN
30
BCK
31
NC
32
NC
ADR1
LRCK
32-Pin RHB (QFN, Top View)
28
27
26
25
24
MODE1
LDOO
2
23
MODE1
22
GPIO2
DGND
3
22
GPO
4
21
AGNS
DVDD
4
21
GPIO3
DVDD
4
21
GPIO3
DVDD
CPVDD
5
20
GPIO4
CPVDD
5
20
GPIO4
CPVDD
5
20
MAST
CAPP
6
19
GPIO5
CAPP
6
19
GPIO5
CAPP
6
19
ATT0
CPGND
7
18
SCL
CPGND
7
18
MC
CPGND
7
18
ATT1
CAPM
8
SDA
CAPM
8
8
ATT2
15
17
16
CAPM
15
17
16
AGND
MODE2
23
VCOM
1
AGND
XSMT
VCOM
MS
Figure 2. SPI Control
11
12 13
14
15
17
16
OUTRP
AVDD
AGND
DEMP
14
10
OUTLN
AVDD
12 13
9
OUTRN
OUTRP
11
MOSI
GND
VNEG
OUTLN
OUTRN
10
AVDD
VNEG
Figure 1. I2C Control
9
OUTRP
14
OUTLN
12 13
OUTRN
11
VNEG
10
OUTLP
9
OUTLP
GND
OUTLP
GND
Figure 3. Hardware Control
Table 1. PCM5242 Pin Functions
PIN
MODE, NAME
I2C
(1)
4
SPI
HW
PIN
I/O
DESCRIPTION
XSMT
1
I
Soft mute control (1) Soft mute (Low) / soft un-mute (High)
LDOO
2
-
Internal logic supply rail pin for decoupling, 1.8V
DGND
3
-
Digital ground
DVDD
4
-
Digital power supply, 3.3V or 1.8V
CPVDD
5
-
Charge pump power supply, 3.3V
CAPP
6
O
Charge pump flying capacitor pin for positive rail
CPGND
7
-
Charge pump ground
CAPM
8
O
Charge pump flying capacitor pin for negative rail
VNEG
9
O
Negative charge pump rail pin for decoupling, -3.3V
OUTLP
10
Positive Differential Analog output from DAC left channel
OUTLN
11
Negative Differential Analog output from DAC left channel
OUTRN
12
Negative Differential Analog output from DAC right channel
OUTRP
13
Positive Differential Analog output from DAC right channel.
AVDD
14
-
Analog power supply, 3.3V
AGND
15
-
Analog ground
Failsafe LVCMOS Schmitt trigger input.
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Pin Assignments (continued)
Table 1. PCM5242 Pin Functions (continued)
PIN
MODE, NAME
2
I C
SPI
HW
VCOM
PIN
16
I/O
DESCRIPTION
O
VCOM output (Optional mode selected by register; default setting is VREF
I2C, SPI mode.) When in VREF mode (default), this pin ties to GND. When in VCOM
mode, decoupling capacitor to GND is required.
I
HW
DEMP: De-emphasis control for 44.1kHz sampling rate: Off (Low) / On (High)
I/O
I2C
Data for I2C (2) (1)
SPI
Input data for SPI (1)
HW
Digital gain and attenuation control pin
I2C
Input clock for I2C (1)
SPI
Input clock for SPI (1)
HW
Digital gain and attenuation control pin
DEMP
SDA
MOSI
17
I
ATT2
SCL
MC
18
I
ATT1
2
GPIO5
ATT0
19
I/O
I C, SPI General purpose digital input and output port
HW
Digital gain and attenuation control pin
I2C, SPI General purpose digital input and output port
GPIO4
MAST
GPIO3
AGNS
20
I/O
21
I/O
GPIO2
22
GPO
I/O
O
(3)
2
HW
I S Master clock select pin : Master (High) BCK/LRCK outputs, Slave (Low)
BCK/LRCK inputs
I2C, SPI General purpose digital input and output port
HW
2
ADR2
(3)
(3)
Analog gain selector : 0dB 2VRMS output (Low), -6dB 1VRMS output (High)
I C
2nd LSB address select bit for I2C (3)
SPI
General purpose digital input and output port
HW
General Purpose Output (Low level)
(3)
Mode control selection pin (1)
MODE1
23
MODE1 = Low, MODE2 = Low : Hardwired mode
I
MODE1 = Low, MODE2 = High: I2C mode
MODE1 = High: SPI mode
MODE2
MODE2
MS
GPIO6
FLT
I2C, HW MODE2 (See definition in Mode 1 description)
24
25
I
I/O
MS pin (chip select for SPI)
I2C, SPI General purpose digital input and output port
I
HW
SCK
26
I
System clock input (1)
BCK
27
I/O
DIN
28
I
29
-
30
-
31
I/O
NC
LRCK
ADR1
MISO
(GPIO1)
32
I/O
FMT
(2)
(3)
SPI
Filter select : Normal latency (Low) / Low latency (High)
Audio data bit clock input (slave) or output (master) (1)
Audio data input (1)
No connect
Audio data word clock input (slave) or output (master) (1)
I2C
LSB address select bit for I2C
SPI
Primary output data for SPI readback. Secondary; general purpose digital
input/output port controlled by register
HW
Audio format selection : I2S (Low) / Left justified (High)
Open-drain configuration in out mode.
Internal Pulldown
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SLASE12A – JULY 2014 – REVISED OCTOBER 2014
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Table 2. Gain and Attenuation in Hardwired Mode
6
ATT PIN CONDITION
(ATT2 : ATT1 : ATT0)
GAIN AND ATTENUATION LEVEL
(000)
0 dB
(001)
+ 3 dB
(010)
+ 6 dB
(011)
+ 9 dB
(100)
+ 12 dB
(101)
+ 15 dB
(110)
- 6 dB
(111)
- 3 dB
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SLASE12A – JULY 2014 – REVISED OCTOBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply Voltage
Digital Input Voltage
MIN
MAX
AVDD, CPVDD, DVDD
–0.3
3.9
LDOO wtih DVDD at 1.8V
–0.3
2.25
DVDD at 1.8V
–0.3
2.25
DVDD at 3.3V
–0.3
3.9
–0.3
3.9
Analog Input Voltage
UNIT
V
7.2 Handling Ratings
Tstg
Storage Temperature
V(ESD)
(1)
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
Electrostatic
Discharge
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins
MIN
MAX
UNIT
–40
125
°C
–2500
2500
–1500
1500
V
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
AVDD
Analog power supply voltage range
Referenced to
AGND (1)
VCOM mode
3.0
3.3
3.46
VREF mode
3.2
3.3
3.46
DVDD
Digital power supply voltage range
Referenced to
DGND (1)
1.8V DVDD
1.65
1.8
1.95
3.3V DVDD
3.1
3.3
3.46
CPVDD
Charge pump supply voltage range
Referenced to CPGND (1)
3.1
3.3
3.46
MCLK
Master Clock Frequency
LOL, LOR
Stereo line output load resistance
CLout
Digital output load capacitance
TJ
Operating Junction Temperature Range
(1)
UNIT
V
V
V
50
2
MHz
10
kΩ
10
–25
pF
85
°C
All grounds on board are tied together; they must not differ in voltage by more than 0.2V max, for any combination of ground signals.
7.4 Thermal Information
THERMAL METRIC
RHB (32 PINS)
RθJA
Junction-to-ambient thermal resistance
72.2
RθJC(top)
Junction-to-case(top) thermal resistance
17.5
RθJB
Junction-to-board thermal resistance
35.0
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
34.5
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
n/a
UNIT
°C/W
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PCM5242
SLASE12A – JULY 2014 – REVISED OCTOBER 2014
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7.5 Electrical Characteristics
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
16
24
32
UNIT
Bits
Digital Input/Output
Logic Family: 3.3V LVCMOS compatible
VIH
VIL
IIH
IIL
VOH
VOL
0.7×DVDD
Input logic level
0.3×DVDD
Input logic current
Output logic level
VIN = VDD
10
VIN = 0V
–10
IOH = –4mA
0.8×DVDD
IOL = 4mA
0.22×DVDD
V
µA
V
Logic Family 1.8V LVCMOS compatible
VIH
VIL
IIH
IIL
VOH
VOL
0.7×DVDD
Input logic level
0.3×DVDD
Input logic current
Output logic level
VIN = VDD
10
VIN = 0V
–10
IOH = –2mA
0.8×DVDD
IOL = 2mA
0.22×DVDD
V
µA
V
Dynamic Performance (PCM Mode) (1) (2)
THD+N at -1 dB
(2)
fS = 48kHz
–94
fS = 96kHz
–94
fS = 192kHz
Dynamic range (2)
Signal-to-noise ratio (2)
EIAJ, A-weighted, fS = 48kHz
–94
108
114
EIAJ, A-weighted, fS = 192kHz
114
EIAJ, A-weighted, fS = 48kHz
114
EIAJ, A-weighted, fS = 96kHz
114
(1)
(2)
(3)
8
dB
114
EIAJ, A-weighted, fS = 48kHz
113
123
EIAJ, A-weighted, fS = 96kHz
113
123
EIAJ, A-weighted, fS = 192kHz
Channel Separation
114
EIAJ, A-weighted, fS = 96kHz
EIAJ, A-weighted, fS = 192kHz
Signal to noise ratio with analog
mute (2) (3)
–87
113
123
fS = 48kHz
100 / 95
109 / 103
fS = 96kHz
100 / 95
109 / 103
fS = 192kHz
100 / 95
109 / 103
dB
Filter condition: THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range: 20Hz HPF, 20kHz AES17 LPF, A-weighted Signal-to-noise
ratio: 20Hz HPF, 20kHz AES17 LPF, A-weighted Channel separation: 20Hz HPF, 20kHz AES17 LPF Analog performance specifications
are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode.
Output load is 10kΩ, with 470Ω output resistor and a 2.2nF shunt capacitor (see recommended output filter).
Assert XSMT or both L-ch and R-ch PCM data are BPZ
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Electrical Characteristics (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Output
Single Ended Output voltage
2.1
Differential Output Voltage
4.2
VRMS
VRMS
Gain error
–6
±2.0
6
Gain mismatch, channel-tochannel
–6
±0.5
6
–2
±1.0
2
Bipolar zero error
At bipolar zero
Load impedance
% of FSR
% of FSR
5
mV
kΩ
Filter Characteristics–1: Normal (8x)
Pass band
0.45fS
Stop band
0.55fS
Stop band attenuation
–60
Pass-band ripple
±0.02
Delay time
20tS
kHz
dB
s
Filter Characteristics–2: Low Latency (8x)
Pass band
0.47fS
Stop band
0.55fS
Stop band attenuation
–52
Pass-band ripple
±0.0001
Delay time
3.5tS
kHz
dB
s
Filter Characteristics–3: Asymmetric FIR (8x)
Pass band
0.40fS
Stop band
0.72fS
Stop band attenuation
–52
Pass-band ripple
±0.05
Delay time
1.2tS
kHz
dB
s
Filter Characteristics–4: High-Attenuation (8x)
Pass band
0.45fS
Stop band
0.45fS
Stop band attenuation
–100
Pass-band ripple
±0.0005
Delay time
33.7tS
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dB
s
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Electrical Characteristics (continued)
All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Requirements
DVDD
Digital supply voltage
Target DVDD = 1.8V
1.65
1.8
1.95
VDC
DVDD
Digital supply voltage
Target DVDD = 3.3V
3.0
3.3
3.6
VDC
AVDD
Analog supply voltage
3.0
3.3
3.6
VDC
CPVDD
Charge-pump supply voltage
3.0
VDC
IDD
IDD
IDD
IDD
IDD
IDD
ICC
DVDD supply current at 1.8V
DVDD supply current at 1.8V
DVDD supply current at 1.8V (4)
DVDD supply current at 3.3V
DVDD supply current at 3.3V
DVDD supply current at 3.3V (4)
AVDD + CPVDD Supply Current
ICC
AVDD + CPVDD Supply Current
ICC
AVDD + CPVDD Supply Current (4)
Power Dissipation, DVDD = 1.8V
Power Dissipation, DVDD = 1.8V
3.3
3.6
fS = 48kHz, Input is Bipolar Zero data
11
14
fS = 96kHz, Input is Bipolar Zero data
12
fS = 192kHz, Input is Bipolar Zero data
14
fS = 48kHz, Input is 1kHz -1dBFS data
11
fS = 96kHz, Input is 1kHz -1dBFS data
12
fS = 192kHz, Input is 1kHz -1dBFS data
14
fS = N/A, Power Down Mode
0.3
0.6
fS = 48kHz, Input is Bipolar Zero data
12
15
fS = 96kHz, Input is Bipolar Zero data
13
fS = 192kHz, Input is Bipolar Zero data
15
fS = 48kHz, Input is 1kHz -1dBFS data
12
fS = 96kHz, Input is 1kHz -1dBFS data
13
fS = 192kHz, Input is 1kHz -1dBFS data
15
fS = N/A, Power Down Mode
0.5
0.8
fS = 48kHz, Input is Bipolar Zero data
11
16
fS = 96kHz, Input is Bipolar Zero data
11
fS = 192kHz, Input is Bipolar Zero data
11
fS = 48kHz, Input is 1kHz -1dBFS data
24
fS = 96kHz, Input is 1kHz -1dBFS data
24
Power Dissipation, DVDD = 3.3V
10
mA
15
mA
32
mA
24
0.4
fS = 48kHz, Input is Bipolar Zero data
59.4
78
fS = 96kHz, Input is Bipolar Zero data
61.2
fS = 192kHz, Input is Bipolar Zero data
64.8
99
fS = 96kHz, Input is 1kHz -1dBFS data
100.8
fS = 192kHz, Input is 1kHz -1dBFS data
104.4
79.2
fS = 96kHz, Input is Bipolar Zero data
82.5
fS = 192kHz, Input is Bipolar Zero data
89.1
fS = 48kHz, Input is 1kHz -1dBFS data
118.8
fS = 96kHz, Input is 1kHz -1dBFS data
122.1
fS = 192kHz, Input is 1kHz -1dBFS data
128.7
2.3
mA
mW
130.8
mW
1.2
fS = 48kHz, Input is Bipolar Zero data
mA
mA
0.2
fS = 48kHz, Input is 1kHz -1dBFS data
mA
mA
fS = N/A, Power Down Mode
Power Dissipation, DVDD = 3.3V (4) fS = N/A, Power Down Mode
(4)
14
fS = 192kHz, Input is 1kHz -1dBFS data
Power Dissipation, DVDD = 1.8V (4) fS = N/A, Power Down Mode
Power Dissipation, DVDD = 3.3V
mA
mW
103
mW
155
mW
4.0
mW
Power Down Mode, with LRCK, BCK, and SCK halted at Low level.
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Product Folder Links: PCM5242
PCM5242
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SLASE12A – JULY 2014 – REVISED OCTOBER 2014
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Data Format (PCM Mode)
fS
(1)
Audio data interface format
I2S, left justified, right justified and TDM
Audio data bit length
16, 20, 24, 32-bit acceptable
Audio data format
MSB First, 2s Complement
Sampling frequency
8
384
kHz
Clocks
System clock frequency
PLL Input Frequency
(1)
(2)
64, 128, 192, 256, 384, 512, 768, 1024, 1152,
1536, 2048, or 3072
fSCK, up to 50Mhz
Clock divider uses fractional divide
D > 0, P=1
(2)
Clock divider uses integer divide
D = 0, P=1
6.7
20
MHz
1
20
MHz
One sample time si defined as the reciprocal of the sampling frequency. 1tS = 1/fS
With the appropriate P coefficient setting, the PLL accepts up to 50MHz. This clock is then divided to meet the ≤ 20MHz requirement.
See PLL Calculation.
7.7 Timing Requirements: SCK Input
Figure 4 shows the timing requirements for the system clock input. For optimal performance, use a clock source
with low phase jitter and noise.
MIN
tSCY
System clock pulse cycle time
tSCKH
System clock pulse width, High
tSCKL
System clock pulse width, Low
20
DVDD = 1.8V
8
DVDD = 3.3V
9
DVDD = 1.8V
8
DVDD = 3.3V
9
TYP
MAX
UNIT
1000
ns
ns
ns
tSCKH
"H"
0.7*DVDD
System Clock
(SCK)
0.3*DVDD
"L"
tS CK L
tSCY
Figure 4. Timing Requirements for SCK Input
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PCM5242
SLASE12A – JULY 2014 – REVISED OCTOBER 2014
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7.8 Timing Requirements: PCM Audio Data
MIN
TYP
MAX
UNIT
tBCY
BCK Pulse Cycle Time
40
ns
tBCL
BCK Pulse Width LOW
16
ns
tBCH
BCK Pulse Width HIGH
16
ns
tBL
BCK Rising Edge to LRCK Edge
tBCK
BCK frequency at DVDD = 3.3V
24.576
MHz
tBCK(1.8V)
BCK frequency at DVDD = 1.8V
12.288
MHz
tLB
LRCK Edge to BCK Rising Edge
8
ns
tDS
DATA Set Up Time
8
ns
tDH
DATA Hold Time
8
ns
tDOD
DATA delay time from BCK falling edge
8
ns
15
LRCK
ns
0. 5 * DVDD
(Input)
tBCH
t LB
t BCL
BCK
0. 5 * DVDD
(Input)
tBCY
tBL
DATA
0. 5 * DVDD
(Input)
tDS
t DH
t DOD
DATA
0. 5 * DVDD
( Output)
Figure 5. PCM5242 Serial Audio Timing - Slave
In software mode, the PCM5242 can act as an I2S master, generating BCK and LRCK as outputs from the SCK
input.
Table 3. I2S Master Mode Registers
Register
Function
Page0, Register 9, D(0), D(4), and D(5)
I2S Master mode select
Register 32, D(6:0)
Register 33, D(7:0)
12
BCK divider and LRCK divider
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Product Folder Links: PCM5242
PCM5242
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SLASE12A – JULY 2014 – REVISED OCTOBER 2014
The I2S master timing is shown in Figure 6.
MIN
TYP
MAX
UNIT
tBCY
BCK Pulse Cycle Time
40
ns
tBCL
BCK Pulse Width LOW
16
ns
tBCH
BCK Pulse Width HIGH
16
tBCK
BCK frequency at DVDD = 3.3V
tBCK(1.8V)
BCK frequency at DVDD = 1.8V
tLRD
LRCKx delay time from BCKx falling edge
tDS
DATA Set Up Time
8
tDH
DATA Hold Time
8
tDOD
DATA delay time from BCK falling edge at DVDD = 3.3V
15
ns
tDOD(1.8V)
DATA delay time from BCK falling edge at DVDD = 1.8V
20
ns
t BCH
ns
–10
24.576
MHz
12.288
MHz
20
ns
ns
ns
t BCL
0. 5 * DVDD
BCK
( Output)
t LRD
tBCY
LRCK
0. 5 * DVDD
( Output)
t DOD
DATA
0. 5 * DVDD
( Output)
tDS
tDH
DATA
0. 5 * DVDD
( Input)
Figure 6. PCM5242 Serial Audio Timing - Master
7.9 Timing Requirements: XSMT
MIN
TYP
MAX
UNIT
tr
Rise time
20
ns
tf
Fall time
20
ns
0.9 * DVDD
XSMT
0.1 * DVDD
tr
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