PCM55

® PCM54 PCM55 DESIGNED FOR AUDIO 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTERS FEATURES q q q q PARALLEL INPUT FORMAT 16-BIT RESOLUTION 15-BIT MONOTONICITY (typ) –92dB TOTAL HARMONIC DISTORTION (K Grade) q 3µs SETTLING TIME (Voltage Out) q 96dB DYNAMIC RANGE q ±3V or ±1mA AUDIO OUTPUT q OPERATES ON ±5V (PCM55) TO ±12V (PCM54) SUPPLIES q 28-PIN DIP (PCM54) q 24-LEAD SOIC (PCM55) DESCRIPTION The PCM54 and PCM55 family of converters are parallel input, fully monotonic, 16-bit digital-to-analog converters that are designed and specified for digital audio applications. These devices employ ultra-stable nichrome (NiCr) thin-film resistors to provide monotonicity, low distortion, and low differential linearity error (especially around bipolar zero) over long periods of time and over the full operating temperature. These converters are completely self-contained with a stable, low noise, internal, zener voltage reference; high speed current switches; a resistor ladder network; and a fast settling, low noise output operational amplifier all on a single monolithic chip. The converters are operated using two power supplies that Reference Voltage RF can range from ±5V (PCM55) to ±12V (PCM54). Power dissipation with ±5V supplies is typically less than 200mW. Also included is a provision for external adjustment of the MSB error (differential linearity error at bipolar zero, PCM54 only) to further improve Total Harmonic Distortion (THD) specifications if desired. A current output (IOUT) wiring option is provided. This output typically settles to within ±0.006% of FSR final value in 350ns (in response to a full-scale change in the digital input code). The PCM54 is packaged in 28-pin plastic DIP package. The PCM55 is available in a 24-lead plastic miniflatpak. Parallel Digital Input 16-Bit Ladder Resistor Network and Current Switches Output Operational Amplifier Audio Output (Voltage) International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1985 Burr-Brown Corporation PDS-619B Printed in U.S.A. August, 1998 SPECIFICATIONS ELECTRICAL At +25°C and ±VCC = 12V, unless otherwise noted. PCM54HP, PCM55HP PARAMETER DIGITAL INPUTS Resolution Dynamic Range Logic Levels (TTL/CMOS Compatible): VIH VIL IIH, VIN = +2.7V IIL, VIN = +0.4V TRANSFER CHARACTERISTICS ACCURACY Gain Error Bipolar Zero Error Differential Linearity Error at Biploar Zero(1) Noise (rms) (20Hz to 20kHz) at Bipolar Zero TOTAL HARMONIC DISTORTION(3) (16-Bit Resolution) VO = ±FS at f = 991Hz VO = –20dB at f = 991Hz VO = –60dB at f = 991Hz MONOTONICITY SETTLING TIME (to ±0.006% of FSR) Voltage Output: 6V Step 1LSB Step Current Output (1mA Step): 10Ω to 100Ω Load 1kΩ Load(4) Deglitcher Delay (THD Test)(5) Slew Rate WARM-UP TIME ANALOG OUTPUT Voltage Output: Bipolar Range Output Current Output Impedance Short-Circuit Duration Current Output:(6) Bipolar Range (±30%) Bipolar Output Impedance (±30%) POWER SUPPLY REQUIREMENTS Voltage: +VCC (PCM54) –VCC (PCM54) +VCC (PCM55) –VCC (PCM55) Supply Drain: +VCC –VCC TEMPERATURE RANGE Operating Storage 1 ±3 V V V V V +15.75 –15.75 +7.5 –7.5 +20 –25 +70 +100 V V V V V V V V V V V V V V V V V V V V V V MIN TYP 16 96 +2.4 0 +5.25 +0.8 +40 –0.5 V V MAX PCM54JP, PCM55JP MIN TYP V V V V V V V V MAX MIN PCM54KP TYP V V V V V V MAX UNITS Bits dB V V µA mA ±2 ±30 ±0.001 12 V V V V V V V V % mV % FSR(2) µV –94 –74 –34 15 3 1 350 350 2.5 10 –82 –68 –28 V V V V V V V V V V V V –88 V V V V V V –80 –40 V V V V V V V –92 –74 –34 dB dB dB Bits µs µs ns ns µs V/µs Min 4 V V V V V V V V V V V V V V V V V V V V V V V ±2 0.1 Indefinite to Common ±1 1.2 +4.75 –4.75 +4.75 –4.75 +12 –12 +5 –5 +13 –16 V mA Ω mA kΩ V V V V mA mA °C °C 0 –55 V V V V V Specifications same as for PCM54HP. NOTES: (1) Externally adjustable. If external adjustment is not used, connect a 0.01µF capacitor to Common to reduce noise pickup. (2) FSR means Full-Scale Range and is 6V for ±3V output. (3) The measurement of total harmonic distortion is highly dependent on the characteristics of the measurement circuit. Burr-Brown may calculate THD from the measured linearity errors using Equation 2 in the section on “Total Harmonic Distortion,” but specifies that the maximum THD measured with the circuit shown in Figure 2 will be less than the limits indicated. (4) Measured with an active clamp to provide a low impedance for approximately 200ns. (5) Deglitcher or sample/hold delay used in THD measurement test circuit. See Figures 2 and 3. (6) Output amplifier disconnected. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM54/55 2 CONNECTION DIAGRAMS PCM54 (Optional) 560kΩ 100kΩ 330kΩ 1MΩ 1 PCM55 –VCC 24 Zener Voltage Reference 16-Bit Ladder Resistor Network and Switches 23 (1) (1) 1 2 3 4 5 6 16-Bit Ladder Resistor Network and Switches Zener Voltage Reference 28 –VCC 27 +VCC 26 (2) 2 3 4 +VCC 1µF + + 1µF 22 21 20 24 23 22 0.1µF + 1µF 1µF + Data Inputs 25 5 6 7 8 Common 19 18 17 16 15 14 13 Data Inputs (2) (2) Data Inputs 7 8 9 10 11 12 13 14 Audio VOUT Common 21 (3) 9 10 20 19 18 17 16 15 Data Inputs Audio VOUT 11 12 NOTES: (1) Connect for bipolar operation. (+VCC ≥ 8.5V for unipolar operation.) (2) Connect for VOUT operation. When VOUT amp is not being used (IOUT mode), terminate with an external 3kΩ feedback resistor between pin 17 and pin 19, and a 1kΩ resistor between pin 19 and pin 20 to reduce possible noise effects. NOTES: (1) MSB error (BPZ differential linearity error) can be adjusted to zero using this external circuit. (2) Connect to bipolar operation (+VCC ≥ 8.5V for unipolar operation). (3) Connect for VOUT operation. When VOUT amp is not being used (IOUT mode), terminate with an external 3kΩ feedback resistor between pin 19 and pin 21, and a 1kΩ resistor between pin 21 and pin 22 to reduce possible noise effects. PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PCM54-DIP Trim Bit 1 (MSB) Bit 2 NC Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 PIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PCM54-DIP Bit 13 Bit 14 Bit 15 Bit 16 (LSB) VOUT RFB SJ Common IOUT NC IBPO +VCC MSB Adjust –VCC PIN ASSIGNMENTS PIN 1 2 3 4 5 6 7 8 9 10 11 12 PCM55-SOIC Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 PIN 13 14 15 16 17 18 19 20 21 22 23 24 PCM55-SOIC Bit 13 Bit 14 Bit 15 Bit 16 VOUT Feedback Resistor Summing Junction Common Current Output Bipolar Offset +VCC –VCC ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION PRODUCT PCM54HP PCM54JP PCM54KP PCM55HP PCM55JP PACKAGE 28-Pin 28-Pin 28-Pin 24-Lead 24-Lead DIP DIP DIP SOIC SOIC PACKAGE DRAWING NUMBER(1) 215 215 215 178 178 DC Supply Voltage ...................................................................... ±18VDC Input Logic Voltage ............................................................... –1V to +5.5V Power Dissipation .................................. PCM54 800mW, PCM55 400mW Storage Temperature ...................................................... –55°C to +100°C Lead Temperature, (soldering, 10s) .............................................. +300°C ORDERING INFORMATION PRODUCT PCM54HP PCM54JP PCM54KP PCM55HP PCM55JP THD at FS 0.008 0.004 0.0025 0.008 0.004 PACKAGE 28-Pin DIP 28-Pin DIP 28-Pin DIP 24-Lead SOIC 24-Lead SOIC ® NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. 3 PCM54/55 DISCUSSION OF SPECIFICATIONS The PCM54 and PCM55 are specified to provide critical performance criteria for a wide variety of applications. The most critical specifications for a D/A converter in audio applications are total harmonic distortion, differential linearity error, bipolar zero error, parameter shifts with time and temperature, and settling time effects on accuracy. The PCM54 and PCM55 are factory-trimmed and tested for all critical key specifications. The accuracy of a D/A converter is described by the transfer function shown in Figure 1. Digital input to analog output relationship is shown in Table I. The errors in the D/A converter are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, power supply rejection, and reference errors. In summary, these errors consist of initial errors including gain, offset, linearity, differential linearity, and power supply sensitivity. Gain drift over temperature rotates the line (Figure 1) about the bipolar zero point and offset drift shifts the line left or right over the operating temperature range. Most of the offset and gain drift with temperature or time is due to the drift of the internal reference zener diode. The converter is designed so that these drifts are in opposite directions. This way, the bipolar zero voltage is virtually unaffected by variations in the reference voltage. DIGITAL INPUT CODES The PCM54 and PCM55 accept complementary digital input codes in any of three binary formats (CSB, unipolar; or COB, bipolar; or CTC, Complementary Two’s Complement, bipolar). See Table II. ANALOG OUTPUT Digital Input Codes 0000H 7FFFH 8000H FFFFH Complementary Straight Binary (CSB) +Full Scale +1/2 Full Scale +1/2 Full Scale –1LSB Zero Complementary Offset Binary (COB) +Full Scale Bipolar Zero –1LSB –Full Scale Complementary Two’s Complement (CTS)(1) –1LSB –Full Scale +Full Scale Bipolar Zero NOTE: (1) Invert the MSB of the COB code with an external inverter to obtain CTC code. 0000…0000 0000…0001 0111…1101 Digital Input 0111…1110 0111…1111 1000…0000 1000…0001 1111…1110 1111…1111 Offset Drift Bipolar Zero Gain Drift All Bits On TABLE II. Digital Input Codes. BIPOLAR ZERO ERROR Initial Bipolar Zero (BPZ) error (Bit 1 “ON” and all other bits “OFF”) is the deviation from 0V out and is factorytrimmed to typically ±10mV at +25°C. DIFFERENTIAL LINEARITY ERROR Differential Linearity Error (DLE) is the deviation from an ideal 1LSB change from one adjacent output state to the next. DLE is important in audio applications because excessive DLE at bipolar zero (at the “major carry”) can result in audible crossover distortion for low level output signals. Initial DLE on the PCM54 and PCM55 is factory-trimmed to typically ±0.001% of FSR. This error is adjustable to zero using the circuit shown in the connection diagram (PCM54 only). –FSR/2 Analog Output (+FSR/2) –1LSB * See Table I for digital code definitions. FIGURE 1. Input vs Output for an Ideal Bipolar D/A Converter. VOLTAGE OUTPUT MODE Analog Output Unipolar (1) Digital Input Code One LSB 0000H FFFFH (µV) (V) (V) 16-Bit 91.6 +5.99991 0 15-Bit 183 +5.99982 0 14-Bit 366 +5.99963 0 16-Bit 91.6 +2.99991 –3.0000 Bipolar 15-Bit 183 +2.99982 –3.0000 14-Bit 366 +2.99963 –3.0000 CURRENT OUTPUT MODE Analog Output Unipolar Digital Input Code One LSB 0000H FFFFH (µA) (mA) (mA) 16-Bit 0.031 –1.99997 0 15-Bit 0.061 –1.99994 0 14-Bit 0.122 –1.99988 0 16-Bit 0.031 –0.99997 +1.00000 Bipolar 15-Bit 0.061 –0.99994 +1.00000 14-Bit 0.122 –0.99988 +1.00000 NOTE: (1) +VCC must be at least +8.5VDC to allow output to swing to +6.0VDC. TABLE I. Digital Input to Analog Output Relationship. ® PCM54/55 4 POWER SUPPLY SENSITIVITY Changes in the DC power supplies will affect accuracy. The PCM54 and PCM55 power supply sensitivity is shown by Figure 2. Normally, regulated power supplies with 1% or less ripple are recommended for use with the DAC. See also Power Supply Connections paragraph in the Installation and Operating Instructions section. 10.0 3.0 1.0 THD (%) –60dB 0.30 0.10 0.03 0.01 0.003 0.001 5 10 15 0dB –20dB STABILITY WITH TIME AND TEMPERATURE The parameters of a D/A converter designed for audio applications should be stable over a relatively wide temperature range and over long periods of time to avoid undesirable periodic readjustment. The most important parameters are bipolar zero, differential linearity error, and total harmonic distortion. Most of the offset and gain drift with temperature or time is due to the drift of the internal reference zener diode. The PCM54 and PCM55 are designed so that these drifts are in opposite directions so that the bipolar zero voltage is virtually unaffected by variations in the reference voltage. Both DLE and THD are dependent upon the matching and tracking of resistor ratios and upon VBE and hFE of the current-source transistors. The PCM54 and PCM55 were designed so that any absolute shift in these components has virtually no effect on DLE or THD. The resistors are made of identical links of ultra-stable nichrome thin-film. The current density in these resistors is very low to further enhance their stability. DYNAMIC RANGE The dynamic range is a measure of the ratio of the smallest signals the converter can produce to the full-scale range and is usually expressed in decibels (dB). The theoretical dynamic range of a converter is approximately 6 x n, or about 96dB for a 16-bit converter. The actual, or useful, dynamic range is limited by noise and linearity errors and is therefore somewhat less than the theoretical limit. However, this does point out that a resolution of at least 16 bits is required to obtain a 90dB minimum dynamic range, regardless of the accuracy of the converter. Another specification that is useful for audio applications is total harmonic distortion. TOTAL HARMONIC DISTORTION THD is useful in audio applications and is a measure of the magnitude and distribution of the linearity error, differential linearity error, and noise as well as quantization error. To be useful, THD should be specified for both high level and low level input signals. This error is unadjustable and is the most meaningful indicator of D/A converter accuracy for audio applications. The THD is defined as the ratio of the square root of the sum of the squares of the values of the harmonics to the value of the fundamental input frequency and is expressed in percent or dB. The rms value of the PCM54/55 error referred to the input can be shown to be: (1) ±VCC Supplies (V) FIGURE 2. Effects of ±VCC on Total Harmonic Distortion (PCM54JP; VCCs with approximately 2% ripple). SETTLING TIME Settling time is the total time (including slew time) required for the output to settle within an error band around its final value after a change in input (see Figure 3). Settling times are specified to ±0.006% of FSR; one for a large output voltage change of 3V and one for a 1LSB change. The 1LSB change is measured at the major carry (0111…11 to 10000.00), the point at which the worst-case settling time occurs. Accuracy Percent Full-Scale Range (%) 1.0 0.3 0.1 0.03 0.01 RL = 200Ω 0.003 0.001 0.01 0.1 1.0 Settling Time (µs) 10.0 Current Output Mode Voltage Output Mode ε rms = 1 n n Σ [Ε L ( i ) i =1 + Ε Q (i)]2 FIGURE 3. Full-Scale Range Settling Time vs Accuracy. where n is the number of samples in one cycle of any given sine wave, EL(i) is the linearity error of the PCM54 or PCM55 at each sampling point, and EQ(i) is the quantization ® 5 PCM54/55 error at each sampling point. The THD can then be expressed as: (2) 1 n n Σ i =1 INSTALLATION AND OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the connections diagram. These capacitors (1µF tantalum or electrolytic recommended) should be located close to the converter. MSB ERROR ADJUSTMENT PROCEDURE (OPTIONAL) The MSB error of the PCM54 and PCM55 can be adjusted to make the differential linearity error (DLE) at BPZ essentially zero. This is important when the signal output levels are very low because zero crossing noise (DLE at BPZ) becomes very significant when compared to the small code changes occurring in the LSB portion of the converter. Differential linearity error at bipolar zero is guaranteed to meet data sheet specifications without any external adjustment. However, a provision has been made for an optional adjustment of the MSB linearity point which makes it possible to eliminate DLE error at BPZ (PCM54 only). Two procedures are given to allow either static or dynamic adjustment. The dynamic procedure is preferred because of the difficulty associated with the static method (accurately measuring 16-bit LSB steps). To statically adjust DLE at BPZ, refer to the circuit shown in Figure 6 or the PCM54 connection diagram. After allowing ample warm-up time (20-30 minutes) to assure stable operation of the PCM54, select input code 8000 hexadecimal (all bits off except the MSB). Measure and record it. Change the digital input code to 7FFF hexadecimal (all bits off except the MSB). Adjust the 100kΩ potentiometer to make the audio output read 92µV more than the voltage reading of the previous code (a ILSB step = 92µV). A much simpler method is to dynamically adjust the DLE at BPZ. Again, refer to Figure 6 or the PCM54 connection diagram for circuitry and component values. Assuming the device has been installed in a digital audio application circuit, send the appropriate digital input to produce a –60dB level sinusoidal output. While measuring the THD of the audio circuit output, adjust the 100kΩ potentiometer until a minimum level of distortion is observed. ε THD = rms = Ε rms [Ε L (i) + Ε Q (i)] Ε rms 2 • 100% where Erms is the rms signal voltage level. This expression indicates that, in general, there is a correlation between the THD and the square root of the sum of the squares of the linearity errors at each digital word of interest. However, this expression does not mean that the worst-case linearity error of the D/A is directly correlated to the THD. For PCM54/55 the test period was chosen to be 22.7µs (44.1kHz) which is compatible with the EIAJ STC-007 specification for PCM audio. The test frequency is 420Hz and the amplitude of the input signal is 0dB, –20dB, and –60dB down from full scale. Figure 4 shows the typical THD as a function of output voltage. Figure 5 shows typical THD as a function of frequency. 10.0 Total Harmonic Distortion (THD) in % 4.0 2.0 1.0 0.4 0.2 0.1 0.04 0.02 0.01 0.004 0.002 0.001 –60 –50 –40 –30 VOUT (dB) 0dB = Full-Scale Range (FSR) 16 Bits 14 Bits –20 –10 0 FIGURE 4. Total Harmonic Distortion (THD) vs VOUT. 0.1 Total Harmonic Distortion (%) 0.05 0.02 0.01 0.005 –20dB 1 27 560kΩ 1MΩ 100kΩ 330kΩ –VCC 0.002 0.001 100 1k Frequency (Hz) Full Scale 10k 20k FIGURE 6. MSB Differential Linearity at Bipolar Zero Adjustment Circuit (optional). FIGURE 5. Total Harmonic Distortion (THD) vs Frequency. ® PCM54/55 6 INSTALLATION CONSIDERATIONS If the optional external MSB error circuitry is used (PCM54), a potentiometer with adequate resolution and a TCR of 100ppm/°C or less is required. Also, extra care must be taken to insure that no leakage path (either AC or DC) exists to pin 27 (PCM54). If circuit is not used, pin 1 (PCM54) should be terminated to common with a 0.01µF capacitor. The PCM converter and the wiring to its connectors should be located to provide the optimum isolation from sources of RFI and EMI. The important consideration in the elimination of RF radiation or pickup is loop area; therefore, signal leads and their return conductors should be kept close together. This reduces the external magnetic field along with any radiation. Also, if a signal lead and its return conductor are wired close together, they represent a small flux-capture cross section for any external field. This reduces radiation pickup in the circuit. Due to the fast settling time of the PCM54-V, it is possible to minimize the delay between the left channel and right channel outputs when using a single D/A converter for both channels. This is important because the left and right channel data is recorded in phase and use of a slower D/A converter would result in significant phase error at the higher audio frequencies. A low-pass filter is required at the S/H output to remove all unwanted frequency components caused by the sampling frequency as well as the discrete nature of the D/A converter output. The filter must have a flat amplitude response over the entire audio band (0 to 20kHz) and a very high attenuation above 20kHz. Most previous digital audio circuits used a high-order (9-13 pole) analog filter. However, the phase response of an analog filter with these amplitude characteristics is nonlinear and can disturb the pulse-shaped characteristics of the transients contained in music. R R C1 B A SW1 A1 Left Channel Output to LPF and Other Circuits R C2 B A A2 SW2 Right Channel Output to LPF and Other Circuits A1, A2 ATE OPA101 or OPA404 APPLICATIONS A sample/hold amplifier, or “deglitcher”, is required at the output of the D/A converter for both the left and right channel, as shown in Figure 7. The S/H amplifier for the left channel is composed of A2, SW1, and associated circuitry. A2 is used as an integrator to hold the analog voltage in C1. Since the source and drain of the FET switch operates at a virtual ground when “C” and “B” are closed in the simple mode, there is no increase in distortion caused by the modulation effect of RON by the audio signal. Figure 8 shows the deglitcher control signals for both the left and right channels which are produced by the timing control logic. A delay of 2.5µs (tω) is provided to eliminate the glitch and allow the output of the PCM54-V to settle within a small error band around its final value before connecting it to the channel output. PCM54/55 C Data to DAC Left Channel Deglitcher Control R C Right Channel Deglitcher Control A LOW signal on the deglitcher control closes switch “A”, while a HIGH signal closes switch “B”. FIGURE 7. A Sample/Hold Amplifier (deglitcher) is Required at the Digital-to-Analog Output for Both Left and Right Channels. 44.1kHz Data for DAC Right Channel Data N Left Channel Data N Right Channel Data N+1 Left Channel Data N+1 tS Right Channel Deglitcher Control tW Left Channel Deglitcher Control Delay Between Left and Right Channel The deglitcher control signals are generated by the timing control logic. The fast settling time of the PCM54/55 makes it possible to minimize the delay between left and right channels to approximately 4.5µs which reduces phase error at the higher audio frequencies. FIGURE 8. Timing Diagram for the Deglitcher Control Signals. ® 7 PCM54/55