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PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
PCM6xx0-Q1 Automotive, 4-Channel and 6-Channel, 768-kHz, Audio ADC
With Integrated Microphone Bias and Input Fault Diagnostics
1 Features
3 Description
•
The
4-channel
PCM6x40-Q1
(PCM6240-Q1,
PCM6340-Q1)
and
6-channel
PCM6x60-Q1
(PCM6260-Q1, PCM6360-Q1) are high-performance,
audio analog-to-digital converters (ADCs) that
support analog input signals up to 10 VRMS. The
PCM6x40-Q1 and PCM6x60-Q1 (PCM6xx0-Q1)
support line and microphone inputs, and allows for
both
single-ended
and
differential
input
configurations. These devices offer an integrated
high-voltage, programmable microphone bias, and
input diagnostic circuitry that allow direct connection
to microphone-based automotive systems with full
fault diagnostic capability for direct-coupled inputs.
The PCM62x0-Q1 integrate an efficient boost
converter to generate a high voltage microphone bias
using an external, low-voltage, 3.3-V supply, whereas
the PCM63x0-Q1 directly uses an external highvoltage supply (HVDD), which is a readily available
supply in the system to generate the high-voltage,
programmable microphone bias. The PCM6xx0-Q1
integrate the programable channel gain, digital
volume control, a low-jitter phase-locked loop (PLL), a
programmable high-pass filter (HPF), biquad filters,
low-latency filter modes, and allows for sample rates
up to 768 kHz. The PCM6xx0-Q1 support timedivision multiplexing (TDM), I2S, or left-justified (LJ)
audio formats, and can be controlled with either the
I2C or SPI interface. These integrated highperformance features, along with a single, 3.3-V
supply operation, make the PCM6xx0-Q1 family an
excellent choice for space-constrained automotive
systems.
1
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•
•
•
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AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C ≤ TA ≤ +125°C
ADC performance:
– Line differential input dynamic range: 110 dB
– Microphone differential input dynamic range:
110 dB
– THD+N: –95 dB
– Channel summing mode supports high SNR
ADC input voltage:
– Differential, 10-VRMS full-scale inputs
– Single-ended, 5-VRMS full-scale inputs
ADC sample rate (fS) = 8 kHz to 768 kHz
Programmable channel settings:
– Channel gain: 0 dB to 42 dB, 1-dB steps
– Digital volume control: –100 dB to 27 dB
– Gain calibration with 0.1-dB resolution
– Phase calibration with 163-ns resolution
Programmable microphone bias (5 V to 9 V):
– With integrated efficient boost converter, or
– With external high voltage HVDD supply
Programmable microphone input fault diagnostics:
– Open inputs or shorted inputs
– Short to ground, MICBIAS or VBAT
– Microphone bias over current protection
Low-latency signal processing filter selection
Programmable HPF and biquad digital filters
I2C or SPI controls
Audio serial data interface:
– Format: TDM, I2S, or left-justified (LJ)
– Word length: 16 bits, 20 bits, 24 bits, or 32 bits
– Master or slave interface
Single-supply, 3.3-V operation
I/O supply operation: 3.3 V or 1.8 V
Power consumption:
– < 20 mW/channel at 48-kHz
Device Information(1)
PART NUMBER
PCM6xx0-Q1
WQFN (32)
Simplified Application Diagram (PCM6260-Q1)
MICBIAS
BSTOUT
BSTSW
BSTVDD
IN1P
IN1M
SHDNZ
Boost Converter and
Programmable MICBIAS
PLL and Clock
Generation
GPIO1
IN2P
2 Applications
IN2M
IN3P
FSYNC
IN3M
IN4P
Automotive active noise cancellation
Automotive head units
Digital cockpit processing units
Automotive external amplifiers
BODY SIZE (NOM)
5.00 mm x 5.00 mm with
0.5-mm pitch
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Noise
Cancellation
Microphones
•
•
•
•
PACKAGE
Multi-Channel ADC
with Front-End PGA
and Input Attenuator
Audio Serial
Interface
2
(TDM, I S, LJ)
Programmable
Digital Filters and
Biquads
BCLK
SDOUT
IN4M
SDA_SSZ
IN5P
SCL_MOSI
IN5M
Hands-free
Calling
Microphones
2
I C or SPI
Control Interface
Input Diagnostics, Regulators
and Voltage Reference
ADDR0_SCLK
IN6P
ADDR1_MISO
IN6M
VBAT_IN
VREF
AREG
DREG
VSS
AVSS
AVDD
IOVDD
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions ......................... 4
Specifications....................................................... 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
Absolute Maximum Ratings ....................................
ESD Ratings............................................................
Recommended Operating Conditions.....................
Thermal Information ................................................
Electrical Characteristics.........................................
Timing Requirements: I2C Interface........................
Switching Characteristics: I2C Interface..................
Timing Requirements: SPI Interface .......................
Switching Characteristics: SPI Interface .................
Timing Requirements: TDM, I2S or LJ Interface...
Switching Characteristics: TDM, I2S or LJ
Interface ...................................................................
7.12 Typical Characteristics ..........................................
8
12
12
12
13
13
17
17
18
18
18
19
21
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagrams ..................................... 25
8.3
8.4
8.5
8.6
9
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
29
66
67
71
Application and Implementation ...................... 144
9.1 Application Information.......................................... 144
9.2 Typical Applications .............................................. 144
9.3 What To Do and What Not To Do......................... 147
10 Power Supply Recommendations ................... 148
11 Layout................................................................. 149
11.1 Layout Guidelines ............................................... 149
11.2 Layout Examples................................................. 150
12 Device and Documentation Support ............... 152
12.1
12.2
12.3
12.4
Device Support....................................................
Documentation Support .....................................
Related Links ......................................................
Receiving Notification of Documentation
Updates..................................................................
12.5 Support Resources .............................................
12.6 Trademarks .........................................................
12.7 Electrostatic Discharge Caution ..........................
12.8 Glossary ..............................................................
152
152
152
152
152
153
153
153
13 Mechanical, Packaging, and Orderable
Information ......................................................... 153
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2020) to Revision A
•
2
Page
Changed document status from advance information to production data ............................................................................. 1
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Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
5 Device Comparison Table
FEATURE
PCM6240-Q1
PCM6260-Q1
PCM6340-Q1
PCM6360-Q1
I2C or SPI
Control interface
TDM or I2S or left-justified (LJ)
Digital audio serial interface
Audio analog channel
4
6
4
6
General-purpose input or output pins
5
1
5
1
Microphone bias voltage
Microphone bias LDO supply
Programmable 5 V to 9 V in steps of 0.5 V
Generated using integrated efficient boost converter with
external low-voltage BSTVDD = 3.3-V supply
Input fault diagnostics
Comprehensive input fault diagnostics for DC-coupled microphone inputs with programmable thresholds
Package
Compatibility
Powered directly using external high-voltage HVDD (as
high as 12 V) supply
WQFN (RTV), 32-pin, 5.00 mm x 5.00 mm (0.5-mm pitch)
Package, and control registers compatible; replacements of each other. See the Scalable Automotive Audio
Solutions Using the PCM6xx0-Q1 Family of Products application report for further details.
Copyright © 2020, Texas Instruments Incorporated
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Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
3
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
www.ti.com
6 Pin Configuration and Functions
PCM6240-Q1 RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions: PCM6240-Q1
PIN
TYPE
DESCRIPTION
NO.
NAME
1
AVDD
Analog supply
Analog power (3.3 V, nominal)
2
AREG
Analog supply
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal)
3
BSTVDD
Analog supply
Boost converter supply voltage (3.3 V, nominal)
4
BSTSW
Analog supply
Boost converter switch input
5
BSTOUT
Analog supply
Boost converter output voltage
6
MICBIAS
Analog
MICBIAS output (programmable output up to 9 V)
7
VREF
Analog
Analog reference voltage filter output
8
AVSS
Analog supply
9
IN1P
Analog input
Analog input 1P pin
10
IN1M
Analog input
Analog input 1M pin
11
IN2P
Analog input
Analog input 2P pin
12
IN2M
Analog input
Analog input 2M pin
13
IN3P
Analog input
Analog input 3P pin
14
IN3M
Analog input
Analog input 3M pin
15
IN4P
Analog input
Analog input 4P pin
16
IN4M
Analog input
Analog input 4M pin
17
GPI2
Digital input
General-purpose digital input 2 (multipurpose functions such as daisy-chain input, PLL input
clock source, and so forth)
18
GPIO3
Digital I/O
19
GPI1
Digital input
20
GPIO2
Digital I/O
21
VBAT_IN
Analog
4
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Analog ground; short directly to the board ground plane.
General-purpose digital input/output 3 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
General-purpose digital input 1 (multipurpose functions such as daisy-chain input, PLL input
clock source, and so forth)
General-purpose digital input/output 2 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
Analog VBAT input monitoring pin (used for input diagnostics)
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Pin Functions: PCM6240-Q1 (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
22
SHDNZ
Digital input
23
ADDR1_MISO
Digital I/O
For I2C operation: I2C slave address A1 pin
For SPI operation: SPI slave output pin
24
ADDR0_SCLK
Digital input
For I2C operation: I2C slave address A0 pin
For SPI operation : SPI serial bit clock
25
SCL_MOSI
Digital input
For I2C operation: clock pin for I2C control bus
For SPI operation: SPI slave input pin
26
SDA_SSZ
Digital I/O
For I2C operation: data pin for I2C control bus
For SPI operation: SPI slave-select pin
27
IOVDD
Digital supply
28
GPIO1
Digital I/O
29
SDOUT
Digital output
30
BCLK
Digital I/O
Audio serial data interface bus bit clock
31
FSYNC
Digital I/O
Audio serial data interface bus frame synchronization signal
32
DREG
Digital supply
Digital regulator output voltage for digital core supply (1.5 V, nominal)
Ground supply
Thermal pad shorted to the internal device ground. Short the thermal pad directly to the
board ground plane.
Thermal Pad (VSS)
Copyright © 2020, Texas Instruments Incorporated
Device hardware shutdown and reset (active low)
Digital I/O power supply (1.8 V or 3.3 V, nominal)
General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
Audio serial data interface bus output
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5
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
www.ti.com
DREG
FSYNC
BCLK
SDOUT
GPIO1
IOVDD
SDA_SSZ
SCL_MOSI
32
31
30
29
28
27
26
25
PCM6260-Q1 RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
AVDD
1
24
ADDR0_SCLK
AREG
2
23
ADDR1_MISO
BSTVDD
3
22
SHDNZ
BSTSW
4
21
VBAT_IN
BSTOUT
5
20
IN6M
MICBIAS
6
19
IN6P
VREF
7
18
IN5M
AVSS
8
17
IN5P
9
10
11
12
13
14
15
16
IN1P
IN1M
IN2P
IN2M
IN3P
IN3M
IN4P
IN4M
Thermal Pad (VSS)
Not to scale
Pin Functions: PCM6260-Q1
PIN
NO.
NAME
TYPE
DESCRIPTION
1
AVDD
Analog supply
Analog power (3.3 V, nominal)
2
AREG
Analog supply
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal)
3
BSTVDD
Analog supply
Boost converter supply voltage (3.3 V, nominal)
4
BSTSW
Analog supply
Boost converter switch input
5
BSTOUT
Analog supply
Boost converter output voltage
6
MICBIAS
Analog
MICBIAS output (programmable output up to 9 V)
7
VREF
Analog
Analog reference voltage filter output
8
AVSS
Analog supply
9
IN1P
Analog input
Analog input 1P pin
10
IN1M
Analog input
Analog input 1M pin
11
IN2P
Analog input
Analog input 2P pin
12
IN2M
Analog input
Analog input 2M pin
13
IN3P
Analog input
Analog input 3P pin
14
IN3M
Analog input
Analog input 3M pin
15
IN4P
Analog input
Analog input 4P pin
16
IN4M
Analog input
Analog input 4M pin
17
IN5P
Analog input
Analog input 5P pin
18
IN5M
Analog input
Analog input 5M pin
19
IN6P
Analog input
Analog input 6P pin
20
IN6M
Analog input
Analog input 6M pin
21
VBAT_IN
Analog
22
SHDNZ
Digital input
23
ADDR1_MISO
Digital I/O
For I2C operation: I2C slave address A1 pin
For SPI operation: SPI slave output pin
24
ADDR0_SCLK
Digital input
For I2C operation: I2C slave address A0 pin
For SPI operation : SPI serial bit clock
25
SCL_MOSI
Digital input
For I2C operation: clock pin for I2C control bus
For SPI operation: SPI slave input pin
26
SDA_SSZ
Digital I/O
For I2C operation: data pin for I2C control bus
For SPI operation: SPI slave-select pin
27
IOVDD
Digital supply
6
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Analog ground. Short this pin directly to the board ground plane.
Analog VBAT input monitoring pin (used for input diagnostics)
Device hardware shutdown and reset (active low)
Digital I/O power supply (1.8 V or 3.3 V, nominal)
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Pin Functions: PCM6260-Q1 (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
28
GPIO1
Digital I/O
29
SDOUT
Digital output
30
BCLK
Digital I/O
Audio serial data interface bus bit clock
31
FSYNC
Digital I/O
Audio serial data interface bus frame synchronization signal
32
DREG
Digital supply
Digital regulator output voltage for digital core supply (1.5 V, nominal)
Ground supply
Thermal pad shorted to internal device ground. Short the thermal pad directly to the board
ground plane.
Thermal Pad (VSS)
Copyright © 2020, Texas Instruments Incorporated
General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
Audio serial data interface bus output
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Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
7
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
www.ti.com
PCM6340-Q1 RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions: PCM6340-Q1
PIN
TYPE
DESCRIPTION
NO.
NAME
1
AVDD
Analog supply
Analog power (3.3 V, nominal)
2
AREG
Analog supply
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal)
3
AVDD
Analog supply
Analog power (3.3 V, nominal)
4
AVSS
Analog supply
Analog ground
5
HVDD
Analog supply
Analog power (11 V, nominal)
6
MICBIAS
Analog
MICBIAS output (programmable output up to 9 V)
7
VREF
Analog
Analog reference voltage filter output
8
AVSS
Analog supply
9
IN1P
Analog input
Analog input 1P pin
10
IN1M
Analog input
Analog input 1M pin
11
IN2P
Analog input
Analog input 2P pin
12
IN2M
Analog input
Analog input 2M pin
13
IN3P
Analog input
Analog input 3P pin
14
IN3M
Analog input
Analog input 3M pin
15
IN4P
Analog input
Analog input 4P pin
16
IN4M
Analog input
Analog input 4M pin
17
GPI2
Digital input
General-purpose digital input 2 (multipurpose functions such as daisy-chain input, PLL input
clock source, and so forth)
18
GPIO3
Digital I/O
19
GPI1
Digital input
20
GPIO2
Digital I/O
21
VBAT_IN
Analog
22
SHDNZ
Digital input
8
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Analog ground. Short this pin directly to the board ground plane.
General-purpose digital input/output 3 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
General-purpose digital input 1 (multipurpose functions such as daisy-chain input, PLL input
clock source, and so forth)
General-purpose digital input/output 2 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
Analog VBAT input monitoring pin (used for input diagnostics)
Device hardware shutdown and reset (active low)
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Pin Functions: PCM6340-Q1 (continued)
PIN
NO.
NAME
TYPE
DESCRIPTION
23
ADDR1_MISO
Digital I/O
For I2C operation: I2C slave address A1 pin
For SPI operation: SPI slave output pin
24
ADDR0_SCLK
Digital input
For I2C operation: I2C slave address A0 pin
For SPI operation: SPI serial bit clock
25
SCL_MOSI
Digital input
For I2C operation: clock pin for I2C control bus
For SPI operation: SPI slave input pin
26
SDA_SSZ
Digital I/O
For I2C operation: data pin for I2C control bus
For SPI operation: SPI slave-select pin
27
IOVDD
Digital supply
28
GPIO1
Digital I/O
29
SDOUT
Digital output
30
BCLK
Digital I/O
Audio serial data interface bus bit clock
31
FSYNC
Digital I/O
Audio serial data interface bus frame synchronization signal
32
DREG
Digital supply
Digital regulator output voltage for digital core supply (1.5 V, nominal)
Ground supply
Thermal pad shorted to internal device ground. Short the thermal pad directly to the board
ground plane.
Thermal Pad (VSS)
Copyright © 2020, Texas Instruments Incorporated
Digital I/O power supply (1.8 V or 3.3 V, nominal)
General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
Audio serial data interface bus output
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Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
9
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
www.ti.com
PCM6360-Q1 RTV Package
32-Pin WQFN With Exposed Thermal Pad
Top View
Pin Functions: PCM6360-Q1
PIN
TYPE
DESCRIPTION
NO.
NAME
1
AVDD
Analog supply
Analog power (3.3 V, nominal)
2
AREG
Analog supply
Analog on-chip regulator output voltage for analog supply (1.8 V, nominal)
3
AVDD
Analog supply
Analog power (3.3 V, nominal)
4
AVSS
Analog supply
Analog ground
5
HVDD
Analog supply
Analog power (11 V, nominal)
6
MICBIAS
Analog
MICBIAS output (programmable output up to 9 V)
7
VREF
Analog
Analog reference voltage filter output
8
AVSS
Analog supply
9
IN1P
Analog input
Analog input 1P pin
10
IN1M
Analog input
Analog input 1M pin
11
IN2P
Analog input
Analog input 2P pin
12
IN2M
Analog input
Analog input 2M pin
13
IN3P
Analog input
Analog input 3P pin
14
IN3M
Analog input
Analog input 3M pin
15
IN4P
Analog input
Analog input 4P pin
16
IN4M
Analog input
Analog input 4M pin
17
IN5P
Analog input
Analog input 5P pin
18
IN5M
Analog input
Analog input 5M pin
19
IN6P
Analog input
Analog input 6P pin
20
IN6M
Analog input
Analog input 6M pin
21
VBAT_IN
Analog
22
SHDNZ
Digital input
23
ADDR1_MISO
Digital I/O
For I2C operation: I2C slave address A1 pin
For SPI operation: SPI slave output pin
24
ADDR0_SCLK
Digital input
For I2C operation: I2C slave address A0 pin
For SPI operation: SPI serial bit clock
10
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Analog ground. Short this pin directly to the board ground plane.
Analog VBAT input monitoring pin (used for input diagnostics)
Device hardware shutdown and reset (active low)
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Pin Functions: PCM6360-Q1 (continued)
PIN
NO.
NAME
TYPE
DESCRIPTION
25
SCL_MOSI
Digital input
For I2C operation: clock pin for I2C control bus
For SPI operation: SPI slave input pin
26
SDA_SSZ
Digital I/O
For I2C operation: data pin for I2C control bus
For SPI operation: SPI slave-select pin
27
IOVDD
Digital supply
28
GPIO1
Digital I/O
29
SDOUT
Digital output
30
BCLK
Digital I/O
Audio serial data interface bus bit clock
31
FSYNC
Digital I/O
Audio serial data interface bus frame synchronization signal
32
DREG
Digital supply
Digital regulator output voltage for digital core supply (1.5 V, nominal)
Ground supply
Thermal pad shorted to internal device ground. Short the thermal pad directly to the board
ground plane.
Thermal Pad (VSS)
Copyright © 2020, Texas Instruments Incorporated
Digital I/O power supply (1.8 V or 3.3V, nominal)
General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input,
audio data output, PLL input clock source, interrupt, and so forth)
Audio serial data interface bus output
Submit Documentation Feedback
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
11
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
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7 Specifications
7.1 Absolute Maximum Ratings
over the operating ambient temperature range (unless otherwise noted) (1)
Supply voltage
MIN
MAX
AVDD to AVSS
–0.3
3.9
BSTVDD (2) to VSS (thermal pad)
–0.3
3.9
IOVDD to VSS (thermal pad)
–0.3
3.9
HVDD
(3)
V
–0.3
14
Ground voltage differences
AVSS to VSS (thermal pad)
–0.3
0.3
V
Battery voltage
VBAT_IN to AVSS
–0.3
18
V
Analog input voltage
Analog input pins voltage to AVSS
–0.3
18
V
Digital input voltage
Digital input pins voltage to VSS (thermal pad)
–0.3
IOVDD + 0.3
V
Operating ambient, TA
–40
125
Junction, TJ
–40
150
Storage, Tstg
–65
150
Temperature
(1)
(2)
(3)
to VSS (thermal pad)
UNIT
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
BSTVDD supply is required only for PCM62x0-Q1
HVDD supply is required only for PCM63x0-Q1.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per AEC
Q100-011
UNIT
±2000
Corner package pins
±750
All other non-corner package pins
±500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
POWER
AVDD (1)
Analog supply voltage to AVSS
3.0
3.3
3.6
V
BSTVDD (2)
Boost converter supply voltage to VSS (thermal pad)
3.0
3.3
3.6
V
IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation
3.0
3.3
3.6
IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation
1.65
1.8
1.95
5.6
11
12
V
VBAT_IN input pin voltage to AVSS
0
12.6
18
V
Analog input pins voltage to AVSS for line-in recording
0
14.2
V
0.1
MICBIAS –
0.1
V
IOVDD
HVDD (3)
MICBIAS LDO supply voltage to VSS (thermal pad)
V
INPUTS
VBAT_IN
INxx
Analog input pins voltage to AVSS for microphone recording
Analog input pins voltage to AVSS during short to VBAT_IN
Digital input pins voltage to VSS (thermal pad)
VBAT_IN
V
0
IOVDD
V
–40
125
°C
TEMPERATURE
TA
(1)
(2)
(3)
12
Operating ambient temperature
AVSS and VSS (thermal pad); all ground pins must be tied together and must not differ in voltage by more than 0.2 V.
BSTVDD is required only for the PCM62x0-Q1.
HVDD is required only for the PCM63x0-Q1 and the minimum voltage must be 0.6 V higher than the programmed MICBIAS value.
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Recommended Operating Conditions (continued)
MIN
NOM
MAX
UNIT
36.864 (4)
MHz
OTHERS
GPIOx or GPIx (used as MCLK input) clock frequency
2
Cb
CL
(4)
SCL and SDA bus capacitance for I C interface supports standard-mode
and fast-mode
400
SCL and SDA bus capacitance for I2C interface supports fast-mode plus
550
pF
Digital output load capacitance
20
Boost converter inductor for 6MHz clocking mode (recommended inductor
CIGW201610GL2R2MLE)
2.2
50
pF
µH
MCLK input rise time (VIL to VIH) and fall time (VIH to VIL) must be less than 5 ns. For better audio noise performance, MCLK input must
be used with low jitter.
7.4 Thermal Information
PCM6xx0-Q1
THERMAL METRIC (1)
RTV (WQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
30.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
17.0
°C/W
RθJB
Junction-to-board thermal resistance
11.0
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
10.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
ADC PERFORMANCE FOR LINE INPUT RECORDING
Differential input full-scale
AC signal voltage
Single-ended input fullscale AC signal voltage
AC-coupled input, input fault diagnostic not supported
DC-coupled input, DC common-mode voltage INxP =
INxM = 7.1 V, input fault diagnostic not supported
DR
(1)
(2)
Signal-to-noise ratio, Aweighted (1) (2)
Dynamic range, Aweighted (2)
VRMS
5
VRMS
AC-coupled input, input fault diagnostic not supported
DC-coupled input, DC common-mode voltage INxP =
INxM = 7.1 V, input fault diagnostic not supported
IN1 differential AC-coupled input selected and AC signal
shorted to ground, 0-dB channel gain
SNR
10
105
110
IN1 differential DC-coupled input selected and AC signal
shorted to ground, 0-dB channel gain
110
IN1 differential DC-coupled input selected and AC signal
shorted to ground, 12-dB channel gain
101
IN1 differential AC-coupled input selected and –60-dB
full-scale AC signal input, 0-dB channel gain
110
IN1 differential DC-coupled input selected and –60-dB
full-scale AC signal input, 0-dB channel gain
110
IN1 differential DC-coupled input selected and –72-dB
full-scale AC signal input, 12-dB channel gain
101
dB
dB
Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured Aweighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can
result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, can affect dynamic specification values.
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Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
THD+N
TEST CONDITIONS
Total harmonic distortion (2)
Channel gain control range
NOM
MAX
IN1 differential AC-coupled input selected and –1-dB
full-scale AC signal input, 0-dB channel gain
–95
–78
IN1 differential DC-coupled input selected and –1-dB
full-scale AC signal input, 0-dB channel gain
–95
IN1 differential DC-coupled input selected and –13-dB
full-scale AC signal input, 12-dB channel gain
–91
Programmable 1-dB steps
MIN
0
UNIT
dB
42
dB
ADC PERFORMANCE FOR MICROPHONE INPUT RECORDING
AC-coupled input, input fault diagnostic not
supported. CHx_MIC_RANGE register bit is set to high.
Differential input full-scale
AC signal voltage (3)
IN1 differential DC-coupled input selected and AC-signal
shorted to ground, DC differential common-mode voltage
IN1P – IN1M < 5.0 V, 0-dB channel gain
Dynamic range, Aweighted (2)
DR
THD+N
Total harmonic distortion
10
IN1 differential AC-coupled input selected and AC signal
shorted to ground, 0-dB channel gain
Signal-to-noise ratio, Aweighted (1) (2)
SNR
DC-coupled input, DC differential common-mode voltage
INxP – INxM > 3.4 V, DC common-mode voltage INxP
< (MICBIAS – 1.7 V) and DC common-mode voltage
INxM > 1.7 V. CHx_MIC_RANGE register bit is set to
high to support AC differential signal max swing > 2
Vrms (4).
(2)
Channel gain control range
110
dB
105
110
IN1 differential AC-coupled input selected and –60-dB
full-scale AC signal input, 0-dB channel gain
110
IN1 differential DC-coupled input selected and –60-dB
full-scale AC signal input, DC differential common-mode
voltage IN1P – IN1M < 5.0 V, 0-dB channel gain
110
IN1 differential AC-coupled input selected and –1-dB
full-scale AC signal input, 0-dB channel gain
–92
IN1 differential DC-coupled input selected and –15-dB
full-scale AC signal input, 0-dB channel gain
–90
Programmable 1-dB steps
VRMS
dB
dB
0
–78
42
dB
ADC OTHER PARAMETERS
Input impedance
PSRR
(3)
(4)
14
Differential input, between INxP and INxM
50
Single-ended input, between INxP and INxM
25
kΩ
Digital volume control
range
Programmable 0.5-dB steps
–100
27
dB
Output data sample rate
Programmable
7.35
768
kHz
Output data sample word
length
Programmable
16
32
Bits
Digital high-pass filter
cutoff frequency
First-order IIR filter with programmable coefficients,
–3-dB point (default setting)
Interchannel isolation
–1-dB full-scale AC signal line-in input to non
measurement channel
Interchannel gain
mismatch
–6-dB full-scale AC signal line-in input, 0-dB channel
gain
Interchannel phase
mismatch
1-kHz sinusoidal signal
Power-supply rejection
ratio
100-mVPP, 1-kHz sinusoidal signal on AVDD, differential
input selected, 0-dB channel gain
12
Hz
–134
dB
0.1
dB
0.01
Degrees
92
dB
Microphone inputs support a 2 VRMS differential input full-scale AC signal voltage, if the CHx_MIC_RANGE register bit is set to low
(default value). However, if the input DC common-mode differential voltage is higher than 4 V, then TI recommends setting the
CHx_MIC_RANGE register bit high to avoid any saturation resulting from the high input DC common-mode differential voltage.
If the CHx_MIC_RANGE register bit is set to high (default value is low) in DC-coupled input configuration mode, then the input
differential DC common-mode along with input differential AC signal must be less than 10 VRMS for differential input configuration mode.
Similarly, for single-ended input configuration mode, the input DC common-mode voltage along with the input AC signal must be less
than 5 VRMS .
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
CMRR
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Differential microphone input selected, 0-dB channel
gain, 1-VRMS AC input, 1-kHz signal on both pins and
measure level at output, CHx_CFG0 D3-2 register bits
set to 2b'10 to configure device in high CMRR
performance mode
70
dB
MICBIAS noise
BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor
between MICBIAS and AVSS
6.8
µVRMS
MICBIAS voltage
Programmable 0.5-V steps
MICBIAS current drive
MICBIAS voltage 9 V
MICBIAS load regulation
MICBIAS voltage 9 V, measured up to maximum load
MICBIAS over current
protection threshold
MICBIAS voltage 9 V
Common-mode rejection
ratio
MICROPHONE BIAS
5
0
9
V
80
mA
1
%
82
mA
INPUT DIAGNOSTICS
Fault monitoring repetition
rate
Programmable, DC-coupled input
Fault response time
Fault monitoring repetition rate 4-ms, DC-coupled input
Threshold voltage for
(INxx – AVSS) input
shorted to ground
Programmable 60-mV steps, DC-coupled input
0
900
mV
Threshold voltage for
(INxP – INxM) input
shorted together
Programmable 30-mV steps, DC-coupled input
0
450
mV
Threshold voltage for
(MICBIAS – INxx) input
shorted to MICBIAS
Programmable 30-mV steps, DC-coupled input
0
450
mV
Threshold voltage for
(VBAT – INxx) input
shorted to VBAT_IN
Programmable 30-mV steps, DC-coupled input
0
450
mV
VIL(SHDNZ)
Low-level digital input logic
voltage threshold
SHDNZ pin
–0.3
0.25 ×
IOVDD
V
VIH(SHDNZ)
High-level digital input logic
SHDNZ pin
voltage threshold
0.75 ×
IOVDD
IOVDD +
0.3
V
Low-level digital input logic
voltage threshold
All digital pins except SDA and SCL, IOVDD 1.8-V
operation
–0.3
VIL
0.35 ×
IOVDD
All digital pins except SDA and SCL, IOVDD 3.3-V
operation
–0.3
0.8
0.65 ×
IOVDD
IOVDD +
0.3
2
IOVDD +
0.3
1
4
8
16
ms
ms
DIGITAL I/O
VIH
VOL
VOH
All digital pins except SDA and SCL, IOVDD 1.8-V
High-level digital input logic operation
voltage threshold
All digital pins except SDA and SCL, IOVDD 3.3-V
operation
Low-level digital output
voltage
High-level digital output
voltage
All digital pins except SDA and SCL, IOL = –2 mA,
IOVDD 1.8-V operation
0.45
All digital pins except SDA and SCL, IOL = –2 mA,
IOVDD 3.3-V operation
0.4
V
V
V
All digital pins except SDA and SCL, IOH = 2 mA, IOVDD
1.8-V operation
IOVDD –
0.45
All digital pins except SDA and SCL, IOH = 2 mA, IOVDD
3.3-V operation
2.4
V
VIL(I2C)
Low-level digital input logic
voltage threshold
SDA and SCL
–0.5
0.3 ×
IOVDD
V
VIH(I2C)
High-level digital input logic
SDA and SCL
voltage threshold
0.7 ×
IOVDD
IOVDD +
0.5
V
VOL1(I2C)
Low-level digital output
voltage
SDA, IOL(I2C) = –3 mA, IOVDD > 2 V
0.4
V
VOL2(I2C)
Low-level digital output
voltage
SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V
0.2 x IOVDD
V
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Electrical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL(I2C)
Low-level digital output
current
IIL
SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode
MIN
NOM
MAX
3
UNIT
mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus
20
Input logic-low leakage for
digital inputs
All digital pins, input = 0 V
–5
0.1
5
µA
IIH
Input logic-high leakage for
digital inputs
All digital pins, input = IOVDD
–5
0.1
5
µA
CIN
Input capacitance for
digital inputs
All digital pins
RPD
Pulldown resistance for
digital I/O pins when
asserted on
5
pF
20
kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD
0.5
IBSTVDD, or
IHVDD
Current consumption in
hardware shutdown mode
SHDNZ = 0, all device external clocks stopped
0.1
IIOVDD
0.1
IAVDD
4
IBSTVDD, or
IHVDD
Current consumption in
sleep mode (software
shutdown mode)
All device external clocks stopped
0.1
IIOVDD
Current consumption when
MICBIAS ON, MICBIAS
voltage 9 V, 40 mA load,
ADC off
IBSTVDD
IHVDD
IIOVDD
IAVDD
IBSTVDD, or
IHVDD
IIOVDD
IAVDD
IBSTVDD, or
IHVDD
IIOVDD
IAVDD
IBSTVDD, or
IHVDD
IIOVDD
IAVDD
IBSTVDD, or
IHVDD
16
µA
0.1
IAVDD
IIOVDD
µA
2.1
fS = 48 kHz, BCLK = 256 × fS
Current consumption with
ADC 2-channel operation
at fS 16-kHz, MICBIAS
off, PLL on, BCLK = 512 ×
fS
Current consumption with
ADC 2-channel operation
at fS 48-kHz, MICBIAS off,
PLL off, BCLK = 512 × fS
162.5
41.1
0.01
13.5
0
mA
0.1
13.5
0
mA
0.1
Current consumption with
ADC 4-channel operation
at fS 48-kHz, MICBIAS
off, PLL on, BCLK = 256 ×
fS
24.7
Current consumption with
ADC 6-channel operation
at fS 48 kHz, MICBIAS off,
PLL on, BCLK = 256 ×
fS, (PCM6x60-Q1)
34.2
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mA
0
mA
0.2
0
mA
0.4
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
7.6 Timing Requirements: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 1 for timing diagram
MIN
NOM
MAX
UNIT
100
kHz
STANDARD-MODE
fSCL
SCL clock frequency
0
tHD;STA
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
4
μs
tLOW
Low period of the SCL clock
4.7
μs
tHIGH
High period of the SCL clock
4
μs
tSU;STA
Setup time for a repeated START condition
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tr
SDA and SCL rise time
1000
ns
tf
SDA and SCL fall time
300
ns
tSU;STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
4.7
μs
0
3.45
μs
250
ns
4
μs
4.7
μs
FAST-MODE
fSCL
SCL clock frequency
tHD;STA
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
0
400
kHz
0.6
μs
tLOW
Low period of the SCL clock
1.3
μs
tHIGH
High period of the SCL clock
0.6
μs
tSU;STA
Setup time for a repeated START condition
0.6
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tr
SDA and SCL rise time
μs
0
0.9
μs
100
ns
20
300
ns
20 ×
(IOVDD /
5.5 V)
300
ns
tf
SDA and SCL fall time
tSU;STO
Setup time for STOP condition
0.6
μs
tBUF
Bus free time between a STOP and START condition
1.3
μs
FAST-MODE PLUS
fSCL
SCL clock frequency
tHD;STA
Hold time (repeated) START condition. After this period, the first clock pulse is
generated.
0
tLOW
tHIGH
1000
kHz
0.26
μs
Low period of the SCL clock
0.5
μs
High period of the SCL clock
0.26
μs
tSU;STA
Setup time for a repeated START condition
0.26
μs
tHD;DAT
Data hold time
0
μs
tSU;DAT
Data setup time
50
ns
tr
SDA and SCL Rise Time
20 ×
(IOVDD /
5.5 V)
tf
SDA and SCL Fall Time
tSU;STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START condition
120
ns
120
ns
0.26
μs
0.5
μs
7.7 Switching Characteristics: I2C Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 1 for timing diagram
PARAMETER
td(SDA)
SCL to SDA delay
TEST CONDITIONS
MIN
TYP
UNIT
Standard-mode
200
1250
ns
Fast-mode
200
850
ns
400
ns
Fast-mode plus
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7.8 Timing Requirements: SPI Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 2 for timing diagram
MIN
NOM
MAX
UNIT
t(SCLK)
SCLK period
40
ns
tH(SCLK)
SCLK high pulse duration
18
ns
tL(SCLK)
SCLK low pulse duration
18
ns
tLEAD
Enable lead time
16
ns
tTRAIL
Enable trail time
16
ns
tDSEQ
Sequential transfer delay
20
ns
tSU(MOSI)
MOSI data setup time
8
ns
tHLD(MOSI)
MOSI data hold time
8
tr(SCLK)
SCLK rise time
10% - 90% rise time
6
ns
tf(SCLK)
SCLK fall time
90% - 10% fall time
6
ns
ns
7.9 Switching Characteristics: SPI Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 2 for timing diagram
PARAMETER
ta(MISO)
TEST CONDITIONS
MISO access time
td(MISO)
SCLK to MISO delay
tdis(MISO)
MISO disable time
MIN
TYP
MAX
IOVDD = 1.8 V
18
IOVDD = 3.3 V
14
50% of SCLK to 50% of MISO,
IOVDD = 1.8 V
19
50% of SCLK to 50% of MISO,
IOVDD = 3.3 V
15
IOVDD = 1.8 V
18
IOVDD = 3.3 V
14
UNIT
ns
ns
ns
7.10 Timing Requirements: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram
MIN
t(BCLK)
BCLK period
tH(BCLK)
BCLK high pulse duration
tL(BCLK)
BCLK low pulse duration
tSU(FSYNC)
NOM
MAX
UNIT
40
ns
18
ns
18
ns
FSYNC setup time
8
ns
tHLD(FSYNC)
FSYNC hold time
8
tr(BCLK)
BCLK rise time
10% - 90% rise time
10
ns
tf(BCLK)
BCLK fall time
90% - 10% fall time
10
ns
(1)
18
(1)
(1)
ns
The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is
latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
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7.11 Switching Characteristics: TDM, I2S or LJ Interface
at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram
PARAMETER
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
TEST CONDITIONS
BCLK to SDOUT delay
FSYNC to SDOUT delay in TDM
or LJ mode (for MSB data with
TX_OFFSET = 0)
MIN
18
50% of BCLK to 50% of
SDOUT, IOVDD = 3.3 V
14
50% of FSYNC to 50% of
SDOUT, IOVDD = 1.8 V
18
50% of FSYNC to 50% of
SDOUT, IOVDD = 3.3 V
14
ns
tH(BCLK)
BCLK high pulse duration;
master mode
IOVDD = 1.8 V
14
IOVDD = 3.3 V
14
tL(BCLK)
BCLK low pulse duration; master
mode
IOVDD = 1.8 V
14
IOVDD = 3.3 V
14
td(FSYNC)
BCLK to FSYNC delay; master
mode
tf(BCLK)
(1)
BCLK fall time; master mode
UNIT
ns
BCLK output clock frequency;
master mode (1)
BCLK rise time; master mode
MAX
50% of BCLK to 50% of
SDOUT, IOVDD = 1.8 V
f(BCLK)
tr(BCLK)
TYP
24.576
MHz
ns
ns
50% of BCLK to 50% of
FSYNC, IOVDD = 1.8 V
18
50% of BCLK to 50% of
FSYNC, IOVDD = 3.3 V
14
10% - 90% rise time, IOVDD =
1.8 V
10
10% - 90% rise time, IOVDD =
3.3 V
10
90% - 10% fall time, IOVDD =
1.8 V
8
90% - 10% fall time, IOVDD =
3.3 V
8
ns
ns
ns
The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on
the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.
SDA
tBUF
tLOW
tr
tHD;STA
td(SDA)
SCL
tHD;STA
tHD;DAT
STO
tHIGH
STA
tSU;DAT
tSU;STA
tSU;STO
tf
STA
STO
2
Figure 1. I C Interface Timing Diagram
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SSZ
tDSEQ
tLAG
t(SCLK)
tLEAD
SCLK
tf(SCLK)
tr(SCLK)
tL(SCLK)
tH(SCLK)
td(MISO)
MISO
tdis(MISO)
MSB OUT
BIT6...1
LSB OUT
ta(MISO)
tSU(MOSI)
tHLD(MOSI)
MOSI
MSB IN
LSB IN
BIT6...1
Figure 2. SPI Interface Timing Diagram
FSYNC
tSU(FSYNC)
tHLD(FSYNC)
t(BCLK)
tL(BCLK)
BCLK
tH(BCLK)
tr(BCLK)
tf(BCLK)
td(FSYNC)
td(SDOUT-BCLK)
td(SDOUT-FSYNC)
SDOUT
Figure 3. TDM/I2S/LJ Interface Timing Diagram
20
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7.12 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63xQ1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase
decimation filter, and MICBIAS programmed voltage = 8 V (unless otherwise noted); all performance measurements are done
with a 20-kHz, low-pass filter and an A-weighted filter
-60
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-70
-80
THD+N (dBFS)
-80
THD+N (dBFS)
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-90
-100
-90
-100
-110
-110
-120
-120
-130
-130
-115
-100
-85
-70
-55
-40
-25
-10
Input Amplitude (dB)
-130
-130
0
Figure 4. THD+N vs Input Amplitude
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
THD+N (dBFS)
THD+N (dBFS)
-25
-10
0
THD+
Line
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-90
-100
-110
-110
-120
-120
50
100
500
1000
5000
Frequency (Hz)
-130
20
10000 20000
50
100
500
1000
5000
10000 20000
Frequency (Hz)
Line
AC-coupled differential line input
Line
AC-coupled single-ended line input
Figure 6. THD+N vs Input Frequency With a –1-dBr Input
Figure 7. THD+N vs Input Frequency With a –1-dBr Input
0
0
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-20
-40
Output Amplitude (dBFS)
Output Amplitude (dBFS)
-40
-80
-100
-60
-80
-100
-120
-140
-80
-100
-120
-140
-160
-180
-180
50
100
500
1000
5000
Frequency (Hz)
AC-coupled differential line input
Figure 8. FFT With Idle Input
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10000 20000
Line
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-60
-160
-200
20
-55
Figure 5. THD+N vs Input Amplitude
-90
-40
-70
-60
-80
-20
-85
AC-coupled single-ended line input
-60
-130
20
-100
Input Amplitude (dB)
AC-coupled differential line input
-70
-115
THD+
Line
-200
20
50
100
500
1000
5000
10000 20000
Frequency (Hz)
Line
AC-coupled differential line input
Figure 9. FFT With a –60-dBr Input
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63xQ1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase
decimation filter, and MICBIAS programmed voltage = 8 V (unless otherwise noted); all performance measurements are done
with a 20-kHz, low-pass filter and an A-weighted filter
-60
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-80
THD+N (dBFS)
THD+N (dBFS)
-80
-90
-100
-90
-100
-110
-110
-120
-120
-130
-130
-115
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-100
-85
-70
-55
-40
-25
Input Amplitude (dB)
-130
-130
-12
-115
DC-coupled differential microphone input with DC common-mode
1NxP = 6 V and INxM = 2 V, high swing mode enabled
-70
-55
-40
-25
-12
THD+
MIC_
DC-coupled single-ended microphone input with DC commonmode 1NxP = 4 V and INxM = 0 V, high swing mode enabled
Figure 10. THD+N vs Input Amplitude
Figure 11. THD+N vs Input Amplitude
-60
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
-80
-90
-100
-90
-100
-110
-110
-120
-120
-130
20
50
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-70
THD+N (dBFS)
-80
THD+N (dBFS)
-85
Input Amplitude (dB)
-60
100
500
1000
5000
10000 20000
Frequency (Hz)
-130
20
Figure 12. THD+N vs Input Frequency With a –15-dBr Input
1000
5000
10000 20000
MIC_
Figure 13. THD+N vs Input Frequency With a –15-dBr Input
0
Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-20
-40
-60
-80
-100
-120
-140
-80
-100
-120
-140
-160
-180
-180
50
100
500
1000
5000
10000 20000
Frequency (Hz)
MIC_
DC-coupled differential microphone input with DC common-mode
1NxP = 6 V and INxM = 2 V, high swing mode enabled
Figure 14. FFT With Idle Input
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Channel-1
Channel-2
Channel-3
Channel-4
Channel-5
Channel-6
-60
-160
-200
20
500
DC-coupled single-ended microphone input with DC commonmode 1NxP = 4 V and INxM = 0 V, high swing mode enabled
Output Amplitude (dBFS)
Output Amplitude (dBFS)
-40
100
Frequency (Hz)
0
-20
50
MIC_
DC-coupled differential microphone input with DC common-mode
1NxP = 6 V and INxM = 2 V, High swing mode enabled
22
-100
THD+
MIC_
-200
20
50
100
500
1000
Frequency (Hz)
5000
10000 20000
MIC_
DC-coupled differential microphone input with DC common-mode
1NxP = 6 V and INxM = 2 V, high swing mode enabled
Figure 15. FFT With a –60-dBr Input
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Typical Characteristics (continued)
-60
-60
-70
-70
-80
-80
PSRR (dB)
PSRR (dB)
at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63xQ1), fIN = 1-kHz sinusoidal
signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, PLL on, channel gain = 0 dB, linear phase
decimation filter, and MICBIAS programmed voltage = 8 V (unless otherwise noted); all performance measurements are done
with a 20-kHz, low-pass filter and an A-weighted filter
-90
-100
-90
-100
-110
-110
-120
-120
-130
20
50
100
500
1000
5000
-130
20
10000 20000
Frequency (Hz)
AC-coupled differential line input
100
500
1000
5000
10000 20000
Frequency (Hz)
MIC_
DC-coupled differential microphone input with DC common-mode
1NxP = 6 V and INxM = 2 V, high swing mode enabled
Figure 16. Power-Supply Rejection Ratio vs Ripple
Frequency With 1-VPP Amplitude
Figure 17. Power-Supply Rejection Ratio vs Ripple
Frequency With 1-VPP Amplitude
0.5
70
MICBIAS 5.0 V
MICBIAS 5.5 V
MICBIAS 6.0 V
MICBIAS 6.5 V
MICBIAS 7.0 V
MICBIAS 7.5 V
MICBIAS 8.0 V
MICBIAS 8.5 V
MICBIAS 9.0 V
0.4
0.3
68
BOOST EFFICIENCY (%)
MICBIAS LOAD REGULATION (%)
50
Line
0.2
66
64
62
60
58
0.1
56
54
10
0
0
10
20
30
40
50
60
70
MICBIAS LOAD (mA)
80
MICB
DC-coupled differential microphone input
Figure 18. MICBIAS Load Regulation vs MICBIAS Load
Current
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20
30
40
50
60
70
80
MICBIAS LOAD (mA)
Effi
DC-coupled differential microphone input with DC common-mode
1NxP = 6 V and INxM = 2 V, high swing mode enabled
Figure 19. Boost Efficiency vs MICBIAS Load Current
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8 Detailed Description
8.1 Overview
The PCM6xx0-Q1 are a scalable family of devices that consist of high-performance, low-power, flexible,
multichannel, audio analog-to-digital converters (ADCs) with extensive feature integration. These devices are
intended for automotive applications such as vehicle cabin active noise cancellation, hands-free in-vehicle
communication, emergency call, and multimedia applications. The high dynamic range of these devices enables
far-field audio recording with high fidelity. These devices integrate a host of features that reduce cost, board
space, and power consumption in space-constrained automotive sub-system designs. Package, performance,
and device-compatible configuration registers make this family of devices well suited for scalable system
designs.
The PCM6xx0-Q1 consist of the following blocks:
• Multichannel, multibit, high-performance delta-sigma (ΔΣ) ADCs
• Configurable single-ended or differential audio inputs with high voltage signal swing
• High-voltage, low-noise programmable microphone bias output
• Highly flexible, comprehensive input fault diagnostic
• Automatic gain controller (AGC)
• Programmable decimation filters with linear-phase or low-latency filter
• Programmable channel gain, volume control, and biquad filters for each channel
• Programmable phase and gain calibration with fine resolution for each channel
• Programmable high-pass filter (HPF) and digital channel mixer
• Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
• Integrated digital and analog voltage regulators to support single-supply operation
Communication to the PCM6xx0-Q1 for configuring the control registers is supported using an I2C or SPI
interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or
left-justified (LJ)] to transmit audio data seamlessly in the system across devices.
The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover,
the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the
shared TDM bus timing requirements and board design complexities when operating multiple devices for
applications requiring high audio data bandwidth.
Table 1 lists the reference abbreviations used throughout this document to registers that control the device.
Table 1. Abbreviations for Register References
REFERENCE
ABBREVIATION
DESCRIPTION
EXAMPLE
Page y, register z, bit k
Py_Rz_Dk
Single data bit. The value of a
single bit in a register.
Page y, register z, bits k-m
Py_Rz_D[k:m]
Range of data bits. A range of
data bits (inclusive).
Page 4, register 36, bits 3-0 = P4_R36_D[3:0]
Page y, register z
Py_Rz
One entire register. All eight
bits in the register as a unit.
Page 4, register 36 = P4_R36
Page y, registers z-n
Py_Rz-Rn
Range of registers. A range of
registers in the same page.
Page 4, registers 36, 37, 38 = P4_R36-R38
24
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Page 4, register 36, bit 0 = P4_R36_D0
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BSTVDD
BSTSW
BSTOUT
8.2 Functional Block Diagrams
GPI1
Audio Clock Generation
PLL
(Input Clock Source BCLK, GPIOx, GPIx)
Boost Converter
MICBIAS
IN1P
IN1M
IN2P
IN2M
IN3P
IN3M
IN4P
IN4M
Programmable
MICBIAS
Multi-Function Pin
(Faults, Interrupt, PLL Input
Clock, etc)
GPI2
GPIO1
GPIO2
GPIO3
Input Attenuator
and
PGA
ADC
Ch1
Input Attenuator
and
PGA
ADC
Ch2
Input Attenuator
and
PGA
ADC
Ch3
Input Attenuator
and
PGA
ADC
Ch4
Digital Filters
(Low Latency
LPF,
Programmable
Biquads)
Audio Serial
Interface
2
(TDM, I S, LJ)
SDOUT
BCLK
FSYNC
SDA_SSZ
SCL_MOSI
2
I C or SPI
Control Interface
Regulators / Current Bias /
Voltage Reference
Input Diagnostics
FAULTS
ADDR0_SCLK
ADDR1_MISO
SHDNZ
IOVDD
Thermal Pad(VSS)
DREG
AREG
AVSS
AVDD
VREF
VBAT_IN
Figure 20. Simplified Device Functional Block Diagram for the PCM6240-Q1
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AVDD
AVSS
HVDD
Functional Block Diagrams (continued)
GPI1
MICBIAS
Audio Clock Generation
PLL
(Input Clock Source BCLK, GPIOx, GPIx)
Programmable
High Voltage
MICBIAS
Multi-Function Pin
(Faults, Interrupt, PLL Input
Clock, etc)
GPI2
GPIO1
GPIO2
GPIO3
IN1P
IN1M
IN2P
IN2M
IN3P
IN3M
IN4P
IN4M
Input Attenuator
and
PGA
ADC
Ch1
Input Attenuator
and
PGA
ADC
Ch2
Input Attenuator
and
PGA
ADC
Ch3
Input Attenuator
and
PGA
ADC
Ch4
Digital Filters
(Low Latency
LPF,
Programmable
Biquads)
Audio Serial
Interface
2
(TDM, I S, LJ)
SDOUT
BCLK
FSYNC
SDA_SSZ
SCL_MOSI
2
I C or SPI
Control Interface
Regulators / Current Bias /
Voltage Reference
Input Diagnostics
FAULTS
ADDR0_SCLK
ADDR1_MISO
SHDNZ
IOVDD
Thermal Pad(VSS)
DREG
AREG
AVSS
AVDD
VREF
VBAT_IN
Figure 21. Simplified Device Functional Block Diagram for the PCM6340-Q1
26
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BSTVDD
BSTSW
BSTOUT
Functional Block Diagrams (continued)
Audio Clock Generation
PLL
(Input Clock Source BCLK, GPIO1)
Boost Converter
MICBIAS
IN1P
IN1M
IN2P
IN2M
IN3P
IN3M
IN4P
IN4M
IN5P
IN5M
IN6P
IN6M
Programmable
MICBIAS
Input Attenuator
and PGA
ADC
Ch1
Input Attenuator
and PGA
ADC
Ch2
Input Attenuator
and PGA
ADC
Ch3
Input Attenuator
and PGA
ADC
Ch4
Input Attenuator
and PGA
ADC
Ch5
Input Attenuator
and PGA
ADC
Ch6
Multi-Function Pin
(Faults, Interrupt, PLL Input
Clock, etc)
Digital Filters
(Low Latency
LPF,
Programmable
Biquads)
Audio Serial
Interface
2
(TDM, I S, LJ)
GPIO1
SDOUT
BCLK
FSYNC
SDA_SSZ
SCL_MOSI
Input Diagnostics
FAULTS
2
I C or SPI
Control Interface
Regulators / Current Bias /
Voltage Reference
ADDR0_SCLK
ADDR1_MISO
SHDNZ
IOVDD
Thermal Pad(VSS)
DREG
AREG
AVSS
AVDD
VREF
VBAT_IN
Figure 22. Simplified Device Functional Block Diagram for the PCM6260-Q1
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MICBIAS
IN1P
IN1M
IN2P
IN2M
IN3P
IN3M
IN4P
IN4M
IN5P
IN5M
IN6P
IN6M
AVDD
AVSS
HVDD
Functional Block Diagrams (continued)
Audio Clock Generation
PLL
(Input Clock Source BCLK, GPIO1)
Programmable
High Voltage
MICBIAS
Input Attenuator
and PGA
ADC
Ch1
Input Attenuator
and PGA
ADC
Ch2
Input Attenuator
and PGA
ADC
Ch3
Input Attenuator
and PGA
ADC
Ch4
Input Attenuator
and PGA
ADC
Ch5
Input Attenuator
and PGA
ADC
Ch6
Multi-Function Pin
(Faults, Interrupt, PLL Input
Clock, etc)
Digital Filters
(Low Latency
LPF,
Programmable
Biquads)
Audio Serial
Interface
2
(TDM, I S, LJ)
GPIO1
SDOUT
BCLK
FSYNC
SDA_SSZ
SCL_MOSI
Input Diagnostics
FAULTS
2
I C or SPI
Control Interface
Regulators / Current Bias /
Voltage Reference
ADDR0_SCLK
ADDR1_MISO
SHDNZ
IOVDD
Thermal Pad(VSS)
DREG
AREG
AVSS
AVDD
VREF
VBAT_IN
Figure 23. Simplified Device Functional Block Diagram for the PCM6360-Q1
28
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8.3 Feature Description
8.3.1 Serial Interfaces
This device has two serial interfaces: control and audio data. The control serial interface is used for device
configuration. The audio data serial interface is used for transmitting audio data to the host device.
8.3.1.1 Control Serial Interfaces
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. All these registers can be accessed using either I2C or SPI
communication to the device. For more information, see the Programming section.
8.3.1.2 Audio Serial Interfaces
Digital audio data flows between the host processor and the PCM6xx0-Q1 on the digital audio serial interface
(ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S
or left-justified protocols format, programmable data length options, very flexible master-slave configurability for
bus clock lines, and the ability to communicate with multiple devices within a system directly.
The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the ASI_FORMAT[1:0],
P0_R7_D[7:6] register bits. As shown in Table 2 and Table 3, these modes are all most significant byte (MSB)first, pulse code modulation (PCM) data format, with the output channel data word-length programmable as 16,
20, 24, or 32 bits by configuring the ASI_WLEN[1:0], P0_R7_D[5:4] register bits.
Table 2. Audio Serial Interface Format
P0_R7_D[7:6] : ASI_FORMAT[1:0]
00 (default)
AUDIO SERIAL INTERFACE FORMAT
Time division multiplexing (TDM) mode
01
Inter IC sound (I2S) mode
10
Left-justified (LJ) mode
11
Reserved (do not use this setting)
Table 3. Audio Output Channel Data Word-Length
P0_R7_D[5:4] : ASI_WLEN[1:0]
AUDIO OUTPUT CHANNEL DATA WORD-LENGTH
00
Output channel data word-length set to 16 bits
01
Output channel data word-length set to 20 bits
10
Output channel data word-length set to 24 bits
11 (default)
Output channel data word-length set to 32 bits
The frame sync pin, FSYNC, is used in this audio bus protocol to define the beginning of a frame and has the
same frequency as the output data sample rates. The bit clock pin, BCLK, is used to clock out the digital audio
data across the serial bus. The number of bit clock cycles in a frame must accommodate multiple device active
output channels with the programmed data word length.
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A frame consists of multiple time-division channel slots (up to 64) to allow all output channel audio data
transmissions to complete on the audio bus by a device or multiple PCM6xx0-Q1 devices sharing the same
audio bus. The device supports up to eight output channels that can be configured to place their audio data on
bus slot 0 to slot 63. Table 4 lists the output channel slot configuration settings. In I2S and LJ mode, the slots are
divided into two sets, left-channel slots and right-channel slots, as described in the Inter IC Sound (I2S) Interface
and Left-Justified (LJ) Interface sections.
Table 4. Output Channel Slot Assignment Settings
P0_R11_D[5:0] : CH1_SLOT[5:0]
OUTPUT CHANNEL 1 SLOT ASSIGNMENT
00 0000 = 0d (default)
Slot 0 for TDM or left slot 0 for I2S, LJ.
00 0001 = 1d
Slot 1 for TDM or left slot 1 for I2S, LJ.
…
…
01 1111 = 31d
Slot 31 for TDM or left slot 31 for I2S, LJ.
10 0000 = 32d
Slot 32 for TDM or right slot 0 for I2S, LJ.
…
…
11 1110 = 62d
Slot 62 for TDM or right slot 30 for I2S, LJ.
11 1111 = 63d
Slot 63 for TDM or right slot 31 for I2S, LJ.
Similarly, the slot assignment setting for output channel 2 to channel 6 can be done using the CH2_SLOT
(P0_R12) to CH6_SLOT (P0_R16) registers, respectively.
The slot word length is the same as the output channel data word length set for the device. The output channel
data word length must be set to the same value for all PCM6xx0-Q1 devices if all devices share the same ASI
bus in a system. The maximum number of slots possible for the ASI bus in a system is limited by the available
bus bandwidth, which depends upon the BCLK frequency, output data sample rate used, and the channel data
word length configured.
The device also includes a feature that offsets the start of the slot data transfer with respect to the frame sync by
up to 31 cycles of the bit clock. Table 5 lists the programmable offset configuration settings.
Table 5. Programmable Offset Settings for the ASI Slot Start
P0_R8_D[4:0] : TX_OFFSET[4:0]
0 0000 = 0d (default)
PROGRAMMABLE OFFSET SETTING FOR SLOT DATA TRANSMISSION START
The device follows the standard protocol timing without any offset.
Slot start is offset by one BCLK cycle, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by one BCLK cycle, as compared to
standard protocol timing.
0 0001 = 1d
......
......
1 1110 = 30d
Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 30 BCLK cycles, as compared to
standard protocol timing.
1 1111 = 31d
Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing.
For I2S or LJ, the left and right slot start is offset by 31 BCLK cycles, as compared to
standard protocol timing.
The device also features the ability to invert the polarity of the frame sync pin, FSYNC, used to transfer the audio
data as compared to the default FSYNC polarity used in standard protocol timing. This feature can be set using
the FSYNC_POL, P0_R7_D3 register bit. Similarly, the device can invert the polarity of the bit clock pin, BCLK,
which can be set using the BCLK_POL, P0_R7_D2 register bit.
8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data
first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and
each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.
Figure 24 to Figure 27 illustrate the protocol timing for TDM operation with various configurations.
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FSYNC
BCLK
SDOUT
N-1
N-2
N-3
2
1
0
N-1
N-2
N-3
2
1
0
N-1
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
N-2
N-3
2
1
0
N-1
N-2
Slot-2 to Slot-7
(Word Length : N)
N-3
2
1
0
Slot-0
(Word Length : N)
nth Sample
(n+1)th Sample
Figure 24. TDM Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
2
1
0
N-1
N-2
2
1
0
N-1
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
TX_OFFSET = 2
N-3
N-2
N-3
2
1
0
N-1
2
1
0
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
TX_OFFSET = 2
nth Sample
(n+1)th Sample
Figure 25. TDM Mode Protocol Timing (TX_OFFSET = 2)
FSYNC
BCLK
SDOUT
1
0
N-1
2
1
0
N-1
N-2
N-3
2
1
0
N-1
N-2
N-3
0
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
N-1
N-2
3
2
1
0
N-1
TX_OFFSET = 2
2
1
0
Slot-0
(Word Length : N)
Slot-2 to Slot-7
(Word Length : N)
nth Sample
(n+1)th Sample
Figure 26. TDM Mode Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 2)
FSYNC
BCLK
SDOUT
N-1
N-2
N-3
2
1
0
N-1
N-2
N-3
2
1
Slot-1
(Word Length : N)
Slot-0
(Word Length : N)
0
N-1
N-2
N-3
2
1
0
N-1
Slot-2 to Slot-7
(Word Length : N)
N-2
N-3
2
1
0
Slot-0
(Word Length : N)
nth Sample
(n+1)th Sample
Figure 27. TDM Mode Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels times the programmed word length of the output channel data.
The device supports FSYNC as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well. For a
higher BCLK frequency operation, using TDM mode with a TX_OFFSET value higher than 0 is recommended.
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8.3.1.2.2 Inter IC Sound (I2S) Interface
The standard I2S protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In I2S mode, the MSB of the left slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the falling edge of FSYNC. Immediately after the left slot 0 data transmission, the
remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted on the falling edge of
BCLK in the second cycle after the rising edge of FSYNC. Immediately after the right slot 0 data transmission,
the remaining right slot data are transmitted in order. FSYNC and each data bit is transmitted on the falling edge
of BCLK. Figure 28 to Figure 31 show the protocol timing for I2S operation with various configurations.
FSYNC
BCLK
SDOUT
N-1
N-2
1
0
Left
Slot-0
(Word Length : N)
N-1
N-2
1
0
1
N-1
Left
Slot-2 to Slot-3
(Word Length : N)
0
N-1
Right
Slot-0
(Word Length : N)
N-2
1
N-1
0
Right
Slot-2 to Slot-3
(Word Length : N)
N-2
1
0
Left
Slot-0
(Word Length : N)
nth Sample
(n+1)th Sample
Figure 28. I2S Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
1
0
Left
Slot-0
TX_OFFSET = 1 (Word Length : N)
N-1
N-2
1
0
Left
Slot-2 to Slot-3
(Word Length : N)
1
N-1
0
N-1
1
N-1
0
1
0
Right
Right
Left
Slot-0
Slot-2 to Slot-3
Slot-0
TX_OFFSET = 1 (Word Length : N) (Word Length : N) TX_OFFSET = 1 (Word Length : N)
nth Sample
(n+1)th Sample
Figure 29. I2S Protocol Timing (TX_OFFSET = 1)
FSYNC
BCLK
SDOUT
0
N-1
N-2
1
0
N-1
N-2
0
N-1
1
0
N-1
1
Left
Slot-1 to Slot-3
(Word Length : N)
0
N-1
N-2
0
N-1
1
0
N-1
N-2
1
0
Left
Slot-0
(Word Length : N)
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
(n+1)th Sample
Figure 30. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
N-2
1
0
Left
Slot-0
(Word Length : N)
N-1
N-2
1
0
N-1
Left
Slot-2 to Slot-3
(Word Length : N)
1
0
Right
Slot-0
(Word Length : N)
N-1
N-2
1
0
Right
Slot-2 to Slot-3
(Word Length : N)
nth Sample
N-1
N-2
1
0
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Figure 31. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)
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For proper operation of the audio bus in I2S mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC high
pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots
times the data word length configured.
8.3.1.2.3 Left-Justified (LJ) Interface
The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol
timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle
after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK.
Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB
of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data
bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining
right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. Figure 32 to Figure 35
illustrate the protocol timing for LJ operation with various configurations.
FSYNC
BCLK
SDOUT
N-1
N-2
1
0
Left
Slot-0
(Word Length : N)
N-1
N-2
1
0
1
N-1
Left
Slot-2 to Slot-3
(Word Length : N)
0
N-1
Right
Slot-0
(Word Length : N)
N-2
1
N-1
0
Right
Slot-2 to Slot-3
(Word Length : N)
1
N-2
0
Left
Slot-0
(Word Length : N)
nth Sample
(n+1)th Sample
Figure 32. LJ Mode Standard Protocol Timing (TX_OFFSET = 0)
FSYNC
BCLK
SDOUT
N-1
1
0
Left
Slot-0
TX_OFFSET = 2 (Word Length : N)
N-1
N-2
1
0
Left
Slot-2 to Slot-3
(Word Length : N)
1
N-1
TX_OFFSET = 2
0
N-1
1
1
N-1
0
0
Right
Right
Left
Slot-0
Slot-2 to Slot-3
Slot-0
(Word Length : N) (Word Length : N) TX_OFFSET = 2 (Word Length : N)
nth Sample
(n+1)th Sample
Figure 33. LJ Protocol Timing (TX_OFFSET = 2)
FSYNC
BCLK
SDOUT
0
N-1
N-2
1
0
N-1
N-2
0
N-1
1
Left
Slot-1 to Slot-3
(Word Length : N)
0
N-1
1
0
N-1
N-2
0
N-1
1
Right
Slot-1 to Slot-3
(Word Length : N)
nth Sample
0
N-1
1
N-2
0
Left
Slot-0
(Word Length : N)
(n+1)th Sample
Figure 34. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
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FSYNC
BCLK
SDOUT
N-1
N-2
1
0
Left
Slot-0
TX_OFFSET = 1 (Word Length : N)
N-1
N-2
1
0
1
N-1
0
N-1
Left
Right
Slot-2 to Slot-3
Slot-0
(Word Length : N) TX_OFFSET = 1 (Word Length : N)
nth Sample
N-2
1
N-1
0
N-2
1
0
Right
Left
Slot-2 to Slot-3
Slot-0
(Word Length : N) TX_OFFSET = 1 (Word Length : N)
(n+1)th Sample
Figure 35. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)
For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or
equal to the number of active output channels (including left and right slots) times the programmed word length
of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater
than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low
pulse must be number of BCLK cycles wide that is greater than or equal to the number of active right slots times
the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET
value higher than 0 is recommended.
8.3.1.3 Using Multiple Devices With Shared Buses
The device has many supported features and flexible options that can be used in the system to seamlessly
connect multiple PCM6xx0-Q1 devices by sharing a single common I2C control bus and an audio serial interface
bus. This architecture enables multiple applications to be applied to a system that require a microphone array for
beam-forming operation, hands-free in-vehicle communication, car cabin active noise cancellation, and so forth.
Figure 36 shows a diagram of multiple PCM6xx0-Q1 devices in a configuration where the control and audio data
buses are shared.
Control Bus ± I2C Interface
PCM6xx0-Q1
PCM6xx0-Q1
PCM6xx0-Q1
PCM6xx0-Q1
U1
U2
U3
U4
Host Processor
Audio Data Bus ± TDM, I2S, LJ Interface
Figure 36. Multiple PCM6xx0-Q1 Devices With Shared Control and Audio Data Buses
The PCM6xx0-Q1 consist of the following features to enable seamless connection and interaction of multiple
devices using a shared bus:
• Supports up to four pin-programmable I2C slave addresses
• I2C broadcast simultaneously writes to (or triggers) all PCM6xx0-Q1 devices
• Supports up to 64 configuration output channel slots for the audio serial interface
• Tri-state feature (with enable and disable) for the unused audio data slots of the device
• Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
• The GPIOx pin can be configured as a secondary output data lane for the audio serial interface
• The GPIOx or GPIx pin can be used in a daisy-chain configuration of multiple PCM6xx0-Q1 devices
• Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
• Programmable master and slave options for the audio serial interface
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• Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices
See the Multiple PCM6xx0-Q1 Devices With Shared TDM and I2C Bus application report for further details.
8.3.2 Phase-Locked Loop (PLL) and Clock Generation
The device has a smart auto-configuration block to generate all necessary internal clocks required for the ADC
modulator and the digital filter engine used for signal processing. This configuration is done by monitoring the
frequency of the FSYNC and BCLK signal on the audio bus.
The device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to
FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.
Table 6 and Table 7 list the supported FSYNC and BCLK frequencies.
Table 6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC
(192 kHz)
FSYNC
(384 kHz)
FSYNC
(768 kHz)
16
Reserved
0.256
0.384
0.512
0.768
1.536
3.072
6.144
12.288
24
Reserved
0.384
0.576
0.768
1.152
2.304
4.608
9.216
18.432
32
0.256
0.512
0.768
1.024
1.536
3.072
6.144
12.288
24.576
48
0.384
0.768
1.152
1.536
2.304
4.608
9.216
18.432
Reserved
64
0.512
1.024
1.536
2.048
3.072
6.144
12.288
24.576
Reserved
96
0.768
1.536
2.304
3.072
4.608
9.216
18.432
Reserved
Reserved
128
1.024
2.048
3.072
4.096
6.144
12.288
24.576
Reserved
Reserved
192
1.536
3.072
4.608
6.144
9.216
18.432
Reserved
Reserved
Reserved
256
2.048
4.096
6.144
8.192
12.288
24.576
Reserved
Reserved
Reserved
384
3.072
6.144
9.216
12.288
18.432
Reserved
Reserved
Reserved
Reserved
512
4.096
8.192
12.288
16.384
24.576
Reserved
Reserved
Reserved
Reserved
1024
8.192
16.384
24.576
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2048
16.384
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK (MHz)
BCLK TO
FSYNC
RATIO
FSYNC
(7.35 kHz)
FSYNC
(14.7 kHz)
FSYNC
(22.05 kHz)
FSYNC
(29.4 kHz)
FSYNC
(44.1 kHz)
FSYNC
(88.2 kHz)
FSYNC
(176.4 kHz)
FSYNC
(352.8 kHz)
FSYNC
(705.6 kHz)
16
Reserved
Reserved
0.3528
0.4704
0.7056
1.4112
2.8224
5.6448
11.2896
24
Reserved
0.3528
0.5292
0.7056
1.0584
2.1168
4.2336
8.4672
16.9344
32
Reserved
0.4704
0.7056
0.9408
1.4112
2.8224
5.6448
11.2896
22.5792
48
0.3528
0.7056
1.0584
1.4112
2.1168
4.2336
8.4672
16.9344
Reserved
64
0.4704
0.9408
1.4112
1.8816
2.8224
5.6448
11.2896
22.5792
Reserved
96
0.7056
1.4112
2.1168
2.8224
4.2336
8.4672
16.9344
Reserved
Reserved
128
0.9408
1.8816
2.8224
3.7632
5.6448
11.2896
22.5792
Reserved
Reserved
192
1.4112
2.8224
4.2336
5.6448
8.4672
16.9344
Reserved
Reserved
Reserved
256
1.8816
3.7632
5.6448
7.5264
11.2896
22.5792
Reserved
Reserved
Reserved
384
2.8224
5.6448
8.4672
11.2896
16.9344
Reserved
Reserved
Reserved
Reserved
512
3.7632
7.5264
11.2896
15.0528
22.5792
Reserved
Reserved
Reserved
Reserved
1024
7.5264
15.0528
22.5792
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2048
15.0528
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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The status register ASI_STS, P0_R21, captures the device auto detect result for the FSYNC frequency and the
BCLK to FSYNC ratio. If the device finds any unsupported combinations of FSYNC frequency and BCLK to
FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly.
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
ADC modulator and digital filter engine, as well as other control blocks. The device also supports an option to
use the BCLK, GPIOx, or the GPIx pin (as MCLK) as the audio clock source without using the PLL to reduce
power consumption. However, the ADC performance may degrade based on jitter from the external clock source,
and some processing features may not be supported if the external audio clock source frequency is not high
enough. Therefore, TI recommends using the PLL for high-performance applications.
The device also supports an audio bus master mode operation using the GPIOx or GPIx pin (as MCLK) as the
reference input clock source and supports various flexible options and a wide variety of system clocks. More
details and information on master mode configuration and operation are discussed in the Configuring and
Operating TLV320ADCx140 as Audio Bus Master application report.
The audio bus clock error detection and auto-detect feature automatically generates all internal clocks, but can
be disabled using the ASI_ERR, P0_R9_D5 and AUTO_CLK_CFG, P0_R19_D6, register bits, respectively. In
the system, this disable feature can be used to support custom clock frequencies that are not covered by the
auto detect scheme. For such application use cases, care must be taken to ensure that the multiple clock
dividers are all configured appropriately. Therefore, TI recommends using the PPC3 GUI for device configuration
settings; for more details see the PCM6xx0Q1EVM-PDK Evaluation Module user's guide and the PurePath™
Console Graphical Development Suite for Audio System Design and Development development suite.
8.3.3 Input Channel Configuration
The PCM6x60-Q1 consist of six pairs and the PCM6x40-Q1 consist of four pairs of analog input pins (INxP and
INxM) that can be configured as either differential or single-ended inputs for the recording channel. These
devices support simultaneous recording of up to six channels in the PCM6x60-Q1 and four channels in the
PCM6x40-Q1 using the multichannel ADC. The input source for the analog pins can be either analog
microphones or line, aux inputs from the system board. Table 8 describes how to set the input configuration for
the record channel.
Table 8. Input Source Selection for the Record Channel
P0_R60_D[6:5] :
CH1_INSRC[1:0]
00 (default)
01
10 or 11
INPUT CHANNEL 1 RECORD SOURCE SELECTION
Analog differential input for channel 1
Analog single-ended input for channel 1
Reserved (do not use this setting)
Similarly, the input source selection setting for input channel 2 to channel 6 can be configured using the
CH2_INSRC[1:0] (P0_R65_D[6:5]) to CH6_INSRC[1:0] (P0_R85_D[6:5]) registers bits, respectively.
The device supports the input DC fault diagnostic feature for microphone recording with the DC-coupled inputs
configuration; however, the device also supports an option for AC-coupled inputs if the DC diagnostic is not
required for the specific input pins. This configuration can be done independently for each channel by setting the
CH1_DC (P0_R60_D4) to CH6_DC (P0_R85_D4) register bits.
For the DC-coupled line input configuration, the DC common-mode difference (INxP – INxM) for the analog input
pins must be 0 V to support the 10-VRMS full-scale differential input. For the DC-coupled microphone input
configuration, the DC common-mode difference (INxP – INxM) for the analog input pins must be within 3.4 V to
5.0 V to support the 2-VRMS full-scale differential input in the default mode of operation. Alternatively, the device
has a mode to support more than a 2-VRMS differential DC-coupled microphone signal by setting the
CH1_MIC_IN_RANGE, P0_R60_D3, register bit for channel 1 and, similarly, the CH2_MIC_IN_RANGE,
P0_R65_D3 to CH6_MIC_IN_RANGE, P0_R85_D3 registers bit (respectively) for channels 2 to 6. If the
CH1_MIC_IN_RANGE bit is set high (the recommended setting to support a higher DC common-mode difference
and a higher AC signal swing), then the device supports the maximum differential input voltage IN1P–IN1M as
high as 8.4 V (for the MICBIAS 9-V setting), including the AC signal and DC differential common-mode voltage.
The DC differential common-mode voltage is later filtered out by the digital high-pass filter and the digital output
full-scale corresponds to the 10-VRMS AC signal in this case.
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Figure 37 and Figure 38 show how to connect a DC-coupled microphone for a differential and single-ended input,
respectively. The value of the external bias resistor, R1, must be appropriately chosen based upon the
microphone impedance. For a differential input, the value of the external bias resistor is recommended to be
used for half of the microphone impedance, whereas for a single-ended input, the external bias resistor is
recommended to be the same as the microphone impedance.
MICBIAS
1 …F
R1
PCM6xx0-Q1
GND
DC-Coupled
Microphone
Differential Input
INxP
INxM
R1
GND
Figure 37. DC-Coupled Microphone Differential Input Connection
MICBIAS
1 …F
R1
PCM6xx0-Q1
GND
DC-Coupled
Microphone
Single-ended Input
INxP
INxM
GND
Figure 38. DC-Coupled Microphone Single-Ended Input Connection
In AC-coupled mode, the value of the coupling capacitor must be so chosen that the high-pass filter formed by
the coupling capacitor and the input impedance do not affect the signal content. At power-up, before proper
recording can begin, this coupling capacitor must be charged up to the common-mode voltage. For single-ended
input configuration, the INxM pin must be grounded after the AC coupling capacitor in AC-coupled mode.
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Figure 39 and Figure 40 show how to connect an AC-coupled microphone or line source for a differential and
single-ended input, respectively. In AC-coupled mode, the device input pins INxP and INxM, must be biased
appropriately for the DC common-mode value either using the on-chip MICBIAS output voltage along with
external bias resistor, R0, or using an external bias generator circuit. The maximum value for resistor R0
depends upon the signal swing and the MICBIAS value programmed. See the PCM6xx0-Q1 AC Coupled
External Resistor Calculator to calculate the R0 value for the desired system configuration.
MICBIAS
1 …F
R0
R0
PCM6xx0-Q1
GND
C0 …F
INxP
AC-Coupled
Microphone or Line
Differential Input
INxM
C0 …F
Figure 39. AC-Coupled Microphone or Line Differential Input Connection
MICBIAS
1 …F
R0
R0
PCM6xx0-Q1
C0 …F
GND
INxP
AC-Coupled
Microphone or Line
Single-ended Input
INxM
C0 …F
GND
Figure 40. AC-Coupled Microphone or Line Single-Ended Input Connection
8.3.4 Reference Voltage
All audio data converters require a DC reference voltage. The PCM6xx0-Q1 family achieves its low-noise
performance by internally generating a low-noise reference voltage. This reference voltage is generated using a
band-gap circuit with good PSRR performance. This audio converter reference voltage must be filtered externally
using a minimum 1-µF capacitor connected from the VREF pin to the analog ground (AVSS).
To achieve low power consumption, this audio reference block is powered down in sleep mode or software
shutdown; see the Sleep Mode or Software Shutdown section for more details. When exiting sleep mode, the
audio reference block is powered up using internal fast-charge scheme and the VREF pin settles to its steadystate voltage after the settling time (a function of the decoupling capacitor on the VREF pin). This time is
approximately equal to 3.5 ms when using a 1-μF decoupling capacitor. If a higher value of the decoupling
capacitor is used on the VREF pin, the fast-charge setting must be reconfigured using the VREF_QCHG,
P0_R2_D[4:3] register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or 100 ms.
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8.3.5 Microphone Bias
The device integrates a built-in, low-noise, programmable, high-voltage, microphone bias pin (MICBIAS) that can
be used in the system for biasing the analog microphone. The integrated bias amplifier supports up to 80 mA of
load current, which can be used for multiple microphones and is designed to provide a combination of high
PSRR, low noise, and programmable bias voltages to allow the biasing to be fine tuned for specific microphone
combinations. The PCM62x0-Q1 have an integrated efficient boost converter to generate the high voltage supply
for the programmable microphone bias using an external, low-voltage, 3.3-V BSTVDD supply. However, The
PCM63x0-Q1 require an external high-voltage supply, HVDD, which requires at least 600 mV higher than the
programmed microphone bias voltage and must be lower than 12 V.
When using the MICBIAS pin for biasing multiple microphones, TI recommends avoiding common impedance on
the board layout for the MICBIAS connection to minimize coupling across microphones. Table 9 shows the
available microphone bias programmable options.
Table 9. MICBIAS Programmable Settings
P0_R59_D[7:4] : MBIAS_VAL[3:0]
0000 to 0110
MICBIAS OUTPUT VOLTAGE
Reserved (do not use these settings)
0111
Set to 5.0 V
1000
Set to 5.5 V
1001
Set to 6.0 V
1010
Set to 6.5 V
1011
Set to 7.0 V
1100
Set to 7.5 V
1101
Set to 8.0 V
1110
Set to 8.5 V
1111
Set to 9.0 V
The microphone bias output can be powered on or powered off (default) by configuring the MICBIAS_PDZ,
P0_R117_D7 register bit. Additionally, the device provides an option to configure the GPIOx pins to directly
control the microphone bias output power on or power off. This feature is useful in some systems to control the
microphone directly without engaging the host for I2C or SPI communication. The MICBIAS_PDZ, P0_R117_D7
register bit value is ignored if the GPIOx pins are configured to control the microphone bias power on or power
off.
8.3.6 Input DC Fault Diagnostics
Each input of the PCM6xx0-Q1 features highly comprehensive DC fault diagnostics that can be configured to
detect fault conditions in the DC-coupled input configuration and trigger an interrupt request to a host processor.
Diagnostics are enabled for each channel by configuring DIAG_CFG0, P0_R100. For channels with diagnostics
enabled, the input pins are scanned automatically by an integrated SAR ADC with a programmable repetition
rate. The repetition rate can be configured using the REP_RATE, P0_R103_D7-6, register bits. For fastest fault
response time and also to get better signal integrity and signal chain performance for the record channel,
REP_RATE must be configured to 0 (non-default setting) . The diagnostic processor averages eight consecutive
samples per test to improve noise performance. The DC fault diagnostics is not supported in the AC-coupled
input configuration.
The device features various programmable threshold registers, P0_R101 to P0_R102, which can by configured
by the host processor to define the fault region for a different category of fault condition detection. Additionally,
there is also a debounce feature, configured with FAULT_DBNCE_SEL, P0_R103_D3-2. This feature sets the
number of consecutive scan counts where the fault condition occurs before the latched status register is tripped,
thus reducing false triggers by transient events. The device also has a moving average feature, P0_R104, which
continuously averages out the newly measured data with old measured data and thus reduces the false triggers
by any short-duration transient events.
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8.3.6.1 Fault Conditions
8.3.6.1.1 Input Pin Short to Ground
A short to ground fault occurs when the voltage of the input pin is measured below the threshold voltage with
respect to ground (AVSS). The threshold can be set by configuring DIAG_SHT_GND, P0_R102_D7-4.
8.3.6.1.2 Input Pin Short to MICBIAS
A short to MICBIAS fault occurs when the difference between the voltage measured for the MICBIAS pin and the
input pin (MICBIAS – INxx) is less than the threshold. The threshold can be set by configuring
DIAG_SHT_MICBIAS, P0_R102_D3-0.
8.3.6.1.3 Open Inputs
In the event that a microphone becomes disconnected from the inputs, the microphone bias resistors pull INxP to
MICBIAS and INxM to ground. The combination of INxP shorted to MICBIAS and INxM shorted to ground for the
same channel in a diagnostic sweep results in an open input fault condition.
8.3.6.1.4 Short Between INxP and INxM
An input terminal shorted fault occurs when the difference between the voltage measured for the input pin INxP
and the input pin INxM of the same channel is less than the threshold. The threshold can be set by configuring
DIAG_SHT_TERM, P0_R101_D7-4.
8.3.6.1.5 Input Pin Overvoltage
An input terminal overvoltage fault occurs when the voltage measured for the input pin is above the voltage
measured for the MICBIAS pin.
8.3.6.1.6 Input Pin Short to VBAT_IN
A short to VBAT_IN fault occurs when the difference between the voltage measured for the VBAT_IN pin and the
input pin, ABS(VBAT_IN – INxx), is less than the threshold or both the VBAT_IN and INxx pin measured voltages
are above 11.7 V. The threshold can be set by configuring DIAG_SHT_VBAT_IN, P0_R101_D3-0.
When VBAT_IN is less than MICBIAS, false fault detections can exist based on the signal level of the INxx pin.
To minimize false detections there is also a separate debounce count for this condition set by configuring
VSHORT_DBNCE, P0_R106_D1.
8.3.6.2 Fault Reporting
Faults are reported in live and latched status registers. The live registers, P1_R45 to P1_R55, are updated
continuously with each new scan and report the most recent measurements reported by the diagnostics
processor. The latched status of each diagnostic fault is reported by the channel in P0_R46 to P0_R55, and a
latched summary by the channel is reported in CHx_LTCH, P0_R45. If LTCH_CLR_ON_READ, P0_R40_D0, is
set to '0', then the latched registers clear upon reading and are latched if the associated bit in the live fault
registers transitions from a ‘0’ to a ‘1’. A transition of any bit in the latched register from a ‘0’ to ‘1’ triggers an
interrupt request.
For detecting a persistent fault, an additional mode is available for the latched registers. In this mode, the latched
registers are only cleared upon reading if the status bit in the associated live status register is ‘0’ at the time of
reading. This mode is enabled (default setting) by configuring LTCH_CLR_ON_READ, P0_R40_D0 to a ‘1’.
8.3.6.2.1 Overcurrent and Overtemperature Protection
The device has an overcurrent protection circuit that limits the current drawn out of the MICBIAS output to the
maximum supported level when an external undesired short event occurs on the MICBIAS pin. The device sets
the status flag, P0_R44_D4 bit, on an overcurrent detection. Additionally, the device has an overtemperature
detection circuit that is enabled by default and sets the status flag, P0_R44_D5 bit, whenever the die junction
temperature goes higher than the supported level.
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Additionally, the P0_R58 and P0_R40_D4:3 register can be configured to shutdown MICBIAS along with the onchip boost on an overtemperature detection. TI recommends configuring PD_ON_FLT_CFG, P0_R40_D4-3 to
"10" so that on an overtemperature detection, the device powers-down MICBIAS, the on-chip boost, and all ADC
channels.
More details and information on fault diagnostics are discussed in the PCM6xx0-Q1 Fault Diagnostics Features
application report.
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8.3.7 Signal-Chain Processing
The PCM6xx0-Q1 signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks
and highly flexible and programmable digital processing blocks. The high performance and flexibility combined
with a compact package makes the PCM6xx0-Q1 optimized for a variety of end-equipment and applications that
require multichannel audio capture. Figure 41 shows a conceptual block diagram that highlights the various
building blocks used in the signal chain, and how the blocks interact in the signal chain.
INxP
INxM
Input
Attenuator
HPF
PGA
Gain
Calibration
ADC
Digital Summer/Mixer
(Applies to Ch1-Ch4
only)
Phase
Calibration
Decimation
Filters
Biquad
Filters
Digital Volume
Control (DVC)
Output
Channel
Data to ASI
Ch1-Ch4 Processed Data after Gain
Calibration
Figure 41. Signal-Chain Processing Flowchart
The front-end input attenuator allows the device to accept the high-voltage input signal that is attenuated by the
input attenuator circuit before being routed to a low-noise programmable gain amplifier (PGA). Along with a lownoise and low-distortion, multibit, delta-sigma ADC, the front-end PGA enables the PCM6xx0-Q1 to record a farfield audio signal with very high fidelity, both in quiet and loud environments. Moreover, the ADC architecture has
inherent antialias filtering with a high rejection of out-of-band frequency noise around multiple modulator
frequency components. Therefore, the device prevents noise from aliasing into the audio band during ADC
sampling. Further on in the signal chain, an integrated, high-performance multistage digital decimation filter
sharply cuts off any out-of-band frequency noise with high stop-band attenuation.
The device also has an integrated programmable biquad filter that allows for custom low-pass, high-pass, or any
other desired frequency shaping. Thus, the overall signal chain architecture removes the requirement to add
external components for antialiasing low-pass filtering, and thus saves drastically on the external system
component cost and board space. See the PCM6xx0-Q1 Integrated Analog Antialiasing Filter and Flexible Digital
Filter application report for further details.
The signal chain also consists of various highly programmable digital processing blocks, such as phase
calibration, gain calibration, high-pass filter, digital summer or mixer, biquad filters, and volume control. The
details on these processing blocks are discussed further in this section.
The desired input channels for recording can be enabled or disabled by using the IN_CH_EN (P0_R115)
register, and the output channels for the audio serial interface can be enabled or disabled by using the
ASI_OUT_EN (P0_R116) register. In general, the device supports simultaneous power-up and power-down of all
active channels for simultaneous recording. However, based on the application needs, if some channels must be
powered-up or powered-down dynamically when the other channel recording is on, then that use case is
supported by setting the DYN_CH_PUPD_EN, P0_R117_D4 register bit to 1'b1 but do not power-down channel
1 in this mode of operation.
The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal to
be recorded by using a 176.4-kHz (or higher) sample rate.
For output sample rates of 48 kHz or lower, the device supports all features for 6-channel recording and various
programmable processing blocks. However, for output sample rates higher than 48 kHz, there are limitations in
the number of simultaneous channel recordings supported and the number of biquad filters and such. See the
PCM6xx0-Q1 Sampling Rates and Programmable Processing Blocks Supported application report for further
details.
8.3.7.1 Programmable Channel Gain and Digital Volume Control
The device has an independent programmable channel gain setting for each input channel that can be set to the
appropriate value based on the maximum input signal expected in the system and the ADC VREF setting used
(see the Reference Voltage section), which determines the ADC full-scale signal level.
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Configure the desired channel gain setting before powering up the ADC channel and do not change this setting
while the ADC is powered on. The programmable range supported for each channel gain is from 0 dB to 42 dB in
steps of 1 dB. To achieve low-noise performance, the device internal logic first maximizes the gain for the frontend low-noise analog PGA, and then applies any residual programmed channel gain in the digital processing
block.
Table 10 shows the programmable options available for the channel gain.
Table 10. Channel Gain Programmable Settings
P0_R61_D[7:2] : CH1_GAIN[5:0]
CHANNEL GAIN SETTING FOR INPUT CHANNEL 1
00 0000 = 0d (default)
Input channel 1 gain is set to 0 dB
00 0001 = 1d
Input channel 1 gain is set to 1 dB
00 0010 = 2d
Input channel 1 gain is set to 2 dB
…
…
10 1001 = 41d
Input channel 1 gain is set to 41 dB
10 1010 = 42d
Input channel 1 gain is set to 42 dB
10 1011 to 11 1111 = 43d to 63d
Reserved (do not use these settings)
Similarly, the channel gain setting for input channel 2 to channel 6 can be configured using the CH2_GAIN
(P0_R66) to CH6_GAIN (P0_R86) register bits, respectively.
The device also has a programmable digital volume control with a range from –100 dB to 27 dB in steps of
0.5 dB with the option to mute the channel recording. The digital volume control value can be changed
dynamically while the ADC channel is powered-up and recording. During volume control changes, the soft rampup or ramp-down volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely
disabled using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
The digital volume control setting is independently available for each output channel, including the digital
microphone record channel. However, the device also supports an option to gang-up the volume control setting
for all channels together using the channel 1 digital volume control setting, regardless if channel 1 is powered up
or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit.
Table 11 shows the programmable options available for the digital volume control.
Table 11. Digital Volume Control (DVC) Programmable Settings
P0_R62_D[7:0] : CH1_DVOL[7:0]
DVC SETTING FOR OUTPUT CHANNEL 1
0000 0000 = 0d
Output channel 1 DVC is set to mute
0000 0001 = 1d
Output channel 1 DVC is set to –100 dB
0000 0010 = 2d
Output channel 1 DVC is set to –99.5 dB
0000 0011 = 3d
Output channel 1 DVC is set to –99 dB
…
…
1100 1000 = 200d
1100 1001 = 201d (default)
1100 1010 = 202d
…
Output channel 1 DVC is set to –0.5 dB
Output channel 1 DVC is set to 0 dB
Output channel 1 DVC is set to 0.5 dB
…
1111 1101 = 253d
Output channel 1 DVC is set to 26 dB
1111 1110 = 254d
Output channel 1 DVC is set to 26.5 dB
1111 1111 = 255d
Output channel 1 DVC is set to 27 dB
Similarly, the digital volume control setting for output channel 2 to channel 6 can be configured using the
CH2_DVOL (P0_R67) to CH6_DVOL (P0_R87) register bits, respectively.
The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume
level when the channel is powered up, and the internal digital processing engine soft ramps down the volume
from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to
prevent abruptly powering up and powering down the record channel. This feature can also be entirely disabled
using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
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8.3.7.2 Programmable Channel Gain Calibration
Along with the programmable channel gain and digital volume, this device also provides programmable channel
gain calibration. The gain of each channel can be finely calibrated or adjusted in steps of 0.1 dB for a range of
–0.8-dB to 0.7-dB gain error. This adjustment is useful when trying to match the gain across channels resulting
from external components and microphone sensitivity. This feature, in combination with the regular digital volume
control, allows the gains across all channels to be matched for a wide gain error range with a resolution of
0.1 dB. Table 12 shows the programmable options available for the channel gain calibration.
Table 12. Channel Gain Calibration Programmable Settings
P0_R63_D[7:4] : CH1_GCAL[3:0]
CHANNEL GAIN CALIBRATION SETTING FOR INPUT CHANNEL 1
0000 = 0d
Input channel 1 gain calibration is set to –0.8 dB
0001 = 1d
Input channel 1 gain calibration is set to –0.7 dB
…
…
1000 = 8d (default)
…
Input channel 1 gain calibration is set to 0 dB
…
1110 = 14d
Input channel 1 gain calibration is set to 0.6 dB
1111 = 15d
Input channel 1 gain calibration is set to 0.7 dB
Similarly, the channel gain calibration setting for input channel 2 to channel 6 can be configured using the
CH2_GCAL (P0_R68) to CH6_GCAL (P0_R88) register bits, respectively.
8.3.7.3 Programmable Channel Phase Calibration
In addition to the gain calibration, the phase delay in each channel can be finely calibrated or adjusted in steps of
one modulator clock cycle for a cycle range of 0 to 255 for the phase error. The modulator clock, the same clock
used for ADC_MOD_CLK, is 6.144 MHz (the output data sample rate is multiples or submultiples of 48 kHz) or
5.6448 MHz (the output data sample rate is multiples or submultiples of 44.1 kHz). This feature is very useful for
many applications that must match the phase with fine resolution between each channel, including any phase
mismatch across channels resulting from external components or microphones. Table 13 shows the available
programmable options for channel phase calibration.
Table 13. Channel Phase Calibration Programmable Settings
P0_R64_D[7:0] : CH1_PCAL[7:0]
0000 0000 = 0d (default)
CHANNEL PHASE CALIBRATION SETTING FOR INPUT CHANNEL 1
Input channel 1 phase calibration with no delay
0000 0001 = 1d
Input channel 1 phase calibration delay is set to one cycle of the modulator clock
0000 0010 = 2d
Input channel 1 phase calibration delay is set to two cycles of the modulator clock
…
…
1111 1110 = 254d
Input channel 1 phase calibration delay is set to 254 cycles of the modulator clock
1111 1111 = 255d
Input channel 1 phase calibration delay is set to 255 cycles of the modulator clock
Similarly, the channel phase calibration setting for input channel 2 to channel 6 can be configured using the
CH2_PCAL (P0_R69) to CH6_PCAL (P0_R89) register bits, respectively.
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8.3.7.4 Programmable Digital High-Pass Filter
To remove the DC offset component and attenuate the undesired low-frequency noise content in the record data,
the device supports a programmable high-pass filter (HPF). The HPF is not a channel-independent filter setting
but is globally applicable for all ADC channels. This HPF is constructed using the first-order infinite impulse
response (IIR) filter, and is efficient enough to filter out possible DC components of the signal. Table 14 shows
the predefined –3-dB cutoff frequencies available that can be set by using the HPF_SEL[1:0] register bits of
P0_R107. Additionally, to achieve a custom –3-dB cutoff frequency for a specific application, the device also
allows the first-order IIR filter coefficients to be programmed when the HPF_SEL[1:0] register bits are set to
2'b00. Figure 42 shows a frequency response plot for the HPF filter.
Table 14. HPF Programmable Settings
-3-dB CUTOFF FREQUENCY
SETTING
-3-dB CUTOFF FREQUENCY AT
16-kHz SAMPLE RATE
-3-dB CUTOFF FREQUENCY AT
48-kHz SAMPLE RATE
00
Programmable 1st-order IIR filter
Programmable 1st-order IIR filter
Programmable 1st-order IIR filter
01 (default)
0.00025 × fS
4 Hz
12 Hz
10
0.002 × fS
32 Hz
96 Hz
11
0.008 × fS
128 Hz
384 Hz
Magnitude (dB)
P0_R107_D[1:0] :
HPF_SEL[1:0]
3
0
-3
-6
-9
-12
-15
-18
-21
-24
-27
-30
-33
-36
-39
-42
-45
5E-5
HPF -3 dB Cutoff = 0.00025 u fS
HPF -3 dB Cutoff = 0.002 u fS
HPF -3 dB Cutoff = 0.008 u fS
0.0001
0.0005
0.001
Normalized Frequency (1/fS)
0.005
0.01
0.05
D003
Figure 42. HPF Filter Frequency Response Plot
Equation 1 gives the transfer function for the first-order programable IIR filter:
00 + 01 V F1
:
;
* V = 31
2 F &1 V F1
(1)
The frequency response for this first-order programmable IIR filter with default coefficients is flat at a gain of 0 dB
(all-pass filter). The host device can override the frequency response by programming the IIR coefficients in
Table 15 to achieve the desired frequency response for high-pass filtering or any other desired filtering. If
HPF_SEL[1:0] are set to 2'b00, the host device must write these coefficients values for the desired frequency
response before powering-up any ADC channel for recording. These programmable coefficients are 32-bit, two’s
complement numbers. Table 15 shows the filter coefficients for the first-order IIR filter.
Table 15. 1st-Order IIR Filter Coefficients
FILTER
Programmable 1st-order IIR filter (can be
allocated to HPF or any other desired filter)
Copyright © 2020, Texas Instruments Incorporated
FILTER
COEFFICIENT
DEFAULT COEFFICIENT
VALUE
COEFFICIENT REGISTER
MAPPING
N0
0x7FFFFFFF
P4_R72-R75
N1
0x00000000
P4_R76-R79
D1
0x00000000
P4_R80-R83
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8.3.7.5 Programmable Digital Biquad Filters
The device supports up to 12 programmable digital biquad filters. These highly efficient filters achieve the desired
frequence response. In digital signal processing, a digital biquad filter is a second-order, recursive linear filter
with two poles and two zeros. Equation 2 gives the transfer function of each biquad filter:
00 + 201 V F1 + 02 V F2
* :V; = 31
2 F 2&1 V F1 F &2 V F2
(2)
The frequency response for the biquad filter section with default coefficients is flat at a gain of 0 dB (all-pass
filter). The host device can override the frequency response by programming the biquad coefficients to achieve
the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The
programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers: Page =
0x02 and Programmable Coefficient Registers: Page = 0x03 sections. If biquad filtering is required, then the host
device must write these coefficients values before powering up any ADC channels for recording. These
programmable coefficients are 32-bit, two’s complement numbers. As described in Table 16, these biquad filters
can be allocated for each output channel based on the BIQUAD_CFG[1:0] register setting of P0_R108. By
setting BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all record channels is disabled and the host device
can choose this setting if no additional filtering is required for the system application. See the PCM6xx0-Q1
Programmable Biquad Filter Configuration and Applications application report for further details.
Table 16. Biquad Filter Allocation to the Record Output Channel
RECORD OUTPUT CHANNEL ALLOCATION USING P0_R108_D[6:5] REGISTER SETTING
PROGRAMMABLE
BIQUAD FILTER
BIQUAD_CFG[1:0] = 2'b01
(1 Biquad per Channel)
BIQUAD_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)
BIQUAD_CFG[1:0] = 2'b11
(3 Biquads per Channel)
SUPPORTS ALL 8 CHANNELS
SUPPORTS UP TO 6 CHANNELS
SUPPORTS UP TO 4 CHANNELS
Biquad filter 1
Allocated to output channel 1
Allocated to output channel 1
Allocated to output channel 1
Biquad filter 2
Allocated to output channel 2
Allocated to output channel 2
Allocated to output channel 2
Biquad filter 3
Allocated to output channel 3
Allocated to output channel 3
Allocated to output channel 3
Biquad filter 4
Allocated to output channel 4
Allocated to output channel 4
Allocated to output channel 4
Biquad filter 5
Not used
Allocated to output channel 1
Allocated to output channel 1
Biquad filter 6
Not used
Allocated to output channel 2
Allocated to output channel 2
Biquad filter 7
Not used
Allocated to output channel 3
Allocated to output channel 3
Biquad filter 8
Not used
Allocated to output channel 4
Allocated to output channel 4
Biquad filter 9
Allocated to output channel 5
Allocated to output channel 5
Allocated to output channel 1
Biquad filter 10
Allocated to output channel 6
Allocated to output channel 6
Allocated to output channel 2
Biquad filter 11
Not used
Allocated to output channel 5
Allocated to output channel 3
Biquad filter 12
Not used
Allocated to output channel 6
Allocated to output channel 4
Table 17 shows the biquad filter coefficients mapping to the register space.
Table 17. Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD
FILTER
BIQUAD FILTER COEFFICIENTS
REGISTER MAPPING
PROGRAMMABLE BIQUAD
FILTER
BIQUAD FILTER COEFFICIENTS
REGISTER MAPPING
Biquad filter 1
P2_R8-R27
Biquad filter 7
P3_R8-R27
Biquad filter 2
P2_R28-R47
Biquad filter 8
P3_R28-R47
Biquad filter 3
P2_R48-R67
Biquad filter 9
P3_R48-R67
Biquad filter 4
P2_R68-R87
Biquad filter 10
P3_R68-R87
Biquad filter 5
P2_R88-R107
Biquad filter 11
P3_R88-R107
Biquad filter 6
P2_R108-R127
Biquad filter 12
P3_R108-R127
46
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8.3.7.6 Programmable Channel Summer and Digital Mixer
For applications that require an even higher SNR than that supported for each channel, the device digital
summing mode can be used. In this mode, the digital record data are summed up across the channel with an
equal weightage factor, which helps in reducing the effective record noise. Table 18 lists the configuration
settings available for channel summing mode.
Table 18. Channel Summing Mode Programmable Settings
P0_R107_D[3:2] : CH_SUM[2:0]
00 (Default)
SNR AND DYNAMIC RANGE
BOOST
CHANNEL SUMMING MODE FOR INPUT CHANNELS
Channel summing mode is disabled
Not applicable
Output channel 1 = (input channel 1 + input channel 2) / 2
01
3-dB boost in SNR and dynamic
range
Output channel 2 = (input channel 1 + input channel 2) / 2
Output channel 3 = (input channel 3 + input channel 4) / 2
3-dB boost in SNR and dynamic
range
Output channel 4 = (input channel 3 + input channel 4) / 2
Output channel 1 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
10
Output channel 2 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
6-dB boost in SNR and dynamic
range
Output channel 3 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
Output channel 4 = (input channel 1 + input channel 2 + input
channel 3 + input channel 4) / 4
11
Reserved (do not use this setting)
Not applicable
The device additionally supports a fully programmable mixer feature that can mix the various input channels with
their custom programmable scale factor to generate the final output channels. The programmable mixer feature
is available only if CH_SUM[2:0] is set to 2'b00. The mixer function is only supported for input channel 1 to
channel 4. Figure 43 shows a block diagram that describes the mixer 1 operation to generate output channel 1.
The programmable coefficients for the mixer operation are located in the Programmable Coefficient Registers:
Page = 0x04 section. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format.
The value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero
data), and any values in between set the mixer attenuation computed using Equation 3. If the MSB is set to '1'
then the attenuation remains the same but the signal phase is inverted.
hex2dec (value) / 231
(3)
Input Channel-1
Processed Data
Attenuated by
MIX1_CH1
factor
Input Channel-2
Processed Data
Attenuated by
MIX1_CH2
factor
Input Channel-3
Processed Data
Attenuated by
MIX1_CH3
factor
Input Channel-4
Processed Data
Attenuated by
MIX1_CH4
factor
Output Channel-1
Routed to Bi-Quad
Filter
+
Figure 43. Programmable Digital Mixer Block Diagram
A similar mixer operation is performed by mixer 2, mixer 3, and mixer 4 to generate output channel 2, channel 3,
and channel 4, respectively.
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8.3.7.7 Configurable Digital Decimation Filters
The device record channel includes a high dynamic range, built-in digital decimation filter to process the
oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist
sampling rate as the FSYNC rate. The decimation filter can be chosen from three different types, depending on
the required frequency response, group delay, and phase linearity requirements for the target application. The
selection of the decimation filter option can be done by configuring the DECI_FILT, P0_R107_D[5:4] register bits.
Table 19 shows the configuration register setting for the decimation filter mode selection for the record channel.
Table 19. Decimation Filter Mode Selection for the Record Channel
P0_R107_D[5:4] : DECI_FILT[1:0]
DECIMATION FILTER MODE SELECTION
00 (default)
Linear phase filters are used for the decimation
01
Low-latency filters are used for the decimation
10
Ultra-low latency filters are used for the decimation
11
Reserved (do not use this setting)
8.3.7.7.1 Linear Phase Filters
The linear phase decimation filters are the default filters set by the device and can be used for all applications
that require a perfect linear phase with zero-phase deviation within the pass-band specification of the filter. The
filter performance specifications and various plots for all supported output sampling rates are listed in this
section.
8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
Figure 44 and Figure 45 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 8 kHz or 7.35 kHz. Table 20 lists the specifications for a decimation filter with an
8-kHz or 7.35-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
0.05
0.1
D001
Figure 44. Linear Phase Decimation Filter Magnitude
Response
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
0.5
D001
Figure 45. Linear Phase Decimation Filter Pass-Band
Ripple
Table 20. Linear Phase Decimation Filter Specifications
PARAMETER
Pass-band ripple
Stop-band attenuation
Group delay or latency
48
TEST CONDITIONS
MIN
Frequency range is 0 to 0.454 × fS
–0.05
Frequency range is 0.58 × fS to 4 × fS
72.7
Frequency range is 4 × fS onwards
81.2
Frequency range is 0 to 0.454 × fS
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TYP
MAX
UNIT
0.05
dB
dB
17.1
1/fS
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8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
Figure 46 and Figure 47 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 16 kHz or 14.7 kHz. Table 21 lists the specifications for a decimation filter with an
16-kHz or 14.7-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
0.05
0.1
D001
Figure 46. Linear Phase Decimation Filter Magnitude
Response
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
0.5
D001
Figure 47. Linear Phase Decimation Filter Pass-Band
Ripple
Table 21. Linear Phase Decimation Filter Specifications
PARAMETER
Pass-band ripple
Stop-band attenuation
Group delay or latency
TEST CONDITIONS
MIN
Frequency range is 0 to 0.454 × fS
–0.05
Frequency range is 0.58 × fS to 4 × fS
73.3
Frequency range is 4 × fS onwards
95.0
TYP
MAX
UNIT
0.05
dB
dB
Frequency range is 0 to 0.454 × fS
15.7
1/fS
8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
Figure 48 and Figure 49 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 24 kHz or 22.05 kHz. Table 22 lists the specifications for a decimation filter with an
24-kHz or 22.05-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
0.05
D001
Figure 48. Linear Phase Decimation Filter Magnitude
Response
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
0.5
D001
Figure 49. Linear Phase Decimation Filter Pass-Band
Ripple
Table 22. Linear Phase Decimation Filter Specifications
PARAMETER
Pass-band ripple
Stop-band attenuation
Group delay or latency
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
MIN
Frequency range is 0.58 × fS to 4 × fS
73.0
Frequency range is 4 × fS onwards
96.4
Frequency range is 0 to 0.454 × fS
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TYP
–0.05
MAX
UNIT
0.05
dB
dB
16.6
1/fS
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8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
Figure 50 and Figure 51 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 32 kHz or 29.4 kHz. Table 23 lists the specifications for a decimation filter with an
32-kHz or 29.4-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
0.05
0.1
D001
Figure 50. Linear Phase Decimation Filter Magnitude
Response
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
0.5
D001
Figure 51. Linear Phase Decimation Filter Pass-Band
Ripple
Table 23. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Pass-band ripple
MIN
Frequency range is 0 to 0.454 × fS
–0.05
Frequency range is 0.58 × fS to 4 × fS
Stop-band attenuation
MAX
UNIT
0.05
dB
73.7
Frequency range is 4 × fS onwards
Group delay or latency
TYP
dB
107.2
Frequency range is 0 to 0.454 × fS
16.9
1/fS
8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
Figure 52 and Figure 53 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 48 kHz or 44.1 kHz. Table 24 lists the specifications for a decimation filter with an
48-kHz or 44.1-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
D001
Figure 52. Linear Phase Decimation Filter Magnitude
Response
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
0.5
D001
Figure 53. Linear Phase Decimation Filter Pass-Band
Ripple
Table 24. Linear Phase Decimation Filter Specifications
PARAMETER
Pass-band ripple
Stop-band attenuation
Group delay or latency
50
TEST CONDITIONS
Frequency range is 0 to 0.454 × fS
MIN
Frequency range is 0.58 × fS to 4 × fS
73.8
Frequency range is 4 × fS onwards
98.1
Frequency range is 0 to 0.454 × fS
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TYP
–0.05
MAX
UNIT
0.05
dB
dB
17.1
1/fS
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8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
Figure 54 and Figure 55 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 96 kHz or 88.2 kHz. Table 25 lists the specifications for a decimation filter with an
96-kHz or 88.2-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
0.05
D001
Figure 54. Linear Phase Decimation Filter Magnitude
Response
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
0.5
D001
Figure 55. Linear Phase Decimation Filter Pass-Band
Ripple
Table 25. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Pass-band ripple
MIN
Frequency range is 0 to 0.454 × fS
Stop-band attenuation
Group delay or latency
TYP
–0.05
Frequency range is 0.58 × fS to 4 × fS
73.6
Frequency range is 4 × fS onwards
97.9
MAX
UNIT
0.05
dB
dB
Frequency range is 0 to 0.454 × fS
17.1
1/fS
8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
Figure 56 and Figure 57 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 192 kHz or 176.4 kHz. Table 26 lists the specifications for a decimation filter with an
192-kHz or 176.4-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
D001
Figure 56. Linear Phase Decimation Filter Magnitude
Response
0.05
0.1
0.15
0.2
0.25
0.3
Normalized Frequency (1/fS)
0.35
0.4
D001
Figure 57. Linear Phase Decimation Filter Pass-Band
Ripple
Table 26. Linear Phase Decimation Filter Specifications
PARAMETER
Pass-band ripple
Stop-band attenuation
Group delay or latency
TEST CONDITIONS
Frequency range is 0 to 0.3 × fS
Frequency range is 0.473 × fS to 4 × fS
Frequency range is 4 × fS onwards
Frequency range is 0 to 0.3 × fS
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MIN
TYP
–0.05
70.0
MAX
UNIT
0.05
dB
dB
111.0
11.9
1/fS
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8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
Figure 58 and Figure 59 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 384 kHz or 352.8 kHz. Table 27 lists the specifications for a decimation filter with an
384-kHz or 352.8-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
D001
Figure 58. Linear Phase Decimation Filter Magnitude
Response
0.05
0.1
0.15
0.2
Normalized Frequency (1/fS)
0.25
0.3
D001
Figure 59. Linear Phase Decimation Filter Pass-Band
Ripple
Table 27. Linear Phase Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
Pass-band ripple
MIN
Frequency range is 0 to 0.212 × fS
–0.05
Frequency range is 0.58 × fS to 4 × fS
Stop-band attenuation
MAX
UNIT
0.05
dB
70.0
Frequency range is 4 × fS onwards
Group delay or latency
TYP
dB
108.8
Frequency range is 0 to 0.212 × fS
7.2
1/fS
8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
Figure 60 and Figure 61 respectively show the magnitude response and the pass-band ripple for a decimation
filter with a sampling rate of 768 kHz or 705.6 kHz. Table 28 lists the specifications for a decimation filter with an
768-kHz or 705.6-kHz sampling rate.
10
0.5
0
0.4
-10
0.3
-30
Magnitude (dB)
Magnitude (dB)
-20
-40
-50
-60
-70
0.2
0.1
0
-0.1
-0.2
-80
-0.3
-90
-100
-0.4
-110
-0.5
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
0
D001
Figure 60. Linear Phase Decimation Filter Magnitude
Response
0.05
0.1
0.15
Normalized Frequency (1/fS)
0.2
D001
Figure 61. Linear Phase Decimation Filter Pass-Band
Ripple
Table 28. Linear Phase Decimation Filter Specifications
PARAMETER
Pass-band ripple
Stop-band attenuation
Group Delay or Latency
52
TEST CONDITIONS
Frequency range is 0 to 0.113 × fS
MIN
Frequency range is 0.58 × fS to 2 × fS
75.0
Frequency range is 2 × fS onwards
88.0
Frequency range is 0 to 0.113 × fS
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TYP
–0.05
MAX
UNIT
0.05
dB
dB
5.9
1/fS
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.3.7.7.2 Low-Latency Filters
For applications where low latency with minimal phase deviation (within the audio band) is critical, the lowlatency decimation filters on the PCM6xx0-Q1 can be used. The device supports these filters with a group delay
of approximately seven samples with an almost linear phase response within the 0.365 × fS frequency band. This
section provides the filter performance specifications and various plots for all supported output sampling rates for
the low-latency filters.
8.3.7.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
10
0.5
0.5
0
0.4
0.4
-10
0.3
0.3
0.2
0.2
0.1
0.1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-0.1
-70
-0.2
-0.2
-80
-0.3
-90
-0.4
-100
-0.5
-60
-0.3
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
0.1
4
Figure 62. Low-Latency Decimation Filter Magnitude
Response
D002
-0.4
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 62 shows the magnitude response and Figure 63 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. Table 29 lists the specifications for a decimation
filter with a 16-kHz or 14.7-kHz sampling rate.
-0.5
0.5
D002
Figure 63. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Table 29. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
0.05
dB
Frequency range is 0 to 0.451 × fS
Stop-band attenuation
Frequency range is 0.61 × fS onwards
Group delay or latency
Frequency range is 0 to 0.363 × fS
Group delay deviation
Frequency range is 0 to 0.363 × fS
–0.022
0.022
1/fS
Phase deviation
Frequency range is 0 to 0.363 × fS
–0.21
0.25
Degrees
Copyright © 2020, Texas Instruments Incorporated
–0.05
MAX
Pass-band ripple
87.3
dB
7.6
1/fS
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8.3.7.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
10
0.5
0.5
0
0.4
0.4
-10
0.3
0.3
0.2
0.2
0.1
0.1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-0.1
-70
-0.2
-0.2
-80
-0.3
-90
-0.4
-100
-0.5
-60
-0.3
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
0.1
4
-0.4
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 64 shows the magnitude response and Figure 65 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. Table 30 lists the specifications for a decimation
filter with a 24-kHz or 22.05-kHz sampling rate.
-0.5
0.5
D002
Figure 65. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 64. Low-Latency Decimation Filter Magnitude
Response
Table 30. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.01
MAX
UNIT
0.01
dB
Pass-band ripple
Frequency range is 0 to 0.459 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.365 × fS
Group delay deviation
Frequency range is 0 to 0.365 × fS
–0.026
0.026
1/fS
Phase deviation
Frequency range is 0 to 0.365 × fS
–0.26
0.30
Degrees
87.2
dB
7.5
1/fS
8.3.7.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
10
0.5
0.5
0
0.4
0.4
-10
0.3
0.3
0.2
0.2
0.1
0.1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
-0.1
-70
-0.2
-0.2
-80
-0.3
-90
-0.4
-100
-0.5
-60
-0.3
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
Figure 66. Low-Latency Decimation Filter Magnitude
Response
54
0
-0.1
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D002
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
-0.4
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 66 shows the magnitude response and Figure 67 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 31 lists the specifications for a decimation
filter with a 32-kHz or 29.4-kHz sampling rate.
-0.5
0.5
D002
Figure 67. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 31. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.04
MAX
UNIT
0.04
dB
Pass-band ripple
Frequency range is 0 to 0.457 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.368 × fS
Group delay deviation
Frequency range is 0 to 0.368 × fS
–0.026
0.026
1/fS
Phase deviation
Frequency range is 0 to 0.368 × fS
–0.26
0.31
Degrees
88.3
dB
8.7
1/fS
8.3.7.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
10
0.5
0.5
0
0.4
0.4
-10
0.3
0.3
0.2
0.2
0.1
0.1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-0.1
-70
-0.2
-0.2
-80
-0.3
-60
-90
-0.4
-100
-0.5
-0.3
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
4
Figure 68. Low-Latency Decimation Filter Magnitude
Response
D002
0.1
-0.4
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 68 shows the magnitude response and Figure 69 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 32 lists the specifications for a decimation
filter with a 48-kHz or 44.1-kHz sampling rate.
-0.5
0.5
D002
Figure 69. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Table 32. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.365 × fS
Group delay deviation
Frequency range is 0 to 0.365 × fS
–0.027
0.027
1/fS
Phase deviation
Frequency range is 0 to 0.365 × fS
–0.25
0.30
Degrees
Copyright © 2020, Texas Instruments Incorporated
–0.015
0.015
Pass-band ripple
86.4
dB
7.7
1/fS
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8.3.7.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
10
0.5
0.5
0
0.4
0.4
-10
0.3
0.3
0.2
0.2
0.1
0.1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-0.1
-70
-0.2
-0.2
-80
-0.3
-90
-0.4
-100
-0.5
-60
-0.3
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
0.1
4
-0.4
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 70 shows the magnitude response and Figure 71 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. Table 33 lists the specifications for a decimation
filter with a 96-kHz or 88.2-kHz sampling rate.
-0.5
0.5
D002
Figure 71. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D002
Figure 70. Low-Latency Decimation Filter Magnitude
Response
Table 33. Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.04
MAX
UNIT
0.04
dB
Pass-band ripple
Frequency range is 0 to 0.466 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.365 × fS
Group delay deviation
Frequency range is 0 to 0.365 × fS
–0.027
0.027
1/fS
Phase deviation
Frequency range is 0 to 0.365 × fS
–0.26
0.30
Degrees
86.3
dB
7.7
1/fS
8.3.7.7.2.6 Sampling Rate: 192 kHz or 176.4 kHz
10
0.5
0.5
0
0.4
0.4
-10
0.3
0.3
0.2
0.2
0.1
0.1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
-0.1
-70
-0.2
-0.2
-80
-0.3
-90
-0.4
-100
-0.5
-60
-0.3
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
Figure 72. Low-Latency Decimation Filter Magnitude
Response
56
0
-0.1
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D002
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
-0.4
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 72 shows the magnitude response and Figure 73 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. Table 34 lists the specifications for a decimation
filter with a 192-kHz or 176.4-kHz sampling rate.
-0.5
0.5
D002
Figure 73. Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 34. Low-Latency Decimation Filter Specifications
TEST CONDITIONS
MIN
Pass-band ripple
PARAMETER
Frequency range is 0 to 463 × fS
–0.03
TYP
MAX
UNIT
0.03
dB
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.365 × fS
Group delay deviation
Frequency range is 0 to 0.365 × fS
–0.027
0.027
1/fS
Phase deviation
Frequency range is 0 to 0.365 × fS
–0.26
0.30
Degrees
85.6
dB
7.7
1/fS
8.3.7.7.3 Ultra-Low-Latency Filters
For applications where ultra-low latency (within the audio band) is critical, the ultra-low-latency decimation filters
on the PCM6xx0-Q1 can be used. The device supports these filters with a group delay of approximately four
samples with an almost linear phase response within the 0.325 × fS frequency band. This section provides the
filter performance specifications and various plots for all supported output sampling rates for the ultra-low-latency
filters.
8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
10
0.5
25
0
0.4
20
-10
0.3
15
0.2
10
0.1
5
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-5
-70
-0.2
-10
-80
-0.3
-90
-0.4
-100
-0.5
-60
-15
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
0.1
4
D003
Figure 74. Ultra-Low-Latency Decimation Filter Magnitude
Response
-20
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 74 shows the magnitude response and Figure 75 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 16 kHz or 14.7 kHz. Table 35 lists the specifications for a decimation
filter with a 16-kHz or 14.7-kHz sampling rate.
-25
0.5
D003
Figure 75. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Table 35. Ultra-Low-Latency Decimation Filter Specifications
TEST CONDITIONS
MIN
Pass-band ripple
PARAMETER
Frequency range is 0 to 0.45 × fS
–0.05
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.325 × fS
Group delay deviation
Frequency range is 0 to 0.325 × fS
–0.512
0.512
1/fS
Phase deviation
Frequency range is 0 to 0.325 × fS
–10.0
14.2
Degrees
Copyright © 2020, Texas Instruments Incorporated
TYP
MAX
UNIT
0.05
dB
87.2
dB
4.3
1/fS
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8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
10
0.5
25
0
0.4
20
-10
0.3
15
0.2
10
0.1
5
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-5
-70
-0.2
-10
-80
-0.3
-90
-0.4
-100
-0.5
-60
-15
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
0.1
4
-20
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 76 shows the magnitude response and Figure 77 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 24 kHz or 22.05 kHz. Table 36 lists the specifications for a decimation
filter with a 24-kHz or 22.05-kHz sampling rate.
-25
0.5
D003
Figure 77. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
D003
Figure 76. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 36. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.01
MAX
UNIT
0.01
dB
Pass-band ripple
Frequency range is 0 to 0.46 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.325 × fS
Group delay deviation
Frequency range is 0 to 0.325 × fS
–0.514
0.514
1/fS
Phase deviation
Frequency range is 0 to 0.325 × fS
–10.0
14.3
Degrees
87.1
dB
4.1
1/fS
8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
10
0.5
25
0
0.4
20
-10
0.3
15
0.2
10
0.1
5
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
-0.1
-5
-70
-0.2
-10
-80
-0.3
-60
-90
-0.4
-100
-0.5
-15
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
D003
Figure 78. Ultra-Low-Latency Decimation Filter Magnitude
Response
58
0
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0.05
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
-20
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 78 shows the magnitude response and Figure 79 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 32 kHz or 29.4 kHz. Table 37 lists the specifications for a decimation
filter with an 32-kHz or 29.4-kHz sampling rate.
-25
0.5
D003
Figure 79. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Copyright © 2020, Texas Instruments Incorporated
Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 37. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.04
MAX
UNIT
0.04
dB
Pass-band ripple
Frequency range is 0 to 0.457 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.325 × fS
Group delay deviation
Frequency range is 0 to 0.325 × fS
–0.492
0.492
1/fS
Phase deviation
Frequency range is 0 to 0.325 × fS
–9.5
13.5
Degrees
88.3
dB
5.2
1/fS
8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
10
0.5
25
0
0.4
20
-10
0.3
15
0.2
10
0.1
5
0
0
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
-0.1
-5
-70
-0.2
-10
-80
-0.3
-90
-0.4
-100
-0.5
-60
-15
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
4
D003
Figure 80. Ultra-Low-Latency Decimation Filter Magnitude
Response
0.1
-20
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 80 shows the magnitude response and Figure 81 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 48 kHz or 44.1 kHz. Table 38 lists the specifications for a decimation
filter with a 48-kHz or 44.1-kHz sampling rate.
-25
0.5
D003
Figure 81. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Table 38. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
Frequency range is 0 to 0.452 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.325 × fS
Group delay deviation
Frequency range is 0 to 0.325 × fS
–0.525
0.525
1/fS
Phase deviation
Frequency range is 0 to 0.325 × fS
–10.3
14.5
Degrees
Copyright © 2020, Texas Instruments Incorporated
–0.015
0.015
Pass-band ripple
86.4
dB
4.1
1/fS
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8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
10
0.5
5
0
0.4
4
-10
0.3
3
0.2
2
0.1
1
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
-60
-70
-80
0
0
-0.1
-1
-0.2
-2
-0.3
-90
-3
Pass-Band Ripple
Phase Deviation
-0.4
-100
-4
-0.5
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0
4
D003
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 82 shows the magnitude response and Figure 83 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 96 kHz or 88.2 kHz. Table 39 lists the specifications for a decimation
filter with a 96-kHz or 88.2-kHz sampling rate.
-5
0.5
D003
Figure 83. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Figure 82. Ultra-Low-Latency Decimation Filter Magnitude
Response
Table 39. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.04
MAX
UNIT
0.04
dB
Pass-band ripple
Frequency range is 0 to 0.466 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.1625 × fS
Group delay deviation
Frequency range is 0 to 0.1625 × fS
–0.091
0.091
1/fS
Phase deviation
Frequency range is 0 to 0.1625 × fS
–0.86
1.30
Degrees
86.3
dB
3.7
1/fS
8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
10
0.5
5
0
0.4
4
-10
0.3
3
0.2
2
0.1
1
0
0
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
-60
-70
-80
-1
-0.2
-2
-0.3
-90
-3
Pass-Band Ripple
Phase Deviation
-0.4
-100
-4
-0.5
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
4
D003
Figure 84. Ultra-Low-Latency Decimation Filter Magnitude
Response
60
-0.1
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0
0.05
0.1
0.15 0.2 0.25 0.3 0.35
Normalized Frequency (1/fS)
0.4
0.45
Phase Deviation from Linear (Degree)
Figure 84 shows the magnitude response and Figure 85 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 192 kHz or 176.4 kHz. Table 40 lists the specifications for a decimation
filter with a 192-kHz or 176.4-kHz sampling rate.
-5
0.5
D003
Figure 85. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
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Table 40. Ultra-Low-Latency Decimation Filter Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
–0.03
MAX
UNIT
0.03
dB
Pass-band ripple
Frequency range is 0 to 0.463 × fS
Stop-band attenuation
Frequency range is 0.6 × fS onwards
Group delay or latency
Frequency range is 0 to 0.085 × fS
Group delay deviation
Frequency range is 0 to 0.085 × fS
–0.024
0.024
1/fS
Phase deviation
Frequency range is 0 to 0.085 × fS
–0.12
0.18
Degrees
85.6
dB
3.7
1/fS
8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
10
0.5
2
0
0.4
1.6
-10
0.3
1.2
0.2
0.8
0.1
0.4
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
0
0
-0.1
-0.4
-70
-0.2
-0.8
-80
-0.3
-60
-90
-0.4
-100
-0.5
-1.2
Pass-Band Ripple
Phase Deviation
0
-110
0
0.4
0.8
1.2 1.6
2
2.4 2.8
Normalized Frequency (1/fS)
3.2
3.6
0.05
4
D002
Figure 86. Ultra-Low-Latency Decimation Filter Magnitude
Response
-1.6
0.1
0.15
Normalized Frequency (1/fS)
0.2
Phase Deviation from Linear (Degree)
Figure 86 shows the magnitude response and Figure 87 shows the pass-band ripple and phase deviation for a
decimation filter with a sampling rate of 384 kHz or 352.8 kHz. Table 41 lists the specifications for a decimation
filter with a 384-kHz or 352.8-kHz sampling rate.
-2
0.25
D002
Figure 87. Ultra-Low-Latency Decimation Filter Pass-Band
Ripple and Phase Deviation
Table 41. Ultra-Low-Latency Decimation Filter Specifications
TEST CONDITIONS
MIN
Pass-band ripple
PARAMETER
Frequency range is 0 to 0.1 × fS
–0.04
Stop-band attenuation
Frequency range is 0.56 × fS onwards
Group delay or latency
Frequency range is 0 to 0.157 × fS
Group delay deviation
Frequency range is 0 to 0.157 × fS
–0.18
0.18
1/fS
Phase deviation
Frequency range is 0 to 0.157 × fS
–0.85
2.07
Degrees
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TYP
MAX
UNIT
0.01
dB
70.1
dB
4.1
1/fS
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8.3.8 Automatic Gain Controller (AGC)
The device includes an automatic gain controller (AGC) for ADC recording that must be used only for the ACcoupled input configuration. As shown in Figure 88, the AGC can be used to maintain a nominally constant
output level when recording speech. Instead of manually setting the channel gain in AGC mode, the circuitry
automatically adjusts the channel gain when the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer to or farther from the microphone. The AGC algorithm has
several programmable parameters, including target level, maximum gain allowed, attack and release (or decay)
time constants, and noise thresholds that allow the algorithm to be fine-tuned for any particular application.
Input
Signal
Output
Signal
Target
Level
AGC
Gain
Decay Time
Attack
Time
Figure 88. AGC Characteristics
The target level (AGC_LVL) represents the nominal output level at which the AGC attempts to hold the ADC
output signal level. The PCM6xx0-Q1 allows programming of different target levels, which can be programmed
from –6 dB to –36 dB relative to a full-scale signal, and the AGC_LVL default value is set to –34 dB. The target
level is recommended to be set with enough margin to prevent clipping when loud sounds occur. Table 42 lists
the AGC target level configuration settings.
Table 42. AGC Target Level Programmable Settings
P0_R112_D[7:4] : AGC_LVL[3:0]
The AGC target level is the –6-dB output signal level
0001
The AGC target level is the –8-dB output signal level
0010
The AGC target level is the –10-dB output signal level
…
62
AGC TARGET LEVEL FOR OUTPUT
0000
…
1110 (default)
The AGC target level is the –34-dB output signal level
1111
The AGC target level is the –36-dB output signal level
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The maximum gain allowed (AGC_MAXGAIN) gives flexibility to the designer to restrict the maximum gain
applied by the AGC. This feature limits the channel gain in situations where environmental noise is greater than
the programmed noise threshold. The AGC_MAXGAIN can be programmed from 3 dB to 42 dB with steps of 3
dB and the default value is set to 24 dB. Table 43 lists the AGC_MAXGAIN configuration settings.
Table 43. AGC Maximum Gain Programmable Settings
P0_R112_D[3:0] : AGC_MAXGAIN[3:0]
AGC MAXIMUM GAIN ALLOWED
0000
The AGC maximum gain allowed is 3 dB
0001
The AGC maximum gain allowed is 6 dB
0010
The AGC maximum gain allowed is 9 dB
…
…
0111 (default)
The AGC maximum gain allowed is 24 dB
…
…
1110
The AGC maximum gain allowed is 39 dB
1111
The AGC maximum gain allowed is 42 dB
For further details on the AGC various configurable parameter and application use, see the Using the Automatic
Gain Controller in PCM6xx0-Q1 application report.
8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
Certain events in the device may require host processor intervention and can be used to trigger interrupts to the
host processor. Such event are an audio serial interface (ASI) bus error and input DC fault diagnostic faults. The
device powers down the record channels if any faults are detected with the ASI bus error clocks, such as:
• Invalid FSYNC frequency
• Invalid SBCLK to FSYNC ratio
• Long pauses of the SBCLK or FSYNC clocks
When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After
all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record
channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the
clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for
readback in the live fault status register bit INT_LIVE0, P1_R44 as well as latched to the fault status register bit
INT_LTCH0, P0_R44, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears
all latched fault statuses. The device can be additionally configured to route the internal IRQ interrupt signal on
the GPIOx pins and also can be configured as an open-drain output so that these pins can be wire-ANDed to the
open-drain interrupt outputs of other devices.
When an input DC fault event is detected, the internal IRQ signal is asserted if the interrupt mask registers
INT_MASK1, P0_R42 and INT_MASK2, P0_R43 are configured appropriately to unmask all the desired fault
diagnostics interrupts. Each input channel can be independently set for an interrupt mask. Table 44 and Table 45
list the mask settings available for the input DC diagnostics fault interrupts.
Table 44. Interrupt Mask Register-1 for DC Faults Diagnostic
P0_R42 : INT_MASK1
INTERRUPT MASK REGISTER 1 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
INT_MASK1[7]
Channel 1 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[6]
Channel 2 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[5]
Channel 3 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[4]
Channel 4 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[3]
Channel 5 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[2]
Channel 6 input DC faults diagnostic interrupt mask and unmask register bit
INT_MASK1[1]
Short to VBAT_IN (when VBAT_IN is lower than MICBIAS) fault interrupt mask and unmask register
bit
INT_MASK1[0]
Reserved
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Table 45. Interrupt Mask Register-2 for DC Faults Diagnostic
P0_R43 : INT_MASK2
INTERRUPT MASK REGISTER 2 FOR DC FAULTS DIAGNOSTIC INTERRUPTS
INT_MASK2[7]
Open input fault interrupt mask and unmask register bit for all channels
INT_MASK2[6]
Inputs shorted each other fault interrupt mask and unmask register bit for all channels
INT_MASK2[5]
INxP input shorted to ground fault interrupt mask and unmask register bit for all channels
INT_MASK2[4]
INxM input shorted to ground fault interrupt mask and unmask register bit for all channels
INT_MASK2[3]
INxP input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INT_MASK2[2]
INxM input shorted to MICBIAS fault interrupt mask and unmask register bit for all channels
INT_MASK2[1]
INxP input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels
INT_MASK2[0]
INxM input shorted to VBAT_IN fault interrupt mask and unmask register bit for all channels
The device supports the channel-specific input DC fault latched status registers for all channels from CH1_LTCH,
P0_R46 to CH6_LTCH, P0_R51, which are read-only registers. The device also has a consolidated summary
status register across channels for the input DC latched fault status register, CHx_LTCH, P0_R45 that the host
can read to quickly know which channel fault has occurred. Reading the latched fault status registers,
CH1_LTCH to CH6_LTCH, clears all the latched fault status including the summary status register, CHx_LTCH.
Table 46 shows various input DC fault diagnostics status bits that are supported by the device.
Table 46. Input DC Faults Diagnostic Latched Status
P0_R46 : CH1_LTCH
CHANNEL 1 INPUT FAULTS DIAGNOSTIC LATCHED STATUS
CH1_LTCH[7]
Channel 1 open input fault detection status bit (self-clearing bit)
CH1_LTCH[6]
Channel 1 inputs shorted together fault detection status bit (self-clearing bit)
CH1_LTCH[5]
Channel 1 IN1P input shorted to ground fault detection status bit (self-clearing bit)
CH1_LTCH[4]
Channel 1 IN1M input shorted to ground fault detection status bit (self-clearing bit)
CH1_LTCH[3]
Channel 1 IN1P input shorted to MICBIAS fault detection status bit (self-clearing bit)
CH1_LTCH[2]
Channel 1 IN1M input shorted to MICBIAS fault detection status bit (self-clearing bit)
CH1_LTCH[1]
Channel 1 IN1P input shorted to VBAT_IN fault detection status bit (self-clearing bit)
CH1_LTCH[0]
Channel 1 IN1M input shorted to VBAT_IN fault detection status bit (self-clearing bit)
Similarly, the DC faults diagnostic latched status for input channel 2 to channel 6 can be monitored using the
CH2_LTCH (P0_R47) to CH6_LTCH (P0_R51) registers, respectively.
The device GPIOx pins can be additionally configured to route the internal IRQ interrupt signal on the GPIOx
pins and also can be configured as an open-drain output so that this pin can be wire-ANDed to the open-drain
interrupt outputs of other devices.
The IRQ interrupt signal can either be configured as an active low or active high polarity by setting the INT_POL,
P0_R40_D7 register bit. This signal can also be configured as a single pulse or a series of pulses by
programming the INT_EVENT[1:0], P0_R40_D[6:5] register bits. If the interrupts are configured as a series of
pulses, the events trigger the start of pulses that stop when the latched fault status register is read to determine
the cause of the interrupt.
The device also supports read-only live status registers that determine if all the channels are powered up or
down and if the device is in sleep mode or not. These status registers are located in P0_R118, DEV_STS0 and
P0_R119, DEV_STS1.
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The device has a GPIO1 multifunction pin that can be configured for a desired specific function. Additionally the
PCM6x40-Q1 has two more GPIO pins and two GPI pins supported that can be used in the system for various
other features. Table 47 shows all possible allocation of these multifunction pins for all the various features.
Table 47. Multifunction Pin Assignments
ROW
PIN FUNCTION
GPIO1
GPIO2
GPIO3
GPI1
GPI2
—
GPIO1_CFG
[4:0]
GPIO2_CFG
[4:0]
GPIO3_CFG
[4:0]
GPI1_CFG[4:0]
GPI2_CFG[4:0]
—
—
P0_R33[7:4]
P0_R34[7:4]
P0_R35[7:4]
P0_R36[7:4]
P0_R37[7:4]
A
Pin disabled
S (1)
S (default)
S (default)
S (default)
S (default)
—
(1)
(2)
NS
(2)
B
General-purpose output (GPO)
S
S
S
C
Interrupt output (IRQ)
S (default)
S
S
NS
NS
NS
D
Secondary ASI output (SDOUT2)
S
S
S
NS
NS
F
MiCBIAS on/off input (BIASEN)
S
S
S
S
S
G
General-purpose input (GPI)
S
S
S
S
S
H
Master clock input (MCLK)
S
S
S
S
S
I
ASI daisy-chain input (SDIN)
S
S
S
S
S
S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column.
Each GPIOx pin can be independently set for the desired drive configurations setting using the GPIOx_DRV[3:0]
register bits. Table 48 lists the drive configuration settings.
Table 48. GPIOx Pins Drive Configuration Settings
P0_R33_D[3:0] : GPIO1_DRV[3:0]
GPIO OUTPUT DRIVE CONFIGURATION SETTINGS FOR GPIO1
000
The GPIO1 pin is set to high impedance (floated)
001
The GPIO1 pin is set to be driven active low or active high
010 (default)
The GPIO1 pin is set to be driven active low or weak high (on-chip pullup)
011
The GPIO1 pin is set to be driven active low or Hi-Z (floated)
100
The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high
101
The GPIO1 pin is set to be driven Hi-Z (floated) or active high
110 and 111
Reserved (do not use these settings)
Similarly, the GPIO2 and GPIO3 pins can
GPIO3_DRV(P0_R35) register bits, respectively.
be
configured
using
the
GPIO2_DRV(P0_R34)
and
When configured as a general-purpose output (GPO), the GPIOx pin values can be driven by writing the
GPIO_VAL P0_R38 registers. The GPIO_MON, P0_R39 register can be used to readback the status of the
GPIOx and GPIx pins when configured as a general-purpose input (GPI).
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8.4 Device Functional Modes
8.4.1 Hardware Shutdown
The device enters hardware shutdown mode when the SHDNZ pin is asserted low or the AVDD supply voltage is
not applied to the device. In hardware shutdown mode, the device consumes the minimum quiescent current
from the AVDD supply. All configuration registers and programmable coefficients lose their value in this mode,
and I2C or SPI communication to the device is not supported.
If the SHDNZ pin is asserted low when the device is in active mode, the device ramps down volume on the
record data, powers down the analog and digital blocks, and puts the device into hardware shutdown mode in 25
ms (typical). The device can also be immediately put into hardware shutdown mode from active mode if the
SHDNZ_CFG[1:0], P0_R5_D[3:2], register bits are set to 2'b00. After the SHDNZ pin is asserted low, and after
the device enters hardware shutdown mode, keep the SHDNZ pin low for at least 1 ms before releasing SHDNZ
for further device operation.
Assert the SHDNZ pin high only when the IOVDD supply settles to a steady voltage level. When the SHDNZ pin
goes high, the device sets all configuration registers and programmable coefficients to their default values, and
then enters sleep mode.
8.4.2 Sleep Mode or Software Shutdown
In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD
supply and, at the same time, allows the I2C or SPI communication to wake the device for active operation.
The device can also enter sleep mode when the host device sets the SLEEP_ENZ, P0_R2_D0 bit to 1'b0. If the
SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the
record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still
continues to retain the last programmed value of the device configuration registers and programmable
coefficients.
In sleep mode, do not perform any I2C or SPI transactions, except for exiting sleep mode in order to enter active
mode. After entering sleep mode, wait at least 10 ms before starting I2C or SPI transactions to exit sleep mode.
8.4.3 Active Mode
If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In
active mode, I2C or SPI transactions can be done to configure and power-up the device for active operation.
After entering active mode, wait at least 1 ms before starting any I2C or SPI transactions in order to allow the
device to complete the internal wake-up sequence.
After configuring all other registers for the target application and system settings, configure the input and output
channel enable registers, P0_R115 (IN_CH_EN) and P0_R116 (ASI_OUT_CH_EN), respectively. Lastly,
configure the device power-up register, P0_R117 (PWR_CFG). All programmable coefficient values must be
written before powering up the respective channel.
In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only
device status bits located in the P0_R117 (DEV_STS0) and P0_R118 (DEV_STS1) registers.
8.4.4 Software Reset
A software reset can be done any time by asserting the SW_RESET bit, P0_R1_D0, which is a self-clearing bit.
This software reset immediately shuts down the device, and restores all device configuration registers and
programmable coefficients to their default values.
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8.5 Programming
The device contains configuration registers and programmable coefficients that can be set to the desired values
for a specific system and application use. These registers are called device control registers and are each eight
bits in width, mapped using a page scheme.
Each page contains 128 configuration registers. All device configuration registers are stored in page 0, which is
the default page setting at power up (and after a software reset). Page 1 consists of the live status registers and
input diagnostic successive-approximation register (SAR) data for advanced diagnostic purposes. All
programmable coefficient registers are located in page 2, page 3, and page 4. The current page of the device
can be switched to a new desired page by using the PAGE[7:0] bits located in register 0 of every page.
8.5.1 Control Serial Interfaces
The device control registers can be accessed using either I2C or SPI communication to the device.
By monitoring the SDA_SSZ, SCL_MOSI, ADDR0_SCLK, and ADDR1_MISO device pins, which are the
multiplexed pins for the I2C or SPI Interface, the device automatically detects whether the host device is using
I2C or SPI communication to configure the device. For a given end application, the host device must always use
either the I2C or SPI interface, but not both, to configure the device.
8.5.1.1 I2C Control Interface
The device supports the I2C control protocol as a slave device, and is capable of operating in standard mode,
fast mode, and fast mode plus. The I2C control protocol requires a 7-bit slave address. The five most significant
bits (MSBs) of the slave address are fixed at 10010 and cannot be changed. The two least significant bits (LSBs)
are programmable and are controlled by the ADDR0_SCLK and ADDR1_MISO pins. These two pins must
always be either pulled to VSS or IOVDD. If the I2C_BRDCAST_EN (P0_R2_D2) bit is set to 1'b1, then the I2C
slave address is fixed to 1001000 in order to allow simultaneous I2C broadcast communication to all PCM6xx0Q1 devices in the system. Table 49 lists the four possible device addresses resulting from this configuration.
Table 49. I2C Slave Address Settings
ADDR1_MISO
ADDR0_SCLK
I2C_BRDCAST_EN (P0_R2_D2)
I2C SLAVE ADDRESS
0
0
0 (default)
1001 000
0
1
0 (default)
1001 001
1
0
0 (default)
1001 010
1
1
0 (default)
1001 011
X
X
1
1001 000
8.5.1.1.1 General I2C Operation
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between the integrated circuits in
a system using serial data transmission. The address and data 8-bit bytes are transferred MSB first. In addition,
each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a START condition on the bus and ends with the master device
driving a STOP condition on the bus. The bus uses transitions on the data pin (SDA) when the clock is at logic
high to indicate START and STOP conditions. A high-to-low transition on SDA indicates a START, and a low-tohigh transition indicates a STOP condition. Normal data-bit transitions must occur within the low time of the clock
period.
The master device drives a START condition followed by the 7-bit slave address and the read/write (R/W) bit to
open communication with another device and then waits for an acknowledgment condition. The slave device
holds SDA low during the acknowledge clock period to indicate acknowledgment. When this step occurs, the
master device transmits the next byte of the sequence. Each slave device is addressed by a unique 7-bit slave
address plus the R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a
wired-AND connection.
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There is no limit on the number of bytes that can be transmitted between START and STOP conditions. When
the last word transfers, the master device generates a STOP condition to release the bus. Figure 89 shows a
generic data transfer sequence.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 89. Typical I2C Sequence
In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus.
The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.
8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
The device I2C interface supports both single-byte and multiple-byte read/write operations for all registers. During
multiple-byte read operations, the device responds with data, a byte at a time, starting at the register assigned,
as long as the master device continues to respond with acknowledges.
The device supports sequential I2C addressing. For write transactions, if a register is issued followed by data for
that register and all the remaining registers that follow, a sequential I2C write transaction takes place. For I2C
sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a STOP or START condition is transmitted, determines how many registers are
written.
8.5.1.1.2.1 I2C Single-Byte Write
As shown in Figure 90, a single-byte data write transfer begins with the master device transmitting a START
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C
slave address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the master
device transmits the register byte corresponding to the device internal register address being accessed. After
receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the master transmits
the byte of data to be written to the specified register. When finished, the slave device responds with an
acknowledge bit (ACK). Finally, the master device transmits a STOP condition to complete the single-byte data
write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
I2C Device Address and
Read/Write Bit
R/W ACK A7
Acknowledge
A6
A5
A4
A3
A2
A1
A0 ACK D7
Acknowledge
D6
Register
D5
D4
D3
Data Byte
D2
D1
D0 ACK
Stop
Condition
Figure 90. I2C Single-Byte Write Transfer
68
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8.5.1.1.2.2 I2C Multiple-Byte Write
As shown in Figure 91, a multiple-byte data write transfer is identical to a single-byte data write transfer except
that multiple data bytes are transmitted by the master device to the slave device. After receiving each data byte,
the device responds with an acknowledge bit (ACK). Finally, the master device transmits a STOP condition after
the last data-byte write transfer.
Register
Figure 91. I2C Multiple-Byte Write Transfer
8.5.1.1.2.3 I2C Single-Byte Read
As shown in Figure 92, a single-byte data read transfer begins with the master device transmitting a START
condition followed by the I2C slave address and the read/write bit. For the data read transfer, both a write
followed by a read are done. Initially, a write is done to transfer the address byte of the internal register address
to be read. As a result, the read/write bit is set to 0.
After receiving the slave address and the read/write bit, the device responds with an acknowledge bit (ACK). The
master device then sends the internal register address byte, after which the device issues an acknowledge bit
(ACK). The master device transmits another START condition followed by the slave address and the read/write
bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the device transmits the data
byte from the register address being read. After receiving the data byte, the master device transmits a notacknowledge (NACK) followed by a STOP condition to complete the single-byte data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
Acknowledge
A0 R/W ACK A7
A6
I2C Device Address and
Read/Write Bit
A5
A4
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
D6
I2C Device Address and
Read/Write Bit
Register
D1
D0 ACK
Stop
Condition
Data Byte
Figure 92. I2C Single-Byte Read Transfer
8.5.1.1.2.4 I2C Multiple-Byte Read
As shown in Figure 93, a multiple-byte data read transfer is identical to a single-byte data read transfer except
that multiple data bytes are transmitted by the device to the master device. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte. After receiving the last
data byte, the master device transmits a not-acknowledge (NACK) followed by a STOP condition to complete the
data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Register
A0 ACK
Acknowledge
A6
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Acknowledge
D0
First Data Byte
ACK D7
Acknowledge
Not
Acknowledge
D0 ACK D7
D0 ACK
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 93. I2C Multiple-Byte Read Transfer
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8.5.1.2 SPI Control Interface
The general SPI protocol allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
synchronizing clock (driven onto SCLK) and initiates transmissions by taking the slave-select pin SSZ from high
to low. The SPI slave devices (such as the PCM6xx0-Q1) depend on a master to start and synchronize
transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins
shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). When the byte
shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register.
The PCM6xx0-Q1 support a standard SPI control protocol with a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0) and a clock phase setting of 1 (typical microprocessor SPI control bit
CPHA = 1). The SSZ pin can remain low between transmissions; however, the device only interprets the first
eight bits transmitted after the falling edge of SSZ as a command byte, and the next eight bits as a data byte only
if writing to a register. The device is entirely controlled by registers. Reading and writing these registers is
accomplished by an 8-bit command sent to the MOSI pin prior to the data for that register. Table 50 shows the
command structure. The first seven bits specify the address of the register that is being written or read, from 0 to
127 (decimal). The command word ends with an R/W bit, which specifies the direction of data flow on the serial
bus.
In the case of a register write, set the R/W bit to 0. A second byte of data is sent to the MOSI pin and contains
the data to be written to the register. A register read is accomplished in a similar fashion. The 8-bit command
word sends the 7-bit register address, followed by the R/W bit equal to 1 to signify a register read. The 8-bit
register data is then clocked out of the device on the MISO pin during the second eight SCLK clocks in the
frame. The device supports sequential SPI addressing for a multiple-byte data write/read transfer until the SSZ
pin is pulled high. A multiple-byte data write or read transfer is identical to a single-byte data write or read
transfer, respectively, until all data byte transfers complete. The host device must keep the SSZ pin low during all
data byte transfers. Figure 94 shows the single-byte write transfer and Figure 95 illustrates the single-byte read
transfer.
Table 50. SPI Command Word
BIT 7
ADDR(6)
BIT 6
ADDR(5)
BIT 5
ADDR(4)
BIT 4
ADDR(3)
BIT 3
ADDR(2)
BIT 2
ADDR(1)
BIT 1
ADDR(0)
BIT 0
R/WZ
SS
SCLK
MOSI
Hi-Z
RA(6)
RA(5)
RA(0)
7-bit Register Address
MISO
D(7)
Write
D(6)
D(0)
Hi-Z
8-bit Register Data
Hi-Z
Hi-Z
Figure 94. SPI Single-Byte Write Transfer
SS
SCLK
MOSI
Hi-Z
RA(6)
RA(5)
7-bit Register Address
MISO
Hi-Z
RA(0)
Hi-Z
Don’t Care
Read
8-bit Register Data
D(7)
D(6)
D(0)
Hi-Z
Figure 95. SPI Single-Byte Read Transfer
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.6 Register Maps
This section describes the control registers for the device in detail. All registers are eight bits in width and are
allocated to the device configuration and programmable coefficients settings. These registers are mapped
internally using a page scheme that can be controlled using either I2C or SPI communication to the device. Each
page contains 128 bytes of registers. All device configuration registers are stored in page 0, which is the default
page setting at power up (and after a software reset). Page 1 consists of the live status registers and input
diagnostic SAR data for advanced diagnostic purposes. All programmable coefficient registers are located in
page 2, page 3, and page 4. The device current page can be switched to a new desired page by using the
PAGE[7:0] bits located in register 0 of every page.
Do not read from or write to reserved pages or reserved registers. Write only default values for the reserved bits
in the valid registers.
The procedure for register access across pages is:
• Select page N (write data N to register 0 regardless of the current page number)
• Read or write data from or to valid registers in page N
• Select the new page M (write data M to register 0 regardless of the current page number)
• Read or write data from or to valid registers in page M
• Repeat as needed
8.6.1 Device Configuration Registers
This section describes the device configuration registers for page 0 and page 1.
8.6.1.1 Register Summary Table Page=0x00
ADDRESS
REGISTER
DESCRIPTION
SECTION
0x00
PAGE_CFG
Device page register
0x01
SW_RESET
Software reset register
SW_RESET Register (P0_R1)
0x02
SLEEP_CFG
Sleep mode register
SLEEP_CFG Register (P0_R2)
0x05
SHDN_CFG
Shutdown configuration register
SHDN_CFG Register (P0_R5)
0x07
ASI_CFG0
ASI configuration register 0
ASI_CFG0 Register (P0_R7)
0x08
ASI_CFG1
ASI configuration register 1
ASI_CFG1 Register (P0_R8)
0x09
ASI_CFG2
ASI configuration register 2
ASI_CFG2 Register (P0_R9)
0x0B
ASI_CH1
Channel 1 ASI slot configuration register
ASI_CH1 Register (P0_R11)
0x0C
ASI_CH2
Channel 2 ASI slot configuration register
ASI_CH2 Register (P0_R12)
0x0D
ASI_CH3
Channel 3 ASI slot configuration register
ASI_CH3 Register (P0_R13)
0x0E
ASI_CH4
Channel 4 ASI slot configuration register
ASI_CH4 Register (P0_R14)
0x0F
ASI_CH5
Channel 5 ASI slot configuration register
ASI_CH5 Register (P0_R15)
0x10
ASI_CH6
Channel 6 ASI slot configuration register
ASI_CH6 Register (P0_R16)
0x13
MST_CFG0
ASI master mode configuration register 0
MST_CFG0 Register (P0_R19)
0x14
MST_CFG1
ASI master mode configuration register 1
MST_CFG1 Register (P0_R20)
0x15
ASI_STS
ASI bus clock monitor status register
ASI_STS Register (P0_R21)
0x16
CLK_SRC
Clock source configuration register
CLK_SRC Register (P0_R22)
0x21
GPIO_CFG0
GPIO configuration register 0
GPIO_CFG0 Register (P0_R33)
0x22
GPIO_CFG1
GPIO configuration register 1
GPIO_CFG1 Register (P0_R34)
0x23
GPIO_CFG2
GPIO configuration register 2
GPIO_CFG2 Register (P0_R35)
0x24
GPI_CFG0
GPI configuration register 0
GPI_CFG0 Register (P0_R36)
0x25
GPI_CFG1
GPI configuration register 1
GPI_CFG1 Register (P0_R37)
0x26
GPIO_VAL
GPIO output value register
GPIO_VAL Register (P0_R38)
0x27
GPIO_MON
GPIO monitor value register
GPIO_MON Register (P0_R39)
0x28
INT_CFG
Interrupt configuration register
0x29
INT_MASK0
Interrupt mask register 0
INT_MASK0 Register (P0_R41)
0x2A
INT_MASK1
Interrupt mask register 1
INT_MASK1 Register (P0_R42)
0x2B
INT_MASK2
Interrupt mask register 2
INT_MASK2 Register (P0_R43)
0x2C
INT_LTCH0
Latched interrupt readback register 0
INT_LTCH0 Register (P0_R44)
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PAGE_CFG Register (P0_R0)
INT_CFG Register (P0_R40)
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Register Maps (continued)
72
0x2D
CHx_LTCH
Channel diagnostic summary latched status register
CHx_LTCH Register (P0_R45)
0x2E
CH1_LTCH
Channel 1 diagnostic latched status register
CH1_LTCH Register (P0_R46)
0x2F
CH2_LTCH
Channel 2 diagnostic latched status register
CH2_LTCH Register (P0_R47)
0x30
CH3_LTCH
Channel 3 diagnostic latched status register
CH3_LTCH Register (P0_R48)
0x31
CH4_LTCH
Channel 4 diagnostic latched status register
CH4_LTCH Register (P0_R49)
0x32
CH5_LTCH
Channel 5 diagnostic latched status register
CH5_LTCH Register (P0_R50)
0x33
CH6_LTCH
Channel 6 diagnostic latched status register
CH6_LTCH Register (P0_R51)
0x34
INT_MASK3
Interrupt mask register 3
INT_MASK3 Register (P0_R52)
0x35
INT_LTCH1
Latched interrupt readback register 1
INT_LTCH1 Register (P0_R53)
0x36
INT_LTCH2
Latched interrupt readback register 2
INT_LTCH2 Register (P0_R54)
0x37
INT_LTCH3
Latched interrupt readback register 3
0x38
MBDIAG_CFG0
MICBIAS diagnostic register 0
MBDIAG_CFG0 Register (P0_R56)
INT_LTCH3 Register (P0_R55)
0x39
MBDIAG_CFG1
MICBIAS diagnostic register 1
MBDIAG_CFG1 Register (P0_R57)
0x3A
MBDIAG_CFG2
MICBIAS diagnostic register 2
MBDIAG_CFG2 Register (P0_R58)
0x3B
BIAS_CFG
Bias configuration register
BIAS_CFG Register (P0_R59)
0x3C
CH1_CFG0
Channel 1 configuration register 0
CH1_CFG0 Register (P0_R60)
0x3D
CH1_CFG1
Channel 1 configuration register 1
CH1_CFG1 Register (P0_R61)
0x3E
CH1_CFG2
Channel 1 configuration register 2
CH1_CFG2 Register (P0_R62)
0x3F
CH1_CFG3
Channel 1 configuration register 3
CH1_CFG3 Register (P0_R63)
0x40
CH1_CFG4
Channel 1 configuration register 4
CH1_CFG4 Register (P0_R64)
0x41
CH2_CFG0
Channel 2 configuration register 0
CH2_CFG0 Register (P0_R65)
0x42
CH2_CFG1
Channel 2 configuration register 1
CH2_CFG1 Register (P0_R66)
0x43
CH2_CFG2
Channel 2 configuration register 2
CH2_CFG2 Register (P0_R67)
0x44
CH2_CFG3
Channel 2 configuration register 3
CH2_CFG3 Register (P0_R68)
0x45
CH2_CFG4
Channel 2 configuration register 4
CH2_CFG4 Register (P0_R69)
0x46
CH3_CFG0
Channel 3 configuration register 0
CH3_CFG0 Register (P0_R70)
0x47
CH3_CFG1
Channel 3 configuration register 1
CH3_CFG1 Register (P0_R71)
0x48
CH3_CFG2
Channel 3 configuration register 2
CH3_CFG2 Register (P0_R72)
0x49
CH3_CFG3
Channel 3 configuration register 3
CH3_CFG3 Register (P0_R73)
0x4A
CH3_CFG4
Channel 3 configuration register 4
CH3_CFG4 Register (P0_R74)
0x4B
CH4_CFG0
Channel 4 configuration register 0
CH4_CFG0 Register (P0_R75)
0x4C
CH4_CFG1
Channel 4 configuration register 1
CH4_CFG1 Register (P0_R76)
0x4D
CH4_CFG2
Channel 4 configuration register 2
CH4_CFG2 Register (P0_R77)
0x4E
CH4_CFG3
Channel 4 configuration register 3
CH4_CFG3 Register (P0_R78)
0x4F
CH4_CFG4
Channel 4 configuration register 4
CH4_CFG4 Register (P0_R79)
0x50
CH5_CFG0
Channel 5 configuration register 0
CH5_CFG0 Register (P0_R80)
0x51
CH5_CFG1
Channel 5 configuration register 1
CH5_CFG1 Register (P0_R81)
0x52
CH5_CFG2
Channel 5 configuration register 2
CH5_CFG2 Register (P0_R82)
0x53
CH5_CFG3
Channel 5 configuration register 3
CH5_CFG3 Register (P0_R83)
0x54
CH5_CFG4
Channel 5 configuration register 4
CH5_CFG4 Register (P0_R84)
0x55
CH6_CFG0
Channel 6 configuration register 0
CH6_CFG0 Register (P0_R85)
0x56
CH6_CFG1
Channel 6 configuration register 1
CH6_CFG1 Register (P0_R86)
0x57
CH6_CFG2
Channel 6 configuration register 2
CH6_CFG2 Register (P0_R87)
0x58
CH6_CFG3
Channel 6 configuration register 3
CH6_CFG3 Register (P0_R88)
0x59
CH6_CFG4
Channel 6 configuration register 4
0x64
DIAG_CFG0
Input diagnostic configuration register 0
DIAG_CFG0 Register (P0_R100)
0x65
DIAG_CFG1
Input diagnostic configuration register 1
DIAG_CFG1 Register (P0_R101)
0x66
DIAG_CFG2
Input diagnostic configuration register 2
DIAG_CFG2 Register (P0_R102)
0x67
DIAG_CFG3
Input diagnostic configuration register 3
DIAG_CFG3 Register (P0_R103)
0x68
DIAG_CFG4
Input diagnostic configuration register 4
DIAG_CFG4 Register (P0_R104)
0x6B
DSP_CFG0
DSP configuration register 0
DSP_CFG0 Register (P0_R107)
0x6C
DSP_CFG1
DSP configuration register 1
DSP_CFG1 Register (P0_R108)
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CH6_CFG4 Register (P0_R89)
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Register Maps (continued)
0x70
AGC_CFG0
AGC configuration register 0
AGC_CFG0 Register (P0_R112)
0x73
IN_CH_EN
Input channel enable configuration register
IN_CH_EN Register (P0_R115)
0x74
ASI_OUT_CH_EN
ASI output channel enable configuration register
0x75
PWR_CFG
Power up configuration register
PWR_CFG Register (P0_R117)
0x76
DEV_STS0
Device status value register 0
DEV_STS0 Register (P0_R118)
0x77
DEV_STS1
Device status value register 1
DEV_STS1 Register (P0_R119)
0x7E
I2C_CKSUM
I2C checksum register
I2C_CKSUM Register (P0_R126)
ASI_OUT_CH_EN Register (P0_R116)
8.6.1.2 Register Summary Table Page=0x01
ADDRESS
REGISTER
DESCRIPTION
SECTION
0x00
PAGE_CFG
Device page register
0x16
MBIAS_LOAD
MICBIAS internal load sink configuration register
0x2C
INT_LIVE0
Live interrupt readback register 0
0x2D
CHx_LIVE
Channel diagnostic summary live status register
CHx_LIVE Register (P1_R45)
0x2E
CH1_LIVE
Channel 1 diagnostic live status register
CH1_LIVE Register (P1_R46)
0x2F
CH2_LIVE
Channel 2 diagnostic live status register
CH2_LIVE Register (P1_R47)
0x30
CH3_LIVE
Channel 3 diagnostic live status register
CH3_LIVE Register (P1_R48)
0x31
CH4_LIVE
Channel 4 diagnostic live status register
CH4_LIVE Register (P1_R49)
0x32
CH5_LIVE
Channel 5 diagnostic live status register
CH5_LIVE Register (P1_R50)
0x33
CH6_LIVE
Channel 6 diagnostic live status register
CH6_LIVE Register (P1_R51)
0x35
INT_LIVE1
Live interrupt readback register 1
INT_LIVE1 Register (P1_R53)
0x37
INT_LIVE3
Live interrupt readback register 3
0x55
MBIAS_OV_CFG
MICBIAS overvoltage threshold register
0x59
DIAGDATA_CFG
Diagnostic data configuration register
0x5A
DIAG_MON_MSB_VBAT
Diagnostic VBAT_IN data MSB byte register
PAGE_CFG Register (P1_R0)
MBIAS_LOAD Register (P1_R22)
INT_LIVE0 Register (P1_R44)
INT_LIVE3 Register (P1_R55)
MBIAS_OV_CFG Register (P1_R85)
DIAGDATA_CFG Register (P1_R89)
DIAG_MON_MSB_VBAT Register (P1_R90)
0x5B
DIAG_MON_LSB_VBAT
Diagnostic VBAT_IN data LSB nibble register
DIAG_MON_LSB_VBAT Register (P1_R91)
0x5C
DIAG_MON_MSB_MBIAS
Diagnostic MICBIAS data MSB byte register
DIAG_MON_MSB_MBIAS Register (P1_R92)
0x5D
DIAG_MON_LSB_MBIAS
Diagnostic MICBIAS data LSB nibble register
DIAG_MON_LSB_MBIAS Register (P1_R93)
0x5E
DIAG_MON_MSB_IN1P
Diagnostic IN1P data MSB byte register
DIAG_MON_MSB_IN1P Register (P1_R94)
0x5F
DIAG_MON_LSB_IN1P
Diagnostic IN1P data LSB nibble register
DIAG_MON_LSB_IN1P Register (P1_R95)
0x60
DIAG_MON_MSB_IN1M
Diagnostic IN1M data MSB byte register
DIAG_MON_MSB_IN1M Register (P1_R96)
0x61
DIAG_MON_LSB_IN1M
Diagnostic IN1M data LSB nibble register
DIAG_MON_LSB_IN1M Register (P1_R97)
0x62
DIAG_MON_MSB_IN2P
Diagnostic IN2P data MSB byte register
DIAG_MON_MSB_IN2P Register (P1_R98)
0x63
DIAG_MON_LSB_IN2P
Diagnostic IN2P data LSB nibble register
DIAG_MON_LSB_IN2P Register (P1_R99)
0x64
DIAG_MON_MSB_IN2M
Diagnostic IN2M data MSB byte register
DIAG_MON_MSB_IN2M Register (P1_R100)
0x65
DIAG_MON_LSB_IN2M
Diagnostic IN2M data LSB nibble register
DIAG_MON_LSB_IN2M Register (P1_R101)
0x66
DIAG_MON_MSB_IN3P
Diagnostic IN3P data MSB byte register
DIAG_MON_MSB_IN3P Register (P1_R102)
0x67
DIAG_MON_LSB_IN3P
Diagnostic IN3P data LSB nibble register
DIAG_MON_LSB_IN3P Register (P1_R103)
0x68
DIAG_MON_MSB_IN3M
Diagnostic IN3M data MSB byte register
DIAG_MON_MSB_IN3M Register (P1_R104)
0x69
DIAG_MON_LSB_IN3M
Diagnostic IN3M data LSB nibble register
DIAG_MON_LSB_IN3M Register (P1_R105)
0x6A
DIAG_MON_MSB_IN4P
Diagnostic IN4P data MSB byte register
DIAG_MON_MSB_IN4P Register (P1_R106)
0x6B
DIAG_MON_LSB_IN4P
Diagnostic IN4P data LSB nibble register
DIAG_MON_LSB_IN4P Register (P1_R107)
0x6C
DIAG_MON_MSB_IN4M
Diagnostic IN4M data MSB byte register
DIAG_MON_MSB_IN4M Register (P1_R108)
0x6D
DIAG_MON_LSB_IN4M
Diagnostic IN4M data LSB nibble register
DIAG_MON_LSB_IN4M Register (P1_R109)
0x6E
DIAG_MON_MSB_IN5P
Diagnostic IN5P data MSB byte register
DIAG_MON_MSB_IN5P Register (P1_R110)
0x6F
DIAG_MON_LSB_IN5P
Diagnostic IN5P data LSB nibble register
DIAG_MON_LSB_IN5P Register (P1_R111)
0x70
DIAG_MON_MSB_IN5M
Diagnostic IN5M data MSB byte register
DIAG_MON_MSB_IN5M Register (P1_R112)
0x71
DIAG_MON_LSB_IN5M
Diagnostic IN5M data LSB nibble register
DIAG_MON_LSB_IN5M Register (P1_R113)
0x72
DIAG_MON_MSB_IN6P
Diagnostic IN6P data MSB byte register
DIAG_MON_MSB_IN6P Register (P1_R114)
0x73
DIAG_MON_LSB_IN6P
Diagnostic IN6P data LSB nibble register
DIAG_MON_LSB_IN6P Register (P1_R115)
0x74
DIAG_MON_MSB_IN6M
Diagnostic IN6M data MSB byte register
DIAG_MON_MSB_IN6M Register (P1_R116)
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0x75
DIAG_MON_LSB_IN6M
Diagnostic IN6M data LSB nibble register
0x76
DIAG_MON_MSB_TEMP
Diagnostic temperature data MSB byte register
DIAG_MON_LSB_IN6M Register (P1_R117)
0x77
DIAG_MON_LSB_TEMP
Diagnostic temperature data LSB nibble register
DIAG_MON_LSB_TEMP Register (P1_R119)
0x78
DIAG_MON_MSB_LOAD
Diagnostic MICBIAS load current data MSB byte register
DIAG_MON_MSB_LOAD Register (P1_R120)
0x79
DIAG_MON_LSB_LOAD
Diagnostic MICBIAS load current data LSB nibble register
DIAG_MON_LSB_LOAD Register (P1_R121)
DIAG_MON_MSB_TEMP Register (P1_R118)
Table 51 lists the access codes used for the PCM6xx0-Q1 registers.
Table 51. PCM6xx0-Q1 Access Type Codes
Access Type
Code
Description
R
R
Read
R-W
R/W
Read or write
W
Write
Read Type
Write Type
W
Reset or Default Value
-n
Value after reset or the default value
8.6.1.3 Register Description: Page = 0x00
8.6.1.3.1 PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
The device memory map is divided into pages. This register sets the page.
Figure 96. PAGE_CFG Register
7
6
5
4
3
2
1
0
PAGE[7:0]
R/W-0h
Table 52. PAGE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
R/W
0h
These bits set the device page.
0d = Page 0
1d = Page 1
...
255d = Page 255
8.6.1.3.2 SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
This register is the software reset register. Asserting a software reset places all register values in their default
power-on-reset (POR) state.
Figure 97. SW_RESET Register
7
6
5
4
Reserved
R-0h
3
2
1
0
SW_RESET
R/W-0h
Table 53. SW_RESET Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
Reserved
R
0h
Reserved
SW_RESET
R/W
0h
Software reset. This bit is self-clearing.
0d = Do not reset
1d = Reset
0
74
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8.6.1.3.3 SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.
Figure 98. SLEEP_CFG Register
7
6
5
4
3
Reserved
Reserved
VREF_QCHG[1:0]
RW-0h
RW-0h
RW-0h
2
I2C_BRDCAST
_EN
RW-0h
1
0
Reserved
SLEEP_ENZ
R-0h
RW-0h
Table 54. SLEEP_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
RW
0h
Reserved
6-5
Reserved
RW
0h
Reserved
4-3
VREF_QCHG[1:0]
RW
0h
The duration of the quick-charge for the VREF external capacitor is set using
an internal series impedance of 200 Ω.
0d = VREF quick-charge duration of 3.5 ms (typical)
1d = VREF quick-charge duration of 10 ms (typical)
2d = VREF quick-charge duration of 50 ms (typical)
3d = VREF quick-charge duration of 100 ms (typical)
2
I2C_BRDCAST_EN
RW
0h
I2C broadcast addressing setting.
0d = I2C broadcast mode disabled; the I2C slave address is determined
based on the ADDR pins
1d = I2C broadcast mode enabled; the I2C slave address is fixed at 1001
100
1
Reserved
R
0h
Reserved
0
SLEEP_ENZ
RW
0h
Sleep mode setting.
0d = Device is in sleep mode
1d = Device is not in sleep mode
8.6.1.3.4 SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
This register configures the device shutdown
Figure 99. SHDN_CFG Register
7
6
5
4
3
2
SHDNZ_CFG[1:0]
RW-1h
Reserved
R-0h
1
0
DREG_KA_TIME[1:0]
RW-1h
Table 55. SHDN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
Reserved
R
0h
Reserved
3-2
SHDNZ_CFG[1:0]
RW
1h
Shutdown configuration.
0d = DREG is powered down immediately after SHDNZ asserts
1d = DREG remains active to enable a clean shut down until a time-out is
reached; after the time-out period, DREG is forced to power off
2d = DREG remains active until the device cleanly shuts down
3d = Reserved
1-0
DREG_KA_TIME[1:0]
RW
1h
These bits set how long DREG remains active after SHDNZ asserts.
0d = DREG remains active for 30 ms (typical)
1d = DREG remains active for 25 ms (typical)
2d = DREG remains active for 10 ms (typical)
3d = DREG remains active for 5 ms (typical)
8.6.1.3.5 ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
This register is the ASI configuration register 0.
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Figure 100. ASI_CFG0 Register
7
6
ASI_FORMAT[1:0]
RW-0h
5
4
ASI_WLEN[1:0]
RW-3h
3
FSYNC_POL
RW-0h
2
BCLK_POL
RW-0h
1
TX_EDGE
RW-0h
0
TX_FILL
RW-0h
Table 56. ASI_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ASI_FORMAT[1:0]
RW
0h
ASI protocol format.
0d = TDM mode
1d = I2S mode
2d = LJ (left-justified) mode
3d = Reserved
5-4
ASI_WLEN[1:0]
RW
3h
ASI word or slot length.
0d = 16 bits
1d = 20 bits
2d = 24 bits
3d = 32 bits
3
FSYNC_POL
RW
0h
ASI FSYNC polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
2
BCLK_POL
RW
0h
ASI BCLK polarity.
0d = Default polarity as per standard protocol
1d = Inverted polarity with respect to standard protocol
1
TX_EDGE
RW
0h
ASI data output (on the primary and secondary data pin) transmit edge.
0d = Default edge as per the protocol configuration setting in bit 2
(BCLK_POL)
1d = Inverted following edge (half cycle delay) with respect to the default
edge setting
0
TX_FILL
RW
0h
ASI data output (on the primary and secondary data pin) for any unused
cycles
0d = Always transmit 0 for unused cycles
1d = Always use Hi-Z for unused cycles
8.6.1.3.6 ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
This register is the ASI configuration register 1.
Figure 101. ASI_CFG1 Register
7
TX_LSB
RW-0h
6
5
TX_KEEPER[1:0]
RW-0h
4
3
2
TX_OFFSET[4:0]
RW-0h
1
0
Table 57. ASI_CFG1 Register Field Descriptions
Bit
7
6-5
76
Field
Type
Reset
Description
TX_LSB
RW
0h
ASI data output (on the primary and secondary data pin) for LSB
transmissions.
0d = Transmit the LSB for a full cycle
1d = Transmit the LSB for the first half cycle and Hi-Z for the second half
cycle
TX_KEEPER[1:0]
RW
0h
ASI data output (on the primary and secondary data pin) bus keeper.
0d = Bus keeper is always disabled
1d = Bus keeper is always enabled
2d = Bus keeper is enabled during LSB transmissions only for one cycle
3d = Bus keeper is enabled during LSB transmissions only for one and half
cycles
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 57. ASI_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4-0
TX_OFFSET[4:0]
RW
0h
ASI data MSB slot 0 offset (on the primary and secondary data pin).
0d = ASI data MSB location has no offset and is as per standard protocol
1d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left
and right slot 0) offset of one BCLK cycle with respect to standard protocol
2d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left
and right slot 0) offset of two BCLK cycles with respect to standard protocol
3d to 30d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is
the left and right slot 0) offset assigned as per configuration
31d = ASI data MSB location (TDM mode is slot 0 or I2S, LJ mode is the left
and right slot 0) offset of 31 BCLK cycles with respect to standard protocol
8.6.1.3.7 ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
This register is the ASI configuration register 2.
Figure 102. ASI_CFG2 Register
7
6
5
ASI_DAISY
Reserved
ASI_ERR
RW-0h
R-0h
RW-0h
4
3
2
ASI_ERR_RCO
V
RW-0h
1
0
Reserved
R-0h
Table 58. ASI_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ASI_DAISY
RW
0h
ASI daisy chain connection.
0d = All devices are connected in the common ASI bus
1d = All devices are daisy-chained for the ASI bus
6
Reserved
R
0h
Reserved
5
ASI_ERR
RW
0h
ASI bus error detection.
0d = Enable bus error detection
1d = Disable bus error detection
4
ASI_ERR_RCOV
RW
0h
ASI bus error auto resume.
0d = Enable auto resume after bus error recovery
1d = Disable auto resume after bus error recovery and remain powered
down until the host configures the device
Reserved
R
0h
Reserved
3-0
8.6.1.3.8 ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
This register is the ASI slot configuration register for channel 1.
Figure 103. ASI_CH1 Register
7
Reserved
R-0h
6
CH1_OUTPUT
RW-0h
5
4
3
2
1
0
CH1_SLOT[5:0]
RW-0h
Table 59. ASI_CH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
6
CH1_OUTPUT
RW
0h
Channel 1 output line.
0d = Channel 1 output is on the ASI primary output pin (SDOUT)
1d = Channel 1 output is on the ASI secondary output pin (GPIO1 or GPOx)
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Table 59. ASI_CH1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
CH1_SLOT[5:0]
RW
0h
Channel 1 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.3.9 ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
This register is the ASI slot configuration register for channel 2.
Figure 104. ASI_CH2 Register
7
Reserved
6
CH2_OUTPUT
R-0h
RW-0h
5
4
3
2
1
0
CH2_SLOT[5:0]
RW-1h
Table 60. ASI_CH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
6
CH2_OUTPUT
RW
0h
Channel 2 output line.
0d = Channel 2 output is on the ASI primary output pin (SDOUT)
1d = Channel 2 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH2_SLOT[5:0]
RW
1h
Channel 2 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.3.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
This register is the ASI slot configuration register for channel 3.
Figure 105. ASI_CH3 Register
7
Reserved
R-0h
6
CH3_OUTPUT
RW-0h
5
4
3
2
1
0
CH3_SLOT[5:0]
RW-2h
Table 61. ASI_CH3 Register Field Descriptions
Bit
78
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
6
CH3_OUTPUT
RW
0h
Channel 3 output line.
0d = Channel 3 output is on the ASI primary output pin (SDOUT)
1d = Channel 3 output is on the ASI secondary output pin (GPIO1 or GPOx)
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Table 61. ASI_CH3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
CH3_SLOT[5:0]
RW
2h
Channel 3 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.3.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
This register is the ASI slot configuration register for channel 4.
Figure 106. ASI_CH4 Register
7
Reserved
6
CH4_OUTPUT
R-0h
RW-0h
5
4
3
2
1
0
CH4_SLOT[5:0]
RW-3h
Table 62. ASI_CH4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
6
CH4_OUTPUT
RW
0h
Channel 4 output line.
0d = Channel 4 output is on the ASI primary output pin (SDOUT)
1d = Channel 4 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH4_SLOT[5:0]
RW
3h
Channel 4 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.3.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
This register is the ASI slot configuration register for channel 5. Applicable only for PCM6x60-Q1.
Figure 107. ASI_CH5 Register
7
Reserved
R-0h
6
CH5_OUTPUT
RW-0h
5
4
3
2
1
0
CH5_SLOT[5:0]
RW-4h
Table 63. ASI_CH5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
6
CH5_OUTPUT
RW
0h
Channel 5 output line.
0d = Channel 5 output is on the ASI primary output pin (SDOUT)
1d = Channel 5 output is on the ASI secondary output pin (GPIO1 or GPOx)
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Table 63. ASI_CH5 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
CH5_SLOT[5:0]
RW
4h
Channel 5 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.3.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
This register is the ASI slot configuration register for channel 6. Applicable only for PCM6x60-Q1.
Figure 108. ASI_CH6 Register
7
Reserved
6
CH6_OUTPUT
R-0h
RW-0h
5
4
3
2
1
0
CH6_SLOT[5:0]
RW-5h
Table 64. ASI_CH6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R
0h
Reserved
6
CH6_OUTPUT
RW
0h
Channel 6 output line.
0d = Channel 6 output is on the ASI primary output pin (SDOUT)
1d = Channel 6 output is on the ASI secondary output pin (GPIO1 or GPOx)
5-0
CH6_SLOT[5:0]
RW
5h
Channel 6 slot assignment.
0d = TDM is slot 0 or I2S, LJ is left slot 0
1d = TDM is slot 1 or I2S, LJ is left slot 1
2d to 30d = Slot assigned as per configuration
31d = TDM is slot 31 or I2S, LJ is left slot 31
32d = TDM is slot 32 or I2S, LJ is right slot 0
33d = TDM is slot 33 or I2S, LJ is right slot 1
34d to 62d = Slot assigned as per configuration
63d = TDM is slot 63 or I2S, LJ is right slot 31
8.6.1.3.14 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
This register is the ASI master mode configuration register 0.
Figure 109. MST_CFG0 Register
7
MST_SLV_CF
G
RW-0h
6
AUTO_CLK_C
FG
RW-0h
5
4
AUTO_MODE_ BCLK_FSYNC_
PLL_DIS
GATE
RW-0h
RW-0h
3
2
1
FS_MODE
MCLK_FREQ_SEL[2:0]
RW-0h
RW-2h
0
Table 65. MST_CFG0 Register Field Descriptions
Bit
80
Field
Type
Reset
Description
7
MST_SLV_CFG
RW
0h
ASI master or slave configuration register setting.
0d = Device is in slave mode (both BCLK and FSYNC are inputs to the
device)
1d = Device is in master mode (both BCLK and FSYNC are generated from
the device)
6
AUTO_CLK_CFG
RW
0h
Automatic clock configuration setting.
0d = Auto clock configuration is enabled (all internal clock divider and PLL
configurations are auto derived)
1d = Auto clock configuration is disabled (custom mode and device GUI
must be used for the device configuration settings)
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 65. MST_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
AUTO_MODE_PLL_DIS
RW
0h
Automatic mode PLL setting.
0d = PLL is enabled in auto clock configuration
1d = PLL is disabled in auto clock configuration
4
BCLK_FSYNC_GATE
RW
0h
BCLK and FSYNC clock gate (valid when the device is in master mode).
0d = Do not gate BCLK and FSYNC
1d = Force gate BCLK and FSYNC when being transmitted from the device
in master mode
3
FS_MODE
RW
0h
Sample rate setting (valid when the device is in master mode).
0d = fS is a multiple (or submultiple) of 48 kHz
1d = fS is a multiple (or submultiple) of 44.1 kHz
MCLK_FREQ_SEL[2:0]
RW
2h
These bits select the MCLK (GPIO or GPIx) frequency for the PLL source
clock input (valid when the device is in master mode and
MCLK_FREQ_SEL_MODE = 0).
0d = 12 MHz
1d = 12.288 MHz
2d = 13 MHz
3d = 16 MHz
4d = 19.2 MHz
5d = 19.68 MHz
6d = 24 MHz
7d = 24.576 MHz
2-0
8.6.1.3.15 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
This register is the ASI master mode configuration register 1.
Figure 110. MST_CFG1 Register
7
6
5
4
3
FS_RATE[3:0]
RW-4h
2
1
FS_BCLK_RATIO[3:0]
RW-8h
0
Table 66. MST_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FS_RATE[3:0]
RW
4h
Programmed sample rate of the ASI bus (not used when the device is
configured in slave mode auto clock configuration).
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 15d = Reserved
3-0
FS_BCLK_RATIO[3:0]
RW
8h
Programmed BCLK to FSYNC frequency ratio of the ASI bus (not used
when the device is configured in slave mode auto clock configuration).
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d = Reserved
14d = Ratio of 144
15d = Reserved
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8.6.1.3.16 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
This register s the ASI bus clock monitor status register
Figure 111. ASI_STS Register
7
6
5
FS_RATE_STS[3:0]
R-Fh
4
3
2
1
FS_RATIO_STS[3:0]
R-Fh
0
Table 67. ASI_STS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
FS_RATE_STS[3:0]
R
Fh
Detected sample rate of the ASI bus.
0d = 7.35 kHz or 8 kHz
1d = 14.7 kHz or 16 kHz
2d = 22.05 kHz or 24 kHz
3d = 29.4 kHz or 32 kHz
4d = 44.1 kHz or 48 kHz
5d = 88.2 kHz or 96 kHz
6d = 176.4 kHz or 192 kHz
7d = 352.8 kHz or 384 kHz
8d = 705.6 kHz or 768 kHz
9d to 14d = Reserved
15d = Invalid sample rate
3-0
FS_RATIO_STS[3:0]
R
Fh
Detected BCLK to FSYNC frequency ratio of the ASI bus.
0d = Ratio of 16
1d = Ratio of 24
2d = Ratio of 32
3d = Ratio of 48
4d = Ratio of 64
5d = Ratio of 96
6d = Ratio of 128
7d = Ratio of 192
8d = Ratio of 256
9d = Ratio of 384
10d = Ratio of 512
11d = Ratio of 1024
12d = Ratio of 2048
13d = Reserved
14d = Ratio of 144
15d = Invalid ratio
8.6.1.3.17 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
This register is the clock source configuration register.
Figure 112. CLK_SRC Register
7
DIS_PLL_SLV_
CLK_SRC
RW-0h
6
MCLK_FREQ_
SEL_MODE
RW-0h
5
4
3
2
1
MCLK_RATIO_SEL[2:0]
Reserved
RW-2h
R-0h
0
Table 68. CLK_SRC Register Field Descriptions
Bit
7
82
Field
Type
Reset
Description
DIS_PLL_SLV_CLK_SRC
RW
0h
Audio root clock source setting when the device is configured with the PLL
disabled in the auto clock configuration for slave mode
(AUTO_MODE_PLL_DIS = 1).
0d = BCLK is used as the audio root clock source
1d = MCLK (GPIOx or GPIx) is used as the audio root clock source (the
MCLK to FSYNC ratio is as per MCLK_RATIO_SEL setting)
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Table 68. CLK_SRC Register Field Descriptions (continued)
Bit
Field
Reset
Description
MCLK_FREQ_SEL_MODE RW
0h
Master mode MCLK (GPIOx or GPIx) frequency selection mode (valid when
the device is in auto clock configuration).
0d = MCLK frequency is based on the MCLK_FREQ_SEL (P0_R19)
configuration
1d = MCLK frequency is specified as a multiple of FSYNC in the
MCLK_RATIO_SEL (P0_R22) configuration
5-3
MCLK_RATIO_SEL[2:0]
RW
2h
These bits select the MCLK (GPIOx or GPIx) to FSYNC ratio for master
mode or when MCLK is used as the audio root clock source in slave mode.
0d = Ratio of 64
1d = Ratio of 256
2d = Ratio of 384
3d = Ratio of 512
4d = Ratio of 768
5d = Ratio of 1024
6d = Ratio of 1536
7d = Ratio of 2304
2-0
Reserved
R
0h
Reserved
6
Type
8.6.1.3.18 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
This register is the GPIO configuration register 0.
Figure 113. GPIO_CFG0 Register
7
6
5
GPIO1_CFG[3:0]
RW-2h
4
3
Reserved
R-0h
2
1
GPIO1_DRV[2:0]
RW-2h
0
Table 69. GPIO_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO1_CFG[3:0]
RW
2h
GPIO1 configuration.
0d = GPIO1 is disabled
1d = GPIO1 is configured as a general-purpose output (GPO)
2d = GPIO1 is configured as a device interrupt output (IRQ)
3d = GPIO1 is configured as a secondary ASI output (SDOUT2)
4d = Reserved
5d = Reserved
6d = Reserved
7d = GPIO1 is configured as an input to power down all ADC channels
8d = GPIO1 is configured as an input to control when MICBIAS turns on or
off (MICBIAS_EN)
9d = GPIO1 is configured as a general-purpose input (GPI)
10d = GPIO1 is configured as a master clock input (MCLK)
11d = GPIO1 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = Reserved
Reserved
R
0h
Reserved
GPIO1_DRV[2:0]
RW
2h
GPIO1 output drive configuration (not used when GPIO1 is configured as
SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
3
2-0
8.6.1.3.19 GPIO_CFG1 Register (page = 0x00, address = 0x22) [reset = 0h]
This register is the GPIO configuration register 1. Not applicable for PCM6x60-Q1.
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Figure 114. GPIO_CFG1 Register
7
6
5
GPIO2_CFG[3:0]
RW-0h
4
3
Reserved
R-0h
2
1
GPIO2_DRV[2:0]
RW-0h
0
Table 70. GPIO_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO2_CFG[3:0]
RW
0h
GPIO2 configuration.
0d = GPIO2 is disabled
1d = GPIO2 is configured as a general-purpose output (GPO)
2d = GPIO2 is configured as a device interrupt output (IRQ)
3d = GPIO2 is configured as a secondary ASI output (SDOUT2)
4d = Reserved
5d = Reserved
6d = Reserved
7d = GPIO2 is configured as an input to power down all ADC channels
8d = GPIO2 is configured as an input to control when MICBIAS turns on or
off (MICBIAS_EN)
9d = GPIO2 is configured as a general-purpose input (GPI)
10d = GPIO2 is configured as a master clock input (MCLK)
11d = GPIO2 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = Reserved
Reserved
R
0h
Reserved
GPIO2_DRV[2:0]
RW
0h
GPIO2 output drive configuration (not used when GPIO2 is configured as
SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
3
2-0
8.6.1.3.20 GPIO_CFG2 Register (page = 0x00, address = 0x23) [reset = 0h]
This register is the GPIO configuration register 2. Not applicable for PCM6x60-Q1.
Figure 115. GPIO_CFG2 Register
7
6
5
GPIO3_CFG[3:0]
RW-0h
4
3
Reserved
R-0h
2
1
GPIO3_DRV[2:0]
RW-0h
0
Table 71. GPIO_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPIO3_CFG[3:0]
RW
0h
GPIO3 configuration.
0d = GPIO3 is disabled
1d = GPIO3 is configured as a general-purpose output (GPO)
2d = GPIO3 is configured as a device interrupt output (IRQ)
3d = GPIO3 is configured as a secondary ASI output (SDOUT2)
4d = Reserved
5d = Reserved
6d = Reserved
7d = GPIO3 is configured as an input to power down all ADC channels
8d = GPIO3 is configured as an input to control when MICBIAS turns on or
off (MICBIAS_EN)
9d = GPIO3 is configured as a general-purpose input (GPI)
10d = GPIO3 is configured as a master clock input (MCLK)
11d = GPIO3 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = Reserved
Reserved
R
0h
Reserved
3
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Table 71. GPIO_CFG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
GPIO3_DRV[2:0]
RW
0h
GPIO3 output drive configuration (not used when GPIO3 is configured as
SDOUT2).
0d = Hi-Z output
1d = Drive active low and active high
2d = Drive active low and weak high
3d = Drive active low and Hi-Z
4d = Drive weak low and active high
5d = Drive Hi-Z and active high
6d to 7d = Reserved
8.6.1.3.21 GPI_CFG0 Register (page = 0x00, address = 0x24) [reset = 0h]
This register is the GPI configuration register 0. Not applicable for PCM6x60-Q1.
Figure 116. GPI_CFG0 Register
7
6
5
4
3
2
1
GPI1_CFG[3:0]
Reserved
RW-0h
R-0h
0
Table 72. GPI_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPI1_CFG[3:0]
RW
0h
GPI1 configuration.
0d = GPI1 is disabled
1d to 6d = Reserved
7d = GPI1 is configured as an input to power down all ADC channels
8d = GPI1 is configured as an input to control when MICBIAS turns on or off
(MICBIAS_EN)
9d = GPI1 is configured as a general-purpose input (GPI)
10d = GPI1 is configured as a master clock input (MCLK)
11d = GPI1 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = Reserved
3-0
Reserved
R
0h
Reserved
8.6.1.3.22 GPI_CFG1 Register (page = 0x00, address = 0x25) [reset = 0h]
This register is the GPI configuration register 1. Not applicable for PCM6x60-Q1.
Figure 117. GPI_CFG1 Register
7
6
5
4
3
GPI2_CFG[3:0]
RW-0h
2
1
0
Reserved
R-0h
Table 73. GPI_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
GPI2_CFG[3:0]
RW
0h
GPI2 configuration.
0d = GPI2 is disabled
1d to 6d = Reserved
7d = GPI2 is configured as an input to power down all ADC channels
8d = GPI2 is configured as an input to control when MICBIAS turns on or off
(MICBIAS_EN)
9d = GPI2 is configured as a general-purpose input (GPI)
10d = GPI2 is configured as a master clock input (MCLK)
11d = GPI2 is configured as an ASI input for daisy-chain (SDIN)
12d = Reserved
13d = Reserved
14d = Reserved
3-0
Reserved
R
0h
Reserved
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8.6.1.3.23 GPIO_VAL Register (page = 0x00, address = 0x26) [reset = 0h]
This register is the GPIO output value register.
Figure 118. GPIO_VAL Register
7
GPIO1_VAL
RW-0h
6
GPIO2_VAL
RW-0h
5
GPIO3_VAL
RW-0h
4
3
2
Reserved
R-0h
1
0
Table 74. GPIO_VAL Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_VAL
RW
0h
GPIO1 output value when configured as a GPO.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
6
GPIO2_VAL
RW
0h
GPIO2 output value when configured as a GPO. Not applicable for
PCM6x60-Q1.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
5
GPIO3_VAL
RW
0h
GPIO3 output value when configured as a GPO. Not applicable for
PCM6x60-Q1.
0d = Drive the output with a value of 0
1d = Drive the output with a value of 1
Reserved
R
0h
Reserved
4-0
8.6.1.3.24 GPIO_MON Register (page = 0x00, address = 0x27) [reset = 0h]
This register is the GPIO monitor value register.
Figure 119. GPIO_MON Register
7
GPIO1_MON
R-0h
6
GPIO2_MON
R-0h
5
GPIO3_MON
R-0h
4
GPI1_MON
R-0h
3
GPI2_MON
R-0h
2
1
Reserved
R-0h
0
Table 75. GPIO_MON Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPIO1_MON
R
0h
GPIO1 monitor value when configured as a GPI.
0d = Input monitor value 0
1d = Input monitor value 1
6
GPIO2_MON
R
0h
GPIO2 monitor value when configured as a GPI. Not applicable for
PCM6x60-Q1.
0d = Input monitor value 0
1d = Input monitor value 1
5
GPIO3_MON
R
0h
GPIO3 monitor value when configured as a GPI. Not applicable for
PCM6x60-Q1.
0d = Input monitor value 0
1d = Input monitor value 1
4
GPI1_MON
R
0h
GPI1 monitor value when configured as a GPI. Not applicable for PCM6x60Q1.
0d = Input monitor value 0
1d = Input monitor value 1
3
GPI2_MON
R
0h
GPI2 monitor value when configured as a GPI. Not applicable for PCM6x60Q1.
0d = Input monitor value 0
1d = Input monitor value 1
Reserved
R
0h
Reserved
2-0
8.6.1.3.25 INT_CFG Register (page = 0x00, address = 0x28) [reset = 0h]
This regiser is the interrupt configuration register.
86
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Figure 120. INT_CFG Register
7
6
5
4
3
INT_POL
INT_EVENT[1:0]
PD_ON_FLT_CFG[1:0]
RW-0h
RW-0h
RW-0h
2
LTCH_READ_
CFG
RW-0h
1
PD_ON_FLT_R
CV_CFG
RW-0h
0
LTCH_CLR_O
N_READ
RW-0h
Table 76. INT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
INT_POL
RW
0h
Interrupt polarity.
0d = Active low (IRQZ)
1d = Active high (IRQ)
6-5
INT_EVENT[1:0]
RW
0h
Interrupt event configuration.
0d = INT asserts on any unmasked latched interrupts event
1d = Reserved
2d = INT asserts for 2 ms (typical) for every 4-ms (typical) duration on any
unmasked latched interrupts event
3d = INT asserts for 2 ms (typical) one time on each pulse for any
unmasked interrupts event
4-3
PD_ON_FLT_CFG[1:0]
RW
0h
Powerdown configuration when fault detected for any channel or MICBIAS
fault detected.
0d = Faults event are not used for ADC and MICBIAS power down. It is
recommend to set these bits as 2d to shutdown the blocks for which fault
occurred.
1d = Only unmasked faults are used for power down of respective ADC
channel; In case of MICBIAS fault detected, MICBIAS and all ADC channels
gets powered-down based on P0_R58 settings
2d = Both masked or unmasked faults are used for power down of
respective ADC channel; In case of MICBIAS fault detected, MICBIAS and
all ADC channels gets powered-down based on P0_R58 settings.
3d = Reserved
2
LTCH_READ_CFG
RW
0h
Interrupt latch registers readback configuration.
0d = All interrupts can be read through the LTCH registers
1d = Only unmasked interrupts can be read through the LTCH registers
1
PD_ON_FLT_RCV_CFG
RW
0h
Recovery configuration for ADC channels when fault goes away.
0d = Auto recovery, ADC channels are re-powered up when fault goes away
1d = Manual recovery, ADC channels are required to power-up manually
using P0_R119 when fault goes away
0
LTCH_CLR_ON_READ
RW
0h
Configuration for clearing LTCH register bits.
0d = LTCH register bits are cleared on register read only if live status is zero
1d = LTCH register bits are cleared on register read irrespective of live
status and set only if live status goes again low to high
7
8.6.1.3.26 INT_MASK0 Register (page = 0x00, address = 0x29) [reset = FFh]
This register is the interrupt masks register 0.
Figure 121. INT_MASK0 Register
7
INT_MASK0[7]
RW-1h
6
INT_MASK0[6]
RW-1h
5
INT_MASK0[5]
RW-1h
4
INT_MASK0[4]
RW-1h
3
Reserved
RW-1h
2
Reserved
RW-1h
1
Reserved
RW-1h
0
Reserved
RW-1h
Table 77. INT_MASK0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK0[7]
RW
1h
ASI clock error mask.
0d = Unmask
1d = Mask
6
INT_MASK0[6]
RW
1h
PLL lock interrupt mask.
0d = Unmask
1d = Mask
5
INT_MASK0[5]
RW
1h
Boost or MICBIAS over temperature interrupt mask.
0d = Unmask
1d = Mask
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Table 77. INT_MASK0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
INT_MASK0[4]
RW
1h
Boost or MICBIAS over current interrupt mask.
0d = Unmask
1d = Mask
3
Reserved
RW
1h
Reserved
2
Reserved
RW
1h
Reserved
1
Reserved
RW
1h
Reserved
0
Reserved
RW
1h
Reserved
8.6.1.3.27 INT_MASK1 Register (page = 0x00, address = 0x2A) [reset = 3h]
This register is the interrupt masks register 1.
Figure 122. INT_MASK1 Register
7
INT_MASK1[7]
RW-0h
6
INT_MASK1[6]
RW-0h
5
INT_MASK1[5]
RW-0h
4
INT_MASK1[4]
RW-0h
3
INT_MASK1[3]
RW-0h
2
INT_MASK1[2]
RW-0h
1
INT_MASK1[1]
RW-1h
0
Reserved
RW-1h
Table 78. INT_MASK1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK1[7]
RW
0h
Channel 1 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
6
INT_MASK1[6]
RW
0h
Channel 2 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
5
INT_MASK1[5]
RW
0h
Channel 3 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
4
INT_MASK1[4]
RW
0h
Channel 4 input DC faults diagnostic interrupt mask.
0d = Unmask
1d = Mask
3
INT_MASK1[3]
RW
0h
Channel 5 input DC faults diagnostic interrupt mask. Applicable only for
PCM6x60-Q1.
0d = Unmask
1d = Mask
2
INT_MASK1[2]
RW
0h
Channel 6 input DC faults diagnostic interrupt mask. Applicable only for
PCM6x60-Q1.
0d = Unmask
1d = Mask
1
INT_MASK1[1]
RW
1h
Input faults diagnostic interrupt mask for "short to VBAT_IN" detect when
VBAT_IN voltage is less than MICBIAS voltage.
0d = Unmask
1d = Mask
0
Reserved
RW
1h
Reserved
8.6.1.3.28 INT_MASK2 Register (page = 0x00, address = 0x2B) [reset = 0h]
This register is the interrupt masks register 2.
Figure 123. INT_MASK2 Register
7
INT_MASK2[7]
RW-0h
88
6
INT_MASK2[6]
RW-0h
5
INT_MASK2[5]
RW-0h
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4
INT_MASK2[4]
RW-0h
3
INT_MASK2[3]
RW-0h
2
INT_MASK2[2]
RW-0h
1
INT_MASK2[1]
RW-0h
0
INT_MASK2[0]
RW-0h
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Table 79. INT_MASK2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK2[7]
RW
0h
Input diagnostics; Open inputs fault interrupt mask.
0d = Unmask
1d = Mask
6
INT_MASK2[6]
RW
0h
Input diagnostics; Inputs shorted fault interrupt mask.
0d = Unmask
1d = Mask
5
INT_MASK2[5]
RW
0h
Input diagnostics; INxP shorted to ground fault interrupt mask.
0d = Unmask
1d = Mask
4
INT_MASK2[4]
RW
0h
Input diagnostics; INxM shorted to ground fault interrupt mask.
0d = Unmask
1d = Mask
3
INT_MASK2[3]
RW
0h
Input diagnostics; INxP shorted to MICBIAS fault interrupt mask.
0d = Unmask
1d = Mask
2
INT_MASK2[2]
RW
0h
Input diagnostics; INxM shorted to MICBIAS fault interrupt mask.
0d = Unmask
1d = Mask
1
INT_MASK2[1]
RW
0h
Input diagnostics; INxP shorted to VBAT_IN fault interrupt mask.
0d = Unmask
1d = Mask
0
INT_MASK2[0]
RW
0h
Input diagnostics; INxM shorted to VBAT_IN fault interrupt mask.
0d = Unmask
1d = Mask
8.6.1.3.29 INT_LTCH0 Register (page = 0x00, address = 0x2C) [reset = 0h]
This register is the latched Interrupt readback register 0.
Figure 124. INT_LTCH0 Register
7
INT_LTCH0[7]
R-0h
6
INT_LTCH0[6]
R-0h
5
INT_LTCH0[5]
R-0h
4
INT_LTCH0[4]
R-0h
3
Reserved
R-0h
2
Reserved
R-0h
1
Reserved
R-0h
0
Reserved
R-0h
Table 80. INT_LTCH0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH0[7]
R
0h
Fault status for an ASI bus clock error (self-clearing bit).
0d = No fault detected
1d = Fault detected
6
INT_LTCH0[6]
R
0h
Status of PLL lock (self-clearing bit).
0d = No PLL lock detected
1d = PLL lock detected
5
INT_LTCH0[5]
R
0h
Fault status for boost or MICBIAS over temperature (self-clearing bit).
0d = No fault detected
1d = Fault detected
4
INT_LTCH0[4]
R
0h
Fault status for boost or MICBIAS over current (self-clearing bit).
0d = No fault detected
1d = Fault detected
3
Reserved
R
0h
Reserved
2
Reserved
R
0h
Reserved
1
Reserved
R
0h
Reserved
0
Reserved
R
0h
Reserved
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8.6.1.3.30 CHx_LTCH Register (page = 0x00, address = 0x2D) [reset = 0h]
This register is the latched Interrupt status register for channel level diagnostic summary.
Figure 125. CHx_LTCH Register
7
6
5
4
3
2
1
STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC STS_CHx_LTC
H[7]
H[6]
H[5]
H[4]
H[3]
H[2]
H[1]
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
0
Reserved
R-0h
Table 81. CHx_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
STS_CHx_LTCH[7]
R
0h
Status of CH1_LTCH (self-clearing bit).
0d = No faults occurred in channel 1
1d = Atleast a fault has occurred in channel 1
6
STS_CHx_LTCH[6]
R
0h
Status of CH2_LTCH (self-clearing bit).
0d = No faults occurred in channel 2
1d = Atleast a fault has occurred in channel 2
5
STS_CHx_LTCH[5]
R
0h
Status of CH3_LTCH (self-clearing bit).
0d = No faults occurred in channel 3
1d = Atleast a fault has occurred in channel 3
4
STS_CHx_LTCH[4]
R
0h
Status of CH4_LTCH (self-clearing bit).
0d = No faults occurred in channel 4
1d = Atleast a fault has occurred in channel 4
3
STS_CHx_LTCH[3]
R
0h
Status of CH5_LTCH (self-clearing bit). Applicable only for PCM6x60-Q1.
0d = No faults occurred in channel 5
1d = Atleast a fault has occurred in channel 5
2
STS_CHx_LTCH[2]
R
0h
Status of CH6_LTCH (self-clearing bit). Applicable only for PCM6x60-Q1.
0d = No faults occurred in channel 6
1d = Atleast a fault has occurred in channel 6
1
STS_CHx_LTCH[1]
R
0h
Status of short to VBAT_IN fault detected when VBAT_IN is less than
MICBIAS (self-clearing bit).
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has not
occurred in any channel
1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has
occurred in atleast one channel
0
Reserved
R
0h
Reserved
8.6.1.3.31 CH1_LTCH Register (page = 0x00, address = 0x2E) [reset = 0h]
This register is the latched Interrupt status register for channel 1 fault diagnostic
Figure 126. CH1_LTCH Register
7
CH1_LTCH[7]
R-0h
6
CH1_LTCH[6]
R-0h
5
CH1_LTCH[5]
R-0h
4
CH1_LTCH[4]
R-0h
3
CH1_LTCH[3]
R-0h
2
CH1_LTCH[2]
R-0h
1
CH1_LTCH[1]
R-0h
0
CH1_LTCH[0]
R-0h
Table 82. CH1_LTCH Register Field Descriptions
Bit
90
Field
Type
Reset
Description
7
CH1_LTCH[7]
R
0h
Channel 1 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
CH1_LTCH[6]
R
0h
Channel 1 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
5
CH1_LTCH[5]
R
0h
Channel 1 IN1P short to ground fault status (self-clearing bit).
0d = IN1P no short to ground detected
1d = IN1P short to ground detected
4
CH1_LTCH[4]
R
0h
Channel 1 IN1M short to ground fault status (self-clearing bit).
0d = IN1M no short to ground detected
1d = IN1M short to ground detected
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 82. CH1_LTCH Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
CH1_LTCH[3]
R
0h
Channel 1 IN1P short to MICBIAS fault status (self-clearing bit).
0d = IN1P no short to MICBIAS detected
1d = IN1P short to MICBIAS detected
2
CH1_LTCH[2]
R
0h
Channel 1 IN1M short to MICBIAS fault status (self-clearing bit).
0d = IN1M no short to MICBIAS detected
1d = IN1M short to MICBIAS detected
1
CH1_LTCH[1]
R
0h
Channel 1 IN1P short to VBAT_IN fault status (self-clearing bit).
0d = IN1P no short to VBAT_IN detected
1d = IN1P short to VBAT_IN detected
0
CH1_LTCH[0]
R
0h
Channel 1 IN1M short to VBAT_IN fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN1M no short to VBAT_IN detected
1d = IN1M short to VBAT_IN detected
8.6.1.3.32 CH2_LTCH Register (page = 0x00, address = 0x2F) [reset = 0h]
This register is the latched Interrupt status register for channel 2 fault diagnostic.
Figure 127. CH2_LTCH Register
7
CH2_LTCH[7]
R-0h
6
CH2_LTCH[6]
R-0h
5
CH2_LTCH[5]
R-0h
4
CH2_LTCH[4]
R-0h
3
CH2_LTCH[3]
R-0h
2
CH2_LTCH[2]
R-0h
1
CH2_LTCH[1]
R-0h
0
CH2_LTCH[0]
R-0h
Table 83. CH2_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH2_LTCH[7]
R
0h
Channel 2 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
CH2_LTCH[6]
R
0h
Channel 2 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
5
CH2_LTCH[5]
R
0h
Channel 2 IN2P short to ground fault status (self-clearing bit).
0d = IN2P no short to ground detected
1d = IN2P short to ground detected
4
CH2_LTCH[4]
R
0h
Channel 2 IN2M short to ground fault status (self-clearing bit).
0d = IN2M no short to ground detected
1d = IN2M short to ground detected
3
CH2_LTCH[3]
R
0h
Channel 2 IN2P short to MICBIAS fault status (self-clearing bit).
0d = IN2P no short to MICBIAS detected
1d = IN2P short to MICBIAS detected
2
CH2_LTCH[2]
R
0h
Channel 2 IN2M short to MICBIAS fault status (self-clearing bit).
0d = IN2M no short to MICBIAS detected
1d = IN2M short to MICBIAS detected
1
CH2_LTCH[1]
R
0h
Channel 2 IN2P short to VBAT_IN fault status (self-clearing bit).
0d = IN2P no short to VBAT_IN detected
1d = IN2P short to VBAT_IN detected
0
CH2_LTCH[0]
R
0h
Channel 2 IN2M short to VBAT_IN fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN2M no short to VBAT_IN detected
1d = IN2M short to VBAT_IN detected
8.6.1.3.33 CH3_LTCH Register (page = 0x00, address = 0x30) [reset = 0h]
This register is the latched Interrupt status register for channel3 fault diagnostic
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Figure 128. CH3_LTCH Register
7
CH3_LTCH[7]
R-0h
6
CH3_LTCH[6]
R-0h
5
CH3_LTCH[5]
R-0h
4
CH3_LTCH[4]
R-0h
3
CH3_LTCH[3]
R-0h
2
CH3_LTCH[2]
R-0h
1
CH3_LTCH[1]
R-0h
0
CH3_LTCH[0]
R-0h
Table 84. CH3_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3_LTCH[7]
R
0h
Channel 3 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
CH3_LTCH[6]
R
0h
Channel 3 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
5
CH3_LTCH[5]
R
0h
Channel 3 IN3P short to ground fault status (self-clearing bit).
0d = IN3P no short to ground detected
1d = IN3P short to ground detected
4
CH3_LTCH[4]
R
0h
Channel 3 IN3M short to ground fault status (self-clearing bit).
0d = IN3M no short to ground detected
1d = IN3M short to ground detected
3
CH3_LTCH[3]
R
0h
Channel 3 IN3P short to MICBIAS fault status (self-clearing bit).
0d = IN3P no short to MICBIAS detected
1d = IN3P short to MICBIAS detected
2
CH3_LTCH[2]
R
0h
Channel 3 IN3M short to MICBIAS fault status (self-clearing bit).
0d = IN3M no short to MICBIAS detected
1d = IN3M short to MICBIAS detected
1
CH3_LTCH[1]
R
0h
Channel 3 IN3P short to VBAT_IN fault status (self-clearing bit).
0d = IN3P no short to VBAT_IN detected
1d = IN3P short to VBAT_IN detected
0
CH3_LTCH[0]
R
0h
Channel 3 IN3M short to VBAT_IN fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN3M no short to VBAT_IN detected
1d = IN3M short to VBAT_IN detected
8.6.1.3.34 CH4_LTCH Register (page = 0x00, address = 0x31) [reset = 0h]
This register is the latched Interrupt status register for channel 4 fault diagnostic.
Figure 129. CH4_LTCH Register
7
CH4_LTCH[7]
R-0h
6
CH4_LTCH[6]
R-0h
5
CH4_LTCH[5]
R-0h
4
CH4_LTCH[4]
R-0h
3
CH4_LTCH[3]
R-0h
2
CH4_LTCH[2]
R-0h
1
CH4_LTCH[1]
R-0h
0
CH4_LTCH[0]
R-0h
Table 85. CH4_LTCH Register Field Descriptions
Bit
92
Field
Type
Reset
Description
7
CH4_LTCH[7]
R
0h
Channel 4 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
CH4_LTCH[6]
R
0h
Channel 4 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
5
CH4_LTCH[5]
R
0h
Channel 4 IN4P short to ground fault status (self-clearing bit).
0d = IN4P no short to ground detected
1d = IN4P short to ground detected
4
CH4_LTCH[4]
R
0h
Channel 4 IN4M short to ground fault status (self-clearing bit).
0d = IN4M no short to ground detected
1d = IN4M short to ground detected
3
CH4_LTCH[3]
R
0h
Channel 4 IN4P short to MICBIAS fault status (self-clearing bit).
0d = IN4P no short to MICBIAS detected
1d = IN4P short to MICBIAS detected
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 85. CH4_LTCH Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CH4_LTCH[2]
R
0h
Channel 4 IN4M short to MICBIAS fault status (self-clearing bit).
0d = IN4M no short to MICBIAS detected
1d = IN4M short to MICBIAS detected
1
CH4_LTCH[1]
R
0h
Channel 4 IN4P short to VBAT_IN fault status (self-clearing bit).
0d = IN4P no short to VBAT_IN detected
1d = IN4P short to VBAT_IN detected
0
CH4_LTCH[0]
R
0h
Channel 4 IN4M short to VBAT_IN fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN4M no short to VBAT_IN detected
1d = IN4M short to VBAT_IN detected
8.6.1.3.35 CH5_LTCH Register (page = 0x00, address = 0x32) [reset = 0h]
This register is the latched Interrupt status register for channel 5 fault diagnostic. Applicable only for PCM6x60Q1.
Figure 130. CH5_LTCH Register
7
CH5_LTCH[7]
R-0h
6
CH5_LTCH[6]
R-0h
5
CH5_LTCH[5]
R-0h
4
CH5_LTCH[4]
R-0h
3
CH5_LTCH[3]
R-0h
2
CH5_LTCH[2]
R-0h
1
CH5_LTCH[1]
R-0h
0
CH5_LTCH[0]
R-0h
Table 86. CH5_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH5_LTCH[7]
R
0h
Channel 5 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
CH5_LTCH[6]
R
0h
Channel 5 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
5
CH5_LTCH[5]
R
0h
Channel 5 IN5P short to ground fault status (self-clearing bit).
0d = IN5P no short to ground detected
1d = IN5P short to ground detected
4
CH5_LTCH[4]
R
0h
Channel 5 IN5M short to ground fault status (self-clearing bit).
0d = IN5M no short to ground detected
1d = IN5M short to ground detected
3
CH5_LTCH[3]
R
0h
Channel 5 IN5P short to MICBIAS fault status (self-clearing bit).
0d = IN5P no short to MICBIAS detected
1d = IN5P short to MICBIAS detected
2
CH5_LTCH[2]
R
0h
Channel 5 IN5M short to MICBIAS fault status (self-clearing bit).
0d = IN5M no short to MICBIAS detected
1d = IN5M short to MICBIAS detected
1
CH5_LTCH[1]
R
0h
Channel 5 IN5P short to VBAT_IN fault status (self-clearing bit).
0d = IN5P no short to VBAT_IN detected
1d = IN5P short to VBAT_IN detected
0
CH5_LTCH[0]
R
0h
Channel 5 IN5M short to VBAT_IN fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN5M no short to VBAT_IN detected
1d = IN5M short to VBAT_IN detected
8.6.1.3.36 CH6_LTCH Register (page = 0x00, address = 0x33) [reset = 0h]
This register is the latched Interrupt status register for channel 6 fault diagnostic. Applicable only for PCM6x60Q1.
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Figure 131. CH6_LTCH Register
7
CH6_LTCH[7]
R-0h
6
CH6_LTCH[6]
R-0h
5
CH6_LTCH[5]
R-0h
4
CH6_LTCH[4]
R-0h
3
CH6_LTCH[3]
R-0h
2
CH6_LTCH[2]
R-0h
1
CH6_LTCH[1]
R-0h
0
CH6_LTCH[0]
R-0h
Table 87. CH6_LTCH Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH6_LTCH[7]
R
0h
Channel 6 open input fault status (self-clearing bit).
0d = No open input detected
1d = Open input detected
6
CH6_LTCH[6]
R
0h
Channel 6 input pair short fault status (self-clearing bit).
0d = No input pair short detected
1d = Input short to each other detected
5
CH6_LTCH[5]
R
0h
Channel 6 IN6P short to ground fault status (self-clearing bit).
0d = IN6P no short to ground detected
1d = IN6P short to ground detected
4
CH6_LTCH[4]
R
0h
Channel 6 IN6M short to ground fault status (self-clearing bit).
0d = IN6M no short to ground detected
1d = IN6M short to ground detected
3
CH6_LTCH[3]
R
0h
Channel 6 IN6P short to MICBIAS fault status (self-clearing bit).
0d = IN6P no short to MICBIAS detected
1d = IN6P short to MICBIAS detected
2
CH6_LTCH[2]
R
0h
Channel 6 IN6M short to MICBIAS fault status (self-clearing bit).
0d = IN6M no short to MICBIAS detected
1d = IN6M short to MICBIAS detected
1
CH6_LTCH[1]
R
0h
Channel 6 IN6P short to VBAT_IN fault status (self-clearing bit).
0d = IN6P no short to VBAT_IN detected
1d = IN6P short to VBAT_IN detected
0
CH6_LTCH[0]
R
0h
Channel 6 IN6M short to VBAT_IN fault status (self-clearing bit - This bit
gets clear on reading Page-0, Register-54d, INT_LTCH2 register).
0d = IN6M no short to VBAT_IN detected
1d = IN6M short to VBAT_IN detected
8.6.1.3.37 INT_MASK3 Register (page = 0x00, address = 0x34) [reset = 0h]
This register is the interrupt masks register 3.
Figure 132. INT_MASK3 Register
7
INT_MASK3[7]
RW-0h
6
INT_MASK3[6]
RW-0h
5
INT_MASK3[5]
RW-0h
4
INT_MASK3[4]
RW-0h
3
INT_MASK3[3]
RW-0h
2
1
Reserved
R-0h
0
Table 88. INT_MASK3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_MASK3[7]
RW
0h
INxP over voltage fault mask.
0d = Unmask
1d = Mask
6
INT_MASK3[6]
RW
0h
INxM over voltage fault mask.
0d = Unmask
1d = Mask
5
INT_MASK3[5]
RW
0h
MICBIAS high current fault mask.
0d = Unmask
1d = Mask
4
INT_MASK3[4]
RW
0h
MICBIAS low current fault mask.
0d = Unmask
1d = Mask
3
INT_MASK3[3]
RW
0h
MICBIAS over voltage fault mask.
0d = Unmask
1d = Mask
Reserved
R
0h
Reserved
2-0
94
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.6.1.3.38 INT_LTCH1 Register (page = 0x00, address = 0x35) [reset = 0h]
This register is the latched Interrupt readback register 1.
Figure 133. INT_LTCH1 Register
7
INT_LTCH1[7]
R-0h
6
INT_LTCH1[6]
R-0h
5
INT_LTCH1[5]
R-0h
4
INT_LTCH1[4]
R-0h
3
INT_LTCH1[3]
R-0h
2
INT_LTCH1[2]
R-0h
1
0
Reserved
R-0h
Table 89. INT_LTCH1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH1[7]
R
0h
Channel 1 IN1P over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-46d, CH1_LTCH register).
0d = No IN1P over voltage fault detected
1d = IN1P over voltage fault has detected
6
INT_LTCH1[6]
R
0h
Channel 2 IN2P over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-47d, CH2_LTCH register).
0d = No IN2P over voltage fault detected
1d = IN2P over voltage fault has detected
5
INT_LTCH1[5]
R
0h
Channel 3 IN3P over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-48d, CH3_LTCH register).
0d = No IN3P over voltage fault detected
1d = IN3P over voltage fault has detected
4
INT_LTCH1[4]
R
0h
Channel 4 IN4P over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-49d, CH4_LTCH register).
0d = No IN4P over voltage fault detected
1d = IN4P over voltage fault has detected
3
INT_LTCH1[3]
R
0h
Channel 5 IN5P over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-50d, CH5_LTCH register). Applicable only
for PCM6x60-Q1.
0d = No IN5P over voltage fault detected
1d = IN5P over voltage fault has detected
2
INT_LTCH1[2]
R
0h
Channel 6 IN6P over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-51d, CH6_LTCH register). Applicable only
for PCM6x60-Q1.
0d = No IN6P over voltage fault detected
1d = IN6P over voltage fault has detected
Reserved
R
0h
Reserved
1-0
8.6.1.3.39 INT_LTCH2 Register (page = 0x00, address = 0x36) [reset = 0h]
This register is the latched Interrupt readback register 2.
Figure 134. INT_LTCH2 Register
7
INT_LTCH2[7]
R-0h
6
INT_LTCH2[6]
R-0h
5
INT_LTCH2[5]
R-0h
4
INT_LTCH2[4]
R-0h
3
INT_LTCH2[3]
R-0h
2
INT_LTCH2[2]
R-0h
1
0
Reserved
R-0h
Table 90. INT_LTCH2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH2[7]
R
0h
Channel 1 IN1M over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-46d, CH1_LTCH register).
0d = No IN1M over voltage fault detected
1d = IN1M over voltage fault has detected
6
INT_LTCH2[6]
R
0h
Channel 2 IN2M over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-47d, CH2_LTCH register).
0d = No IN2M over voltage fault detected
1d = IN2M over voltage fault has detected
5
INT_LTCH2[5]
R
0h
Channel 3 IN3M over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-48d, CH3_LTCH register).
0d = No IN3M over voltage fault detected
1d = IN3M over voltage fault has detected
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Table 90. INT_LTCH2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
INT_LTCH2[4]
R
0h
Channel 4 IN4M over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-49d, CH4_LTCH register).
0d = No IN4M over voltage fault detected
1d = IN4M over voltage fault has detected
3
INT_LTCH2[3]
R
0h
Channel 5 IN5M over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-50d, CH5_LTCH register). Applicable only
for PCM6x60-Q1.
0d = No IN5M over voltage fault detected
1d = IN5M over voltage fault has detected
2
INT_LTCH2[2]
R
0h
Channel 6 IN6M over voltage fault status (self-clearing bit - This bit gets
clear on reading Page-0, Register-51d, CH6_LTCH register). Applicable only
for PCM6x60-Q1.
0d = No IN6M over voltage fault detected
1d = IN6M over voltage fault has detected
Reserved
R
0h
Reserved
1-0
8.6.1.3.40 INT_LTCH3 Register (page = 0x00, address = 0x37) [reset = 0h]
This register is the latched Interrupt readback register 3.
Figure 135. INT_LTCH3 Register
7
INT_LTCH3[7]
R-0h
6
INT_LTCH3[6]
R-0h
5
INT_LTCH3[5]
R-0h
4
3
2
Reserved
R-0h
1
0
Table 91. INT_LTCH3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LTCH3[7]
R
0h
Fault status for MICBIAS high current (self-clearing bit).
0d = No fault detected
1d = Fault detected
6
INT_LTCH3[6]
R
0h
Fault status for MICBIAS low current (self-clearing bit)
0d = No fault detected
1d = Fault detected
5
INT_LTCH3[5]
R
0h
Fault status for MICBIAS over voltage (self-clearing bit).
0d = No fault detected
1d = Fault detected
Reserved
R
0h
Reserved
4-0
8.6.1.3.41 MBDIAG_CFG0 Register (page = 0x00, address = 0x38) [reset = BAh]
This register is the MICBIAS diagnostic configuration register 0.
Figure 136. MBDIAG_CFG0 Register
7
96
6
5
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4
3
MBIAS_HIGH_CURR_THRS[7:0]
RW-BAh
2
1
0
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 92. MBDIAG_CFG0 Register Field Descriptions
Bit
Field
7-0
MBIAS_HIGH_CURR_THR RW
S[7:0]
Type
Reset
Description
BAh
Threshold for MICBIAS high load current fault diagnostic.
0d to 56d = Reserved
57d = High load current threshold is set as 0 mA (typ)
58d = High load current threshold is set as 0.54 mA (typ)
59d = High load current threshold is set as 1.08 mA (typ)
60d to 185d = High load current threshold is set as per configuration
186d = High load current threshold is set as 69.66 mA (typ)
187d to 241d = High load current threshold is set as per configuration
242d = High load current threshold is set as 99.90 mA (typ)
243d to 255d = Reserved
8.6.1.3.42 MBDIAG_CFG1 Register (page = 0x00, address = 0x39) [reset = 4Bh]
This register is the MICBIAS diagnostic configuration register 1.
Figure 137. MBDIAG_CFG1 Register
7
6
5
4
3
MBIAS_LOW_CURR_THRS[7:0]
RW-4Bh
2
1
0
Table 93. MBDIAG_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
MBIAS_LOW_CURR_THR
S[7:0]
RW
4Bh
Threshold for MICBIAS low load current fault diagnostic.
0d to 56d = Reserved
57d = Low load current threshold is set as 0 mA (typ)
58d = Low load current threshold is set as 0.54 mA (typ)
59d = Low load current threshold is set as 1.08 mA (typ)
60d to 74d = Low load current threshold is set as per configuration
75d = Low load current threshold is set as 9.72 mA (typ)
76d to 241d = Low load current threshold is set as per configuration
242d = Low load current threshold is set as 99.90 mA (typ)
243d to 255d = Reserved
8.6.1.3.43 MBDIAG_CFG2 Register (page = 0x00, address = 0x3A) [reset = 10h]
This register is the MICBIAS diagnostic configuration register 2.
Figure 138. MBDIAG_CFG2 Register
7
6
5
4
PD_MBIAS_FA PD_MBIAS_FA PD_MBIAS_FA PD_MBIAS_FA
ULT1
ULT2
ULT3
ULT4
RW-0h
RW-0h
RW-0h
RW-1h
3
2
1
Reserved
Reserved
RW-0h
R-0h
0
Table 94. MBDIAG_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PD_MBIAS_FAULT1
RW
0h
Powerdown configuration of MICBIAS fault 1
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when low current fault
occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when high current
fault occurs and P0_R40, PD_ON_FLT_CFG = 2d
6
PD_MBIAS_FAULT2
RW
0h
Powerdown configuration of MICBIAS fault 2
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when over voltage
fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when low current fault
occurs and P0_R40, PD_ON_FLT_CFG = 2d
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Table 94. MBDIAG_CFG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
PD_MBIAS_FAULT3
RW
0h
Powerdown configuration of MICBIAS fault 3
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when over
temperature fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when over voltage
fault occurs and P0_R40, PD_ON_FLT_CFG = 2d
4
PD_MBIAS_FAULT4
RW
1h
Powerdown configuration of MICBIAS fault 4
0d = No powerdown when MICBIAS fault detected
1d = MICBIAS and all ADC channels gets powerdown when high current
fault occurs and P0_R40, PD_ON_FLT_CFG = 1d
1d = MICBIAS and all ADC channels gets powerdown when over
temperature fault occurs and P0_R40, PD_ON_FLT_CFG = 2d. It is
recommended to use this setting to protect chip from over temperature fault.
3
Reserved
RW
0h
Reserved
2-0
Reserved
R
0h
Reserved
8.6.1.3.44 BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = D0h]
This register is the MICBIAS configuration register.
Figure 139. BIAS_CFG Register
7
6
5
MBIAS_VAL[3:0]
RW-Dh
4
3
2
1
Reserved
R-0h
0
Reserved
RW-0h
Table 95. BIAS_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
MBIAS_VAL[3:0]
RW
Dh
MICBIAS value.
0d = Reserved
1d = Reserved
2d = Reserved
3d = Reserved
4d = Reserved
5d = Reserved
6d = Reserved
7d = Microphone bias is set to 5 V
8d = Microphone bias is set to 5.5 V
9d = Microphone bias is set to 6 V
10d = Microphone bias is set to 6.5 V
11d = Microphone bias is set to 7 V
12d = Microphone bias is set to 7.5 V
13d = Microphone bias is set to 8 V
14d = Microphone bias is set to 8.5 V
15d = Microphone bias is set to 9 V
3-2
Reserved
R
0h
Reserved
1-0
Reserved
RW
0h
Reserved
8.6.1.3.45 CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 10h]
This register is configuration register 0 for channel 1.
Figure 140. CH1_CFG0 Register
7
98
6
5
4
CH1_INTYP
CH1_INSRC[1:0]
CH1_DC
RW-0h
RW-0h
RW-1h
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3
CH1_MIC_IN_
RANGE
RW-0h
2
1
0
CH1_PGA_CFG[1:0]
CH1_AGCEN
RW-0h
RW-0h
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 96. CH1_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
CH1_INTYP
RW
0h
Channel 1 input type.
0d = Microphone input
1d = Line input
CH1_INSRC[1:0]
RW
0h
Channel 1 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
CH1_DC
RW
1h
Channel 1 input coupling.
0d = AC-coupled input
1d = DC-coupled input
3
CH1_MIC_IN_RANGE
RW
0h
Channel 1 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS
supported provided DC differential common mode voltage IN1P - IN1M < 4.2
V. Single-ended AC signal 1-VRMS supported provided DC common mode
voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to
14.14 V or single ended 7.07 V supported. User rquired to adjust the
channel gain and digital volume control based on the max signal level used
in system.
CH1_PGA_CFG[1:0]
RW
0h
Channel 1 CMRR Configuration.
0d = High SNR performance mode
1d = Reserved
2d = High CMRR performance mode
3d = Reserved
CH1_AGCEN
RW
0h
Channel 1 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
7
6-5
2-1
0
8.6.1.3.46 CH1_CFG1 Register (page = 0x00, address = 0x3D) [reset = 0h]
This register is configuration register 1 for channel 1.
Figure 141. CH1_CFG1 Register
7
6
5
4
3
2
1
Reserved
RW-0h
CH1_GAIN[5:0]
RW-0h
0
Reserved
R-0h
Table 97. CH1_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH1_GAIN[5:0]
RW
0h
Channel 1 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
8.6.1.3.47 CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
This register is configuration register 2 for channel 1.
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Figure 142. CH1_CFG2 Register
7
6
5
4
3
2
1
0
CH1_DVOL[7:0]
RW-C9h
Table 98. CH1_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH1_DVOL[7:0]
RW
C9h
Channel 1 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.3.48 CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
This register is configuration register 3 for channel 1.
Figure 143. CH1_CFG3 Register
7
6
5
4
3
2
CH1_GCAL[3:0]
RW-8h
1
0
Reserved
R-0h
Table 99. CH1_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH1_GCAL[3:0]
RW
8h
Channel 1 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
8.6.1.3.49 CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
This register is configuration register 4 for channel 1.
Figure 144. CH1_CFG4 Register
7
6
5
4
3
2
1
0
CH1_PCAL[7:0]
RW-0h
Table 100. CH1_CFG4 Register Field Descriptions
100
Bit
Field
Type
Reset
Description
7-0
CH1_PCAL[7:0]
RW
0h
Channel 1 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.6.1.3.50 CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 10h]
This register is configuration register 0 for channel 2.
Figure 145. CH2_CFG0 Register
7
6
5
4
CH2_INTYP
CH2_INSRC[1:0]
CH2_DC
RW-0h
RW-0h
RW-1h
3
CH2_MIC_IN_
RANGE
RW-0h
2
1
0
CH2_PGA_CFG[1:0]
CH2_AGCEN
RW-0h
RW-0h
Table 101. CH2_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
CH2_INTYP
RW
0h
Channel 2 input type.
0d = Microphone input
1d = Line input
CH2_INSRC[1:0]
RW
0h
Channel 2 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
CH2_DC
RW
1h
Channel 2 input coupling.
0d = AC-coupled input
1d = DC-coupled input
3
CH2_MIC_IN_RANGE
RW
0h
Channel 2 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS
supported provided DC differential common mode voltage IN1P - IN1M < 4.2
V. Single-ended AC signal 1-VRMS supported provided DC common mode
voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to
14.14 V or single ended 7.07 V supported. User rquired to adjust the
channel gain and digital volume control based on the max signal level used
in system.
CH2_PGA_CFG[1:0]
RW
0h
Channel 2 CMRR Configuration.
0d = High SNR performance mode
1d = Reserved
2d = High CMRR performance mode
3d = Reserved
CH2_AGCEN
RW
0h
Channel 2 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
7
6-5
2-1
0
8.6.1.3.51 CH2_CFG1 Register (page = 0x00, address = 0x42) [reset = 0h]
This register is configuration register 1 for channel 2.
Figure 146. CH2_CFG1 Register
7
6
5
4
3
2
1
Reserved
RW-0h
CH2_GAIN[5:0]
RW-0h
0
Reserved
R-0h
Table 102. CH2_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH2_GAIN[5:0]
RW
0h
Channel 2 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
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8.6.1.3.52 CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
This register is configuration register 2 for channel 2.
Figure 147. CH2_CFG2 Register
7
6
5
4
3
2
1
0
CH2_DVOL[7:0]
RW-C9h
Table 103. CH2_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH2_DVOL[7:0]
RW
C9h
Channel 2 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.3.53 CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
This register is configuration register 3 for channel 2.
Figure 148. CH2_CFG3 Register
7
6
5
4
3
2
CH2_GCAL[3:0]
RW-8h
1
0
Reserved
R-0h
Table 104. CH2_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH2_GCAL[3:0]
RW
8h
Channel 2 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
8.6.1.3.54 CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
This register is configuration register 4 for channel 2.
Figure 149. CH2_CFG4 Register
7
6
5
4
3
2
1
0
CH2_PCAL[7:0]
RW-0h
102
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 105. CH2_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH2_PCAL[7:0]
RW
0h
Channel 2 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
8.6.1.3.55 CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 10h]
This register is configuration register 0 for channel 3.
Figure 150. CH3_CFG0 Register
7
6
5
4
CH3_INTYP
CH3_INSRC[1:0]
CH3_DC
RW-0h
RW-0h
RW-1h
3
CH3_MIC_IN_
RANGE
RW-0h
2
1
0
CH3_PGA_CFG[1:0]
CH3_AGCEN
RW-0h
RW-0h
Table 106. CH3_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
CH3_INTYP
RW
0h
Channel 3 input type.
0d = Microphone input
1d = Line input
CH3_INSRC[1:0]
RW
0h
Channel 3 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
CH3_DC
RW
1h
Channel 3 input coupling.
0d = AC-coupled input
1d = DC-coupled input
3
CH3_MIC_IN_RANGE
RW
0h
Channel 3 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS
supported provided DC differential common mode voltage IN1P - IN1M < 4.2
V. Single-ended AC signal 1-VRMS supported provided DC common mode
voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to
14.14 V or single ended 7.07 V supported. User rquired to adjust the
channel gain and digital volume control based on the max signal level used
in system.
CH3_PGA_CFG[1:0]
RW
0h
Channel 3 CMRR Configuration.
0d = High SNR performance mode
1d = Reserved
2d = High CMRR performance mode
3d = Reserved
CH3_AGCEN
RW
0h
Channel 3 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
7
6-5
2-1
0
8.6.1.3.56 CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h]
This register is configuration register 1 for channel 3.
Figure 151. CH3_CFG1 Register
7
6
5
4
CH3_GAIN[5:0]
RW-0h
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3
2
1
Reserved
RW-0h
0
Reserved
R-0h
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Table 107. CH3_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH3_GAIN[5:0]
RW
0h
Channel 3 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
8.6.1.3.57 CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
This register is configuration register 2 for channel 3.
Figure 152. CH3_CFG2 Register
7
6
5
4
3
2
1
0
CH3_DVOL[7:0]
RW-C9h
Table 108. CH3_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH3_DVOL[7:0]
RW
C9h
Channel 3 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.3.58 CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
This register is configuration register 3 for channel 3.
Figure 153. CH3_CFG3 Register
7
6
5
4
3
CH3_GCAL[3:0]
RW-8h
2
1
0
Reserved
R-0h
Table 109. CH3_CFG3 Register Field Descriptions
104
Bit
Field
Type
Reset
Description
7-4
CH3_GCAL[3:0]
RW
8h
Channel 3 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
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8.6.1.3.59 CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
This register is configuration register 4 for channel 3.
Figure 154. CH3_CFG4 Register
7
6
5
4
3
2
1
0
CH3_PCAL[7:0]
RW-0h
Table 110. CH3_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH3_PCAL[7:0]
RW
0h
Channel 3 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
8.6.1.3.60 CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 10h]
This register is configuration register 0 for channel 4.
Figure 155. CH4_CFG0 Register
7
6
5
4
CH4_INTYP
CH4_INSRC[1:0]
CH4_DC
RW-0h
RW-0h
RW-1h
3
CH4_MIC_IN_
RANGE
RW-0h
2
1
0
CH4_PGA_CFG[1:0]
CH4_AGCEN
RW-0h
RW-0h
Table 111. CH4_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
CH4_INTYP
RW
0h
Channel 4 input type.
0d = Microphone input
1d = Line input
CH4_INSRC[1:0]
RW
0h
Channel 4 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
3d = Reserved
4
CH4_DC
RW
1h
Channel 4 input coupling.
0d = AC-coupled input
1d = DC-coupled input
3
CH4_MIC_IN_RANGE
RW
0h
Channel 4 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS
supported provided DC differential common mode voltage IN1P - IN1M < 4.2
V. Single-ended AC signal 1-VRMS supported provided DC common mode
voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to
14.14 V or single ended 7.07 V supported. User rquired to adjust the
channel gain and digital volume control based on the max signal level used
in system.
CH4_PGA_CFG[1:0]
RW
0h
Channel 4 CMRR Configuration.
0d = High SNR performance mode
1d = Reserved
2d = High CMRR performance mode
3d = Reserved
CH4_AGCEN
RW
0h
Channel 4 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
7
6-5
2-1
0
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8.6.1.3.61 CH4_CFG1 Register (page = 0x00, address = 0x4C) [reset = 0h]
This register is configuration register 1 for channel 4.
Figure 156. CH4_CFG1 Register
7
6
5
4
3
2
1
Reserved
RW-0h
CH4_GAIN[5:0]
RW-0h
0
Reserved
R-0h
Table 112. CH4_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH4_GAIN[5:0]
RW
0h
Channel 4 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
8.6.1.3.62 CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
This register is configuration register 2 for channel 4.
Figure 157. CH4_CFG2 Register
7
6
5
4
3
2
1
0
CH4_DVOL[7:0]
RW-C9h
Table 113. CH4_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH4_DVOL[7:0]
RW
C9h
Channel 4 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.3.63 CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
This register is configuration register 3 for channel 4.
Figure 158. CH4_CFG3 Register
7
6
5
CH4_GCAL[3:0]
RW-8h
106
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4
3
2
1
0
Reserved
R-0h
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 114. CH4_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH4_GCAL[3:0]
RW
8h
Channel 4 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
8.6.1.3.64 CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
This register is configuration register 4 for channel 4.
Figure 159. CH4_CFG4 Register
7
6
5
4
3
2
1
0
CH4_PCAL[7:0]
RW-0h
Table 115. CH4_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH4_PCAL[7:0]
RW
0h
Channel 4 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
8.6.1.3.65 CH5_CFG0 Register (page = 0x00, address = 0x50) [reset = 10h]
This register is configuration register 0 for channel 5.
Figure 160. CH5_CFG0 Register
7
6
5
4
CH5_INTYP
CH5_INSRC[1:0]
CH5_DC
RW-0h
RW-0h
RW-1h
3
CH5_MIC_IN_
RANGE
RW-0h
2
1
0
CH5_PGA_CFG[1:0]
CH5_AGCEN
RW-0h
RW-0h
Table 116. CH5_CFG0 Register Field Descriptions
Bit
7
6-5
4
Field
Type
Reset
Description
CH5_INTYP
RW
0h
Channel 5 input type.
0d = Microphone input
1d = Line input
CH5_INSRC[1:0]
RW
0h
Channel 5 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
CH5_DC
RW
1h
Channel 5 input coupling.
0d = AC-coupled input
1d = DC-coupled input
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Table 116. CH5_CFG0 Register Field Descriptions (continued)
Bit
3
2-1
0
Field
Type
Reset
Description
CH5_MIC_IN_RANGE
RW
0h
Channel 5 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS
supported provided DC differential common mode voltage IN1P - IN1M < 4.2
V. Single-ended AC signal 1-VRMS supported provided DC common mode
voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to
14.14 V or single ended 7.07 V supported. User rquired to adjust the
channel gain and digital volume control based on the max signal level used
in system.
CH5_PGA_CFG[1:0]
RW
0h
Channel 5 CMRR Configuration.
0d = High SNR performance mode
1d = Reserved
2d = High CMRR performance mode
3d = Reserved
CH5_AGCEN
RW
0h
Channel 5 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
8.6.1.3.66 CH5_CFG1 Register (page = 0x00, address = 0x51) [reset = 0h]
This register is configuration register 1 for channel 5. Applicable only for PCM6x60-Q1.
Figure 161. CH5_CFG1 Register
7
6
5
4
3
2
CH5_GAIN[5:0]
RW-0h
1
Reserved
RW-0h
0
Reserved
R-0h
Table 117. CH5_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
CH5_GAIN[5:0]
RW
0h
Channel 5 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
8.6.1.3.67 CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
This register is configuration register 2 for channel 5. Applicable only for PCM6x60-Q1.
Figure 162. CH5_CFG2 Register
7
6
5
4
3
2
1
0
CH5_DVOL[7:0]
RW-C9h
108
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 118. CH5_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH5_DVOL[7:0]
RW
C9h
Channel 5 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.3.68 CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
This register is configuration register 3 for channel 5. Applicable only for PCM6x60-Q1.
Figure 163. CH5_CFG3 Register
7
6
5
4
3
2
CH5_GCAL[3:0]
RW-8h
1
0
Reserved
R-0h
Table 119. CH5_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH5_GCAL[3:0]
RW
8h
Channel 5 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
8.6.1.3.69 CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
This register is configuration register 4 for channel 5. Applicable only for PCM6x60-Q1.
Figure 164. CH5_CFG4 Register
7
6
5
4
3
2
1
0
CH5_PCAL[7:0]
RW-0h
Table 120. CH5_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH5_PCAL[7:0]
RW
0h
Channel 5 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
8.6.1.3.70 CH6_CFG0 Register (page = 0x00, address = 0x55) [reset = 10h]
This register is configuration register 0 for channel 6.
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Figure 165. CH6_CFG0 Register
7
6
5
4
CH6_INTYP
CH6_INSRC[1:0]
CH6_DC
RW-0h
RW-0h
RW-1h
3
CH6_MIC_IN_
RANGE
RW-0h
2
1
0
CH6_PGA_CFG[1:0]
CH6_AGCEN
RW-0h
RW-0h
Table 121. CH6_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
CH6_INTYP
RW
0h
Channel 6 input type.
0d = Microphone input
1d = Line input
CH6_INSRC[1:0]
RW
0h
Channel 6 input configuration.
0d = Analog differential input
1d = Analog single-ended input
2d = Reserved
4
CH6_DC
RW
1h
Channel 6 input coupling.
0d = AC-coupled input
1d = DC-coupled input
3
CH6_MIC_IN_RANGE
RW
0h
Channel 6 microphone input range.
0d = Low swing mode; Differential input AC signal full-scale of 2-VRMS
supported provided DC differential common mode voltage IN1P - IN1M < 4.2
V. Single-ended AC signal 1-VRMS supported provided DC common mode
voltage is < 2.1 V.
1d = High swing mode; Differential Input IN1P-IN1M peak voltage up to
14.14 V or single ended 7.07 V supported. User rquired to adjust the
channel gain and digital volume control based on the max signal level used
in system.
CH6_PGA_CFG[1:0]
RW
0h
Channel 6 CMRR Configuration.
0d = High SNR performance mode
1d = Reserved
2d = High CMRR performance mode
3d = Reserved
CH6_AGCEN
RW
0h
Channel 6 automatic gain controller (AGC) setting.
0d = AGC disabled
1d = AGC enabled based on the configuration of bit 3 in register 108
(P0_R108); This must be used only with AC-coupled input
7
6-5
2-1
0
8.6.1.3.71 CH6_CFG1 Register (page = 0x00, address = 0x56) [reset = 0h]
This register is configuration register 1 for channel 6. Applicable only for PCM6x60-Q1.
Figure 166. CH6_CFG1 Register
7
6
5
4
3
2
CH6_GAIN[5:0]
RW-0h
1
Reserved
RW-0h
0
Reserved
R-0h
Table 122. CH6_CFG1 Register Field Descriptions
110
Bit
Field
Type
Reset
Description
7-2
CH6_GAIN[5:0]
RW
0h
Channel 6 gain.
0d = Channel gain is set to 0 dB
1d = Channel gain is set to 1 dB
2d = Channel gain is set to 2 dB
3d to 41d = Channel gain is set as per configuration
42d = Channel gain is set to 42 dB
43d to 63d = Reserved
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.6.1.3.72 CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
This register is configuration register 2 for channel 6. Applicable only for PCM6x60-Q1.
Figure 167. CH6_CFG2 Register
7
6
5
4
3
2
1
0
CH6_DVOL[7:0]
RW-C9h
Table 123. CH6_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH6_DVOL[7:0]
RW
C9h
Channel 6 digital volume control.
0d = Digital volume is muted
1d = Digital volume control is set to -100 dB
2d = Digital volume control is set to -99.5 dB
3d to 200d = Digital volume control is set as per configuration
201d = Digital volume control is set to 0 dB
202d = Digital volume control is set to 0.5 dB
203d to 253d = Digital volume control is set as per configuration
254d = Digital volume control is set to 26.5 dB
255d = Digital volume control is set to 27 dB
8.6.1.3.73 CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
This register is configuration register 3 for channel 6. Applicable only for PCM6x60-Q1.
Figure 168. CH6_CFG3 Register
7
6
5
4
3
2
CH6_GCAL[3:0]
RW-8h
1
0
Reserved
R-0h
Table 124. CH6_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CH6_GCAL[3:0]
RW
8h
Channel 6 gain calibration.
0d = Gain calibration is set to -0.8 dB
1d = Gain calibration is set to -0.7 dB
2d = Gain calibration is set to -0.6 dB
3d to 7d = Gain calibration is set as per configuration
8d = Gain calibration is set to 0 dB
9d = Gain calibration is set to 0.1 dB
10d to 13d = Gain calibration is set as per configuration
14d = Gain calibration is set to 0.6 dB
15d = Gain calibration is set to 0.7 dB
3-0
Reserved
R
0h
Reserved
8.6.1.3.74 CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
This register is configuration register 4 for channel 6. Applicable only for PCM6x60-Q1.
Figure 169. CH6_CFG4 Register
7
6
5
4
3
2
1
0
CH6_PCAL[7:0]
RW-0h
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Table 125. CH6_CFG4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CH6_PCAL[7:0]
RW
0h
Channel 6 phase calibration with modulator clock resolution.
0d = No phase calibration
1d = Phase calibration delay is set to one cycle of the modulator clock
2d = Phase calibration delay is set to two cycles of the modulator clock
3d to 254d = Phase calibration delay as per configuration
255d = Phase calibration delay is set to 255 cycles of the modulator clock
8.6.1.3.75 DIAG_CFG0 Register (page = 0x00, address = 0x64) [reset = 0h]
This register is configuration register 0 for input fault diagnostics setting.
Figure 170. DIAG_CFG0 Register
7
6
5
4
3
2
CH1_DIAG_EN CH2_DIAG_EN CH3_DIAG_EN CH4_DIAG_EN CH5_DIAG_EN CH6_DIAG_EN
RW-0h
RW-0h
RW-0h
RW-0h
RW-0h
1
INCL_SE_INM
RW-0h
RW-0h
0
INCL_AC_COU
P
RW-0h
Table 126. DIAG_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_DIAG_EN
RW
0h
Channel 1 input (IN1P and IN1M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
6
CH2_DIAG_EN
RW
0h
Channel 2 input (IN2P and IN2M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
5
CH3_DIAG_EN
RW
0h
Channel 3 input (IN3P and IN3M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
4
CH4_DIAG_EN
RW
0h
Channel 4 input (IN4P and IN4M) scan for diagnostics.
0d = Diagnostic disabled
1d = Diagnostic enabled
3
CH5_DIAG_EN
RW
0h
Channel 5 input (IN5P and IN5M) scan for diagnostics. Applicable only for
PCM6x60-Q1.
0d = Diagnostic disabled
1d = Diagnostic enabled
2
CH6_DIAG_EN
RW
0h
Channel 6 input (IN6P and IN6M) scan for diagnostics. Applicable only for
PCM6x60-Q1.
0d = Diagnostic disabled
1d = Diagnostic enabled
1
INCL_SE_INM
RW
0h
INxM pin diagnostics scan selection for single-ended configuration.
0d = INxM pins of single-ended channels are excluded for diagnosis
1d = INxM pins of single-ended channels are included for diagnosis
0
INCL_AC_COUP
RW
0h
AC-coupled channels pins scan selection for diagnostics.
0d = INxP and INxM pins of AC-coupled channels are excluded for
diagnosis
1d = INxP and INxM pins of AC-coupled channels are included for diagnosis
8.6.1.3.76 DIAG_CFG1 Register (page = 0x00, address = 0x65) [reset = 37h]
This register is configuration register 1 for input fault diagnostics setting.
Figure 171. DIAG_CFG1 Register
7
112
6
5
DIAG_SHT_TERM[3:0]
RW-3h
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4
3
2
1
DIAG_SHT_VBAT_IN[3:0]
RW-7h
0
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 127. DIAG_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_SHT_TERM[3:0]
RW
3h
INxP and INxM terminal short detect threshold.
0d = INxP and INxM terminal short detect threshold value is 0 mV (typ)
1d = INxP and INxM terminal short detect threshold value is 30 mV (typ)
2d = INxP and INxM terminal short detect threshold value is 60 mV (typ)
10d to 13d = INxP and INxM terminal short detect threshold value is set as
per configuration
14d = INxP and INxM terminal short detect threshold value is 420 mV (typ)
15d = INxP and INxM terminal short detect threshold value is 450 mV (typ)
3-0
DIAG_SHT_VBAT_IN[3:0]
RW
7h
Short to VBAT_IN detect threshold.
0d = Short to VBAT_IN detect threshold value is 0 mV (typ)
1d = Short to VBAT_IN detect threshold value is 30 mV (typ)
2d = Short to VBAT_IN detect threshold value is 60 mV (typ)
10d to 13d = Short to VBAT_IN detect threshold value is set as per
configuration
14d = Short to VBAT_IN detect threshold value is 420 mV (typ)
15d = Short to VBAT_IN detect threshold value is 450 mV (typ)
8.6.1.3.77 DIAG_CFG2 Register (page = 0x00, address = 0x66) [reset = 87h]
This register is configuration register 2 for input fault diagnostics setting.
Figure 172. DIAG_CFG2 Register
7
6
5
DIAG_SHT_GND[3:0]
RW-8h
4
3
2
1
DIAG_SHT_MICBIAS[3:0]
RW-7h
0
Table 128. DIAG_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_SHT_GND[3:0]
RW
8h
Short to ground detect threshold.
0d = Short to ground detect threshold value is 0 mV (typ)
1d = Short to ground detect threshold value is 60 mV (typ)
2d = Short to ground detect threshold value is 120 mV (typ)
10d to 13d = Short to ground detect threshold value is set as per
configuration
14d = Short to ground detect threshold value is 840 mV (typ)
15d = Short to ground detect threshold value is 900 mV (typ)
3-0
DIAG_SHT_MICBIAS[3:0]
RW
7h
Short to MICBIAS detect threshold.
0d = Short to MICBIAS detect threshold value is 0 mV (typ)
1d = Short to MICBIAS detect threshold value is 30 mV (typ)
2d = Short to MICBIAS detect threshold value is 60 mV (typ)
10d to 13d = Short to MICBIAS detect threshold value is set as per
configuration
14d = Short to MICBIAS detect threshold value is 420 mV (typ)
15d = Short to MICBIAS detect threshold value is 450 mV (typ)
8.6.1.3.78 DIAG_CFG3 Register (page = 0x00, address = 0x67) [reset = B8h]
This register is configuration register 3 for input fault diagnostics setting.
Figure 173. DIAG_CFG3 Register
7
6
5
4
3
2
REP_RATE[1:0]
Reserved
FAULT_DBNCE_SEL[1:0]
RW-2h
RW-3h
RW-2h
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1
VSHORT_DBN
CE
RW-0h
0
DIAG_2X_THR
ES
RW-0h
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Table 129. DIAG_CFG3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
REP_RATE[1:0]
RW
2h
Fault monitoring scan repetition rate.
0d = Continuos back to back scanning of selected channels input pins
without any idle time
1d = Fault monitoring repetition rate of 1 ms for selected channels input pins
scanning
2d = Fault monitoring repetition rate of 4 ms for selected channels input pins
scanning
3d = Fault monitoring repetition rate of 8 ms for selected channels input pins
scanning
5-4
Reserved
RW
3h
Reserved
3-2
FAULT_DBNCE_SEL[1:0]
RW
2h
Debounce count for all the faults (except VBAT_IN short when VBAT_IN <
MICBIAS).
0d = 16 counts for debounce to filter-out any false faults detection
1d = 8 counts for debounce to filter-out any false faults detection
2d = 4 counts for debounce to filter-out any false faults detection
3d = No debounce count
1
VSHORT_DBNCE
RW
0h
VBAT_IN short debounce count only when VBAT_IN < MICBIAS.
0d = 16 counts for debounce to filter-out any false faults detection
1d = 8 counts for debounce to filter-out any false faults detection
0
DIAG_2X_THRES
RW
0h
Diagnostic thresholds range scale.
0d = Thresholds same as configured in P0_R101 and P0_R102
1d = All the configuration thresholds gets scale by 2 times
8.6.1.3.79 DIAG_CFG4 Register (page = 0x00, address = 0x68) [reset = 0h]
This register is configuration register 4 for input fault diagnostics setting.
Figure 174. DIAG_CFG4 Register
7
6
DIAG_MOV_AVG_CFG[1:0]
RW-0h
5
MOV_AVG_DI
S_MBIAS_LOA
D
RW-0h
4
MOV_AVG_DI
S_TEMP_SEN
S
RW-0h
3
2
1
0
Reserved
R-0h
Table 130. DIAG_CFG4 Register Field Descriptions
Bit
Field
Reset
Description
7-6
DIAG_MOV_AVG_CFG[1:0 RW
]
0h
Moving average configuration.
0d = Moving average disabled
1d = Moving average enabled with 0.5 weightage for old scanned data and
new scanned data
2d = Moving average enabled with 0.75 weightage for old scanned data and
0.25 weightage for new scanned data
3d = Reserved
5
MOV_AVG_DIS_MBIAS_L
OAD
RW
0h
Moving average configuration for MICBIAS high and low load current fault
detection
0d = Moving average as defined by DIAG_MOV_AVG_CFG setting
1d = Moving average is forced disabled for MICBIAS load current fault
detection to achieve faster response time
4
MOV_AVG_DIS_TEMP_S
ENS
RW
0h
Moving average configuration for over temperature fault detection
0d = Moving average as defined by DIAG_MOV_AVG_CFG setting
1d = Moving average is forced disabled for over temperature fault detection
to achieve faster response time
Reserved
R
0h
Reserved
3-0
Type
8.6.1.3.80 DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
This register is the digital signal processor (DSP) configuration register 0.
114
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Figure 175. DSP_CFG0 Register
7
6
5
Reserved
R-0h
4
3
DECI_FILT[1:0]
RW-0h
2
1
CH_SUM[1:0]
RW-0h
0
HPF_SEL[1:0]
RW-1h
Table 131. DSP_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
Reserved
R
0h
Reserved
5-4
DECI_FILT[1:0]
RW
0h
Decimation filter response.
0d = Linear phase
1d = Low latency
2d = Ultra-low latency
3-2
CH_SUM[1:0]
RW
0h
Channel summation mode for higher SNR
0d = Channel summation mode is disabled
1d = 2-channel summation mode is enabled to generate a (CH1 + CH2) / 2
and a (CH3 + CH4) / 2 output
2d = 4-channel summation mode is enabled to generate a (CH1 + CH2 +
CH3 + CH4) / 4 output
3d = Reserved
1-0
HPF_SEL[1:0]
RW
1h
High-pass filter (HPF) selection.
0d = Programmable first-order IIR filter for a custom HPF with default
coefficient values in P4_R72 to P4_R83 set as the all-pass filter
1d = HPF with a cutoff of 0.00025 x fS (12 Hz at fS = 48 kHz) is selected
2d = HPF with a cutoff of 0.002 x fS (96 Hz at fS = 48 kHz) is selected
3d = HPF with a cutoff of 0.008 x fS (384 Hz at fS = 48 kHz) is selected
8.6.1.3.81 DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 48h]
This register is the digital signal processor (DSP) configuration register 1.
Figure 176. DSP_CFG1 Register
7
6
5
DVOL_GANG
BIQUAD_CFG[1:0]
RW-0h
RW-2h
4
DISABLE_SOF
T_STEP
RW-0h
3
2
1
0
AGC_SEL
Reserved
Reserved
RW-1h
RW-0h
R-0h
Table 132. DSP_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
DVOL_GANG
RW
0h
DVOL control ganged across channels.
0d = Each channel has its own DVOL CTRL settings as programmed in the
CHx_DVOL bits
1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL)
irrespective of whether channel 1 is turned on or not
BIQUAD_CFG[1:0]
RW
2h
Number of biquads per channel configuration.
0d = No biquads per channel; biquads are all disabled
1d = 1 biquad per channel
2d = 2 biquads per channel
3d = 3 biquads per channel
4
DISABLE_SOFT_STEP
RW
0h
Soft-stepping disable during DVOL change, mute, and unmute.
0d = Soft-stepping enabled
1d = Soft-stepping disabled
3
AGC_SEL
RW
1h
AGC master enable setting.
0d = Reserved; Write always 1 to this register bit
1d = AGC selected as configured for each channel using CHx_CFG0
register
2
Reserved
RW
0h
Reserved
1-0
Reserved
R
0h
Reserved
7
6-5
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8.6.1.3.82 AGC_CFG0 Register (page = 0x00, address = 0x70) [reset = E7h]
This register is the automatic gain controller (AGC) configuration register 0.
Figure 177. AGC_CFG0 Register
7
6
5
4
3
2
1
AGC_MAXGAIN[3:0]
RW-7h
AGC_LVL[3:0]
RW-Eh
0
Table 133. AGC_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
AGC_LVL[3:0]
RW
Eh
AGC output signal target level.
0d = Output signal target level is -6 dB
1d = Output signal target level is -8 dB
2d = Output signal target level is -10 dB
3d to 13d = Output signal target level is as per configuration
14d = Output signal target level is -34 dB
15d = Output signal target level is -36 dB
3-0
AGC_MAXGAIN[3:0]
RW
7h
AGC maximum gain allowed.
0d = Maximum gain allowed is 3 dB
1d = Maximum gain allowed is 6 dB
2d = Maximum gain allowed is 9 dB
3d to 11d = Maximum gain allowed is as per configuration
12d = Maximum gain allowed is 39 dB
13d = Maximum gain allowed is 42 dB
14d to 15d = Reserved
8.6.1.3.83 IN_CH_EN Register (page = 0x00, address = 0x73) [reset = FCh]
This register is the input channel enable configuration register.
Figure 178. IN_CH_EN Register
7
IN_CH1_EN
RW-1h
6
IN_CH2_EN
RW-1h
5
IN_CH3_EN
RW-1h
4
IN_CH4_EN
RW-1h
3
IN_CH5_EN
RW-1h
2
IN_CH6_EN
RW-1h
1
Reserved
RW-0h
0
Reserved
RW-0h
Table 134. IN_CH_EN Register Field Descriptions
Bit
116
Field
Type
Reset
Description
7
IN_CH1_EN
RW
1h
Input channel 1 enable setting.
0d = Channel 1 is disabled
1d = Channel 1 is enabled
6
IN_CH2_EN
RW
1h
Input channel 2 enable setting.
0d = Channel 2 is disabled
1d = Channel 2 is enabled
5
IN_CH3_EN
RW
1h
Input channel 3 enable setting.
0d = Channel 3 is disabled
1d = Channel 3 is enabled
4
IN_CH4_EN
RW
1h
Input channel 4 enable setting.
0d = Channel 4 is disabled
1d = Channel 4 is enabled
3
IN_CH5_EN
RW
1h
Input channel 5 enable setting. Applicable only for PCM6x60-Q1.
0d = Channel 5 is disabled
1d = Channel 5 is enabled
2
IN_CH6_EN
RW
1h
Input channel 6 enable setting. Applicable only for PCM6x60-Q1.
0d = Channel 6 is disabled
1d = Channel 6 is enabled
1
Reserved
RW
0h
Reserved
0
Reserved
RW
0h
Reserved
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8.6.1.3.84 ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
This register is the ASI output channel enable configuration register.
Figure 179. ASI_OUT_CH_EN Register
7
ASI_OUT_CH1
_EN
RW-0h
6
ASI_OUT_CH2
_EN
RW-0h
5
ASI_OUT_CH3
_EN
RW-0h
4
ASI_OUT_CH4
_EN
RW-0h
3
ASI_OUT_CH5
_EN
RW-0h
2
ASI_OUT_CH6
_EN
RW-0h
1
0
Reserved
Reserved
RW-0h
RW-0h
Table 135. ASI_OUT_CH_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ASI_OUT_CH1_EN
RW
0h
ASI output channel 1 enable setting.
0d = Channel 1 output slot is in a tri-state condition
1d = Channel 1 output slot is enabled
6
ASI_OUT_CH2_EN
RW
0h
ASI output channel 2 enable setting.
0d = Channel 2 output slot is in a tri-state condition
1d = Channel 2 output slot is enabled
5
ASI_OUT_CH3_EN
RW
0h
ASI output channel 3 enable setting.
0d = Channel 3 output slot is in a tri-state condition
1d = Channel 3 output slot is enabled
4
ASI_OUT_CH4_EN
RW
0h
ASI output channel 4 enable setting.
0d = Channel 4 output slot is in a tri-state condition
1d = Channel 4 output slot is enabled
3
ASI_OUT_CH5_EN
RW
0h
ASI output channel 5 enable setting. Applicable only for PCM6x60-Q1.
0d = Channel 5 output slot is in a tri-state condition
1d = Channel 5 output slot is enabled
2
ASI_OUT_CH6_EN
RW
0h
ASI output channel 6 enable setting. Applicable only for PCM6x60-Q1.
0d = Channel 6 output slot is in a tri-state condition
1d = Channel 6 output slot is enabled
1
Reserved
RW
0h
Reserved
0
Reserved
RW
0h
Reserved
8.6.1.3.85 PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
This register is the power-up configuration register.
Figure 180. PWR_CFG Register
7
6
5
MICBIAS_PDZ
ADC_PDZ
PLL_PDZ
RW-0h
RW-0h
RW-0h
4
DYN_CH_PUP
D_EN
RW-0h
3
2
1
0
DYN_MAXCH_SEL[1:0]
Reserved
Reserved
RW-0h
RW-0h
R-0h
Table 136. PWR_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MICBIAS_PDZ
RW
0h
Power control for MICBIAS.
0d = Power down MICBIAS
1d = Power up MICBIAS
6
ADC_PDZ
RW
0h
Power control for ADC channels.
0d = Power down all ADC channels
1d = Power up all enabled ADC channels
5
PLL_PDZ
RW
0h
Power control for the PLL.
0d = Power down the PLL
1d = Power up the PLL
4
DYN_CH_PUPD_EN
RW
0h
Dynamic channel power-up, power-down enable.
0d = Channel power-up, power-down is not supported if any channel
recording is on
1d = Channel can be powered up or down individually, even if channel
recording is on. Do not powered-down channel 1 if this bit is set to '1'
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Table 136. PWR_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-2
DYN_MAXCH_SEL[1:0]
RW
0h
Dynamic mode maximum channel select configuration.
0d = Channel 1 and channel 2 are used with dynamic channel power-up,
power-down feature enabled
1d = Channel 1 to channel 4 are used with dynamic channel power-up,
power-down feature enabled
2d = Channel 1 to channel 6 are used with dynamic channel power-up,
power-down feature enabled
1
Reserved
RW
0h
Reserved
0
Reserved
R
0h
Reserved
8.6.1.3.86 DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
This register is the device status value register 0.
Figure 181. DEV_STS0 Register
7
CH1_STATUS
R-0h
6
CH2_STATUS
R-0h
5
CH3_STATUS
R-0h
4
CH4_STATUS
R-0h
3
CH5_STATUS
R-0h
2
CH6_STATUS
R-0h
1
Reserved
R-0h
0
Reserved
R-0h
Table 137. DEV_STS0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_STATUS
R
0h
ADC channel 1 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
6
CH2_STATUS
R
0h
ADC channel 2 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
5
CH3_STATUS
R
0h
ADC channel 3 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
4
CH4_STATUS
R
0h
ADC channel 4 power status.
0d = ADC channel is powered down
1d = ADC channel is powered up
3
CH5_STATUS
R
0h
ADC channel 5 power status. Applicable only for PCM6x60-Q1.
0d = ADC channel is powered down
1d = ADC channel is powered up
2
CH6_STATUS
R
0h
ADC channel 6 power status. Applicable only for PCM6x60-Q1.
0d = ADC channel is powered down
1d = ADC channel is powered up
1
Reserved
R
0h
Reserved
0
Reserved
R
0h
Reserved
8.6.1.3.87 DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
This register is the device status value register 1.
Figure 182. DEV_STS1 Register
7
118
6
5
4
3
MODE_STS[2:0]
BOOST_STS
MBIAS_STS
R-4h
R-0h
R-0h
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CHx_PD_FLT_
STS
R-0h
1
ALL_CHx_PD_
FLT_STS
R-0h
0
MAN_RCV_PD
_FLT_CHK
RW-0h
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Table 138. DEV_STS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
MODE_STS[2:0]
R
4h
Device mode status.
4d = Device is in sleep mode or software shutdown mode
6d = Device is in active mode with all ADC channels turned off
7d = Device is in active mode with at least one ADC channel turned on
4
BOOST_STS
R
0h
Boost power up status.
0d = Boost is powered down
1d = Boost is powered up
3
MBIAS_STS
R
0h
MICBIAS power up status.
0d = MICBIAS is powered down
1d = MICBIAS is powered up
2
CHx_PD_FLT_STS
R
0h
ADC channel power down status caused by INxx inputs faults.
0d = No ADC channel is powered down caused by INxx inputs faults
1d = Atleast a ADC channel is powered down caused by INxx inputs faults
1
ALL_CHx_PD_FLT_STS
R
0h
ADC channel power down status caused by MICBIAS faults.
0d = No ADC channel is powered down caused by MICBIAS faults
1d = All ADC channels are powered down caused by MICBIAS faults
0
MAN_RCV_PD_FLT_CHK
RW
0h
Manual recovery (self-clearing bit).
0d = No effect
1d = Recheck all fault status and re-powerup ADC channels and/or
MICBIAS if they do not have any faults. Before setting this bit, reset P0_R58
register and re-configure P0_R58 to desired setting only after manual
recover gets over.
8.6.1.3.88 I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
This register returns the I2C transactions checksum value.
Figure 183. I2C_CKSUM Register
7
6
5
4
3
I2C_CKSUM[7:0]
R/W-0h
2
1
0
Table 139. I2C_CKSUM Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
I2C_CKSUM[7:0]
R/W
0h
These bits return the I2C transactions checksum value. Writing to this
register resets the checksum to the written value. This register is updated on
writes to other registers on all pages.
8.6.1.4 Register Description: Page = 0x01
8.6.1.4.1 PAGE_CFG Register (page = 0x01, address = 0x00) [reset = 0h]
The device memory map is divided into pages. This register sets the page.
Figure 184. PAGE_CFG Register
7
6
5
4
3
2
1
0
PAGE[7:0]
RW-0h
Table 140. PAGE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PAGE[7:0]
RW
0h
These bits set the device page.
0d = Page 0
1d = Page 1
...
255d = Page 255
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8.6.1.4.2 MBIAS_LOAD Register (page = 0x01, address = 0x16) [reset = 0h]
This register is the MICBIAS internal load sink configuration register.
Figure 185. MBIAS_LOAD Register
7
MICBIAS_INT_
LOAD_SINK_E
N
RW-0h
6
5
4
3
2
1
MICBIAS_INT_LOAD_SINK_VAL[2:0]
Reserved
RW-0h
R-0h
0
Table 141. MBIAS_LOAD Register Field Descriptions
Bit
Field
Type
Reset
Description
7
MICBIAS_INT_LOAD_SIN
K_EN
RW
0h
MICBIAS internal load sink setting.
0d = MICBIAS internal load sink is enabled with setting automatically
calculated based on device configuration
1d = MICBIAS internal load sink is enabled based on D6-4 register bits; This
setting must be used for single-ended AC-coupled input to support high
signal swing
6-4
MICBIAS_INT_LOAD_SIN
K_VAL[2:0]
RW
0h
MICBIAS internal load sink current value
0d = MICBIAS internal load sink current is
1d = MICBIAS internal load sink current is
2d = MICBIAS internal load sink current is
3d = MICBIAS internal load sink current is
4d = MICBIAS internal load sink current is
5d = MICBIAS internal load sink current is
6d = MICBIAS internal load sink current is
7d = MICBIAS internal load sink current is
Reserved
R
3-0
0h
set to 0 mA (typ)
set to 4.3 mA (typ)
set to 8.6 mA (typ)
set to 12.9 mA (typ)
set to 17.2 mA (typ)
set to 21.5 mA (typ)
set to 25.8 mA (typ)
set to 30.1 mA (typ)
Reserved
8.6.1.4.3 INT_LIVE0 Register (page = 0x01, address = 0x2C) [reset = 0h]
This register is the live Interrupt readback register 0.
Figure 186. INT_LIVE0 Register
7
INT_LIVE0[7]
R-0h
6
INT_LIVE0[6]
R-0h
5
INT_LIVE0[5]
R-0h
4
INT_LIVE0[4]
R-0h
3
Reserved
R-0h
2
Reserved
R-0h
1
Reserved
R-0h
0
Reserved
R-0h
Table 142. INT_LIVE0 Register Field Descriptions
Bit
120
Field
Type
Reset
Description
7
INT_LIVE0[7]
R
0h
Fault status for an ASI bus clock error.
0d = No fault detected
1d = Fault detected
6
INT_LIVE0[6]
R
0h
Status of PLL lock.
0d = No PLL lock detected
1d = PLL lock detected
5
INT_LIVE0[5]
R
0h
Fault status for boost or MICBIAS over temperature.
0d = No fault detected
1d = Fault detected
4
INT_LIVE0[4]
R
0h
Fault status for boost or MICBIAS over current.
0d = No fault detected
1d = Fault detected
3
Reserved
R
0h
Reserved
2
Reserved
R
0h
Reserved
1
Reserved
R
0h
Reserved
0
Reserved
R
0h
Reserved
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8.6.1.4.4 CHx_LIVE Register (page = 0x01, address = 0x2D) [reset = 0h]
This register is the live Interrupt status register for channel level diagnostic summary.
Figure 187. CHx_LIVE Register
7
STS_CHx_LIV
E[7]
R-0h
6
STS_CHx_LIV
E[6]
R-0h
5
STS_CHx_LIV
E[5]
R-0h
4
STS_CHx_LIV
E[4]
R-0h
3
STS_CHx_LIV
E[3]
R-0h
2
STS_CHx_LIV
E[2]
R-0h
1
STS_CHx_LIV
E[1]
R-0h
0
Reserved
R-0h
Table 143. CHx_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
STS_CHx_LIVE[7]
R
0h
Status of CH1_LIVE.
0d = No faults occurred in channel 1
1d = Atleast a fault has occurred in channel 1
6
STS_CHx_LIVE[6]
R
0h
Status of CH2_LIVE.
0d = No faults occurred in channel 2
1d = Atleast a fault has occurred in channel 2
5
STS_CHx_LIVE[5]
R
0h
Status of CH3_LIVE.
0d = No faults occurred in channel 3
1d = Atleast a fault has occurred in channel 3
4
STS_CHx_LIVE[4]
R
0h
Status of CH4_LIVE.
0d = No faults occurred in channel 4
1d = Atleast a fault has occurred in channel 4
3
STS_CHx_LIVE[3]
R
0h
Status of CH5_LIVE. Applicable only for PCM6x60-Q1.
0d = No faults occurred in channel 5
1d = Atleast a fault has occurred in channel 5
2
STS_CHx_LIVE[2]
R
0h
Status of CH6_LIVE. Applicable only for PCM6x60-Q1.
0d = No faults occurred in channel 6
1d = Atleast a fault has occurred in channel 6
1
STS_CHx_LIVE[1]
R
0h
Status of short to VBAT_IN fault detected when VBAT_IN is less than
MICBIAS.
0d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has not
occurred in any channel
1d = Short to VBAT_IN fault when VBAT_IN is less than MICBIAS has
occurred in atleast one channel
0
Reserved
R
0h
Reserved
8.6.1.4.5 CH1_LIVE Register (page = 0x01, address = 0x2E) [reset = 0h]
This register is the live Interrupt status register for channel 1 fault diagnostic
Figure 188. CH1_LIVE Register
7
CH1_LIVE[7]
R-0h
6
CH1_LIVE[6]
R-0h
5
CH1_LIVE[5]
R-0h
4
CH1_LIVE[4]
R-0h
3
CH1_LIVE[3]
R-0h
2
CH1_LIVE[2]
R-0h
1
CH1_LIVE[1]
R-0h
0
CH1_LIVE[0]
R-0h
Table 144. CH1_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1_LIVE[7]
R
0h
Channel 1 open input fault status.
0d = No open input detected
1d = Open input detected
6
CH1_LIVE[6]
R
0h
Channel 1 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
5
CH1_LIVE[5]
R
0h
Channel 1 IN1P short to ground fault status.
0d = IN1P no short to ground detected
1d = IN1P short to ground detected
4
CH1_LIVE[4]
R
0h
Channel 1 IN1M short to ground fault status.
0d = IN1M no short to ground detected
1d = IN1M short to ground detected
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Table 144. CH1_LIVE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
CH1_LIVE[3]
R
0h
Channel 1 IN1P short to MICBIAS fault status.
0d = IN1P no short to MICBIAS detected
1d = IN1P short to MICBIAS detected
2
CH1_LIVE[2]
R
0h
Channel 1 IN1M short to MICBIAS fault status.
0d = IN1M no short to MICBIAS detected
1d = IN1M short to MICBIAS detected
1
CH1_LIVE[1]
R
0h
Channel 1 IN1P short to VBAT_IN fault status.
0d = IN1P no short to VBAT_IN detected
1d = IN1P short to VBAT_IN detected
0
CH1_LIVE[0]
R
0h
Channel 1 IN1M short to VBAT_IN fault status.
0d = IN1M no short to VBAT_IN detected
1d = IN1M short to VBAT_IN detected
8.6.1.4.6 CH2_LIVE Register (page = 0x01, address = 0x2F) [reset = 0h]
This register is the live Interrupt status register for channel 2 fault diagnostic.
Figure 189. CH2_LIVE Register
7
CH2_LIVE[7]
R-0h
6
CH2_LIVE[6]
R-0h
5
CH2_LIVE[5]
R-0h
4
CH2_LIVE[4]
R-0h
3
CH2_LIVE[3]
R-0h
2
CH2_LIVE[2]
R-0h
1
CH2_LIVE[1]
R-0h
0
CH2_LIVE[0]
R-0h
Table 145. CH2_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH2_LIVE[7]
R
0h
Channel 2 open input fault status.
0d = No open input detected
1d = Open input detected
6
CH2_LIVE[6]
R
0h
Channel 2 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
5
CH2_LIVE[5]
R
0h
Channel 2 IN2P short to ground fault status.
0d = IN2P no short to ground detected
1d = IN2P short to ground detected
4
CH2_LIVE[4]
R
0h
Channel 2 IN2M short to ground fault status.
0d = IN2M no short to ground detected
1d = IN2M short to ground detected
3
CH2_LIVE[3]
R
0h
Channel 2 IN2P short to MICBIAS fault status.
0d = IN2P no short to MICBIAS detected
1d = IN2P short to MICBIAS detected
2
CH2_LIVE[2]
R
0h
Channel 2 IN2M short to MICBIAS fault status.
0d = IN2M no short to MICBIAS detected
1d = IN2M short to MICBIAS detected
1
CH2_LIVE[1]
R
0h
Channel 2 IN2P short to VBAT_IN fault status.
0d = IN2P no short to VBAT_IN detected
1d = IN2P short to VBAT_IN detected
0
CH2_LIVE[0]
R
0h
Channel 2 IN2M short to VBAT_IN fault status.
0d = IN2M no short to VBAT_IN detected
1d = IN2M short to VBAT_IN detected
8.6.1.4.7 CH3_LIVE Register (page = 0x01, address = 0x30) [reset = 0h]
This register is the live Interrupt status register for channel3 fault diagnostic
Figure 190. CH3_LIVE Register
7
CH3_LIVE[7]
R-0h
122
6
CH3_LIVE[6]
R-0h
5
CH3_LIVE[5]
R-0h
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4
CH3_LIVE[4]
R-0h
3
CH3_LIVE[3]
R-0h
2
CH3_LIVE[2]
R-0h
1
CH3_LIVE[1]
R-0h
0
CH3_LIVE[0]
R-0h
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 146. CH3_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH3_LIVE[7]
R
0h
Channel 3 open input fault status.
0d = No open input detected
1d = Open input detected
6
CH3_LIVE[6]
R
0h
Channel 3 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
5
CH3_LIVE[5]
R
0h
Channel 3 IN3P short to ground fault status.
0d = IN3P no short to ground detected
1d = IN3P short to ground detected
4
CH3_LIVE[4]
R
0h
Channel 3 IN3M short to ground fault status.
0d = IN3M no short to ground detected
1d = IN3M short to ground detected
3
CH3_LIVE[3]
R
0h
Channel 3 IN3P short to MICBIAS fault status.
0d = IN3P no short to MICBIAS detected
1d = IN3P short to MICBIAS detected
2
CH3_LIVE[2]
R
0h
Channel 3 IN3M short to MICBIAS fault status.
0d = IN3M no short to MICBIAS detected
1d = IN3M short to MICBIAS detected
1
CH3_LIVE[1]
R
0h
Channel 3 IN3P short to VBAT_IN fault status.
0d = IN3P no short to VBAT_IN detected
1d = IN3P short to VBAT_IN detected
0
CH3_LIVE[0]
R
0h
Channel 3 IN3M short to VBAT_IN fault status.
0d = IN3M no short to VBAT_IN detected
1d = IN3M short to VBAT_IN detected
8.6.1.4.8 CH4_LIVE Register (page = 0x01, address = 0x31) [reset = 0h]
This register is the live Interrupt status register for channel 4 fault diagnostic.
Figure 191. CH4_LIVE Register
7
CH4_LIVE[7]
R-0h
6
CH4_LIVE[6]
R-0h
5
CH4_LIVE[5]
R-0h
4
CH4_LIVE[4]
R-0h
3
CH4_LIVE[3]
R-0h
2
CH4_LIVE[2]
R-0h
1
CH4_LIVE[1]
R-0h
0
CH4_LIVE[0]
R-0h
Table 147. CH4_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH4_LIVE[7]
R
0h
Channel 4 open input fault status.
0d = No open input detected
1d = Open input detected
6
CH4_LIVE[6]
R
0h
Channel 4 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
5
CH4_LIVE[5]
R
0h
Channel 4 IN4P short to ground fault status.
0d = IN4P no short to ground detected
1d = IN4P short to ground detected
4
CH4_LIVE[4]
R
0h
Channel 4 IN4M short to ground fault status.
0d = IN4M no short to ground detected
1d = IN4M short to ground detected
3
CH4_LIVE[3]
R
0h
Channel 4 IN4P short to MICBIAS fault status.
0d = IN4P no short to MICBIAS detected
1d = IN4P short to MICBIAS detected
2
CH4_LIVE[2]
R
0h
Channel 4 IN4M short to MICBIAS fault status.
0d = IN4M no short to MICBIAS detected
1d = IN4M short to MICBIAS detected
1
CH4_LIVE[1]
R
0h
Channel 4 IN4P short to VBAT_IN fault status.
0d = IN4P no short to VBAT_IN detected
1d = IN4P short to VBAT_IN detected
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Table 147. CH4_LIVE Register Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
CH4_LIVE[0]
R
0h
Channel 4 IN4M short to VBAT_IN fault status.
0d = IN4M no short to VBAT_IN detected
1d = IN4M short to VBAT_IN detected
8.6.1.4.9 CH5_LIVE Register (page = 0x01, address = 0x32) [reset = 0h]
This register is the live Interrupt status register for channel 5 fault diagnostic. Applicable only for PCM6x60-Q1.
Figure 192. CH5_LIVE Register
7
CH5_LIVE[7]
R-0h
6
CH5_LIVE[6]
R-0h
5
CH5_LIVE[5]
R-0h
4
CH5_LIVE[4]
R-0h
3
CH5_LIVE[3]
R-0h
2
CH5_LIVE[2]
R-0h
1
CH5_LIVE[1]
R-0h
0
CH5_LIVE[0]
R-0h
Table 148. CH5_LIVE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH5_LIVE[7]
R
0h
Channel 5 open input fault status.
0d = No open input detected
1d = Open input detected
6
CH5_LIVE[6]
R
0h
Channel 5 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
5
CH5_LIVE[5]
R
0h
Channel 5 IN5P short to ground fault status.
0d = IN5P no short to ground detected
1d = IN5P short to ground detected
4
CH5_LIVE[4]
R
0h
Channel 5 IN5M short to ground fault status.
0d = IN5M no short to ground detected
1d = IN5M short to ground detected
3
CH5_LIVE[3]
R
0h
Channel 5 IN5P short to MICBIAS fault status.
0d = IN5P no short to MICBIAS detected
1d = IN5P short to MICBIAS detected
2
CH5_LIVE[2]
R
0h
Channel 5 IN5M short to MICBIAS fault status.
0d = IN5M no short to MICBIAS detected
1d = IN5M short to MICBIAS detected
1
CH5_LIVE[1]
R
0h
Channel 5 IN5P short to VBAT_IN fault status.
0d = IN5P no short to VBAT_IN detected
1d = IN5P short to VBAT_IN detected
0
CH5_LIVE[0]
R
0h
Channel 5 IN5M short to VBAT_IN fault status.
0d = IN5M no short to VBAT_IN detected
1d = IN5M short to VBAT_IN detected
8.6.1.4.10 CH6_LIVE Register (page = 0x01, address = 0x33) [reset = 0h]
This register is the live Interrupt status register for channel 6 fault diagnostic. Applicable only for PCM6x60-Q1.
Figure 193. CH6_LIVE Register
7
CH6_LIVE[7]
R-0h
6
CH6_LIVE[6]
R-0h
5
CH6_LIVE[5]
R-0h
4
CH6_LIVE[4]
R-0h
3
CH6_LIVE[3]
R-0h
2
CH6_LIVE[2]
R-0h
1
CH6_LIVE[1]
R-0h
0
CH6_LIVE[0]
R-0h
Table 149. CH6_LIVE Register Field Descriptions
Bit
7
124
Field
Type
Reset
Description
CH6_LIVE[7]
R
0h
Channel 6 open input fault status.
0d = No open input detected
1d = Open input detected
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Table 149. CH6_LIVE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
CH6_LIVE[6]
R
0h
Channel 6 input pair short fault status.
0d = No input pair short detected
1d = Input short to each other detected
5
CH6_LIVE[5]
R
0h
Channel 6 IN6P short to ground fault status.
0d = IN6P no short to ground detected
1d = IN6P short to ground detected
4
CH6_LIVE[4]
R
0h
Channel 6 IN6M short to ground fault status.
0d = IN6M no short to ground detected
1d = IN6M short to ground detected
3
CH6_LIVE[3]
R
0h
Channel 6 IN6P short to MICBIAS fault status.
0d = IN6P no short to MICBIAS detected
1d = IN6P short to MICBIAS detected
2
CH6_LIVE[2]
R
0h
Channel 6 IN6M short to MICBIAS fault status.
0d = IN6M no short to MICBIAS detected
1d = IN6M short to MICBIAS detected
1
CH6_LIVE[1]
R
0h
Channel 6 IN6P short to VBAT_IN fault status.
0d = IN6P no short to VBAT_IN detected
1d = IN6P short to VBAT_IN detected
0
CH6_LIVE[0]
R
0h
Channel 6 IN6M short to VBAT_IN fault status.
0d = IN6M no short to VBAT_IN detected
1d = IN6M short to VBAT_IN detected
8.6.1.4.11 INT_LIVE1 Register (page = 0x01, address = 0x35) [reset = 0h]
This register is the live Interrupt readback register 1.
Figure 194. INT_LIVE1 Register
7
INT_LIVE1[7]
R-0h
6
INT_LIVE1[6]
R-0h
5
INT_LIVE1[5]
R-0h
4
INT_LIVE1[4]
R-0h
3
INT_LIVE1[3]
R-0h
2
INT_LIVE1[2]
R-0h
1
0
Reserved
R-0h
Table 150. INT_LIVE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE1[7]
R
0h
Channel 1 IN1P over voltage fault status.
0d = No IN1P over voltage fault detected
1d = IN1P over voltage fault has detected
6
INT_LIVE1[6]
R
0h
Channel 2 IN2P over voltage fault status.
0d = No IN2P over voltage fault detected
1d = IN2P over voltage fault has detected
5
INT_LIVE1[5]
R
0h
Channel 3 IN3P over voltage fault status.
0d = No IN3P over voltage fault detected
1d = IN3P over voltage fault has detected
4
INT_LIVE1[4]
R
0h
Channel 4 IN4P over voltage fault status.
0d = No IN4P over voltage fault detected
1d = IN4P over voltage fault has detected
3
INT_LIVE1[3]
R
0h
Channel 5 IN5P over voltage fault status. Applicable only for PCM6x60-Q1.
0d = No IN5P over voltage fault detected
1d = IN5P over voltage fault has detected
2
INT_LIVE1[2]
R
0h
Channel 6 IN6P over voltage fault status. Applicable only for PCM6x60-Q1.
0d = No IN6P over voltage fault detected
1d = IN6P over voltage fault has detected
Reserved
R
0h
Reserved
1-0
8.6.1.4.12 INT_LIVE3 Register (page = 0x01, address = 0x37) [reset = 0h]
This register is the live Interrupt readback register 3.
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Figure 195. INT_LIVE3 Register
7
INT_LIVE3[7]
R-0h
6
INT_LIVE3[6]
R-0h
5
INT_LIVE3[5]
R-0h
4
3
2
Reserved
R-0h
1
0
1
0
Table 151. INT_LIVE3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
INT_LIVE3[7]
R
0h
Fault status for MICBIAS high current.
0d = No fault detected
1d = Fault detected
6
INT_LIVE3[6]
R
0h
Fault status for MICBIAS low current
0d = No fault detected
1d = Fault detected
5
INT_LIVE3[5]
R
0h
Fault status for MICBIAS over voltage.
0d = No fault detected
1d = Fault detected
Reserved
R
0h
Reserved
4-0
8.6.1.4.13 MBIAS_OV_CFG Register (page = 0x01, address = 0x55) [reset = 40h]
This register is the MICBIAS overvoltage configuration register.
Figure 196. MBIAS_OV_CFG Register
7
6
MBIAS_OV_THRES[2:0]
RW-2h
5
4
3
2
Reserved
R-0h
Table 152. MBIAS_OV_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
MBIAS_OV_THRES[2:0]
RW
2h
MICBIAS overvoltage fault detection threshold above MICBIAS programmed
voltage.
0d = No threshold over programmed voltage
1d = 10 mV (typ) threshold over programmed voltage
2d = 40 mV (typ) threshold over programmed voltage (default)
3d to 6d = Threshold value is set as per configuration with step size of 30mV
(typ)
7d = 190 mV (typ) threshold over programmed voltage (default)
4-0
Reserved
R
0h
Reserved
8.6.1.4.14 DIAGDATA_CFG Register (page = 0x01, address = 0x59) [reset = 0h]
This register is the diagnostic data configuration register.
Figure 197. DIAGDATA_CFG Register
7
6
5
4
3
2
Reserved
Reserved
RW-0h
R-0h
1
0
HOLD_SAR_D
ATA
RW-0h
Table 153. DIAGDATA_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
Reserved
RW
0h
Reserved
3-1
Reserved
R
0h
Reserved
HOLD_SAR_DATA
RW
0h
Hold SAR data update during register readback.
0b= Data update is not held, data register is continuously updated; this
setting must be used when moving average is enabled for fault detection
1b= Data update is held, data register readback can be done
0
126
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8.6.1.4.15 DIAG_MON_MSB_VBAT Register (page = 0x01, address = 0x5A) [reset = 0h]
This register is the MSB data byte of VBAT_IN monitoring.
Figure 198. DIAG_MON_MSB_VBAT Register
7
6
5
4
3
DIAG_MON_MSB_VBAT[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-0h
0
Table 154. DIAG_MON_MSB_VBAT Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_VBAT[7: R
0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.16 DIAG_MON_LSB_VBAT Register (page = 0x01, address = 0x5B) [reset = 0h]
This register is the LSB data nibble of VBAT_IN monitoring.
Figure 199. DIAG_MON_LSB_VBAT Register
7
6
5
DIAG_MON_LSB_VBAT[3:0]
R-0h
4
3
Table 155. DIAG_MON_LSB_VBAT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DIAG_MON_LSB_VBAT[3:
0]
R
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
R
0h
Channel ID value
8.6.1.4.17 DIAG_MON_MSB_MBIAS Register (page = 0x01, address = 0x5C) [reset = 0h]
This register is the MSB data byte of MICBIAS monitoring.
Figure 200. DIAG_MON_MSB_MBIAS Register
7
6
5
4
3
DIAG_MON_MSB_MBIAS[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-1h
0
Table 156. DIAG_MON_MSB_MBIAS Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIAG_MON_MSB_MBIAS[
7:0]
R
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.18 DIAG_MON_LSB_MBIAS Register (page = 0x01, address = 0x5D) [reset = 1h]
This register is the LSB data nibble of MICBIAS monitoring.
Figure 201. DIAG_MON_LSB_MBIAS Register
7
6
5
DIAG_MON_LSB_MBIAS[3:0]
R-0h
4
3
Table 157. DIAG_MON_LSB_MBIAS Register Field Descriptions
Bit
Field
7-4
DIAG_MON_LSB_MBIAS[3 R
:0]
Type
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Reset
Description
0h
Diagnostic SAR monitor data LSB nibble
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Table 157. DIAG_MON_LSB_MBIAS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
CHANNEL_ID[3:0]
R
1h
Channel ID value
8.6.1.4.19 DIAG_MON_MSB_IN1P Register (page = 0x01, address = 0x5E) [reset = 0h]
This register is the MSB data byte of IN1P monitoring.
Figure 202. DIAG_MON_MSB_IN1P Register
7
6
5
4
3
DIAG_MON_MSB_CH1P[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-2h
0
Table 158. DIAG_MON_MSB_IN1P Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_CH1P[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.20 DIAG_MON_LSB_IN1P Register (page = 0x01, address = 0x5F) [reset = 2h]
This register is the LSB data nibble of IN1P monitoring.
Figure 203. DIAG_MON_LSB_IN1P Register
7
6
5
DIAG_MON_LSB_CH1P[3:0]
R-0h
4
3
Table 159. DIAG_MON_LSB_IN1P Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH1P[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
2h
Channel ID value
R
8.6.1.4.21 DIAG_MON_MSB_IN1M Register (page = 0x01, address = 0x60) [reset = 0h]
This register is the MSB data byte of IN1M monitoring.
Figure 204. DIAG_MON_MSB_IN1M Register
7
6
5
4
3
DIAG_MON_MSB_CH1N[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-3h
0
Table 160. DIAG_MON_MSB_IN1M Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_CH1N[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.22 DIAG_MON_LSB_IN1M Register (page = 0x01, address = 0x61) [reset = 3h]
This register is the LSB data nibble of IN1M monitoring.
Figure 205. DIAG_MON_LSB_IN1M Register
7
128
6
5
DIAG_MON_LSB_CH1N[3:0]
R-0h
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4
3
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www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 161. DIAG_MON_LSB_IN1M Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH1N[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
3h
Channel ID value
R
8.6.1.4.23 DIAG_MON_MSB_IN2P Register (page = 0x01, address = 0x62) [reset = 0h]
This register is the MSB data byte of IN2P monitoring.
Figure 206. DIAG_MON_MSB_IN2P Register
7
6
5
4
3
DIAG_MON_MSB_CH2P[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-4h
0
Table 162. DIAG_MON_MSB_IN2P Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_CH2P[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.24 DIAG_MON_LSB_IN2P Register (page = 0x01, address = 0x63) [reset = 4h]
This register is the LSB data nibble of IN2P monitoring.
Figure 207. DIAG_MON_LSB_IN2P Register
7
6
5
DIAG_MON_LSB_CH2P[3:0]
R-0h
4
3
Table 163. DIAG_MON_LSB_IN2P Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH2P[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
4h
Channel ID value
R
8.6.1.4.25 DIAG_MON_MSB_IN2M Register (page = 0x01, address = 0x64) [reset = 0h]
This register is the MSB data byte of IN2M monitoring.
Figure 208. DIAG_MON_MSB_IN2M Register
7
6
5
4
3
DIAG_MON_MSB_CH2N[7:0]
R-0h
2
1
0
Table 164. DIAG_MON_MSB_IN2M Register Field Descriptions
Bit
Field
7-0
DIAG_MON_MSB_CH2N[7 R
:0]
Type
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.26 DIAG_MON_LSB_IN2M Register (page = 0x01, address = 0x65) [reset = 5h]
This register is the LSB data nibble of IN2M monitoring.
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Figure 209. DIAG_MON_LSB_IN2M Register
7
6
5
DIAG_MON_LSB_CH2N[3:0]
R-0h
4
3
2
1
CHANNEL_ID[3:0]
R-5h
0
Table 165. DIAG_MON_LSB_IN2M Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH2N[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
5h
Channel ID value
R
8.6.1.4.27 DIAG_MON_MSB_IN3P Register (page = 0x01, address = 0x66) [reset = 0h]
This register is the MSB data byte of IN3P monitoring.
Figure 210. DIAG_MON_MSB_IN3P Register
7
6
5
4
3
DIAG_MON_MSB_CH3P[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-6h
0
Table 166. DIAG_MON_MSB_IN3P Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_CH3P[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.28 DIAG_MON_LSB_IN3P Register (page = 0x01, address = 0x67) [reset = 6h]
This register is the LSB data nibble of IN3P monitoring.
Figure 211. DIAG_MON_LSB_IN3P Register
7
6
5
DIAG_MON_LSB_CH3P[3:0]
R-0h
4
3
Table 167. DIAG_MON_LSB_IN3P Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH3P[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
6h
Channel ID value
R
8.6.1.4.29 DIAG_MON_MSB_IN3M Register (page = 0x01, address = 0x68) [reset = 0h]
This register is the MSB data byte of IN3M monitoring.
Figure 212. DIAG_MON_MSB_IN3M Register
7
6
5
4
3
DIAG_MON_MSB_CH3N[7:0]
R-0h
2
1
0
Table 168. DIAG_MON_MSB_IN3M Register Field Descriptions
130
Bit
Field
Type
7-0
DIAG_MON_MSB_CH3N[7 R
:0]
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Reset
Description
0h
Diagnostic SAR monitor data MSB byte
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PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.6.1.4.30 DIAG_MON_LSB_IN3M Register (page = 0x01, address = 0x69) [reset = 7h]
This register is the LSB data nibble of IN3M monitoring.
Figure 213. DIAG_MON_LSB_IN3M Register
7
6
5
DIAG_MON_LSB_CH3N[3:0]
R-0h
4
3
2
1
CHANNEL_ID[3:0]
R-7h
0
Table 169. DIAG_MON_LSB_IN3M Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
DIAG_MON_LSB_CH3N[3: R
0]
0h
Diagnostic SAR monitor data LSB nibble
CHANNEL_ID[3:0]
7h
Channel ID value
R
8.6.1.4.31 DIAG_MON_MSB_IN4P Register (page = 0x01, address = 0x6A) [reset = 0h]
This register is the MSB data byte of IN4P monitoring.
Figure 214. DIAG_MON_MSB_IN4P Register
7
6
5
4
3
DIAG_MON_MSB_CH4P[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-8h
0
Table 170. DIAG_MON_MSB_IN4P Register Field Descriptions
Bit
Field
7-0
DIAG_MON_MSB_CH4P[7 R
:0]
Type
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.32 DIAG_MON_LSB_IN4P Register (page = 0x01, address = 0x6B) [reset = 8h]
This register is the LSB data nibble of IN4P monitoring.
Figure 215. DIAG_MON_LSB_IN4P Register
7
6
5
DIAG_MON_LSB_CH4P[3:0]
R-0h
4
3
Table 171. DIAG_MON_LSB_IN4P Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
DIAG_MON_LSB_CH4P[3: R
0]
0h
Diagnostic SAR monitor data LSB nibble
CHANNEL_ID[3:0]
8h
Channel ID value
R
8.6.1.4.33 DIAG_MON_MSB_IN4M Register (page = 0x01, address = 0x6C) [reset = 0h]
This register is the MSB data byte of IN4M monitoring.
Figure 216. DIAG_MON_MSB_IN4M Register
7
6
5
Copyright © 2020, Texas Instruments Incorporated
4
3
DIAG_MON_MSB_CH4N[7:0]
R-0h
2
1
0
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Table 172. DIAG_MON_MSB_IN4M Register Field Descriptions
Bit
Field
7-0
DIAG_MON_MSB_CH4N[7 R
:0]
Type
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.34 DIAG_MON_LSB_IN4M Register (page = 0x01, address = 0x6D) [reset = 9h]
This register is the LSB data nibble of IN4M monitoring.
Figure 217. DIAG_MON_LSB_IN4M Register
7
6
5
DIAG_MON_LSB_CH4N[3:0]
R-0h
4
3
2
1
CHANNEL_ID[3:0]
R-9h
0
Table 173. DIAG_MON_LSB_IN4M Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH4N[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
9h
Channel ID value
R
8.6.1.4.35 DIAG_MON_MSB_IN5P Register (page = 0x01, address = 0x6E) [reset = 0h]
This register is the MSB data byte of IN5P monitoring. Applicable only for PCM6x60-Q1.
Figure 218. DIAG_MON_MSB_IN5P Register
7
6
5
4
3
DIAG_MON_MSB_CH5P[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-Ah
0
Table 174. DIAG_MON_MSB_IN5P Register Field Descriptions
Bit
Field
7-0
DIAG_MON_MSB_CH5P[7 R
:0]
Type
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.36 DIAG_MON_LSB_IN5P Register (page = 0x01, address = 0x6F) [reset = Ah]
This register is the LSB data nibble of IN5P monitoring. Applicable only for PCM6x60-Q1.
Figure 219. DIAG_MON_LSB_IN5P Register
7
6
5
DIAG_MON_LSB_CH5P[3:0]
R-0h
4
3
Table 175. DIAG_MON_LSB_IN5P Register Field Descriptions
Bit
Field
7-4
3-0
Type
Reset
Description
DIAG_MON_LSB_CH5P[3: R
0]
0h
Diagnostic SAR monitor data LSB nibble
CHANNEL_ID[3:0]
Ah
Channel ID value
R
8.6.1.4.37 DIAG_MON_MSB_IN5M Register (page = 0x01, address = 0x70) [reset = 0h]
This register is the MSB data byte of IN5M monitoring. Applicable only for PCM6x60-Q1.
132
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Figure 220. DIAG_MON_MSB_IN5M Register
7
6
5
4
3
DIAG_MON_MSB_CH5N[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-Bh
0
Table 176. DIAG_MON_MSB_IN5M Register Field Descriptions
Bit
Field
7-0
DIAG_MON_MSB_CH5N[7 R
:0]
Type
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.38 DIAG_MON_LSB_IN5M Register (page = 0x01, address = 0x71) [reset = Bh]
This register is the LSB data nibble of IN5M monitoring. Applicable only for PCM6x60-Q1.
Figure 221. DIAG_MON_LSB_IN5M Register
7
6
5
DIAG_MON_LSB_CH5N[3:0]
R-0h
4
3
Table 177. DIAG_MON_LSB_IN5M Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH5N[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
Bh
Channel ID value
R
8.6.1.4.39 DIAG_MON_MSB_IN6P Register (page = 0x01, address = 0x72) [reset = 0h]
This register is the MSB data byte of IN6P monitoring. Applicable only for PCM6x60-Q1.
Figure 222. DIAG_MON_MSB_IN6P Register
7
6
5
4
3
DIAG_MON_MSB_CH6P[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-Ch
0
Table 178. DIAG_MON_MSB_IN6P Register Field Descriptions
Bit
Field
7-0
DIAG_MON_MSB_CH6P[7 R
:0]
Type
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.40 DIAG_MON_LSB_IN6P Register (page = 0x01, address = 0x73) [reset = Ch]
This register is the LSB data nibble of IN6P monitoring. Applicable only for PCM6x60-Q1.
Figure 223. DIAG_MON_LSB_IN6P Register
7
6
5
DIAG_MON_LSB_CH6P[3:0]
R-0h
4
3
Table 179. DIAG_MON_LSB_IN6P Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH6P[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
Ch
Channel ID value
R
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8.6.1.4.41 DIAG_MON_MSB_IN6M Register (page = 0x01, address = 0x74) [reset = 0h]
This register is the MSB data byte of IN6M monitoring. Applicable only for PCM6x60-Q1.
Figure 224. DIAG_MON_MSB_IN6M Register
7
6
5
4
3
DIAG_MON_MSB_CH6N[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-Dh
0
Table 180. DIAG_MON_MSB_IN6M Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_CH6N[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.42 DIAG_MON_LSB_IN6M Register (page = 0x01, address = 0x75) [reset = Dh]
This register is the LSB data nibble of IN6M monitoring. Applicable only for PCM6x60-Q1.
Figure 225. DIAG_MON_LSB_IN6M Register
7
6
5
DIAG_MON_LSB_CH6N[3:0]
R-0h
4
3
Table 181. DIAG_MON_LSB_IN6M Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_CH6N[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
Dh
Channel ID value
R
8.6.1.4.43 DIAG_MON_MSB_TEMP Register (page = 0x01, address = 0x76) [reset = 0h]
This register is the MSB data byte of temperature monitoring.
Figure 226. DIAG_MON_MSB_TEMP Register
7
6
5
4
3
DIAG_MON_MSB_TEMP[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-Eh
0
Table 182. DIAG_MON_MSB_TEMP Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_TEMP[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.44 DIAG_MON_LSB_TEMP Register (page = 0x01, address = 0x77) [reset = Eh]
This register is the LSB data nibble of temperature monitoring.
Figure 227. DIAG_MON_LSB_TEMP Register
7
6
5
DIAG_MON_LSB_TEMP[3:0]
R-0h
4
3
Table 183. DIAG_MON_LSB_TEMP Register Field Descriptions
134
Bit
Field
7-4
DIAG_MON_LSB_TEMP[3: R
0]
Type
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Reset
Description
0h
Diagnostic SAR monitor data LSB nibble
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Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 183. DIAG_MON_LSB_TEMP Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
CHANNEL_ID[3:0]
R
Eh
Channel ID value
8.6.1.4.45 DIAG_MON_MSB_LOAD Register (page = 0x01, address = 0x78) [reset = 0h]
This register is the MSB data byte of MICBIAS load current monitoring.
Figure 228. DIAG_MON_MSB_LOAD Register
7
6
5
4
3
DIAG_MON_MSB_LOAD[7:0]
R-0h
2
1
0
2
1
CHANNEL_ID[3:0]
R-Fh
0
Table 184. DIAG_MON_MSB_LOAD Register Field Descriptions
Bit
Field
Type
7-0
DIAG_MON_MSB_LOAD[7 R
:0]
Reset
Description
0h
Diagnostic SAR monitor data MSB byte
8.6.1.4.46 DIAG_MON_LSB_LOAD Register (page = 0x01, address = 0x79) [reset = Fh]
This register is the LSB data nibble of MICBIAS load current monitoring.
Figure 229. DIAG_MON_LSB_LOAD Register
7
6
5
DIAG_MON_LSB_LOAD[3:0]
R-0h
4
3
Table 185. DIAG_MON_LSB_LOAD Register Field Descriptions
Bit
Field
Reset
Description
7-4
DIAG_MON_LSB_LOAD[3: R
0]
Type
0h
Diagnostic SAR monitor data LSB nibble
3-0
CHANNEL_ID[3:0]
Fh
Channel ID value
R
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8.6.2 Programmable Coefficient Registers
8.6.2.1 Programmable Coefficient Registers: Page = 0x02
This register page (shown in Register Description: Page = 0x00 ) consists of the programmable coefficients for
the biquad 1 to biquad 6 filters. To optimize the coefficients register transaction time for page 2, page 3, and
page 4, the device also supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads.
After a transaction of register address 0x7F, the device auto increments to the next page at register 0x08 to
transact the next coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For
a successful coefficient register transaction, the host device must write and read all four bytes starting with the
most significant byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register
read transaction, the device transmits the first byte as a dummy read byte; therefore, the host must read five
bytes, including the first dummy read byte and the last four bytes corresponding to the coefficient register value
starting with the most significant byte (BYT1).
Table 186. Page 0x02 Programmable Coefficient Registers
ADDRESS
136
REGISTER
0x00
PAGE[7:0]
0x08
0x09
RESET
DESCRIPTION
0x00
Device page register
BQ1_N0_BYT1[7:0]
0x7F
Programmable biquad 1, N0 coefficient byte[31:24]
BQ1_N0_BYT2[7:0]
0xFF
Programmable biquad 1, N0 coefficient byte[23:16]
0x0A
BQ1_N0_BYT3[7:0]
0xFF
Programmable biquad 1, N0 coefficient byte[15:8]
0x0B
BQ1_N0_BYT4[7:0]
0xFF
Programmable biquad 1, N0 coefficient byte[7:0]
0x0C
BQ1_N1_BYT1[7:0]
0x00
Programmable biquad 1, N1 coefficient byte[31:24]
0x0D
BQ1_N1_BYT2[7:0]
0x00
Programmable biquad 1, N1 coefficient byte[23:16]
0x0E
BQ1_N1_BYT3[7:0]
0x00
Programmable biquad 1, N1 coefficient byte[15:8]
0x0F
BQ1_N1_BYT4[7:0]
0x00
Programmable biquad 1, N1 coefficient byte[7:0]
0x10
BQ1_N2_BYT1[7:0]
0x00
Programmable biquad 1, N2 coefficient byte[31:24]
0x11
BQ1_N2_BYT2[7:0]
0x00
Programmable biquad 1, N2 coefficient byte[23:16]
0x12
BQ1_N2_BYT3[7:0]
0x00
Programmable biquad 1, N2 coefficient byte[15:8]
0x13
BQ1_N2_BYT4[7:0]
0x00
Programmable biquad 1, N2 coefficient byte[7:0]
0x14
BQ1_D1_BYT1[7:0]
0x00
Programmable biquad 1, D1 coefficient byte[31:24]
0x15
BQ1_D1_BYT2[7:0]
0x00
Programmable biquad 1, D1 coefficient byte[23:16]
0x16
BQ1_D1_BYT3[7:0]
0x00
Programmable biquad 1, D1 coefficient byte[15:8]
0x17
BQ1_D1_BYT4[7:0]
0x00
Programmable biquad 1, D1 coefficient byte[7:0]
0x18
BQ1_D2_BYT1[7:0]
0x00
Programmable biquad 1, D2 coefficient byte[31:24]
0x19
BQ1_D2_BYT2[7:0]
0x00
Programmable biquad 1, D2 coefficient byte[23:16]
0x1A
BQ1_D2_BYT3[7:0]
0x00
Programmable biquad 1, D2 coefficient byte[15:8]
0x1B
BQ1_D2_BYT4[7:0]
0x00
Programmable biquad 1, D2 coefficient byte[7:0]
0x1C
BQ2_N0_BYT1[7:0]
0x7F
Programmable biquad 2, N0 coefficient byte[31:24]
0x1D
BQ2_N0_BYT2[7:0]
0xFF
Programmable biquad 2, N0 coefficient byte[23:16]
0x1E
BQ2_N0_BYT3[7:0]
0xFF
Programmable biquad 2, N0 coefficient byte[15:8]
0x1F
BQ2_N0_BYT4[7:0]
0xFF
Programmable biquad 2, N0 coefficient byte[7:0]
0x20
BQ2_N1_BYT1[7:0]
0x00
Programmable biquad 2, N1 coefficient byte[31:24]
0x21
BQ2_N1_BYT2[7:0]
0x00
Programmable biquad 2, N1 coefficient byte[23:16]
0x22
BQ2_N1_BYT3[7:0]
0x00
Programmable biquad 2, N1 coefficient byte[15:8]
0x23
BQ2_N1_BYT4[7:0]
0x00
Programmable biquad 2, N1 coefficient byte[7:0]
0x24
BQ2_N2_BYT1[7:0]
0x00
Programmable biquad 2, N2 coefficient byte[31:24]
0x25
BQ2_N2_BYT2[7:0]
0x00
Programmable biquad 2, N2 coefficient byte[23:16]
0x26
BQ2_N2_BYT3[7:0]
0x00
Programmable biquad 2, N2 coefficient byte[15:8]
0x27
BQ2_N2_BYT4[7:0]
0x00
Programmable biquad 2, N2 coefficient byte[7:0]
0x28
BQ2_D1_BYT1[7:0]
0x00
Programmable biquad 2, D1 coefficient byte[31:24]
0x29
BQ2_D1_BYT2[7:0]
0x00
Programmable biquad 2, D1 coefficient byte[23:16]
0x2A
BQ2_D1_BYT3[7:0]
0x00
Programmable biquad 2, D1 coefficient byte[15:8]
0x2B
BQ2_D1_BYT4[7:0]
0x00
Programmable biquad 2, D1 coefficient byte[7:0]
0x2C
BQ2_D2_BYT1[7:0]
0x00
Programmable biquad 2, D2 coefficient byte[31:24]
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 186. Page 0x02 Programmable Coefficient Registers (continued)
0x2D
BQ2_D2_BYT2[7:0]
0x00
Programmable biquad 2, D2 coefficient byte[23:16]
0x2E
BQ2_D2_BYT3[7:0]
0x00
Programmable biquad 2, D2 coefficient byte[15:8]
0x2F
BQ2_D2_BYT4[7:0]
0x00
Programmable biquad 2, D2 coefficient byte[7:0]
0x30
BQ3_N0_BYT1[7:0]
0x7F
Programmable biquad 3, N0 coefficient byte[31:24]
0x31
BQ3_N0_BYT2[7:0]
0xFF
Programmable biquad 3, N0 coefficient byte[23:16]
0x32
BQ3_N0_BYT3[7:0]
0xFF
Programmable biquad 3, N0 coefficient byte[15:8]
0x33
BQ3_N0_BYT4[7:0]
0xFF
Programmable biquad 3, N0 coefficient byte[7:0]
0x34
BQ3_N1_BYT1[7:0]
0x00
Programmable biquad 3, N1 coefficient byte[31:24]
0x35
BQ3_N1_BYT2[7:0]
0x00
Programmable biquad 3, N1 coefficient byte[23:16]
0x36
BQ3_N1_BYT3[7:0]
0x00
Programmable biquad 3, N1 coefficient byte[15:8]
0x37
BQ3_N1_BYT4[7:0]
0x00
Programmable biquad 3, N1 coefficient byte[7:0]
0x38
BQ3_N2_BYT1[7:0]
0x00
Programmable biquad 3, N2 coefficient byte[31:24]
0x39
BQ3_N2_BYT2[7:0]
0x00
Programmable biquad 3, N2 coefficient byte[23:16]
0x3A
BQ3_N2_BYT3[7:0]
0x00
Programmable biquad 3, N2 coefficient byte[15:8]
0x3B
BQ3_N2_BYT4[7:0]
0x00
Programmable biquad 3, N2 coefficient byte[7:0]
0x3C
BQ3_D1_BYT1[7:0]
0x00
Programmable biquad 3, D1 coefficient byte[31:24]
0x3D
BQ3_D1_BYT2[7:0]
0x00
Programmable biquad 3, D1 coefficient byte[23:16]
0x3E
BQ3_D1_BYT3[7:0]
0x00
Programmable biquad 3, D1 coefficient byte[15:8]
0x3F
BQ3_D1_BYT4[7:0]
0x00
Programmable biquad 3, D1 coefficient byte[7:0]
0x40
BQ3_D2_BYT1[7:0]
0x00
Programmable biquad 3, D2 coefficient byte[31:24]
0x41
BQ3_D2_BYT2[7:0]
0x00
Programmable biquad 3, D2 coefficient byte[23:16]
0x42
BQ3_D2_BYT3[7:0]
0x00
Programmable biquad 3, D2 coefficient byte[15:8]
0x43
BQ3_D2_BYT4[7:0]
0x00
Programmable biquad 3, D2 coefficient byte[7:0]
0x44
BQ4_N0_BYT1[7:0]
0x7F
Programmable biquad 4, N0 coefficient byte[31:24]
0x45
BQ4_N0_BYT2[7:0]
0xFF
Programmable biquad 4, N0 coefficient byte[23:16]
0x46
BQ4_N0_BYT3[7:0]
0xFF
Programmable biquad 4, N0 coefficient byte[15:8]
0x47
BQ4_N0_BYT4[7:0]
0xFF
Programmable biquad 4, N0 coefficient byte[7:0]
0x48
BQ4_N1_BYT1[7:0]
0x00
Programmable biquad 4, N1 coefficient byte[31:24]
0x49
BQ4_N1_BYT2[7:0]
0x00
Programmable biquad 4, N1 coefficient byte[23:16]
0x4A
BQ4_N1_BYT3[7:0]
0x00
Programmable biquad 4, N1 coefficient byte[15:8]
0x4B
BQ4_N1_BYT4[7:0]
0x00
Programmable biquad 4, N1 coefficient byte[7:0]
0x4C
BQ4_N2_BYT1[7:0]
0x00
Programmable biquad 4, N2 coefficient byte[31:24]
0x4D
BQ4_N2_BYT2[7:0]
0x00
Programmable biquad 4, N2 coefficient byte[23:16]
0x4E
BQ4_N2_BYT3[7:0]
0x00
Programmable biquad 4, N2 coefficient byte[15:8]
0x4F
BQ4_N2_BYT4[7:0]
0x00
Programmable biquad 4, N2 coefficient byte[7:0]
0x50
BQ4_D1_BYT1[7:0]
0x00
Programmable biquad 4, D1 coefficient byte[31:24]
0x51
BQ4_D1_BYT2[7:0]
0x00
Programmable biquad 4, D1 coefficient byte[23:16]
0x52
BQ4_D1_BYT3[7:0]
0x00
Programmable biquad 4, D1 coefficient byte[15:8]
0x53
BQ4_D1_BYT4[7:0]
0x00
Programmable biquad 4, D1 coefficient byte[7:0]
0x54
BQ4_D2_BYT1[7:0]
0x00
Programmable biquad 4, D2 coefficient byte[31:24]
0x55
BQ4_D2_BYT2[7:0]
0x00
Programmable biquad 4, D2 coefficient byte[23:16]
0x56
BQ4_D2_BYT3[7:0]
0x00
Programmable biquad 4, D2 coefficient byte[15:8]
0x57
BQ4_D2_BYT4[7:0]
0x00
Programmable biquad 4, D2 coefficient byte[7:0]
0x58
BQ5_N0_BYT1[7:0]
0x7F
Programmable biquad 5, N0 coefficient byte[31:24]
0x59
BQ5_N0_BYT2[7:0]
0xFF
Programmable biquad 5, N0 coefficient byte[23:16]
0x5A
BQ5_N0_BYT3[7:0]
0xFF
Programmable biquad 5, N0 coefficient byte[15:8]
0x5B
BQ5_N0_BYT4[7:0]
0xFF
Programmable biquad 5, N0 coefficient byte[7:0]
0x5C
BQ5_N1_BYT1[7:0]
0x00
Programmable biquad 5, N1 coefficient byte[31:24]
0x5D
BQ5_N1_BYT2[7:0]
0x00
Programmable biquad 5, N1 coefficient byte[23:16]
0x5E
BQ5_N1_BYT3[7:0]
0x00
Programmable biquad 5, N1 coefficient byte[15:8]
0x5F
BQ5_N1_BYT4[7:0]
0x00
Programmable biquad 5, N1 coefficient byte[7:0]
0x60
BQ5_N2_BYT1[7:0]
0x00
Programmable biquad 5, N2 coefficient byte[31:24]
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Table 186. Page 0x02 Programmable Coefficient Registers (continued)
138
0x61
BQ5_N2_BYT2[7:0]
0x00
Programmable biquad 5, N2 coefficient byte[23:16]
0x62
BQ5_N2_BYT3[7:0]
0x00
Programmable biquad 5, N2 coefficient byte[15:8]
0x63
BQ5_N2_BYT4[7:0]
0x00
Programmable biquad 5, N2 coefficient byte[7:0]
0x64
BQ5_D1_BYT1[7:0]
0x00
Programmable biquad 5, D1 coefficient byte[31:24]
0x65
BQ5_D1_BYT2[7:0]
0x00
Programmable biquad 5, D1 coefficient byte[23:16]
0x66
BQ5_D1_BYT3[7:0]
0x00
Programmable biquad 5, D1 coefficient byte[15:8]
0x67
BQ5_D1_BYT4[7:0]
0x00
Programmable biquad 5, D1 coefficient byte[7:0]
0x68
BQ5_D2_BYT1[7:0]
0x00
Programmable biquad 5, D2 coefficient byte[31:24]
0x69
BQ5_D2_BYT2[7:0]
0x00
Programmable biquad 5, D2 coefficient byte[23:16]
0x6A
BQ5_D2_BYT3[7:0]
0x00
Programmable biquad 5, D2 coefficient byte[15:8]
0x6B
BQ5_D2_BYT4[7:0]
0x00
Programmable biquad 5, D2 coefficient byte[7:0]
0x6C
BQ6_N0_BYT1[7:0]
0x7F
Programmable biquad 6, N0 coefficient byte[31:24]
0x6D
BQ6_N0_BYT2[7:0]
0xFF
Programmable biquad 6, N0 coefficient byte[23:16]
0x6E
BQ6_N0_BYT3[7:0]
0xFF
Programmable biquad 6, N0 coefficient byte[15:8]
0x6F
BQ6_N0_BYT4[7:0]
0xFF
Programmable biquad 6, N0 coefficient byte[7:0]
0x70
BQ6_N1_BYT1[7:0]
0x00
Programmable biquad 6, N1 coefficient byte[31:24]
0x71
BQ6_N1_BYT2[7:0]
0x00
Programmable biquad 6, N1 coefficient byte[23:16]
0x72
BQ6_N1_BYT3[7:0]
0x00
Programmable biquad 6, N1 coefficient byte[15:8]
0x73
BQ6_N1_BYT4[7:0]
0x00
Programmable biquad 6, N1 coefficient byte[7:0]
0x74
BQ6_N2_BYT1[7:0]
0x00
Programmable biquad 6, N2 coefficient byte[31:24]
0x75
BQ6_N2_BYT2[7:0]
0x00
Programmable biquad 6, N2 coefficient byte[23:16]
0x76
BQ6_N2_BYT3[7:0]
0x00
Programmable biquad 6, N2 coefficient byte[15:8]
0x77
BQ6_N2_BYT4[7:0]
0x00
Programmable biquad 6, N2 coefficient byte[7:0]
0x78
BQ6_D1_BYT1[7:0]
0x00
Programmable biquad 6, D1 coefficient byte[31:24]
0x79
BQ6_D1_BYT2[7:0]
0x00
Programmable biquad 6, D1 coefficient byte[23:16]
0x7A
BQ6_D1_BYT3[7:0]
0x00
Programmable biquad 6, D1 coefficient byte[15:8]
0x7B
BQ6_D1_BYT4[7:0]
0x00
Programmable biquad 6, D1 coefficient byte[7:0]
0x7C
BQ6_D2_BYT1[7:0]
0x00
Programmable biquad 6, D2 coefficient byte[31:24]
0x7D
BQ6_D2_BYT2[7:0]
0x00
Programmable biquad 6, D2 coefficient byte[23:16]
0x7E
BQ6_D2_BYT3[7:0]
0x00
Programmable biquad 6, D2 coefficient byte[15:8]
0x7F
BQ6_D2_BYT4[7:0]
0x00
Programmable biquad 6, D2 coefficient byte[7:0]
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Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
www.ti.com
SBAS884A – MARCH 2020 – REVISED JUNE 2020
8.6.2.2 Programmable Coefficient Registers: Page = 0x03
This register page (shown in Table 187) consists of the programmable coefficients for the biquad 7 to biquad 12
filters. To optimize the coefficients register transaction time for page 2, page 3, and page 4, the device also
supports (by default) auto-incremented pages for the I2C and SPI burst writes and reads. After a transaction of
register address 0x7F, the device auto increments to the next page at register 0x08 to transact the next
coefficient value. These programmable coefficients are 32-bit, two’s complement numbers. For a successful
coefficient register transaction, the host device must write and read all four bytes starting with the most significant
byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register read
transaction, the device transmits the first byte as a dummy read byte; therefore, the host must read five bytes,
including the first dummy read byte and the last four bytes corresponding to the coefficient register value starting
with the most significant byte (BYT1).
Table 187. Page 0x03 Programmable Coefficient Registers
ADDR
REGISTER
0x00
PAGE[7:0]
0x08
0x09
RESET
DESCRIPTION
0x00
Device page register
BQ7_N0_BYT1[7:0]
0x7F
Programmable biquad 7, N0 coefficient byte[31:24]
BQ7_N0_BYT2[7:0]
0xFF
Programmable biquad 7, N0 coefficient byte[23:16]
0x0A
BQ7_N0_BYT3[7:0]
0xFF
Programmable biquad 7, N0 coefficient byte[15:8]
0x0B
BQ7_N0_BYT4[7:0]
0xFF
Programmable biquad 7, N0 coefficient byte[7:0]
0x0C
BQ7_N1_BYT1[7:0]
0x00
Programmable biquad 7, N1 coefficient byte[31:24]
0x0D
BQ7_N1_BYT2[7:0]
0x00
Programmable biquad 7, N1 coefficient byte[23:16]
0x0E
BQ7_N1_BYT3[7:0]
0x00
Programmable biquad 7, N1 coefficient byte[15:8]
0x0F
BQ7_N1_BYT4[7:0]
0x00
Programmable biquad 7, N1 coefficient byte[7:0]
0x10
BQ7_N2_BYT1[7:0]
0x00
Programmable biquad 7, N2 coefficient byte[31:24]
0x11
BQ7_N2_BYT2[7:0]
0x00
Programmable biquad 7, N2 coefficient byte[23:16]
0x12
BQ7_N2_BYT3[7:0]
0x00
Programmable biquad 7, N2 coefficient byte[15:8]
0x13
BQ7_N2_BYT4[7:0]
0x00
Programmable biquad 7, N2 coefficient byte[7:0]
0x14
BQ7_D1_BYT1[7:0]
0x00
Programmable biquad 7, D1 coefficient byte[31:24]
0x15
BQ7_D1_BYT2[7:0]
0x00
Programmable biquad 7, D1 coefficient byte[23:16]
0x16
BQ7_D1_BYT3[7:0]
0x00
Programmable biquad 7, D1 coefficient byte[15:8]
0x17
BQ7_D1_BYT4[7:0]
0x00
Programmable biquad 7, D1 coefficient byte[7:0]
0x18
BQ7_D2_BYT1[7:0]
0x00
Programmable biquad 7, D2 coefficient byte[31:24]
0x19
BQ7_D2_BYT2[7:0]
0x00
Programmable biquad 7, D2 coefficient byte[23:16]
0x1A
BQ7_D2_BYT3[7:0]
0x00
Programmable biquad 7, D2 coefficient byte[15:8]
0x1B
BQ7_D2_BYT4[7:0]
0x00
Programmable biquad 7, D2 coefficient byte[7:0]
0x1C
BQ8_N0_BYT1[7:0]
0x7F
Programmable biquad 8, N0 coefficient byte[31:24]
0x1D
BQ8_N0_BYT2[7:0]
0xFF
Programmable biquad 8, N0 coefficient byte[23:16]
0x1E
BQ8_N0_BYT3[7:0]
0xFF
Programmable biquad 8, N0 coefficient byte[15:8]
0x1F
BQ8_N0_BYT4[7:0]
0xFF
Programmable biquad 8, N0 coefficient byte[7:0]
0x20
BQ8_N1_BYT1[7:0]
0x00
Programmable biquad 8, N1 coefficient byte[31:24]
0x21
BQ8_N1_BYT2[7:0]
0x00
Programmable biquad 8, N1 coefficient byte[23:16]
0x22
BQ8_N1_BYT3[7:0]
0x00
Programmable biquad 8, N1 coefficient byte[15:8]
0x23
BQ8_N1_BYT4[7:0]
0x00
Programmable biquad 8, N1 coefficient byte[7:0]
0x24
BQ8_N2_BYT1[7:0]
0x00
Programmable biquad 8, N2 coefficient byte[31:24]
0x25
BQ8_N2_BYT2[7:0]
0x00
Programmable biquad 8, N2 coefficient byte[23:16]
0x26
BQ8_N2_BYT3[7:0]
0x00
Programmable biquad 8, N2 coefficient byte[15:8]
0x27
BQ8_N2_BYT4[7:0]
0x00
Programmable biquad 8, N2 coefficient byte[7:0]
0x28
BQ8_D1_BYT1[7:0]
0x00
Programmable biquad 8, D1 coefficient byte[31:24]
0x29
BQ8_D1_BYT2[7:0]
0x00
Programmable biquad 8, D1 coefficient byte[23:16]
0x2A
BQ8_D1_BYT3[7:0]
0x00
Programmable biquad 8, D1 coefficient byte[15:8]
0x2B
BQ8_D1_BYT4[7:0]
0x00
Programmable biquad 8, D1 coefficient byte[7:0]
0x2C
BQ8_D2_BYT1[7:0]
0x00
Programmable biquad 8, D2 coefficient byte[31:24]
0x2D
BQ8_D2_BYT2[7:0]
0x00
Programmable biquad 8, D2 coefficient byte[23:16]
0x2E
BQ8_D2_BYT3[7:0]
0x00
Programmable biquad 8, D2 coefficient byte[15:8]
Copyright © 2020, Texas Instruments Incorporated
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139
PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1
SBAS884A – MARCH 2020 – REVISED JUNE 2020
www.ti.com
Table 187. Page 0x03 Programmable Coefficient Registers (continued)
140
0x2F
BQ8_D2_BYT4[7:0]
0x00
Programmable biquad 8, D2 coefficient byte[7:0]
0x30
BQ9_N0_BYT1[7:0]
0x7F
Programmable biquad 9, N0 coefficient byte[31:24]
0x31
BQ9_N0_BYT2[7:0]
0xFF
Programmable biquad 9, N0 coefficient byte[23:16]
0x32
BQ9_N0_BYT3[7:0]
0xFF
Programmable biquad 9, N0 coefficient byte[15:8]
0x33
BQ9_N0_BYT4[7:0]
0xFF
Programmable biquad 9, N0 coefficient byte[7:0]
0x34
BQ9_N1_BYT1[7:0]
0x00
Programmable biquad 9, N1 coefficient byte[31:24]
0x35
BQ9_N1_BYT2[7:0]
0x00
Programmable biquad 9, N1 coefficient byte[23:16]
0x36
BQ9_N1_BYT3[7:0]
0x00
Programmable biquad 9, N1 coefficient byte[15:8]
0x37
BQ9_N1_BYT4[7:0]
0x00
Programmable biquad 9, N1 coefficient byte[7:0]
0x38
BQ9_N2_BYT1[7:0]
0x00
Programmable biquad 9, N2 coefficient byte[31:24]
0x39
BQ9_N2_BYT2[7:0]
0x00
Programmable biquad 9, N2 coefficient byte[23:16]
0x3A
BQ9_N2_BYT3[7:0]
0x00
Programmable biquad 9, N2 coefficient byte[15:8]
0x3B
BQ9_N2_BYT4[7:0]
0x00
Programmable biquad 9, N2 coefficient byte[7:0]
0x3C
BQ9_D1_BYT1[7:0]
0x00
Programmable biquad 9, D1 coefficient byte[31:24]
0x3D
BQ9_D1_BYT2[7:0]
0x00
Programmable biquad 9, D1 coefficient byte[23:16]
0x3E
BQ9_D1_BYT3[7:0]
0x00
Programmable biquad 9, D1 coefficient byte[15:8]
0x3F
BQ9_D1_BYT4[7:0]
0x00
Programmable biquad 9, D1 coefficient byte[7:0]
0x40
BQ9_D2_BYT1[7:0]
0x00
Programmable biquad 9, D2 coefficient byte[31:24]
0x41
BQ9_D2_BYT2[7:0]
0x00
Programmable biquad 9, D2 coefficient byte[23:16]
0x42
BQ9_D2_BYT3[7:0]
0x00
Programmable biquad 9, D2 coefficient byte[15:8]
0x43
BQ9_D2_BYT4[7:0]
0x00
Programmable biquad 9, D2 coefficient byte[7:0]
0x44
BQ10_N0_BYT1[7:0]
0x7F
Programmable biquad 10, N0 coefficient byte[31:24]
0x45
BQ10_N0_BYT2[7:0]
0xFF
Programmable biquad 10, N0 coefficient byte[23:16]
0x46
BQ10_N0_BYT3[7:0]
0xFF
Programmable biquad 10, N0 coefficient byte[15:8]
0x47
BQ10_N0_BYT4[7:0]
0xFF
Programmable biquad 10, N0 coefficient byte[7:0]
0x48
BQ10_N1_BYT1[7:0]
0x00
Programmable biquad 10, N1 coefficient byte[31:24]
0x49
BQ10_N1_BYT2[7:0]
0x00
Programmable biquad 10, N1 coefficient byte[23:16]
0x4A
BQ10_N1_BYT3[7:0]
0x00
Programmable biquad 10, N1 coefficient byte[15:8]
0x4B
BQ10_N1_BYT4[7:0]
0x00
Programmable biquad 10, N1 coefficient byte[7:0]
0x4C
BQ10_N2_BYT1[7:0]
0x00
Programmable biquad 10, N2 coefficient byte[31:24]
0x4D
BQ10_N2_BYT2[7:0]
0x00
Programmable biquad 10, N2 coefficient byte[23:16]
0x4E
BQ10_N2_BYT3[7:0]
0x00
Programmable biquad 10, N2 coefficient byte[15:8]
0x4F
BQ10_N2_BYT4[7:0]
0x00
Programmable biquad 10, N2 coefficient byte[7:0]
0x50
BQ10_D1_BYT1[7:0]
0x00
Programmable biquad 10, D1 coefficient byte[31:24]
0x51
BQ10_D1_BYT2[7:0]
0x00
Programmable biquad 10, D1 coefficient byte[23:16]
0x52
BQ10_D1_BYT3[7:0]
0x00
Programmable biquad 10, D1 coefficient byte[15:8]
0x53
BQ10_D1_BYT4[7:0]
0x00
Programmable biquad 10, D1 coefficient byte[7:0]
0x54
BQ10_D2_BYT1[7:0]
0x00
Programmable biquad 10, D2 coefficient byte[31:24]
0x55
BQ10_D2_BYT2[7:0]
0x00
Programmable biquad 10, D2 coefficient byte[23:16]
0x56
BQ10_D2_BYT3[7:0]
0x00
Programmable biquad 10, D2 coefficient byte[15:8]
0x57
BQ10_D2_BYT4[7:0]
0x00
Programmable biquad 10, D2 coefficient byte[7:0]
0x58
BQ11_N0_BYT1[7:0]
0x7F
Programmable biquad 11, N0 coefficient byte[31:24]
0x59
BQ11_N0_BYT2[7:0]
0xFF
Programmable biquad 11, N0 coefficient byte[23:16]
0x5A
BQ11_N0_BYT3[7:0]
0xFF
Programmable biquad 11, N0 coefficient byte[15:8]
0x5B
BQ11_N0_BYT4[7:0]
0xFF
Programmable biquad 11, N0 coefficient byte[7:0]
0x5C
BQ11_N1_BYT1[7:0]
0x00
Programmable biquad 11, N1 coefficient byte[31:24]
0x5D
BQ11_N1_BYT2[7:0]
0x00
Programmable biquad 11, N1 coefficient byte[23:16]
0x5E
BQ11_N1_BYT3[7:0]
0x00
Programmable biquad 11, N1 coefficient byte[15:8]
0x5F
BQ11_N1_BYT4[7:0]
0x00
Programmable biquad 11, N1 coefficient byte[7:0]
0x60
BQ11_N2_BYT1[7:0]
0x00
Programmable biquad 11, N2 coefficient byte[31:24]
0x61
BQ11_N2_BYT2[7:0]
0x00
Programmable biquad 11, N2 coefficient byte[23:16]
0x62
BQ11_N2_BYT3[7:0]
0x00
Programmable biquad 11, N2 coefficient byte[15:8]
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Table 187. Page 0x03 Programmable Coefficient Registers (continued)
0x63
BQ11_N2_BYT4[7:0]
0x00
Programmable biquad 11, N2 coefficient byte[7:0]
0x64
BQ11_D1_BYT1[7:0]
0x00
Programmable biquad 11, D1 coefficient byte[31:24]
0x65
BQ11_D1_BYT2[7:0]
0x00
Programmable biquad 11, D1 coefficient byte[23:16]
0x66
BQ11_D1_BYT3[7:0]
0x00
Programmable biquad 11, D1 coefficient byte[15:8]
0x67
BQ11_D1_BYT4[7:0]
0x00
Programmable biquad 11, D1 coefficient byte[7:0]
0x68
BQ11_D2_BYT1[7:0]
0x00
Programmable biquad 11, D2 coefficient byte[31:24]
0x69
BQ11_D2_BYT2[7:0]
0x00
Programmable biquad 11, D2 coefficient byte[23:16]
0x6A
BQ11_D2_BYT3[7:0]
0x00
Programmable biquad 11, D2 coefficient byte[15:8]
0x6B
BQ11_D2_BYT4[7:0]
0x00
Programmable biquad 11, D2 coefficient byte[7:0]
0x6C
BQ12_N0_BYT1[7:0]
0x7F
Programmable biquad 12, N0 coefficient byte[31:24]
0x6D
BQ12_N0_BYT2[7:0]
0xFF
Programmable biquad 12, N0 coefficient byte[23:16]
0x6E
BQ12_N0_BYT3[7:0]
0xFF
Programmable biquad 12, N0 coefficient byte[15:8]
0x6F
BQ12_N0_BYT4[7:0]
0xFF
Programmable biquad 12, N0 coefficient byte[7:0]
0x70
BQ12_N1_BYT1[7:0]
0x00
Programmable biquad 12, N1 coefficient byte[31:24]
0x71
BQ12_N1_BYT2[7:0]
0x00
Programmable biquad 12, N1 coefficient byte[23:16]
0x72
BQ12_N1_BYT3[7:0]
0x00
Programmable biquad 12, N1 coefficient byte[15:8]
0x73
BQ12_N1_BYT4[7:0]
0x00
Programmable biquad 12, N1 coefficient byte[7:0]
0x74
BQ12_N2_BYT1[7:0]
0x00
Programmable biquad 12, N2 coefficient byte[31:24]
0x75
BQ12_N2_BYT2[7:0]
0x00
Programmable biquad 12, N2 coefficient byte[23:16]
0x76
BQ12_N2_BYT3[7:0]
0x00
Programmable biquad 12, N2 coefficient byte[15:8]
0x77
BQ12_N2_BYT4[7:0]
0x00
Programmable biquad 12, N2 coefficient byte[7:0]
0x78
BQ12_D1_BYT1[7:0]
0x00
Programmable biquad 12, D1 coefficient byte[31:24]
0x79
BQ12_D1_BYT2[7:0]
0x00
Programmable biquad 12, D1 coefficient byte[23:16]
0x7A
BQ12_D1_BYT3[7:0]
0x00
Programmable biquad 12, D1 coefficient byte[15:8]
0x7B
BQ12_D1_BYT4[7:0]
0x00
Programmable biquad 12, D1 coefficient byte[7:0]
0x7C
BQ12_D2_BYT1[7:0]
0x00
Programmable biquad 12, D2 coefficient byte[31:24]
0x7D
BQ12_D2_BYT2[7:0]
0x00
Programmable biquad 12, D2 coefficient byte[23:16]
0x7E
BQ12_D2_BYT3[7:0]
0x00
Programmable biquad 12, D2 coefficient byte[15:8]
0x7F
BQ12_D2_BYT4[7:0]
0x00
Programmable biquad 12, D2 coefficient byte[7:0]
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8.6.2.3 Programmable Coefficient Registers: Page = 0x04
This register page (shown in Table 188) consists of the programmable coefficients for mixer 1 to mixer 4 and the
first-order IIR filter. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format. The
value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero data)
and all values in between set the mixer attenuation computed using Equation 4. If the MSB is set to '1' then the
attenuation remains the same but the signal phase is inverted. All IIR filter programmable coefficients are 32-bit,
two’s complement numbers. For a successful coefficient register transaction, the host device must write and read
all four bytes starting with the most significant byte (BYT1) for a target coefficient register transaction. When
using SPI for a coefficient register read transaction, the device transits the first byte as a dummy read byte;
therefore, the host must read five bytes, including the first dummy read byte and the last four bytes
corresponding to the coefficient register value starting with the most significant byte (BYT1).
hex2dec (value) / 231
(4)
Table 188. Page 0x04 Programmable Coefficient Registers
ADDR
142
REGISTER
0x00
PAGE[7:0]
0x08
0x09
RESET
DESCRIPTION
0x00
Device page register
MIX1_CH1_BYT1[7:0]
0x7F
Digital mixer 1, channel 1 coefficient byte[31:24]
MIX1_CH1_BYT2[7:0]
0xFF
Digital mixer 1, channel 1 coefficient byte[23:16]
0x0A
MIX1_CH1_BYT3[7:0]
0xFF
Digital mixer 1, channel 1 coefficient byte[15:8]
0x0B
MIX1_CH1_BYT4[7:0]
0xFF
Digital mixer 1, channel 1 coefficient byte[7:0]
0x0C
MIX1_CH2_BYT1[7:0]
0x00
Digital mixer 1, channel 2 coefficient byte[31:24]
0x0D
MIX1_CH2_BYT2[7:0]
0x00
Digital mixer 1, channel 2 coefficient byte[23:16]
0x0E
MIX1_CH2_BYT3[7:0]
0x00
Digital mixer 1, channel 2 coefficient byte[15:8]
0x0F
MIX1_CH2_BYT4[7:0]
0x00
Digital mixer 1, channel 2 coefficient byte[7:0]
0x10
MIX1_CH3_BYT1[7:0]
0x00
Digital mixer 1, channel 3 coefficient byte[31:24]
0x11
MIX1_CH3_BYT2[7:0]
0x00
Digital mixer 1, channel 3 coefficient byte[23:16]
0x12
MIX1_CH3_BYT3[7:0]
0x00
Digital mixer 1, channel 3 coefficient byte[15:8]
0x13
MIX1_CH3_BYT4[7:0]
0x00
Digital mixer 1, channel 3 coefficient byte[7:0]
0x14
MIX1_CH4_BYT1[7:0]
0x00
Digital mixer 1, channel 4 coefficient byte[31:24]
0x15
MIX1_CH4_BYT2[7:0]
0x00
Digital mixer 1, channel 4 coefficient byte[23:16]
0x16
MIX1_CH4_BYT3[7:0]
0x00
Digital mixer 1, channel 4 coefficient byte[15:8]
0x17
MIX1_CH4_BYT4[7:0]
0x00
Digital mixer 1, channel 4 coefficient byte[7:0]
0x18
MIX2_CH1_BYT1[7:0]
0x00
Digital mixer 2, channel 1 coefficient byte[31:24]
0x19
MIX2_CH1_BYT2[7:0]
0x00
Digital mixer 2, channel 1 coefficient byte[23:16]
0x1A
MIX2_CH1_BYT3[7:0]
0x00
Digital mixer 2, channel 1 coefficient byte[15:8]
0x1B
MIX2_CH1_BYT4[7:0]
0x00
Digital mixer 2, channel 1 coefficient byte[7:0]
0x1C
MIX2_CH2_BYT1[7:0]
0x7F
Digital mixer 2, channel 2 coefficient byte[31:24]
0x1D
MIX2_CH2_BYT2[7:0]
0xFF
Digital mixer 2, channel 2 coefficient byte[23:16]
0x1E
MIX2_CH2_BYT3[7:0]
0xFF
Digital mixer 2, channel 2 coefficient byte[15:8]
0x1F
MIX2_CH2_BYT4[7:0]
0xFF
Digital mixer 2, channel 2 coefficient byte[7:0]
0x20
MIX2_CH3_BYT1[7:0]
0x00
Digital mixer 2, channel 3 coefficient byte[31:24]
0x21
MIX2_CH3_BYT2[7:0]
0x00
Digital mixer 2, channel 3 coefficient byte[23:16]
0x22
MIX2_CH3_BYT3[7:0]
0x00
Digital mixer 2, channel 3 coefficient byte[15:8]
0x23
MIX2_CH3_BYT4[7:0]
0x00
Digital mixer 2, channel 3 coefficient byte[7:0]
0x24
MIX2_CH4_BYT1[7:0]
0x00
Digital mixer 2, channel 4 coefficient byte[31:24]
0x25
MIX2_CH4_BYT2[7:0]
0x00
Digital mixer 2, channel 4 coefficient byte[23:16]
0x26
MIX2_CH4_BYT3[7:0]
0x00
Digital mixer 2, channel 4 coefficient byte[15:8]
0x27
MIX2_CH4_BYT4[7:0]
0x00
Digital mixer 2, channel 4 coefficient byte[7:0]
0x28
MIX3_CH1_BYT1[7:0]
0x00
Digital mixer 3, channel 1 coefficient byte[31:24]
0x29
MIX3_CH1_BYT2[7:0]
0x00
Digital mixer 3, channel 1 coefficient byte[23:16]
0x2A
MIX3_CH1_BYT3[7:0]
0x00
Digital mixer 3, channel 1 coefficient byte[15:8]
0x2B
MIX3_CH1_BYT4[7:0]
0x00
Digital mixer 3, channel 1 coefficient byte[7:0]
0x2C
MIX3_CH2_BYT1[7:0]
0x00
Digital mixer 3, channel 2 coefficient byte[31:24]
0x2D
MIX3_CH2_BYT2[7:0]
0x00
Digital mixer 3, channel 2 coefficient byte[23:16]
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SBAS884A – MARCH 2020 – REVISED JUNE 2020
Table 188. Page 0x04 Programmable Coefficient Registers (continued)
0x2E
MIX3_CH2_BYT3[7:0]
0x00
Digital mixer 3, channel 2 coefficient byte[15:8]
0x2F
MIX3_CH2_BYT4[7:0]
0x00
Digital mixer 3, channel 2 coefficient byte[7:0]
0x30
MIX3_CH3_BYT1[7:0]
0x7F
Digital mixer 3, channel 3 coefficient byte[31:24]
0x31
MIX3_CH3_BYT2[7:0]
0xFF
Digital mixer 3, channel 3 coefficient byte[23:16]
0x32
MIX3_CH3_BYT3[7:0]
0xFF
Digital mixer 3, channel 3 coefficient byte[15:8]
0x33
MIX3_CH3_BYT4[7:0]
0xFF
Digital mixer 3, channel 3 coefficient byte[7:0]
0x34
MIX3_CH4_BYT1[7:0]
0x00
Digital mixer 3, channel 4 coefficient byte[31:24]
0x35
MIX3_CH4_BYT2[7:0]
0x00
Digital mixer 3, channel 4 coefficient byte[23:16]
0x36
MIX3_CH4_BYT3[7:0]
0x00
Digital mixer 3, channel 4 coefficient byte[15:8]
0x37
MIX3_CH4_BYT4[7:0]
0x00
Digital mixer 3, channel 4 coefficient byte[7:0]
0x38
MIX4_CH1_BYT1[7:0]
0x00
Digital mixer 4, channel 1 coefficient byte[31:24]
0x39
MIX4_CH1_BYT2[7:0]
0x00
Digital mixer 4, channel 1 coefficient byte[23:16]
0x3A
MIX4_CH1_BYT3[7:0]
0x00
Digital mixer 4, channel 1 coefficient byte[15:8]
0x3B
MIX4_CH1_BYT4[7:0]
0x00
Digital mixer 4, channel 1 coefficient byte[7:0]
0x3C
MIX4_CH2_BYT1[7:0]
0x00
Digital mixer 4, channel 2 coefficient byte[31:24]
0x3D
MIX4_CH2_BYT2[7:0]
0x00
Digital mixer 4, channel 2 coefficient byte[23:16]
0x3E
MIX4_CH2_BYT3[7:0]
0x00
Digital mixer 4, channel 2 coefficient byte[15:8]
0x3F
MIX4_CH2_BYT4[7:0]
0x00
Digital mixer 4, channel 2 coefficient byte[7:0]
0x40
MIX4_CH3_BYT1[7:0]
0x00
Digital mixer 4, channel 3 coefficient byte[31:24]
0x41
MIX4_CH3_BYT2[7:0]
0x00
Digital mixer 4, channel 3 coefficient byte[23:16]
0x42
MIX4_CH3_BYT3[7:0]
0x00
Digital mixer 4, channel 3 coefficient byte[15:8]
0x43
MIX4_CH3_BYT4[7:0]
0x00
Digital mixer 4, channel 3 coefficient byte[7:0]
0x44
MIX4_CH4_BYT1[7:0]
0x7F
Digital mixer 4, channel 4 coefficient byte[31:24]
0x45
MIX4_CH4_BYT2[7:0]
0xFF
Digital mixer 4, channel 4 coefficient byte[23:16]
0x46
MIX4_CH4_BYT3[7:0]
0xFF
Digital mixer 4, channel 4 coefficient byte[15:8]
0x47
MIX4_CH4_BYT4[7:0]
0xFF
Digital mixer 4, channel 4 coefficient byte[7:0]
0x48
IIR_N0_BYT1[7:0]
0x7F
Programmable first-order IIR, N0 coefficient byte[31:24]
0x49
IIR_N0_BYT2[7:0]
0xFF
Programmable first-order IIR, N0 coefficient byte[23:16]
0x4A
IIR_N0_BYT3[7:0]
0xFF
Programmable first-order IIR, N0 coefficient byte[15:8]
0x4B
IIR_N0_BYT4[7:0]
0xFF
Programmable first-order IIR, N0 coefficient byte[7:0]
0x4C
IIR_N1_BYT1[7:0]
0x00
Programmable first-order IIR, N1 coefficient byte[31:24]
0x4D
IIR_N1_BYT2[7:0]
0x00
Programmable first-order IIR, N1 coefficient byte[23:16]
0x4E
IIR_N1_BYT3[7:0]
0x00
Programmable first-order IIR, N1 coefficient byte[15:8]
0x4F
IIR_N1_BYT4[7:0]
0x00
Programmable first-order IIR, N1 coefficient byte[7:0]
0x50
IIR_D1_BYT1[7:0]
0x00
Programmable first-order IIR, D1 coefficient byte[31:24]
0x51
IIR_D1_BYT2[7:0]
0x00
Programmable first-order IIR, D1 coefficient byte[23:16]
0x52
IIR_D1_BYT3[7:0]
0x00
Programmable first-order IIR, D1 coefficient byte[15:8]
0x53
IIR_D1_BYT4[7:0]
0x00
Programmable first-order IIR, D1 coefficient byte[7:0]
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The PCM6xx0-Q1 are multichannel, automotive qualified audio analog-to-digital converters (ADCs) that support
output sample rates of up to 384 kHz. The PCM6x60-Q1 support up to six analog microphones and the
PCM6x40-Q1 support up to four analog microphones for simultaneous recording applications. The PCM6xx0-Q1
family is intended for automotive applications such as vehicle cabin active noise cancellation, hands-free invehicle communication, emergency call, and multi-media applications. These devices integrate a host of features
to reduce cost, board space, and power consumption in space-constrained automotive subsystem designs.
Communication to the PCM6xx0-Q1 for configuration of the control registers is supported using an I2C or SPI
interface. The device supports a highly flexible audio serial interface (TDM, I2S, or LJ) to transmit audio data
seamlessly in the system across devices.
9.2 Typical Applications
9.2.1 Four-Channel Analog Microphone Recording Using the PCM6240-Q1
Figure 230 shows a typical configuration of the PCM6240-Q1 for an application using four analog microphones
for simultaneous recording operation with an I2C control interface and the TDM audio data slave interface.
2.2 F
3.3 V
(3.0 V to 3.6 V)
2.2 F
10 F
1 F
3.3 V
(3.0 V to 3.6 V)
0.1 F
GND
VBAT_IN
(Max 18V)
0.1 F
GND
0.1 F
GND
0.1 F
GND
AVDD
AREG
VREF
AVSS
BSTVDD
BSTSW
1 F
GND
BSTOUT
VBAT_IN
1 F
GND
2.2µH
10 F
DREG
0.1 F
MICBIAS
R1
GND
IN1P
Mic 1
10 F
IN1M
R1
IOVDD
3.3 V
(3.0 V to 3.6 V)
OR
1.8 V
(1.65 V to 1.95 V)
R1
0.1 F
GND
IN2P
Mic 2
GND
Thermal Pad
(VSS)
PCM6240-Q1
IN2M
R1
GND
R1
ADDR1_MISO
(ADDR1)
GND
IN3P
GND
IN3M
R1
ADDR0_SCLK
(ADDR0)
GND
SDA_SSZ
(SDA)
GPIO1
BCLK
SDOUT
SHDNZ
R1
FSYNC
GPIO2
GPIO3
IN4M
GPI1
IN4P
Mic 4
GPI2
R1
GND
SCL_MOSI
(SCL)
Mic 3
R2
GND
R2
Host
Processor
Figure 230. Four-Channel Analog Microphone Recording
144
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Typical Applications (continued)
9.2.1.1 Design Requirements
Table 189 lists the design parameters for this application.
Table 189. Design Parameters
KEY PARAMETER
SPECIFICATION
AVDD, BSTVDD
3.3 V
AVDD supply current
24 mA (PLL on, four-channel record, fS = 44.1 kHz)
IOVDD
1.8 V or 3.3 V
Maximum MICBIAS current
< 28 mA (MICBIAS voltage = 8 V, microphone
impedance = 680 Ω and R1 = 340 Ω)
9.2.1.2 Detailed Design Procedure
This section describes the necessary steps to configure the PCM6240-Q1 for this specific application. The
following steps give a sequence of items that must be executed in the time between powering the device up and
reading data from the device or transitioning from one mode to other mode of operation.
1. Apply Power to Device:
a. Power up the IOVDD, AVDD, and BSTVDD power supplies, keeping the SHDNZ pin voltage low
b. The device now goes into hardware shutdown mode (ultra-low-power mode < 1 µA)
2. Transition From Hardware Shutdown Mode to Sleep Mode (or Software Shutdown Mode):
a. Release SHDNZ only when the IOVDD, AVDD, and BSTVDD power supplies settle to the steady-state
operating voltage
b. Wait for at least 1 ms to allow the device to initialize the internal registers
c. The device now goes into sleep mode (low-power mode < 20 µA)
3. Transition From Sleep Mode to Active Mode Whenever Required for the Record Operation:
a. Wake-up the device by writing P0_R2 to disable sleep mode
b. Wait for at least 1ms to allow the device internal wake-up sequence to complete
c. Override the default configuration registers or programmable coefficients value as required (optional)
d. Enable all desired input channels by writing P0_R115
e. Enable all desired audio serial interface output channels by writing P0_R116
f. Power-up the ADC, MICBIAS, and PLL by writing P0_R117
g. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio
This specific step can be done at any point in the sequence after step a
See the Phase-Locked Loop (PLL) and Clock Generation section for the supported sample rates and the
BCLK to FSYNC ratio
h. The device recording data are now sent to the host processor via the TDM audio serial data bus
i. Wait for at least 10 ms to allow the MICBIAS to power up
j. Enable the fault diagnostics for all desired input channels by writing P0_R100
4. Transition From Active Mode to Sleep Mode (Again) as Required in the System Low Power:
a. Disable the fault diagnostics for all desired input channels by writing P0_R100
b. Go to sleep mode by writing P0_R2 to enable sleep mode
c. Wait at least 20 ms to allow the volume to gradually ramp down and for all blocks to power down
d. Read P0_R119 to check the device shutdown and sleep mode status
e. If the device P0_R119_D7 status bit is 1'b1, then stop FSYNC and BCLK in the system
f. The device now goes into sleep mode (low-power mode < 20 µA) and retains all register values
5. Transition From Sleep Mode to Active Mode (Again) as Required for the Record Operation:
a. Wake-up the device by writing P0_R2 to disable sleep mode
b. Wait for at least 1 ms to allow the device internal wake-up sequence to complete
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c. Apply FSYNC and BCLK with the desired output sample rates and BCLK to FSYNC ratio
d. The device recording data are now sent to the host processor via the TDM audio serial data bus
e. Wait for at least 10 ms to allow the MICBIAS to power up
f. Enable the fault diagnostics for all desired input channels by writing P0_R100
6. Repeat Step 4 and Step 5 as Required for Mode Transitions
7. Assert the SHDNZ Pin Low to Enter Hardware Shutdown Mode (Again) at Any Time
8. Follow Step 2 Onwards to Exit Hardware Shutdown Mode (Again)
9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
This section provides a typical EVM I2C register control script that shows how to set up the PCM6240-Q1 in a 4channel analog microphone record mode with differential inputs.
#
# Key: w 98 XX YY ==> write to I2C address 0x98, to register 0xXX, data 0xYY
#
# ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# Refer to the PCM6240-Q1 EVM user guide for key jumper settings and audio connections:
#
# Differential 4-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2, INP3/INM3 - Ch3 and INP4/INM4 - Ch4
# High swing mode enabled
# FSYNC = 44.1 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD, AVDD and BSTVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD, AVDD and BSTVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms.
#
# Wake-up device by I2C write into P0_R2 using internal AREG
w 90 02 81
#
# Powerdown MICBIAS and ADC channels on fault detection (overtemperature, and so forth)
w 90 28 10
#
# Configure channel 1 DC-coupled, differential microphone input with high-swing mode
w 90 3C 18
#
# Configure channel 2 DC-coupled, differential microphone input with high-swing mode
w 90 41 18
#
# Configure channel 3 DC-coupled, differential microphone input with high-swing mode
w 90 46 18
#
# Configure channel 4 DC-coupled, differential microphone input with high-swing mode
w 90 4B 18
#
# Enable input channel 1 to channel 4 by I2C write into P0_R115
w 90 73 F0
#
# Enable ASI output channel 1 to channel 4 slots by I2C write into P0_R116
w 90 74 F0
#
# Power-up ADC,MICBIAS and PLL by I2C write into P0_R117
w 90 75 E0
#
# Apply FSYNC = 44.1 kHz and BCLK = 11.2896 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bit channel word length
#
# Wait for 10 ms.
# Enable diagnostics for channel 1 to channel 4 by I2C write into P0_R100
w 90 64 F0
#
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9.2.1.3 Application Curves
0
-20
-70
Channel-1
Channel-2
Channel-3
Channel-4
-80
-60
THD+N (dBFS)
Output Amplitude (dBFS)
-40
-60
Channel-1
Channel-2
Channel-3
Channel-4
-80
-100
-120
-140
-90
-100
-110
-160
-120
-180
-200
20
50
100
500
1000
5000
Frequency (Hz)
10000 20000
EVM_
DC-coupled differential microphone input with DC common-mode
1NxP = ~6 V and INxM = ~2 V, high swing mode enabled,
measured using an external audio input source
Figure 231. FFT With a –60-dBr Input
-130
-130
-115
-100
-85
-70
-55
-40
-25
Input Amplitude (dB)
-12
EVM_
THD+
DC-coupled differential microphone input with DC common-mode
1NxP = ~6 V and INxM = ~2 V, high swing mode enabled,
measured using an external audio input source
Figure 232. THD+N vs Input Amplitude
9.3 What To Do and What Not To Do
In master mode operation with I2S or LJ format, the device generates FSYNC half a cycle earlier than the normal
protocol timing behavior expected. This timing behavior can still function for most of the system, however for
further details and a suggested workaround for this weakness, see the Configuring and Operating
TLV320ADCx140 as Audio Bus Master application report.
The automatic gain controller (AGC) feature has some limitation when using sampling rates lower than 44.1 kHz.
For further details about this limitation, see the Using the Automatic Gain Controller in PCM6xx0-Q1 application
report.
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10 Power Supply Recommendations
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, keep
the SHDNZ pin low until the IOVDD supply voltage settles to a stable and supported operating voltage range.
After the IOVDD and AVDD supplies are stable, set the SHDNZ pin high to initialize the device. BSTVDD (or
HVDD for the PCM63x0-Q1) can be either applied along with AVDD or later but before turning on the MICBIAS.
Figure 233 shows the power supply sequencing requirements.
AVDD
t1
IOVDD
t3
SHDNZ
t2
t4
Figure 233. Power-Supply Sequencing Requirement
For the supply power-up requirement, t1 and t2 must be at least 100 µs. For the supply power-down requirement,
t3 and t4 must be at least 10 ms. This time allows the device to ramp down the volume on the record data, and
power down the analog and digital blocks, and lastly put the device into hardware shutdown mode. The device
can also be immediately put into hardware shutdown mode from active mode if SHDNZ_CFG[1:0] is set to 2'b00
using the P0_R5_D[3:2] bits. In that case, t3 and t4 are required to be at least 100 µs.
Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a
power-up event is at least 100 ms. For a supply ramp rate slower than 0.1 V/ms, the host device must apply a
software reset as the first transaction before configuring the device.
After releasing SHDNZ, or after a software reset, delay any additional I2C or SPI transactions to the device for at
least 2 ms to allow the device to initialize the internal registers. See the Device Functional Modes section to
operate the device in various modes after the device power supplies are settled to the recommended operating
voltage levels.
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11 Layout
11.1 Layout Guidelines
Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in
the context of a specific PCB design. However, the following guidelines can optimize the device performance:
• Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, the area directly
under the device, to the ground planes. This connection helps dissipate heat from the device.
• The decoupling capacitors for the power supplies must be placed close to the device pins.
• The supply decoupling capacitors used must be of a ceramic type with low ESR.
• The boost converter inductor and decoupling capacitors for the power supplies must be placed close to the
device pins.
• Route analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing
digital and analog signals to avoid undesirable crosstalk.
• The device internal voltage references must be filtered using external capacitors. Place the filter capacitors
near the VREF pin for optimal performance.
• Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply for multiple
microphones to avoid coupling across microphones.
• Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace
impedance.
• Use MICBIAS and BSTOUT capacitors with a high voltage rating (> 25V) to support higher voltage MICBIAS
operation.
• An external circuit must be used to suppress or filter the amount of high-frequency electromagnetic
interference (EMI) noise found in the microphone input path resulting from long cables (if used) in the system.
• Use ground planes to provide the lowest impedance for power and signal current between the device and the
decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and
all device grounds must be connected directly to that area.
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11.2 Layout Examples
1: AVDD
24: ADDR0_SCLK
2: AREG
23: ADDR1_MISO
3: BSTVDD
22: SHDNZ
4: BSTSW
21: VBAT_IN
5: BSTOUT
20: IN6M
6: MICBIAS
19: IN6P
18: IN5M
7: VREF
8: AVSS
16: IN4M
15: IN4P
14: IN3M
13: IN3P
12: IN2M
11: IN2P
9: IN1P
10: IN1M
17: IN5P
Analog input and digital interface
25: SCL_MOSI
26: SDA_SSZ
28: GPIO1
27: IOVDD
29: SDOUT
30: BCLK
32: DREG
Power connections
31: FSYNC
Audio output and digital interface
Analog input signals
Figure 234. Layout Example of the PCM6260-Q1
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Layout Examples (continued)
1: AVDD
24: ADDR0_SCLK
2: AREG
23: ADDR1_MISO
3: AVDD
22: SHDNZ
4: AVSS
21: VBAT_IN
20: IN6M
5: HVDD
6: MICBIAS
19: IN6P
15: IN4P
16: IN4M
13: IN3P
14: IN3M
11: IN2P
12: IN2M
17: IN5P
9: IN1P
18: IN5M
8: AVSS
10: IN1M
7: VREF
Analog input and digital interface
25: SCL_MOSI
26: SDA_SSZ
28: GPIO1
27: IOVDD
30: BCLK
29: SDOUT
32: DREG
Power connections
31: FSYNC
Audio output and digital interface
Analog input signals
Figure 235. Layout Example of the PCM6360-Q1
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
PurePath™ console graphical development suite
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Multiple PCM6xx0-Q1 Devices With Shared TDM and I2C Bus application report
• Texas Instruments, PCM6xx0-Q1 Programmable Biquad Filter Configuration and Applications application
report
• Texas Instruments, PCM6xx0-Q1 Sampling Rates and Programmable Processing Blocks Supported
application report
• Texas Instruments, PCM6xx0-Q1 Integrated Analog Anti-Aliasing Filter and Flexible Digital Filter application
report
• Texas Instruments, Configuring and Operating TLV320ADCx140 as Audio Bus Master application report
• Texas Instruments, Using the Automatic Gain Controller in PCM6xx0-Q1 application report
• Texas Instruments, PCM6xx0-Q1 Fault Diagnostics Features application report
• Texas Instruments, Scalable Automotive Audio Solutions Using the PCM6xx0-Q1 Family of Products
application report
• Texas Instruments, PCM6xx0-Q1 Use-Case Scenarios in Automotive Audio Applications application report
• Texas Instruments, PCM6xx0-Q1 AC-Coupled External Resistor Calculator
• Texas Instruments, PCM6xx0-Q1 SIMULATION IBIS Models
• Texas Instruments, PCM6xx0Q1EVM-PDK Evaluation Module user's guide
• Texas Instruments, PurePath™ Console Graphical Development Suite for Audio System Design and
Development development suite
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 190. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PCM6240-Q1
Click here
Click here
Click here
Click here
Click here
PCM6260-Q1
Click here
Click here
Click here
Click here
Click here
PCM6340-Q1
Click here
Click here
Click here
Click here
Click here
PCM6360-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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12.6 Trademarks
PurePath, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM6240QRTVRQ1
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PCM6240
PCM6260QRTVRQ1
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PCM6260
PCM6340QRTVRQ1
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PCM6340
PCM6360QRTVRQ1
ACTIVE
WQFN
RTV
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PCM6360
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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