PCM67P

® PCM67P/U PCM69AP/AU Advanced 1-Bit BiCMOS Dual 18-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES q 18-BIT RESOLUTION DUAL AUDIO DAC q EXCELLENT THD PERFORMANCE: 0.0025% (–92dB) at F/S, K Grade 1.0% (–40dB) at –60dB, K Grade q HIGH S/N RATIO: 110dB typ (IHF-A) q DUAL, CO-PHASE q SINGLE SUPPLY +5V OPERATION q LOW POWER: 75mW typical q CAPABLE OF 16X OVERSAMPLING q AVAILABLE IN SPACE SAVING 16-PIN DIP OR 20-PIN SOIC q OPERATING TEMP RANGE: –25°C to +85°C q EXTREMELY LOW GLITCH ENERGY DESCRIPTION The PCM67 and PCM69A dual 18-bit DAC are low cost, dual output 18-bit BiCMOS digital-to-analog converters utilizing a novel architecture to achieve excellent low level performance. By combining a conventional thin-film R-2R ladder DAC, a digital offset technique with analog correction and an advanced one-bit DAC using first order noise shaping technique, the PCM67 and PCM69A achieve high resolution, minimal glitch, and low zero-crossing distortion. PCM67 digital offset occurs at bit 9, making it ideal for high-performance CD players. PCM69A digital offset occurs at bit 4, making it an excellent choice for digital musical instruments and audio DSP. Both PCM67 and PCM69A operate from a single +5V supply. The low power consumption and small size (16pin PDIP or 20-pin SOIC) make these converters ideal for a variety of digital audio applications. 10-Bit DAC plus Analog Correction Reference Servo Advanced 1-Bit DAC Analog Output Lch Buffer VCOM Lch 10-Bit DAC plus Analog Correction Digital Signal In Input Interface Advanced 1-Bit DAC Buffer VCOM Rch Analog Output Rch International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1992 Burr-Brown Corporation • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PDS-1168A Printed in U.S.A. August, 1993 SBAS024 SPECIFICATIONS ELECTRICAL All specifications at +25°C and +VA, +VD = +5V unless otherwise noted PCM67/69A PARAMETER RESOLUTION DYNAMIC RANGE, THD+N at –60dB Referred to Full Scale DIGITAL INPUT Logic Family Logic Level: VIH VIL Data Format Input System Clock Frequency TOTAL HARMONIC DISTORTION + N(2,3,4) PCM67P/69AP, PCM67U/69AU f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) PCM67P-J/69AP-J, PCM67U-J/69AU-J f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) PCM67P-K/69AP-K, PCM67U-K/69AU-K f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) CHANNEL SEPARATION ACCURACY Level Linearity Gain Error Gain Mismatch, Channel-to-Channel Gain Drift Warm-up Time IDLE CHANNEL SNR(5) ANALOG OUTPUT Output Range (±3%) Output Impedance (±30%) VCOM Glitch Energy POWER SUPPLY REQUIREMENTS, System Clock = 16.9344MHz +VA, +VD Supply Voltage Range +VA = +VD +IA, +ID Combined Supply Current +VA, +VD = +5V Power Dissipation +VA, +VD = +5V TEMPERATURE RANGE Operating Storage CONDITIONS MIN TYP 18 106 MAX UNITS Bits dB TTL/CMOS Compatible IIH = ±5µA IIL = ±5µA +2 0 Serial, MSB First, BTC(1) 16.9344 +VD 0.8 V V MHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz (f = 1kHz) –86 –68 –40 –91 –72 –46 –95 –74 –46 106 ±1 ±3 ±1 95 1 110 –82 –34 –88 –40 –92 –40 dB dB dB dB dB dB dB dB dB dB at –90dB Signal Level 0°C to +70°C 20Hz to 40kHz at BPZ(6) ±10 ±5 dB % % ppm/°C Minute dB 3.35 1.2 1.8 3.50 No Glitch Around Zero 3.65 mA kΩ V +4.75 +5.00 15 75 +5.25 20 105 V mA mW °C °C –25 –55 +85 +100 NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS)/SignalRMS. (3) D/A converter output frequency/signal level (both left and right channels are “on”). (4) D/A converter sample frequency (8 x 44.1kHz; 8X oversampling per channel). (5) Ratio of NoiseRMS/SignalRMS. Measured using a 40kHz 3rd-order GIC (Generalized Immittance Converter) filter and an A-weighted filter. (6) Bipolar Zero. USA OEM PRICES The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM67/69A 2 PIN ASSIGNMENTS PCM67P PCM67U DESCRIPTION +5V Analog Supply Voltage Left Voltage Common No Connection Left Current Output (0 to 1.2mA) Servo Decoupling Capacitor Reference Decoupling Capacitor Right Current Output (0 to 1.2mA) No Connection Right Voltage Common Analog Common Digital Common Mode Control 2 Right Data Input Bit Clock System Clock Word Clock Left Data Input Mode Control 3 Mode Control 1 +5V Digital Supply Voltage MNEMONIC +VA LVCOM NC LIOUT SRVCAP REFCAP RIOUT NC RVCOM ACOM DCOM MC2 RDATA BTCK SYSCK WDCK LDATA MC3 MC1 +VD PCM69AP PCM69AU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ABSOLUTE MAXIMUM RATINGS +VA, +VD to ACOM, DCOM ................................................... 0V to +6.5V ACOM to DCOM ............................................................................... ±0.5V Digital Inputs to DCOM ............................................ –0.3V to +VD + 0.3V Power Dissipation ................ 300mW (U Package), 500mW (P Package) Lead Temperature, (soldering, 10s) .............................................. +260°C Max Junction Temperature ............................................................ +165°C NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE INFORMATION MODEL PCM67P/69AP PCM67U/69AU PACKAGE 16-Pin Plastic DIP 20-Pin SOIC PACKAGE DRAWING NUMBER(1) 180 248 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 PCM67/69A PIN CONFIGURATION — PCM67P/69AP (16-Pin DIP) Data-L WDCK SYS CLOCK BCK 1µF Data-R 16 15 14 13 12 11 10 9 PCM67P/69AP +VCC (+5V) 1 10µF 2 3 4 5 6 7 8 3.3µF RNF 3.3µF RNF 10µF Lch OUT 10µF Rch OUT PIN CONFIGURATION — PCM67U/69AU (20-Pin SOIC) Data-L WDCK SYS CLOCK BCK 1µF Data-R 20 19 18 17 16 15 14 13 12 11 PCM67U/69AU +VCC (+5V) 1 10µF 2 3 4 5 6 7 8 9 10 3.3µF RNF 3.3µF RNF 10µF Lch OUT 10µF Rch OUT ® PCM67/69A 4 TYPICAL PERFORMANCE CURVES All specifications at +25°C and VCC = +5.0V unless otherwise noted. THD vs POWER SUPPLY VOLTAGE 0.01% –60dB 0.005% 0.5% 1.0% 3 2 GAIN ERROR / VCOM vs POWER SUPPLY 3.70 Gain Error (%) THD (–60dB) 1 0 –1 VCOM –2 THD (F/S) F/S 0.002% 0.2% 3.50 0.001% 4.75 5.0 VCC (V) 0.1% 5.25 –3 4.75 5.0 VCC (V) 3.40 5.25 THD vs TEMPERATURE 0.01% –60dB 2 GAIN ERROR / VCOM vs TEMPERATURE 1.0% 3 3.70 THD (–60dB) Gain Error (%) 0.005% 0.5% F/S 1 0 –1 –2 3.60 THD (F/S) 0.002% 0.2% 3.50 0.001% –25 0 25 50 85 Temperature (°C) 0.1% 100 –3 –25 0 25 50 75 85 Temperature (%) 3.40 100 THD vs SYSTEM CLOCK FREQUENCY 0.01% fs = 44.1kHz –60dB Separation (dB) CHANNEL SEPARATION vs SIGNAL FREQUENCY 1.0% 115 0.005% THD (F/S) 0.5% THD (–60dB) 110 105 F/S 0.002% 0.2% 100 0.001% 384 192 fs (Hz) 96 48 0.1% 95 100 500 1k f (Hz) 2k 4k 8k 16k … 128k 5 PCM67/69A VCOM (V) ® VCOM (V) Gain Error 3.60 DISCUSSION OF SPECIFICATIONS The PCM67 and PCM69A are specified to provide critical performance criteria for a variety of applications. The accuracy of a D/A converter is described by the transfer function shown in Figure 1. VOUT = 1.2mA • RNF VOUT RNF VCOM 1.2mA Digital In 011...11 +FSR Gain Error IOUT VOUT VCOM (3.5V) FIGURE 2. I/V Amplifier Circuit. 000...00 111...11 BPZ Analog Out BPZ – 1LSB S/N RATIO S/N ratio is defined as the ratio of full scale output and no input noise level at BPZ point. The PCM67/69A is specified at 110dB typical with “IHF-A” filter. LEVEL LINEARITY ERROR Level linearity error is defined as the deviation of actual analog output level from digital input level. PCM67/69A is specified at 1dB typical at –90dB output level. The 0.5LSB quantization error at –90dB of 16-bit conversion is equal to +1.94dB, –2.5dB. TOTAL HARMONIC DISTORTION THD is a key parameter in audio applications, THD is a measure of the magnitude and distribution of the linearity error, differential linearity error, and noise, as well as quantization error. To be useful, THD should be specified for both high level and low level input signals. This error is unadjustable and is the most meaningful indicator of D/A converter accuracy for audio applications. THD is defined as the ratio of the square root of the sum of the squares of the values of the harmonics to the value of the fundamental input frequency and is expressed in percent or dB. The rms value of the PCM67/69A error referred to the input can be shown to be 100...00 –FSR (V = 3.5V) COM FIGURE 1. Transfer Performance. DIGITAL INPUT CODE The PCM67/69A accepts Binary Two’s Complement (BTC) digital input code (MSB FIRST).The relationship of digital input to analog output is shown in Table 1. ANALOG OUTPUT (VOLTAGE) +FSR BPZ BPZ – 1LSB –FSR ANALOG OUTPUT (CURRENT) –1.2mA –0.6mA –0.59995mA 0mA DIGITAL INPUT 7FFFFF (HEX) 00003F (HEX) FFFFFF (HEX) 80003F (HEX) TABLE I. Digital Code and Analog Out. GAIN ERROR AND GAIN MISMATCH, CHANNEL-TO-CHANNEL Gain error is defined as deviation of the output current span from the ideal span of 1.2mA (FSR) on each channel. Gain error of PCM67/69A is typically ±3% of FSR. Gain mismatch, channel-to-channel is defined as the difference in gain error between the left channel and right channel. THE RELATIONSHIP OF VCOM AND I/V OUT The output current range of PCM67 and PCM69A is 0mA to 1.2mA as shown in Table 1. In the typical application, the non-inverting input of the external I/V op amp is connected to the VCOM pin of PCM67 and PCM69A. Accordingly, the output voltage level at FSR after I/V conversion is VCOM voltage (+3.5V) as shown in Figure 2. ε rms = 1 n i=1   ∑ E L (i ) + E Q (i )  n 2 (1) where n is the number of samples in one cycle of any given sine wave, EL(i) is the linearity error of the PCM67 or PCM69A at each sampling point. THD can then be expressed as THD = ε rms Er ms 2 1  n ∑  EL (i ) + EQ (i )  n = i =1 E rms × 100% (2) where Erms is the rms signal-voltage level. ® PCM67/69A 6 This expression indicates that, in general, there is a correlation between the THD and the square root of the sum of the squares of the linearity errors at each digital word of interest. However, this expression does not mean that the worst-case linearity error of the D/A is directly correlated to THD. For PCM67 and PCM69A the test period is set at an 8X oversampling rate (352.8kHz = 44.1kHz • 8), which is the typical sample rate for CD player applications. The test signal frequency is 991Hz and the amplitude of the signal level is F/S (0dB), and –60dB down from F/S. All THD tests are performed without a deglitcher circuit and without a 20kHz low pass filter. SYSTEM CLOCK REQUIREMENTS The PCM67 and PCM69A need a system clock for the one-bit noise shaping DAC operation. The PCM67 is capable of only a 384Fs corollary system clock frequency such as 192Fs, 96Fs (24 times word rate or integer multiple of 24). The PCM69A is capable of any system clock up from 48Fs to 384Fs such as 384Fs, 256Fs, 100Fs with condition for timing as described in “Timing of PCM69A” in Figure 5. The user can choose either model for their application. Table II shows the different SYSCLK options. The PCM67/69A accepts TTL compatible logic input levels. The data format of the PCM67/69A is BTC with the most significant bit (MSB) being first in the serial input bit stream. tSL tSH SYS Clock tDH Data LSB tDSU Bit Clock tCH WD Clock tCL tCW tWC tDHO tWH tWL tSH: tSL: tDW: tDSU: tDHO: tCH: tCL: tCW: tWC: tWH: tWL: SYS Clock High Pulse Width : 15ns, min SYS Clock Low Pulse Width : 15ns, min Data Valid Time : 20ns, min Data Setup Time : 10ns, min Data Hold Time : 5ns, min Bit Clock High Pulse Width : 15ns, min Bit Clock Low Pulse Width : 15ns, min WD Clock Fall Time From Bit Clock Rise : 10ns, min Bit Clock Rise Time From WD Clock Fall : 15ns, min WD Clock High Pulse Width : 1 SYS Clock Cycle, min WD Clock Low Pulse Width : 1 SYS Clock Cycle, min MODEL PCM67 PCM69A BASIC SYSCLK 384Fs OTHER CAPABLE SYSCLK 192Fs, 96Fs FIGURE 4. Timing Specification. TIMING OF PCM69A PCM69A timing is similar to PCM67 except that PCM69A is capable of operating from any system clock up to 384Fs. For synchronized operation, PCM69A system clock and WDCK timing must be as shown in Figure 5. Any Clock (with timing condition) Examples: 384Fs, 300Fs, 256Fs, 200Fs, 90Fs TABLE II. System Clock Requirements. LOGIC TIMING The serial data bit transfers are triggered on positive bit clock (BCK) edges. The serial-to-parallel data transfer to the DAC occurs on the falling edge of Word Clock (WDCK). The change in the output of the DAC coincides with the falling edge of WDCK. Refer to Figure 3 for graphical relationships of these signals. The setup and hold timing relationships for these signals are shown in Figure 4. WDCK tn1 SYSCLK tn2 SYSCLK R-ch Data L-ch Data Bit Clock WD Clock SYS Clock MSB bit2 bit17 LSB MSB bit2 bit17 LSB tn1: WDCK Fall Delay From Rise of SYSCLK : min 10ns tn2: SYSCLK Rise Delay From Fall of WDCK : min 20ns MSB bit2 bit17 LSB MSB bit2 bit17 LSB FIGURE 5. Timing of PCM69A for SYSCLK and WDCK. 1 WDCK FIGURE 3. Timing Diagram. ® 7 PCM67/69A INSTALLATION POWER SUPPLIES Refer to “Pin Configuration” diagram for proper connection of the PCM67/69A. The PCM67/69A requires only a +5V supply. Both analog and digital supplies should be tied together at a single point, as no real advantage is gained by using separate supplies. It is more important that both these supplies be as “clean” as possible to reduce coupling of supply noise to the output. FILTER CAPACITOR REQUIREMENTS As shown in the “Pin Configuration” diagram, various sizes of decoupling capacitors can be used with no special tolerances required. All capacitors should be as close to the appropriate pins of the PCM67/69A as possible to reduce noise pickup from surrounding circuitry. A power supply decoupling capacitor should be used near the analog supply pin to maximize power supply rejection, as shown in Figure 6, regardless of how good the supplies are. Both commons should be connected to an analog ground plane as close to the PCM67/69A as possible. The value of these capacitors is influenced by actual board layout design and noise from power supplies and other digital input lines. The best suitable value for the capacitors should be determined by the user’s actual application board. SHIFT OF I/V OUT VOLTAGE If the user requires a bipolar voltage output centered around 0V or one-half of VCC, the output can be shifted by adding an offset current on the inverting point of the I/V op amp as shown in Figure 6. +VCC (+5V) R1 820Ω RNF 5kΩ 10µF ~ 100µF IOUT + C1 R2 330Ω VOUT VCOM 10µF ~ 100µF + C2 0V 6V Note: R1 and C1 are noise de-coupling circuits from noise on +VCC power supply line. FIGURE 7. Useful Application Circuit for Shift of I/V Out Voltage. VCOM + VO 2 VCOM (+3.5V) VO VCC 2 or 0V VS VO INTERFACE CONTROL FUNCTION Both the PCM67 and PCM69A (SOIC package type) are capable of 16-bit L/R serial input and 20-bit L/R parallel input as shown in Table 3. MC1 0 0 0 0 1 1 1 1 MC2 0 0 1 1 0 0 1 1 MC3 1 1 1 1 1 0 1 0 DATA-R 0 1 0 1 X X X X INPUT FORMAT 16-Bit 16-Bit 18-Bit 18-Bit 20-Bit 20-Bit 18-Bit 18-Bit L/R L/R L/R L/R L/R L/R L/R L/R Serial(1) Serial(1) Serial(1) Serial(1) Parallel Parallel Parallel Parallel LR L R LR L R LR L R LR L R WDCK WDCK WDCK WDCK VSHT +VCC RNF ROS IOUT VOUT VCOM (3.5V) IOS [WDCK Invert] [WDCK Invert] NOTE: (1) Data input to Data-Lch (Pin 17) for L/R serial format. In case of shift to ±3V swing, 0V center V 6V RNF = OUT = = 5kΩ 1.2mA 1.2mA –FSR±(VS) = –3V after offset addition, shift voltage VSHT is given by VSHT = VCOM + 3V = 3.5 + 3 = 6.5V Offset Current IOS is given by VSHT 6.5V IOS = = = 1.3mA RNF 5kΩ Offset Resistor ROS is given by V – VCOM ROS = CC = 5 – 3.5V = 1.15kΩ 1.3mA IOS TABLE III. Interface Control Function of SOIC. PCM67P and PCM69AP (DIP package) have only 18-bit L/R serial input function as shown in Table 4. MC1 0 0 1 DATA-R 0 1 X INPUT FORMAT 18-Bit L/R Serial 18-Bit L/R Serial 18-Bit L/R Parallel L R L R WDCK L R L R WDCK TABLE IV. Interface Control Function of DIP. FIGURE 6. Shift of I/V Out Voltage. ® PCM67/69A 8 DIGITAL FILTER INTERFACE 16-Bit L/R Serial — 1 +VDD PCM67U/69AU 11 DGND 12 MC2 CXD2551 BCK0 X0 or X1 LRCK0 Data L-ch 13 Data R-ch 14 BCK 15 SYSCLK 16 WDCK 17 Data L-ch 18 MC3 4FS, 16-Bit Mode 19 MC1 20 +VDD 18-Bit Mode –VDD DOR BCK0 XTi WDCK0 DOL 18-Bit L/R Parallel SM5840 PCM67U/69AU 11 DGND 12 MC2 13 Data R-ch 14 BCK 15 SYSCLK 16 WDCK 17 Data L-ch 18 MC3 19 MC1 20 +VDD FIGURE 8. Using Sony CXD2551. 16-Bit L/R Serial — 2 FIGURE 10. Using NPC SM5840. 20-Bit L/R Parallel SM5807 PCM67U/69AU 11 DGND 12 MC2 13 Data R-ch DF1700 PCM67U/69AU 11 DGND 12 MC2 DOR BCK0 XTi WDCK0 DOL 13 Data R-ch 14 BCK 15 SYSCLK 16 WDCK 17 Data L-ch 18 MC3 19 MC1 20 +VDD BCK0 XTi LRC0 DOUT 14 BCK 15 SYSCLK 16 WDCK 17 Data L-ch 18 MC3 19 MC1 20 +VDD SOMD = H +VDD 20-Bit Mode +VDD FIGURE 9. Using NPC SM5807. FIGURE 11. Using Burr-Brown DF1700. ® 9 PCM67/69A THEORY OF OPERATION Digital converters in audio systems have traditionally utilized a laser-trimmed, current-source DAC architecture. Unfortunately, this type of technology suffers from the problems inherent in switching widely varying current levels. Design improvements have helped, but DACs of this type still exhibit low-level nonlinearity due to errors at the major carry. Recently, DACs employing a different architecture have been introduced. Most of these DACs utilize a one-bit DAC with “noise shaping” techniques and very high oversampling rate to achieve the digital-to-analog conversion. Basically, the trade-off is from very accurate but slow current sources to one rapidly sampled current source whose average output in the audio frequency range is equal to the current desired. Noise shaping insures that the “undesirable” frequencies associated with one-bit DAC output lie outside the audio range. These “Bitstream”, “MASH”, or one-bit DACs overcome the low level linearity problems of conventional DACs, since there can be no major carry error. However, this architecture exhibits problems of its own: signal-to-noise performance is usually worse than a similar conventional DAC, “dither noise” may be needed in order to get rid of unwanted tones, a separate high-speed clock may be required, the part may show sensitivity to clock jitter, and a high-order low-pass filter is necessary to filter the DAC output. The PCM67/69A is a cross between these two architectures. It includes both a conventional laser-trimmed, current-source DAC and an advanced one-bit DAC. The conventional DAC is a 10-bit DAC where each bit weight has been trimmed to 18bit linearity. The one-bit DAC has a weight equal to bit 10 and employs a first-order noise shaper to generate the “bitstream.” This approach does not eliminate all the problems associated with the two architectures but rather minimizes them as much as possible. The conventional DAC still exhibits some major carry error which would normally reduce low-level linearity. However, to reduce this error even further, the PCM67/69A utilizes an offset technique whereby bit n is subtracted from the digital input code whenever it is positive (see Figure 1 and Table I). When this is done, an offset current equal to the weight of bit n is switched in to compensate. This offset comes from a one-bit DAC which has also been trimmed to 18-bit linearity. While this technique doesn’t remove the major carry error completely, the “glitch” is only present in higher amplitude signals where it is much less audible. As for the one-bit DAC, a number of problems with this architecture are also reduced: the DAC is designed to operate from the system clock, thus eliminating the need for a separate clock; the lower quantizing level of the DAC make it less sensitive to clock jitter; and output filtering requirements are reduced because “out-of-band noise” has smaller amplitude, is “farther-out,” and increases much more slowly due to the first-order noise shaper. Still, it is important to keep in mind that the one-bit DAC imposes some design considerations. Figure 2 shows the THD + N of the converter versus “System Clock” frequency. This is the clock used to operate the one-bit DAC and noise shaper. Generally, the higher the oversampling the better. However, near full-scale, the converter is limited by other constraints and higher clock frequencies (past 96fs) tend to slightly worsen its performance. At low levels, performance improves almost linearly with increasing clock frequency. The one-bit DAC was designed to operate between 96fs (4X oversampling) and 384fs (16X oversampling). But, it can be operated at 48fs (2X oversampling) with slightly reduced performance. TOTAL HARMONIC DISTORTION + NOISE A key specification for audio DACs is usually total harmonic distortion plus noise (THD + N). For the PCM67/69A, THD + N is tested in production as shown in Figure 12. Digital data words are read into the PCM67/69A at eight times the standard compact disk audio sampling frequency of 44.1kHz (352.8kHz) so that a sine wave output of 991Hz is realized. The output of the DAC goes to an I-to-V converter, then to a programmable gain amplifier to provide gain at lower signal output test levels, and then through a 40kHz low pass filter before being fed into an analog type distortion analyzer. ® PCM67/69A 10 Use 400Hz High-Pass Filter and 30kHz Low-Pass Filter Meter Settings Distortion Analyzer (Shiba Soku Model 725 or Equivalent) Programmable Gain Amp 0dB to 60dB Low-Pass Filter 40kHz 3rd-Order GIC Type Binary Counter Digital Code (EPROM) Parallel-to-Serial Conversion DUT (PCM67/69A) I-to-V Converter OPA627 System Clock Bit Clock Word Clock Sampling Rate = 44.1kHz x 8 (352.8kHz) Output Frequency = 991Hz Timing Logic FIGURE 12. PCM67/69A THD+N Production Test. C10 1000pF R5 2kΩ +5V 11 12 13 14 Digital In 15 16 17 18 19 20 PCM67 or PCM69A 10 9 8 7 6 5 4 3 A1 2 + 1 + C3 100µF R2 680Ω R1 680Ω VCC (+5V) +C 2 100µF C7 10µF + C11 2200pF C5 +C 6 R4 680Ω R3 680Ω + 100µF C8 10µF C9 1000pF R6 2kΩ + C12 2200pF R7 200Ω A2 OUT R-ch 2.5V ± 1.2V + 10µF + C4 10µF R8 200Ω OUT L-ch 2.5V ± 1.2V + C1 0.1µF A1, A2; NJM2100 or LM833 FIGURE 13. Single +5V Power Supply, with LPF, I/V Amp Application Circuit for Portable Digital Audio. ® 11 PCM67/69A +5V 4.7µF +5V +5V 10µF 4.7µF 4.7µF 3 1 16 18-Bit D/A Converter 10 RDATA 11 BTCK 12 SYSCK WCK 25 LIOUT 3 DOL 24 3.3µF 4 5 3 150Ω 4700pF 100pF 14 4 8 10 16 21 3.3µF 8 4 14 9 Burr-Brown PCM67P/69AP (Note: 16-Pin DIP) 14 LDATA 220pF Burr-Brown DF1700P 10µF 5kΩ 13 WDCK LVCOM 2 6 5 A1 2.7kΩ 15 8X Interpolation Digital Filter DOR 23 17 22 NOTE: Only left channel shown. 7 0.1µF + 1µF 4.7µF + + 1 Digital Interface Format Receiver 28 17.1kΩ ® + 1.5kΩ 6 7 A4 5 1.5kΩ –15V 1.5kΩ 3 2 8 A3 4 1 –15V 4.7µF + 2200pF A1 to A4 = Burr-Brown OPA2604AP or NE5532 equivalent. + FIGURE 14. HiFi D/A Converter Unit Application with Digital Audio Interface Format. PCM67/69A φA 8 6 5 L/R 15 28 1 DA 17 Yamaha YM3623 BCO 12 2 6 BCO 26 +15V 4.7µF + 510Ω 2200pF DGND AGND 2200pF +15V 4.7µF 3.3µF 3 100kΩ 2 8 A2 4 1 4.7µF +5V Interleaved Digital Input 16.9344MHz (192F ) S 1MΩ 10pF 10pF 12 VOUT Left IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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