PGA103U

® PGA103 Programmable Gain AMPLIFIER FEATURES DESCRIPTION ● DIGITALLY PROGRAMABLE GAINS: G=1, 10, 100V/V The PGA103 is a programmable-gain amplifier for general purpose applications. Gains of 1, 10, or 100 are digitally selected by two CMOS/TTL-compatible inputs. The PGA103 is ideal for systems that must handle wide dynamic range signals. ● CMOS/TTL-COMPATIBLE INPUTS ● LOW GAIN ERROR: ±0.05% max, G=10 ● LOW OFFSET VOLTAGE DRIFT: 2µV/°C The PGA103’s high speed circuitry provides fast settling time, even at G=100 (8µs to 0.01%). Bandwidth is 250kHz at G=100, yet quiescent current is only 2.6mA. It operates from ±4.5V to ±18V power supplies. ● LOW QUIESCENT CURRENT: 2.6mA ● LOW COST ● 8-PIN PLASTIC DIP, SO-8 PACKAGES The PGA103 is available in 8-pin plastic DIP and SO-8 surface-mount packages, specified for the –40°C to +85°C temperature range. APPLICATIONS ● DATA ACQUISITION SYSTEMS ● GENERAL PURPOSE ANALOG BOARDS ● MEDICAL INSTRUMENTATION V+ V– 8 6 4 7 PGA103 VIN VO 3 1 VO = G • VIN 2 GAIN A1 A0 1 10 100 0 0 1 0 1 0 International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © SBOS031 1993 Burr-Brown Corporation PDS-1208B 1 PGA103 Printed in U.S.A. November, 1993 SPECIFICATIONS ELECTRICAL TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise specified. PGA103P, U PARAMETER CONDITIONS INPUT Offset Voltage, RTI G=1 G = 10 G = 100 vs Temperature G=1 G = 10 G = 100 vs Power Supply G=1 G = 10 G = 100 Impedance MIN TA = +25°C TA = TMIN to TMAX VS = ±4.5V to ±18V GAIN Gain Error G=1 G = 10 G = 100 Gain vs Temperature G=1 G = 10 G = 100 Nonlinearity G=1 G = 10 G = 100 ±200 ±100 ±100 ±1500 ±500 ±500 µV µV µV µV/°C µV/°C µV/°C 30 10 10 108 || 2 70 35 35 µV/V µV/V µV/V Ω || pF ±50 ±100 ±150 nA pA/°C 16 11 11 0.6 nV/√Hz nV/√Hz nV/√Hz µVp-p 2.8 0.3 76 pA/√Hz pA/√Hz pAp-p ±0.005 ±0.02 ±0.04 ±0.02 ±0.05 ±0.2 ±2 ±10 ±30 ±0.001 ±0.002 ±0.004 OUTPUT Voltage, Positive Negative Load Capacitance, max Short-Circuit Current (V+) –3.5 (V–) +3.5 VO = ±10V 50% Overdrive DIGITAL LOGIC INPUTS Digital Low Voltage Digital Low or High Current Digital High Voltage ppm/°C ppm/°C ppm/°C ±0.003 ±0.005 ±0.01 2 % of FSR % of FSR % of FSR V V pF mA 1.5 750 250 9 MHz kHz kHz V/µs 2 2.2 6.5 µs µs µs 2.5 2.5 8 2.5 µs µs µs µs 0.8 1 2 % % % (V+) –2.5 (V–) +2.5 1000 ±25 –5.6 ® PGA103 UNITS G = 100, RS = 0Ω NOISE CURRENT f = 10Hz f = 1kHz fB = 0.1Hz to 10Hz FREQUENCY RESPONSE Bandwidth, –3dB G=1 G = 10 G = 100 Slew Rate Settling Time, 0.1% G=1 G = 10 G = 100 Settling Time, 0.01% G=1 G = 10 G = 100 Overload Recovery MAX ±5 ±2 ±2 INPUT BIAS CURRENT Initial Bias Current vs Temperature NOISE VOLTAGE, RTI f = 10Hz f = 100Hz f = 1kHz fB = 0.1Hz to 10Hz TYP V+ V µA V SPECIFICATIONS (CONT) ELECTRICAL TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise specified. PGA103P, U PARAMETER CONDITIONS POWER SUPPLY Voltage Range Current MIN TYP MAX UNITS ±4.5 ±15 ±2.6 ±18 ±3.5 V mA +85 +125 °C °C °C/W VIN = 0V TEMPERATURE RANGE Specification Operating θJA: P or U Package –40 –40 100 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View Supply Voltage ................................................................................. ±18V Analog Input Voltage Range ..................................................... V– to V+ Logic Input Voltage Range ........................................................ V– to V+ Output Short Circuit (to ground) ............................................ Continuous Operating Temperature ................................................ –40°C to +125°C Storage Temperature .................................................... –40°C to +125°C Junction Temperature ................................................................... +150°C Lead Temperature (soldering,10s) .............................................. +300°C DIP/SO-8 A0 1 8 V+ A1 2 7 VO Ground 3 6 V– VIN 4 5 NC PACKAGE INFORMATION MODEL ORDERING INFORMATION MODEL PGA103P PGA103U PACKAGE TEMPERATURE RANGE 8-Pin Plastic DIP SO-8 Surface-Mount –40°C to +85°C –40°C to +85°C PGA103P PGA103U PACKAGE PACKAGE DRAWING NUMBER(1) 8-Pin Plastic DIP SO-8 Surface-Mount 006 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PGA103 DICE INFORMATION NC 6 NC NC NC NC 7 4C FUNCTION 1 2 3A, 3B, 3C(1) 4A, 4B, 4C(2) 6 7 8 A0 A1 Ground VIN V– VO V+ NC: No Connection NOTES: (1) Connect all three indicated pads. (2) Connect all three indicated pads. Substrate Bias: Internally connected to V– power supply. 8 1 2 PAD MECHANICAL INFORMATION 3A 3B 3C 4A 4B MILS (0.001") MILLIMETERS 69 x 105 ±5 20 ±3 4x4 1.75 x 2.67 ±0.13 0.51 ±0.08 0.1 x 0.1 Die Size Die Thickness Min. Pad Size PGA103 DIE TOPOGRAPHY Backing Gold TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±15V unless otherwise noted. VOLTAGE GAIN vs FREQUENCY POWER SUPPLY REJECTION vs FREQUENCY 120 50 Voltage Gain (dB) Power Supply Rejection (dB) G=100 40 30 G=10 20 10 G=1 0 –10 100 80 G=100 60 G=10 40 G=1 20 0 10k 100k 1M 10 10M ® PGA103 100 1k 10k Frequency (Hz) Frequency (Hz) 4 100k 1M TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±15V unless otherwise noted. 100 100 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) INPUT CURRENT NOISE vs FREQUENCY INPUT VOLTAGE NOISE vs FREQUENCY 1000 G=1 G=10 G=100 10 Bandwidth Limited 10 1 All Gains 0.1 1 1 10 100 1k 10k 100k 1 1M 10 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) SMALL SIGNAL RESPONSE QUIESCENT CURRENT vs TEMPERATURE 4 G=100 50mV/div G=10 2 1 0 –50 –25 0 25 50 75 100 2µs/div 125 Temperature (°C) LARGE SIGNAL RESPONSE G=10 G=1 G=100 5V/div Quiescent Current (mA) G=1 3 2µs/div ® 5 PGA103 APPLICATION INFORMATION Some applications select gain of the PGA103 with switches or jumpers. Figure 2 shows pull-up resistors connected to assure a noise-free logic “1” when the switch or jumper is off or open. Fixed-gain applications can connect the logic inputs directly to V+ or ground (or other valid logic level) without a series resistor. Figure 1 shows the basic connections required for operation of the PGA103. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. V+ +15V V– –15V 0.1µF V+ V– 8 0.1µF 4 VIN 8 A1 100kΩ 6 6 7 PGA103 2 A0 VO 3 1 V+ 4 7 PGA103 VIN A0 A1 100kΩ VO = G • VIN 3 GAIN 1 S1 2 GAIN A1 A0 1 10 100 Not Valid 0 0 1 1 0 1 0 1 S0 1 10 100 Not Valid S1 S0 Closed Closed Open Open Closed Open Closed Open FIGURE 2. Switch or Jumper-Selected Gains. OFFSET TRIMMING Offset voltage is laser-trimmed to typically less than 200µV (referred to input) in all three gains. The input-referred offset voltage can be different for each gain. Logic 0: (–5.6) ≤ V ≤ 0.8V Logic 1: 2V ≤ V ≤ (V+) Logic voltages referred to pin 3. NOTE: (1) Low impedance ground connection required for good gain accuracy—see text. FIGURE 1. Basic Connections. +15V –15V The input and output are referred to the ground terminal, pin 3. This must be a low-impedance connection to assure good gain accuracy. A resistance of 0.1Ω in series with the ground pin will cause the gain in G=100 to decrease by approximately 0.2%. VIN PGA103 A0 3 A1 1 VTRIM 2 VO = G (VIN – VTRIM) (1) DIGITAL INPUTS The digital inputs, A0 and A1, select the gain according to the logic table in Figure 1. The digital inputs interface directly to common CMOS and TTL logic components. The logic inputs are referenced to the ground terminal, pin 3. OPA602 100kΩ 50kΩ ±5mV Trim Range 33Ω Logic threshold voltage is altered by VTRIM. OK for VTRIM ≤ 100mV. The logic table in Figure 1 shows that logic “1” on both A0 and A1 is invalid. This logic code will not cause damage, but the amplifier output will not be predictable while this code is selected. The output will recover when a valid code is selected. –15V NOTE: (1) Op amp buffer is required to preserve good gain accuracy—see text. The digital inputs are not latched, so a change in logic inputs immediately selects a new gain. Switching time of the logic is approximately 0.5µs. The time to respond to gain change is equal to the switching time plus the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). FIGURE 3. Offset Voltage Trim Circuit. Figure 3 shows a circuit used to trim the offset voltage of the PGA103. An op amp buffers the trim voltage to provide a low impedance at the ground terminal. This is required to maintain accurate gain. Remember that the logic inputs, A0 and A1, are referenced to this ground connection, so the logic threshold voltage will be affected by the trim voltage. This is insignificant if the offset adjustment is used only to trim offset voltage. If a large offset is used (greater than 0.1V), be sure that the logic input signals provide valid logic levels when referred to the voltage at the ground terminal, pin 3. Many applications use an external logic latch to access gain control signals from a high speed data bus. Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the latch circuitry as far as practical from analog circuitry to avoid coupling digital noise into the analog circuitry. ® PGA103 +15V 6 +15V –15V V+ V– V+ V – G1 = 1, 2, 4, 8 VIN– 8 4 PGA205 VIN+ G2 = 1, 10, 100 6 PGA103 A0 3 A1 1 7 102kΩ VO G = 0.1, 1, 10 D2 D1 PGA103 A0 VIN G = G 1 • G2 VO A1 Accepts inputs to ±120V. 2 True instrumentation amplifier input. 11.3kΩ D1, D2; IN4148 A1 GAIN 1 2 4 8 10 20 40 80 100 200 400 800 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 A0 FIGURE 5. Wide Input Voltage Range Amplifer. FIGURE 4. Programmable Gain Instrumentation Amplifier. MODEL INA103 INA105 INA106 INA114 INA117 INA111 INA131 G1 CHARACTERISTICS G2 = 1, 10, 100 VIN+ Low Noise, 1nV/√Hz IA G = 1 Difference Amp G = 10 Difference Amp Resistor-Programmed Gain, Precision ±200V C-M Input Range Difference Amp FET Input, High Speed IA Precision, G = 100 IA INA PGA103 VIN– VO G = G 1 • G2 A 1 A0 FIGURE 6. Instrumentation Amplifier with Programmable Gain Output Amp. ® 7 PGA103 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) PGA103U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA 103U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of