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PGA112, PGA113, PGA116, PGA117
SBOS424C – MARCH 2008 – REVISED NOVEMBER 2015
PGA11x Zerø-Drift Programmable Gain Amplifier With Mux
1 Features
2 Applications
•
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1
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Rail-to-Rail Input and Output
Offset: 25 μV (Typical), 100 μV (Maximum)
Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C
(Maximum)
Low Noise: 12 nV/√Hz
Input Offset Current: ±5 nA Maximum (25°C)
Gain Error: 0.1% Maximum (G ≤ 32),
0.3% Maximum (G > 32)
Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
PGA116)
Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
(PGA113, PGA117)
Gain Switching Time: 200 ns
2 Channel MUX: PGA112, PGA113
10 Channel MUX: PGA116, PGA117
Four Internal Calibration Channels
Amplifier Optimized for Driving CDAC ADCs
Output Swing: 50 mV to Supply Rails
AVDD and DVDD for Mixed Voltage Systems
IQ = 1.1 mA (Typical)
Software and Hardware Shutdown: IQ ≤ 4 μA
(Typical)
Temperature Range: –40°C to 125°C
SPI™ Interface (10 MHz) With Daisy-Chain
Capability
Remote e-Meter Reading
Automatic Gain Control
Portable Data Acquisition
PC-Based Signal Acquisition Systems
Test and Measurement
Programmable Logic Controllers
Battery-Powered Instruments
Handheld Test Equipment
3 Description
The PGA112 and PGA113 devices (binary and scope
gains) offer two analog inputs, a three-pin SPI
interface, and software shutdown in a 10-pin, VSSOP
package. The PGA116 and PGA117 (binary and
scope gains) offer 10 analog inputs, a SPI interface
with daisy-chain capability, and hardware and
software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for
system-level calibration. The channels are tied to
GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively.
VCAL, an external voltage connected to Channel 0, is
used as the system calibration reference. Binary
gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains
are: 1, 2, 5, 10, 20, 50, 100, and 200.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
PGA112, PGA113
VSSOP (10)
3.00 mm × 3.00 mm
PGA116, PGA117
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
+3V
+5V
CBYPASS
0.1mF
CBYPASS
0.1mF
AVDD
CBYPASS
0.1mF
DVDD
1
10
MSP430
Microcontroller
PGA112
PGA113
VCAL/CH0
CH1
3
MUX
2
Output
Stage
5
VOUT
7
SCLK
8
DIO
9
CS
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
G=1
CAL2
CAL3
CAL4
10kW
RF
VREF
RI
SPI
Interface
CAL2/3
6
4
GND
VREF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PGA112, PGA113, PGA116, PGA117
SBOS424C – MARCH 2008 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: VS = AVDD = DVDD = 5 V. 6
SPI Timing: VS = AVDD = DVDD = 2.2 V to 5 V......... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 20
8.5 Programming........................................................... 21
8.6 Serial Interface Information..................................... 21
9
Applications and Implementation ...................... 31
9.1 Application Information............................................ 31
9.2 Typical Applications ................................................ 43
10 Power Supply Recommendations ..................... 46
11 Layout................................................................... 47
11.1 Layout Guidelines ................................................. 47
11.2 Layout Example .................................................... 48
12 Device and Documentation Support ................. 49
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
49
49
49
49
49
49
13 Mechanical, Packaging, and Orderable
Information ........................................................... 49
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2008) to Revision C
•
2
Page
Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
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Copyright © 2008–2015, Texas Instruments Incorporated
Product Folder Links: PGA112 PGA113 PGA116 PGA117
PGA112, PGA113, PGA116, PGA117
www.ti.com
SBOS424C – MARCH 2008 – REVISED NOVEMBER 2015
5 Device Comparison
SHUTDOWN
DEVICE
NO. OF MUX
INPUTS
GAINS
(EIGHT EACH)
SPI DAISYCHAIN
HARDWARE
SOFTWARE
PGA112
2
Binary
No
No
✓
VSSOP-10
PGA113
2
Scope
No
No
✓
VSSOP-10
PGA116
10
Binary
✓
✓
✓
TSSOP-20
PGA117
10
Scope
✓
✓
✓
TSSOP-20
PACKAGE
6 Pin Configuration and Functions
DGS Package
10-Pin VSSOP
Top View
AVDD
1
CH1
2
PGA112
PGA113
10
DVDD
9
CS
8
DIO
VCAL/CH0
3
VREF
4
7
SCLK
VOUT
5
6
GND
Pin Functions: PGA112, PGA113
PIN
I/O
DESCRIPTION
NO.
NAME
1
AVDD
I
Analog supply voltage (2.2 V to 5.5 V)
2
CH1
I
Input MUX channel 1
3
VCAL/CH0
I
Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a lowimpedance external reference voltage to use internal calibration channels. The four internal
calibration channels are connected to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL is
loaded with 100 kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected.
Otherwise, VCAL/CH0 appears as high impedance.
4
VREF
I
Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply
referenced systems. VREF must be connected to a low-impedance reference capable of sourcing and
sinking at least 2 mA or VREF must be connected to GND.
5
VOUT
O
Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300 mV.
6
GND
—
Ground pin
7
SCLK
I
Clock input for SPI serial interface
8
DIO
I
Data input/output for SPI serial interface. DIO contains a weak, 10-μA internal pulldown current
source.
9
CS
I
Chip select line for SPI serial interface
I
Digital and op amp output stage supply voltage (2.2 V to 5.5 V). Useful in multi-supply systems to
prevent overvoltage and lockup condition on an analog-to-digital (ADC) input (for example, a
microcontroller with an ADC running on 3 V and the PGA powered from 5 V). Digital I/O levels to be
relative to DVDD. DVDD should be bypassed with a 0.1-μF ceramic capacitor, and DVDD must supply
the current for the digital portion of the PGA as well as the load current for the op amp output stage.
10
DVDD
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PW Package
20-Pin TSSOP
Top View
AVDD
1
20
CH6
CH5
2
19
DVDD
CH4
3
18
CS
CH3
4
17
DOUT
16
DIN
PGA116
PGA117
CH2
5
CH1
6
15
SCLK
VCAL/CH0
7
14
GND
VREF
8
13
ENABLE
VOUT
9
12
CH9
CH7
10
11
CH8
Pin Functions: PGA116, PGA117
PIN
I/O
DESCRIPTION
NO.
NAME
1
AVDD
I
Analog supply voltage (2.2 V to 5.5 V)
2
CH5
I
Input MUX channel 5
3
CH4
I
Input MUX channel 4
4
CH3
I
Input MUX channel 3
5
CH2
I
Input MUX channel 2
6
CH1
I
Input MUX channel 1
7
VCAL/CH0
I
Input MUX channel 0 and VCAL input. For system calibration purposes, connect this pin to a lowimpedance external reference voltage to use internal calibration channels. The four internal
calibration channels are connected to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL is
loaded with 100 kΩ (typical) when internal calibration channels CAL2 or CAL3 are selected.
Otherwise, VCAL/CH0 appears as high impedance.
8
VREF
I
Reference input pin. Connect external reference for VOUT offset shift or to midsupply for midsupply
referenced systems. VREF must be connected to a low-impedance reference capable of sourcing
and sinking at least 2 mA or to GND.
9
VOUT
O
Analog voltage output. When AVDD < DVDD, VOUT is clamped to AVDD + 300 mV.
10
CH7
I
Input MUX channel 7
11
CH8
I
Input MUX channel 8
12
CH9
I
Input MUX channel 9
13
ENABLE
I
Hardware enable pin. Logic low puts the part into Shutdown mode (IQ < 1 μA).
14
GND
—
15
SCLK
I
Clock input for SPI serial interface
16
DIN
I
Data input for SPI serial interface. DIN contains a weak, 10-μA internal pulldown current source to
allow for ease of daisy-chain configurations.
17
DOUT
O
Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard
SPI interface.
18
CS
I
Chip select line for SPI serial interface
Ground pin
19
DVDD
I
Digital and op amp output stage supply voltage (2.2 V to 5.5 V). Useful in multi-supply systems to
prevent overvoltage and lockup condition on an ADC input (for example, a microcontroller with an
ADC running on 3 V and the PGA powered from 5 V). Digital I/O levels to be relative to DVDD. DVDD
should be bypassed with a 0.1-μF ceramic capacitor, and DVDD must supply the current for the
digital portion of the PGA as well as the load current for the op amp output stage.
20
CH6
I
Input MUX channel 6
4
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Product Folder Links: PGA112 PGA113 PGA116 PGA117
PGA112, PGA113, PGA116, PGA117
www.ti.com
SBOS424C – MARCH 2008 – REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
Supply voltage
Signal input terminals, voltage
(2)
GND – 0.5
V
±10
mA
125
°C
150
°C
150
°C
–40
Junction temperature
Storage temperature
(2)
V
Continuous
Operating temperature
(1)
UNIT
7
AVDD + 0.5
Signal input terminals, current (2)
Output short circuit
MAX
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current-limited to 10 mA or less.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine Model (MM)
±300
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD
2.2
5
5.5
DVDD
2.2
5
5.5
V
Operating temperature
–40
25
125
°C
V
7.4 Thermal Information
THERMAL METRIC (1)
PGA112,
PGA113
PGA116,
PGA117
DGS (VSSOP)
PW (TSSOP)
10 PINS
20 PINS
98.3
100.3
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
57
36.9
°C/W
RθJB
Junction-to-board thermal resistance
51.2
50.6
°C/W
ψJT
Junction-to-top characterization parameter
1.3
2.6
°C/W
ψJB
Junction-to-board characterization parameter
36.9
50.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.8
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2008–2015, Texas Instruments Incorporated
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7.5 Electrical Characteristics: VS = AVDD = DVDD = 5 V
at TA = 25°C, RL = 10kΩ//CL = 100 pF connected to DVDD/2, and VREF = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 2.5 V
±25
±100
μV
AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 4.5 V
±75
±325
μV
0.35
1.2
μV/°C
0.15
0.9
μV/°C
0.6
1.8
μV/°C
0.3
1.3
μV/°C
5
20
μV/V
5
40
μV/V
±1.5
±5
nA
OFFSET VOLTAGE
Input offset voltage
vs temperature, –40°C to
125°C
VOS
dVOS/dT
AVDD = DVDD = 5 V, VCM = 2.5 V
vs temperature, –40°C to 85°C
AVDD = DVDD = 5 V, VCM = 2.5 V
vs temperature, –40°C to 125°C
AVDD = DVDD = 5 V, VCM = 4.5 V
vs temperature, –40°C to 85°C
AVDD = DVDD = 5 V, VCM = 4.5 V
vs power supply
AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V,
VREF = VIN = AVDD/2
PSRR
AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V,
VREF = VIN = AVDD/2
Over temperature, –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = –40°C to 125°C
INPUT ON-CHANNEL CURRENT
Input on-channel current (Ch0,
Ch1)
IIN
Over temperature, –40°C to 125°C
VREF = VIN = AVDD/2
VREF = VIN = AVDD/2
See Typical Characteristics
nA
INPUT VOLTAGE RANGE
Input voltage range (1)
IVR
No output phase reversal (2)
Overvoltage input range
GND – 0.1
AVDD + 0.1
V
GND – 0.3
AVDD + 0.3
V
INPUT IMPEDANCE (Channel On) (3)
Channel input capacitance
CCH
2
Channel switch resistance
RSW
150
pF
Ω
Amplifier input capacitance
CAMP
3
pF
Amplifier input resistance
RAMP
Input resistance to GND
10
GΩ
VCAL/CH0
RIN
CAL1 or CAL2 selected
100
kΩ
GAIN SELECTIONS
Nominal gains
DC gain error
DC gain drift
Binary gains: 1, 2, 4, 8, 16, 32, 64, 128
1
Scope gains: 1, 2, 5, 10, 20, 50, 100, 200
1
VOUT = GND + 85 mV to DVDD – 85 mV
1 < G ≤ 32
VOUT = GND + 85 mV to DVDD – 85 mV
G ≥ 50
VOUT = GND + 85 mV to DVDD – 85 mV
G=1
VOUT = GND + 85 mV to DVDD – 85 mV
TA = –40°C to 125°C
0.5
ppm/°C
1 < G ≤ 32
VOUT = GND + 85 mV to DVDD – 85 mV
TA = –40°C to 125°C
2
ppm/°C
G ≥ 50
VOUT = GND + 85 mV to DVDD – 85 mV
TA = –40°C to 125°C
6
ppm/°C
Op Amp + Input = 0.9 VCAL,
VREF = VCAL = AVDD/2, G = 1
CAL2 DC gain drift (4)
Op Amp + Input = 0.9 VCAL,
VREF = VCAL = AVDD/2, G = 1
CAL3 DC gain error (4)
Op Amp + Input = 0.1 VCAL,
VREF = VCAL = AVDD/2, G = 1
CAL3 DC gain drift (4)
Op Amp + Input = 0.1 VCAL,
VREF = VCAL = AVDD/2, G = 1
INPUT IMPEDANCE (CHANNEL OFF)
(1)
(2)
(3)
(4)
6
200
G=1
CAL2 DC gain error (4)
Input impedance
128
0.006%
0.1%
0.1%
0.3%
0.02%
TA = –40°C to 125°C
2
ppm/°C
0.02%
TA = –40°C to 125°C
2
ppm/°C
2
pF
(3)
CCH
See Figure 55
Gain error is a function of the input voltage. Gain error outside of the range (GND + 85 mV ≤ VOUT ≤ DVDD – 85 mV) increases to 0.5%
(typical).
Input voltages beyond this range must be current-limited to < |10 mA| through the input protection diodes on each channel to prevent
permanent destruction of the device.
See Figure 55.
Total VOUT error must be computed using input offset voltage error multiplied by gain. Includes op amp G = 1 error.
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Electrical Characteristics: VS = AVDD = DVDD = 5 V (continued)
at TA = 25°C, RL = 10kΩ//CL = 100 pF connected to DVDD/2, and VREF = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.05
±1
UNIT
INPUT OFF-CHANNEL CURRENT
Input Off-Channel Current (Ch0,
Ch1) (5)
ILKG
Over temperature, –40°C to 125°C
VREF = GND, VOFF-CHANNEL = AVDD/2,
VON-CHANNEL = AVDD/2 – 0.1 V
VREF = GND, VOFF-CHANNEL = AVDD/2,
VON-CHANNEL = AVDD/2 – 0.1 V
nA
See Typical Characteristics
Channel-to-Channel Crosstalk
130
dB
OUTPUT
Voltage output swing from rail
IOUT = ±0.25 mA, AVDD ≥ DVDD (6)
GND + 0.05
DVDD – 0.05
IOUT = ±5 mA, AVDD ≥ DVDD (6)
GND + 0.25
DVDD – 0.25
VOUT = GND + 85 mV to DVDD – 85 mV (7)
DC output nonlinearity
Short circuit current
ISC
Capacitive load drive
CLOAD
V
V
0.0015
%FSR
–30/+60
mA
See Typical Characteristics
NOISE
Input voltage noise density
Input voltage noise
Input current density
en
en
In
f > 10 kHz, CL = 100 pF, VS = 5 V
12
nV/√Hz
f > 10 kHz, CL = 100 pF, VS = 2.2 V
22
nV/√Hz
f = 0.1 Hz to 10 Hz, CL = 100 pF, VS = 5 V
0.362
f = 0.1 Hz to 10 Hz, CL = 100 pF, VS = 2.2 V
0.736
f = 10 kHz, CL = 100 pF
μVPP
μVPP
400
fA/√Hz
SLEW RATE
Slew rate
SR
See Table 1
V/μs
tS
See Table 1
μs
See Table 1
MHz
SETTLING TIME
Settling time
FREQUENCY RESPONSE
Frequency response
THD + NOISE
G = 1, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.003%
G = 10, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.005%
G = 50, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.03%
G = 128, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.08%
G = 200, f = 1 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.1%
G = 1, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.02%
G = 10, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.01%
G = 50, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.03%
G = 128, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.08%
G = 200, f = 20 kHz, VOUT = 4 VPP at 2.5VDC, CL = 100 pF
0.11%
POWER SUPPLY
Operating voltage range (6)
Quiescent current analog
AVDD
2.2
5.5
DVDD
2.2
5.5
V
0.45
mA
0.45
mA
1.2
mA
1.2
mA
IQA
IO = 0, G = 1, VOUT = VREF
Over temperature, –40°C to 125°C
Quiescent current digital (8) (9) (10)
IQD
Over temperature, –40°C to 125°C (8) (9) (10)
Shutdown current analog +
digital (8) (9)
ISDA + ISDD
0.33
TA = –40°C to 125°C
IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz,
CS = Logic 0, DIO or DIN = Logic 0
IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz,
CS = Logic 0, DIO or DIN = Logic 0
0.75
TA = –40°C to 125°C
V
4
μA
IO = 0, VOUT = 0, G = 1, SCLK at 10MHz,
CS = Logic 0, DIO or DIN = Logic 0
245
μA
Digital interface disabled and Command Register set to POR values for
DVDD < POR Trip Voltage
1.6
V
IO = 0, VOUT = VREF, G = 1, SCLK Idle
POWER-ON RESET (POR)
POR trip voltage
(5)
(6)
(7)
(8)
(9)
(10)
Maximum specification limitation limited by final test time and capability.
When AVDD is less than DVDD, the output is clamped to AVDD + 300 mV.
Measurement limited by noise in test equipment and test time.
Does not include current into or out of the VREF pin. Internal RF and RI are always connected between VOUT and VREF.
Digital logic levels: DIO or DIN = logic 0. 10-μA internal pulldown current source.
Includes current from op amp output structure.
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Electrical Characteristics: VS = AVDD = DVDD = 5 V (continued)
at TA = 25°C, RL = 10kΩ//CL = 100 pF connected to DVDD/2, and VREF = GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE RANGE
Specified range
–40
125
°C
Operating range
–40
125
°C
Thermal resistance
θJA
VSSOP-10
164
°C/W
DIGITAL INPUTS (SCLK, CS, DIO, DIN)
Logic low
Input leakage current (SCLK and CS only)
0
0.3DVDD
V
–1
1
μA
Weak pulldown current (DIO, DIN only)
μA
10
Logic high
0.7DVDD
Hysteresis
DVDD
700
V
mV
DIGITAL OUTPUT (DIO, DOUT)
Logic high
IOH = –3 mA (sourcing)
Logic low
IOL = 3 mA (sinking)
DVDD – 0.4
DVDD
V
GND
GND + 0.4
V
CHANNEL AND GAIN TIMING
Channel select time
0.2
μs
Gain select time
0.2
μs
4
μs
2
μs
40
μs
5
μs
SHUTDOWN MODE TIMING
Enable time
Disable time
VOUT goes high-impedance, RF and RI remain connected between VOUT and
VREF
POWER-ON-RESET (POR) TIMING
POR power-up time
DVDD ≥ 2 V
POR power-down time
DVDD ≤ 1.5 V
8
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SBOS424C – MARCH 2008 – REVISED NOVEMBER 2015
7.6 SPI Timing: VS = AVDD = DVDD = 2.2 V to 5 V
At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
MIN
NOM
Input capacitance (SCLK, CS, and DIO pins)
tRFI
Input rise and fall time (1)
(CS, SCLK, and DIO pins)
tRFO
Output rise and fall time (DIO pin) (1)
MAX
UNIT
1
pF
CLOAD = 60 pF
(1)
2
μs
10
ns
tCSH
CS high time (CS pin)
40
ns
tCSO
SCLK edge to CS fall setup time (1)
10
ns
tCSSC
CS fall to first SCLK edge setup time
10
ns
fSCLK
SCLK Frequency
(2)
tHI
SCLK high time (3)
40
ns
tLO
SCLK low time (3)
40
ns
tSCCS
SCLK last edge to CS rise setup time (1)
10
ns
10
(1)
MHz
tCS1
CS rise to SCLK edge setup time
10
ns
tSU
DIN setup time
10
ns
tHD
DIN hold time
10
ns
tDO
SCLK to DOUT valid propagation delay
tSOZ
CS rise to DOUT forced to Hi-Z (1)
(1)
(2)
(3)
(1)
25
ns
20
ns
Ensured by design; not production tested.
When using devices in daisy-chain mode, the maximum clock frequency for SCLK is limited by SCLK rise and fall time, DIN setup time,
and DOUT propagation delay. See Figure 61. Based on this limitation, the maximum SCLK frequency for daisy-chain mode is 9.09 MHz.
tHI and tLO must not be less than 1/SCLK (maximum).
tCSH
CS
tCSSC
tSCCS
tLO
tCS1
tCS0
tHI
SCLK
1/fSCLK
tSU
tHD
DIN
tDO
tSOZ
Hi-Z
Hi-Z
DOUT
Figure 1. SPI Mode 0, 0
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tCSH
CS
tCSSC
tSCCS
tHI
tCS1
tCS0
tLO
SCLK
1/fSCLK
tSU
tHD
DIN
tDO
tSOZ
Hi-Z
Hi-Z
DOUT
Figure 2. SPI Mode 1, 1
10
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7.7 Typical Characteristics
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
VCM = 4.5V
-325.0
-292.5
-260.0
-227.5
-195.0
-162.5
-130.0
-97.5
-65.0
-32.5
0
32.5
65.0
97.5
130.0
162.5
195.0
227.5
260.0
292.5
325.0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Population
Population
VCM = 2.5V
Offset Voltage (mV)
Offset Voltage (mV)
Figure 4. Offset Voltage
Figure 3. Offset Voltage
VCM = 4.5V
-0.90
-0.81
-0.72
-0.63
-0.54
-0.45
-0.36
-0.27
-0.18
-0.09
0
0.09
0.18
0.27
0.36
0.45
0.54
0.63
0.72
0.81
0.90
-1.30
-1.17
-1.04
-0.91
-0.78
-0.65
-0.52
-0.39
-0.26
-0.13
0
0.13
0.26
0.39
0.52
0.65
0.78
0.91
1.04
1.17
1.30
Population
Population
VCM = 2.5V
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 5. Offset Voltage Drift (–40°C to 85°C)
Figure 6. Offset Voltage Drift (–40°C to 85°C)
VCM = 4.5V
-1.20
-1.08
-0.96
-0.84
-0.72
-0.60
-0.48
-0.36
-0.24
-0.12
0
0.12
0.24
0.36
0.48
0.60
0.72
0.84
0.96
1.08
1.20
-1.80
-1.62
-1.44
-1.26
-1.08
-0.90
-0.72
-0.54
-0.36
-0.18
0
0.18
0.36
0.54
0.72
0.90
1.08
1.26
1.44
1.62
1.80
Population
Population
VCM = 2.5V
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 7. Offset Voltage Drift (–40°C to 125°C)
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Figure 8. Offset Voltage Drift (–40°C to 125°C)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
0.0010
DC Output Nonlinearity Error (%FSR)
100
80
Input Offset Voltage (mV)
60
40
20
0
-20
-40
-60
-80
AVDD = DVDD = +5V
0.0008
G=1
0.0006
G=2
0.0004
0.0002
0
-0.0002
G = 16
-0.0004
-0.0006
G = 128
-0.0008
-0.0010
-100
0
1
2
3
4
0
5
0.5
1.0
1.5
Input Voltage (V)
2.5
3.0
3.5
4.0
4.5
5.0
VOUT (V)
Figure 10. PGA112 and PGA116 Nonlinearity
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Population
Figure 9. Input Offset Voltage vs Input Voltage
Population
2.0
Gain Error (%)
Gain Error (%)
Figure 12. Gain Error (1 < G ≤ 32)
Figure 11. Gain Error (G = 1)
Gain Error (%)
Figure 13. Gain Error (G ≥ 50)
12
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0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
-0.300
-0.270
-0.240
-0.210
-0.180
-0.150
-0.120
-0.090
-0.060
-0.030
0
0.030
0.060
0.090
0.120
0.150
0.180
0.210
0.240
0.270
0.300
Population
Population
G=1
Gain Error Drift (ppm/°C)
Figure 14. Gain Error Drift (–40°C to 125°C)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
1 < G £ 32
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
Population
Population
G ³ 50
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Population
Figure 16. Gain Error Drift (–40°C to 125°C)
-0.10
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Population
Figure 15. Gain Error Drift (–40°C to 125°C)
Gain Error (%)
Gain Error (%)
Figure 18. CAL3 Gain Error
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
> 2.0
Population
Population
Figure 17. CAL2 Gain Error
Gain Error Drift (ppm/°C)
Gain Error Drift (ppm/°C)
Figure 19. CAL2 Gain Error Drift (–40°C to 125°C)
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Figure 20. CAL3 Gain Error Drift (–40°C to 125°C)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
100nV/div
VS = 5V
250nV/div
VS = 2.2V
2.5s/div
2.5s/div
Figure 21. 0.1 Hz To 10 Hz NOISE
Figure 22. 0.1 Hz to 10 Hz NOISE
100
1
1k
G = 128
G = 32
500
Current Noise, VS = 5V
Voltage Noise, VS = 2.2V
20
200
0.01
0.001
Voltage Noise, VS = 5V
G=1
10
1
10
100
1k
G=2
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 24. PGA112, PGA116 THD + Noise vs Frequency
(VOUT = 2 VPP)
Figure 23. Spectral NOISE Density
1
1
G = 200 G = 100
G = 128
G = 32
G = 64
G = 50
G = 20
G = 16
0.1
THD+N (%)
0.1
THD+N (%)
G=8
G=4
0.0001
100
100k
10k
G = 16
0.1
THD+N (%)
50
Current Noise (fA/ÖHz)
Voltage Noise (nV/ÖHz)
G = 64
0.01
0.01
G=8
0.001
0.001
G=2
G=4
G=1
G=1
0.0001
G=2
10
100
1k
10k
100k
10
100
Frequency (Hz)
Figure 25. PGA112, PGA116 THD + NOISE vs Frequency
(VOUT = 4 VPP)
14
G=5
G = 10
0.0001
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1k
10k
100k
Frequency (Hz)
Figure 26. PGA113, PGA117 THD + Noise vs Frequency
(VOUT = 2 VPP)
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
1
0.8
G = 100
G = 200
G = 50
0.7
G = 20
0.1
0.6
Digital
IQ (mA)
THD+N (%)
0.5
0.01
0.4
0.3
Analog
G=1
0.001
0.2
G=2
G=5
VS = 5.5V
0.1
G = 10
0.0001
VS = 2.2V
fSCLK = 10MHz
0
10
100
1k
10k
100k
-50
-25
0
25
Frequency (Hz)
50
75
100
125
Temperature (°C)
Figure 27. PGA113, PGA117 THD + Noise vs Frequency
(VOUT = 4 VPP)
Figure 28. Quiescent Current vs Temperature
4.0
1.2
SCLK = 5MHz
SCLK = 10MHz
3.5
1.0
Digital
Shutdown IQ (mA)
IQA + IQD (mA)
3.0
0.8
SCLK = 2MHz
SCLK = 500kHz
0.6
0.4
2.5
2.0
1.5
Analog
1.0
0.2
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-50
5.5
-25
0
25
Supply Voltage (V)
75
100
125
Figure 29. Total Quiescent Current vs Supply Voltage
Figure 30. Shutdown Quiescent Current vs Temperature
2.2
5.5
VS = 2.2V
G=1
2.0
1.8
4.5
1.6
4.0
1.4
1.2
+125°C
1.0
+25°C
-40°C
0.8
0.6
VS = 5.5V
G=1
5.0
Output Voltage (V)
Output Voltage (V)
50
Temperature (°C)
3.5
+125°C
3.0
+25°C
2.5
2.0
-40°C
1.5
0.4
1.0
0.2
0.5
0
0
0
2
4
6
8
10
12
14
16
18
20
22 24
Output Current (mA)
Figure 31. Output Voltage vs Output Current
Copyright © 2008–2015, Texas Instruments Incorporated
0
10
20
30
40
50
60
70
80
90
100
Output Current (mA)
Figure 32. Output Voltage vs Output Current
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
2.5
2.5
AVDD = DVDD = 2.2V
AVDD = DVDD = 2.2V
G=4
2.0
G=8
1.5
G=2
1.0
Output Voltage (V)
Output Voltage (V)
2.0
0.5
1.5
G = 16
G = 64
1.0
G = 32
0.5
G=1
G = 128
0
0
1k
10k
100k
1M
10M
1k
10k
100k
1M
Frequency (Hz)
Figure 33. PGA112, PGA116 Output Voltage Swing vs
Frequency
Figure 34. PGA112, PGA116 Output Voltage Swing vs
Frequency
6
6
G=8
G = 16
5
G=4
4
3
G=1
2
G=2
Output Voltage (V)
Output Voltage (V)
5
1
0
100
3
G = 64
2
1k
10k
100k
1M
AVDD = DVDD = 5.5V
0
100
1k
10k
10M
G = 128
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 35. PGA112, PGA116 Output Voltage Swing vs
Frequency
Figure 36. PGA112, PGA116 Output Voltage Swing vs
Frequency
2.5
2.5
2.0
G = 10
1.5
G=2
1.0
G=1
0.5
Output Voltage (V)
2.0
Output Voltage (V)
G = 32
4
1
AVDD = DVDD = 5.5V
G = 20
1.5
G = 50
G = 100
1.0
G = 200
0.5
G=5
AVDD = DVDD = 2.2V
AVDD = DVDD = 2.2V
0
0
1k
16
10M
Frequency (Hz)
10k
100k
1M
10M
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 37. PGA113, PGA117 Output Voltage Swing vs
Frequency
Figure 38. PGA113, PGA117 Output Voltage Swing vs
Frequency
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
6
6
5
G = 10
G = 50
Output Voltage (V)
Output Voltage (V)
5
4
G=5
3
2
4
G = 20
3
G = 100
2
G=1
1
1
G=2
AVDD = DVDD = 5.5V
0
0
100
10k
1k
100k
10M
1M
100
10k
1k
100k
10M
1M
Frequency (Hz)
Frequency (Hz)
Figure 39. PGA113, PGA117 Output Voltage Swing vs
Frequency
Figure 40. PGA113, PGA117 Output Voltage Swing vs
Frequency
50
12
40
10
30
G>2
20
CL = 100pF//RL = 10kW
VOUT = 4VPP
0.01%
Settling Time (ms)
G=1
Overshoot (%)
G = 200
AVDD = DVDD = 5.5V
8
6
0.1%
4
10
2
0
0
100
200
300
400
500
600
700
0
800
0
50
100
Load Capacitance (pF)
Figure 41. Small-Signal Overshoot vs Load Capacitance
20
CH0
15
10
5
CH1 to
CH9
-5
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 43. Input ON-Channel Current vs Temperature
Copyright © 2008–2015, Texas Instruments Incorporated
Figure 42. Gain vs Settling Time
Channel 0 Input Off-Channel Current (nA)
Measurement made with channel pin
connected to midsupply
0
200
25
0.15
Measurement made with channel pin
connected to midsupply
20
0.10
CH1 to
CH9
15
0.05
10
0
5
-0.05
CH0
0
-5
-50
-0.01
Channel 1 to Channel 9
Input Off-Channel Current (nA)
Input On-Channel Current (nA)
25
150
Gain
-0.15
-25
0
25
50
75
100
125
Temperature (°C)
Figure 44. Input OFF-Channel Leakage Current vs
Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
140
110
100
G=1
130
90
PSRR (dB)
G = 50
G³2
70
G = 200
60
50
40
30
G=2
Crosstalk (dB)
120
80
110
100
90
80
20
70
10
G = 10
0
0.1
1
10
100
1k
10k
100k
1M
60
10
10M
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 45. Power-Supply Rejection Ratio vs Frequency
Figure 46. Crosstalk vs Frequency
G = 20
G = 10
G=1
100mV
10M
100mV
G = 50
Output
Output
0V
G = 100, 200
0V
VIN/G
VIN/G
Input
Input
0V
0V
2.5ms/div
2.5ms/div
Figure 47. Small-Signal Pulse Response
Figure 48. Small-Signal Pulse Response
G = 50
Output
2V/div
2V/div
G = 10
G=2
G=1
Input
Output
G = 100, 200
Input
2.5ms/div
Figure 49. Large-Signal Pulse Response
18
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2.5ms/div
Figure 50. Large-Signal Pulse Response
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Typical Characteristics (continued)
at TA = 25°C, AVDD = DVDD = 5 V, RL = 10 kΩ connected to DVDD/2, VREF = GND, and CL = 100 pF, unless otherwise noted.
VIN
5V
1V/div
Output (1V/div)
0V
VOUT
Supply (5V/div)
0V
0V
VS = 5V
RL = 10kW
CL = 100pF
25ms/div
1ms/div
Figure 51. Power-Up and Power-Down Timing
2V/div
In
Shutdown
Active
In
Shutdown
Output
Output
Output
CS
2V/div
Active
Figure 52. Output Overdrive Performance
Enable
CS
10ms/div
10ms/div
Figure 53. Output Voltage vs Shutdown Mode
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Figure 54. PGA116, PGA117 Hardware Shutdown Mode
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8 Detailed Description
8.1 Overview
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface,
and software shutdown in an 10-pin VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer
10 analog inputs, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9
VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system
calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100,
and 200.
The PGA uses a SPI interface with daisy-chain capability, a standard serial peripheral interface (SPI). Both SPI
Mode 0,0 and Mode 1,1 are supported, as shown in Figure 56 and described in Table 2.
8.2 Functional Block Diagram
AVDD
VCAL/CH0
CH1
DVDD
+
MUX
Output
Stage
±
CAL1
10 k
VOUT
RF
0.9VCAL
0.1VCAL
80 k
CAL2
CAL3
CAL4
R1
VREF
CAL2/3
SCLK
10
SPI
Interface
DIO
CS
GND
VREF
8.3 Feature Description
Featuring low offset, low offset drift and low noise, the PGA11x series provides a flexible analog building block
for a variety of applications. The PGA112 and PGA116 offer binary gains of 1, 2, 4, 8, 16, 32, 64, 128 and a 2
channel MUX while the PGA113 and PGA117 offer scope gains of 1, 2, 5, 10, 20, 50, 100, 200 and a 10 channel
MUX.
8.4 Device Functional Modes
The PGA112 and PGA113 devices have a software shutdown mode, and the PGA116 and PGA117 devices offer
both a hardware and software shutdown mode, see Shutdown and Power-On-Reset (POR) for additional
information. The PGA uses a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are
supported. More information regarding serial communications, including daisy chaining can be found in Serial
Interface Information.
20
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8.5 Programming
Table 1. Frequency Response Versus Gain (CL = 100 pf, RL= 10 kω)
TYPICAL
BINARY
–3-dB
GAIN (V/V) FREQUENCY
(MHz)
SLEW
RATEFALL
(V/μs)
SLEW
RATERISE
(V/μs)
0.1%
SETTLING
TIME:
4 VPP
(μs)
0.01%
SETTLING
TIME:
4 VPP
(μs)
SCOPE
GAIN
(V/V)
TYPICAL
–3-dB
FREQUENCY
(MHz)
SLEW
RATEFALL
(V/μs)
SLEW
RATERISE
(V/μs)
0.1%
SETTLING
TIME:
4 VPP
(μs)
0.01%
SETTLING
TIME:
4 VPP
(μs)
1
10
8
3
2
2.55
1
10
8
3
2
2.55
2
3.8
9
6.4
2
2.6
2
3.8
9
6.4
2
2.6
4
2
12.8
10.6
2
2.6
5
1.8
12.8
10.6
2
2.6
8
1.8
12.8
10.6
2
2.6
10
1.8
12.8
10.6
2.2
2.6
16
1.6
12.8
12.8
2.3
2.6
20
1.3
12.8
9.1
2.3
2.8
32
1.8
12.8
13.3
2.3
3
50
0.9
9.1
7.1
2.4
3.8
64
0.6
4
3.5
3
6
100
0.38
4
3.5
4.4
7
128
0.35
2.5
2.5
4.8
8
200
0.23
2.3
2
6.9
10
Mux
Switch
CHx
(Input)
RSW
CCH
VOUT
RAMP
CAMP
Break-Before-Make
RF
RI
VREF
Figure 55. Equivalent Input Circuit
8.6 Serial Interface Information
SPI Mode 0, 0 (CPOL = 0, CPHA = 0)
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DOUT
SPI Mode 1, 1 (CPOL = 1, CPHA = 1)
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
DIN
DOUT
Figure 56. SPI Mode 0,0 And Mode 1,1
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Serial Interface Information (continued)
Table 2. SPI Mode Setting Description
MODE
CPOL
CPHA
CPOL DESCRIPTION
CPHA DESCRIPTION
0, 0
0
0 (1)
Clock idles low
Data are read on the rising edge of clock. Data change on the falling edge of clock.
1, 1
1
1 (2)
Clock idles high
Data are read on the rising edge of clock. Data change on the falling edge of clock.
(1)
(2)
CPHA = 0 means sample on first clock edge (rising or falling) after a valid CS.
CPHA = 1 means sample on second clock edge (rising or falling) after a valid CS.
8.6.1 Serial Digital Interface: SPI Modes
The PGA uses a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are supported, as
shown in Figure 56 and described in Table 2.
If there are not even-numbered increments of 16 clocks (that is, 16, 32, 64, and so forth) between CS going low
(falling edge) and CS going high (rising edge), the device takes no action. This condition provides reliable serial
communication. Furthermore, this condition also provides a way to quickly reset the SPI interface to a known
starting condition for data synchronization. Transmitted data are latched internally on the rising edge of CS.
On the PGA116 and PGA117 devices, CS, DIN, and SCLK are Schmitt-triggered CMOS logic inputs. DIN has a
weak internal pulldown to support daisy-chain communications on the PGA116 and PGA117 devices. DOUT is a
CMOS logic output. When CS is high, the state of DOUT is high-impedance. When CS is low, DOUT is driven as
illustrated in Figure 57.
DOUT
DIN
10mA
PGA116
PGA117
Figure 57. Digital I/O Structure—PGA116 and PGA117
On the PGA112 and PGA113 devices, there are digital output and digital input gates both internally connected to
the DIO pin. DIN is an input-only gate and DOUT is a digital output that can give a 3-state output. The DIO pin
has a weak 10-μA pulldown current source to prevent the pin from floating in systems with a high-impedance SPI
DOUT line. When CS is high, the state of the internal DOUT gate is high-impedance. When CS is low, the state
of DIO depends on the previous valid SPI communication; either DIO becomes an output to clock out data or it
remains an input to receive data. This structure is shown in Figure 58.
DOUT
DIO
DIN
10mA
PGA112
PGA113
Figure 58. Digital I/O Structure—PGA112 and PGA113
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8.6.2 Serial Digital Interface: SPI Daisy-Chain Communications
To reduce the number of I/O port pins used on a microcontroller, the PGA116 and PGA117 support SPI daisychain communications with full read and write capability. A two-device daisy-chain configuration is shown in
Figure 59, although any number of devices can be daisy-chained. The SPI daisy-chain communication uses a
common SCLK and CS line for all devices in the daisy chain, rather than each device requiring a separate CS
line. The daisy-chain mode of communication routes data serially through each device in the chain by using its
respective DIN and DOUT pins as shown. Special commands are used (see Table 4) to ensure that data are
written or read in the proper sequence. There is a special daisy-chain NOP command (No OPeration) which,
when presented to the desired device in the daisy-chain, causes no changes in that respective device. Detailed
timing diagrams for daisy-chain operation are shown in Figure 63 through Figure 65.
CS
SCLK
DOUT
DIN
PGA116/PGA117
PGA116/PGA117
MSP430
CS
SCLK
DIN1
U1
DOUT1
CS
SCLK
DIN2
U2
DOUT2
Figure 59. Daisy-Chain Read and Write Configuration
The PGA112 and PGA113 devices can be used as the last device in a daisy-chain as shown in Figure 60 if
write-only communication is acceptable, because the PGA112 and PGA113 devices have no separate DOUT pin
to connect back to the microcontroller DIN pin to read back data in this configuration.
CS
SCLK
DOUT
DIN
PGA116/PGA117
PGA112/PGA113
MSP430
CS
SCLK
DIN1
U1
DOUT1
CS
SCLK
DIO
U2
Figure 60. Daisy-Chain Write-Only Configuration
The maximum SCLK frequency that can be used in daisy-chain operation is directly related to SCLK rise and fall
times, DIN setup time, and DOUT propagation delay. Any number of two or more devices have the same
limitations because it is the timing considerations between adjacent devices that limit the clock speed.
Figure 61 analyzes the maximum SCLK frequency for daisy-chain mode based on the circuit of Figure 59. A
clock rise and fall time of 10 ns is assumed to allow for extra bus capacitance that could occur as a result of
multiple devices in the daisy-chain.
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tRFI
10ns
tRFI
10ns
SCLK
tDO
25ns
DOUT1
tSU
10ns
DIN2
tMIN = 55ns
tMIN = 55ns
SCLKMAX = 9.09MHz
Figure 61. Daisy-Chain Maximum SCLK Frequency
24
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8.6.3 SPI Serial Interface
SPI Write, Mode = 0, 0
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
DIN
DIO
Pin
DOUT
Hi-Z
SPI Write, Mode = 1, 1
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
11
12
13
14
15
16
SCLK
DIN
DIO
Pin
DOUT
Hi-Z
SPI Read, Mode = 0, 0
CS
1
2
3
4
5
6
7
8
9
10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SCLK
DIN
DIO
Pin
0
1
1
D15
D14
D13
0
D12
1
0
1
0
0
0
0
0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Hi-Z
0
0
0
0
0
0
0
0
G3
G2
G1
G0
CH3
CH2
CH1
CH0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
SPI Read, Mode = 1, 1
CS
4
5
6
1
2
3
0
D15
1
D14
1
0
1
0
D13
D12
D11
D10
7
8
9
1
0
D9
D8
0
D7
10
11
12
13
14
15
16
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
17
18
19
21
20
22
23
24
25
26
27
28
29
30
31
32
SCLK
DIN
DIO
Pin
DOUT
Hi-Z
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
G3
D7
G2
D6
G1
D5
G0
D4
CH3
D3
CH2
D2
CH1
D1
CH0
D0
Hi-Z
Figure 62. SPI Serial Interface Timing Diagrams
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CS
SCLK
DOUT
DIN
PGA116/PGA117
PGA116/PGA117
MSP430
CS
SCLK
DIN1
CS
SCLK
DIN2
U1
DOUT1
U2
DOUT2
Daisy-Chain SPI Write, Mode = 0,0
CS
1
2
3
4
5
6
7
D15
D14
D13
D12
D11
D10
D9
8
9
10
11
12
13
14
15
16
17
18
19
20
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
21
22
23
24
25
26
27
28
29
30
31
32
SCLK
DOUT
DIN1
D11
D10
D9
DOUT1
DIN2
D8
D7
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
26
27
29
30
Command U1
Command U2
D15
D14
D13
D12
D11
D10
D9
D8
D7
DOUT Hi-Z Pulled Low by DIN Weak Pull-Down
Command U2
Daisy-Chain SPI Write, Mode = 1,1
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
23
24
25
28
31
32
SCLK
DOUT
DIN1
D9
D8
Command U2
DOUT1
DIN2
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
Command U1
D15
D14
D13
D12
D11
D10
DOUT Hi-Z Pulled Low by DIN Weak Pull-Down
D9
D8
D7
D6
Command U2
Figure 63. SPI Daisy-Chain Write Timing Diagrams
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CS
SCLK
DOUT
DIN
PGA116/PGA117
PGA116/PGA117
MSP430
CS
SCLK
DIN1
CS
SCLK
DIN2
U1
DOUT1
U2
DOUT2
Daisy-Chain SPI Read, Mode = 0,0
CS
1
2
3
4
5
6
7
0
1
1
1
1
0
1
8
9
10
11
12
13
14
15
16
17
18
19
20
0
0
0
0
0
0
0
0
0
0
1
1
1
21
22
23
24
25
26
27
28
29
30
31
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCLK
DOUT
DIN1
0
1
0
1
DOUT1
DIN2
0
Command U1
Command U2
0
1
1
1
0
1
0
1
0
DOUT Hi-Z Pulled Low by DIN Weak Pull-Down
Command U2
CS
1
2
3
5
4
6
7
8
9
10
11
12
13
14
15
16
CH3
CH2
CH1
CH0
CH2
CH1
CH0
17
18
19
20
21
22
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
CH3
CH2
CH1
32
SCLK
DOUT1
DIN2
0
0
0
0
0
0
0
0
G3
G2
G1
G0
Data Byte U1
DOUT2
DIN
0
0
0
0
0
0
0
0
G3
G2
G1
G0
CH3
0
0
Data Byte U2
G3
G2
G1
G0
CH0
Hi-Z
Data Byte U1
Figure 64. SPI Daisy-Chain Read Timing Diagram (Mode 0,0)
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CS
SCLK
DOUT
DIN
PGA116/PGA117
PGA116/PGA117
MSP430
CS
SCLK
DIN1
CS
SCLK
DIN2
U1
DOUT1
U2
DOUT2
Daisy-Chain SPI Read, Mode = 1,1
CS
1
2
3
4
5
6
7
0
1
1
1
1
0
1
8
9
10
11
12
13
14
15
16
17
18
19
20
0
0
0
0
0
0
0
0
0
0
1
1
1
21
22
23
24
25
26
27
28
29
30
31
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCLK
DOUT
DIN1
0
1
0
1
DOUT1
DIN2
0
Command U1
Command U2
1
0
1
1
1
0
1
0
0
DOUT Hi-Z Pulled Low by DIN Weak Pull-Down
Command U2
CS
17
18
19
21
20
22
23
24
25
26
27
28
29
30
31
32
CH3
CH2
CH1
CH0
CH2
CH1
CH0
17
18
19
20
21
22
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
CH3
CH2
CH1
32
SCLK
DOUT1
DIN2
0
0
0
0
0
0
0
0
G3
G2
G1
G0
Data Byte U1
DOUT2
DIN
0
0
0
0
0
0
0
0
G3
G2
G1
G0
CH3
0
0
Data Byte U2
G3
G2
G1
G0
CH0
Hi-Z
Data Byte U1
Figure 65. SPI Daisy-Chain Read Timing Diagram (Mode 1,1)
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8.6.4 SPI Commands
Table 3. SPI Commands (PGA112 and PGA113) (1) (2)
THREE-WIRE
SPI COMMAND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
READ
0
0
1
0
1
0
1
0
G3
G2
G1
G0
CH3
CH2
CH1
CH0
WRITE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOP WRITE
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
SDN_DIS
WRITE
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
SDN_EN WRITE
(1)
SDN = Shutdown mode. Enter Shutdown mode by issuing an SDN_EN command. Shutdown mode is cleared (returned to the last valid
write configuration) by a SDN_DIS command or by any valid Write command.
POR (Power-on-Reset) value of internal Gain/Channel Select Register is all 0s; this value sets Gain = 1, and Channel = VCAL/CH0.
(2)
Table 4. SPI Daisy-Chain Commands (1) (2)
DAISY-CHAIN
COMMAND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
NOP
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
SDN_DIS
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
SDN_EN
0
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
READ
0
0
1
1
1
0
1
0
G3
G2
G1
G0
CH3
CH2
CH1
CH0
WRITE
(1)
(2)
SDN = Shutdown Mode. Shutdown Mode is entered by an SDN_EN command. Shutdown Mode is cleared (returned to the last valid
write configuration) by a SDN_DIS command or by any valid Write command.
POR (Power-on-Reset) value of internal Gain/Channel Register is all 0s; this value sets Gain = 1, VCAL/CH0 selected.
Table 5. Gain Selection Bits (PGA112 and PGA113)
G3
G2
G1
G0
BINARY GAIN
SCOPE GAIN
0
0
0
0
1
1
0
0
0
1
2
2
0
0
1
0
4
5
0
0
1
1
8
10
0
1
0
0
16
20
0
1
0
1
32
50
0
1
1
0
64
100
0
1
1
1
128
200
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Table 6. MUX Channel Selection Bits
CH3
CH2
CH1
CH0
PGA112, PGA113
PGA116, PGA117
0
0
0
0
VCAL/CH0
VCAL/CH0
0
0
0
1
CH1
CH1
0
0
1
0
X (1)
CH2
0
0
1
1
X
CH3
0
1
0
0
X
CH4
0
1
0
1
X
CH5
0
1
1
0
X
CH6
0
1
1
1
X
CH7
1
0
0
0
X
CH8
1
0
0
1
X
CH9
1
0
1
0
X
X (1)
1
0
1
1
Factory Reserved
Factory Reserved
1
1
0
0
CAL1 (2)
CAL1 (2)
(3)
CAL2 (3)
1
1
0
1
CAL2
1
1
1
0
CAL3 (4)
CAL3 (4)
1
(5)
CAL4 (5)
1
(1)
(2)
(3)
(4)
(5)
30
1
1
CAL4
X = channel is not used.
CAL1: connects to GND.
CAL2: connects to 0.9 VCAL.
CAL3: connects to 0.1 VCAL.
CAL4: connects to VREF.
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9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The PGA11x family of devices are single-ended input, single-supply, programmable gain amplifiers (PGAs) with
an input multiplexer. Multiplexer channel selection and gain selection are done through a standard SPI interface.
The PGA112 and PGA113 have a two-channel input MUX and the PGA116 and PGA117 devices have a 10channel input MUX. The PGA112 and PGA116 devices provide binary gain selections (1, 2, 4, 8, 16, 32, 64, 128)
and the PGA113 and PGA117 devices provide scope gain selections (1, 2, 5, 10, 20, 50, 100, 200). All models
use a split-supply architecture with an analog supply, AVDD, and a digital supply, DVDD. This split-supply
architecture allows for ease of interface to analog-to-digital converters (ADCs) and microcontrollers in mixedsupply voltage systems, such as where the analog supply is 5 V and the digital supply is 3 V. Four internal
calibration channels are provided for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL,
and VREF, respectively. VCAL, an external voltage connected to VCAL/CH0, acts as the system calibration
reference. If VCAL is the system ADC reference, then gain and offset calibration on the ADC are easily
accomplished through the PGA11x devices using only one MUX input. If calibration is not used, then VCAL/CH0
can be used as a standard MUX input. All four versions provide a VREF pin that can be tied to ground or, for ease
of scaling, to midsupply in single-supply systems where midsupply is used as a virtual ground. The PGA112 and
PGA113 devices offer a software-controlled shutdown feature for low standby power. The PGA116 and PGA117
devices offer both hardware- and software-controlled shutdown for low standby power. The PGA112 and
PGA113 devices have a 3-wire SPI digital interface; the PGA116 and PGA117 devices have a four-wire SPI
digital interface. The PGA116 and PGA117 devices also have daisy-chain capability.
9.1.1 Op Amp: Input Stage
The PGA op amp is a rail-to-rail input and output (RRIO) single-supply op amp. The input topology uses two
separate input stages in parallel to achieve rail-to-rail input. As Figure 66 shows, there is a PMOS transistor on
each input for operation down to ground; there is also an NMOS transistor on each input in parallel for operation
to the positive supply rail. When the common-mode input voltage (that is, the single-ended input, because this
PGA is configured internally for noninverting gain) crosses a level that is typically about 1.5 V less than the
positive supply, there is a transition between the NMOS and PMOS transistors. The result of this transition
appears as a small input offset voltage transition that is reflected to the output by the selected PGA gain. This
transition may be either increasing or decreasing, and differs from part to part as described in Figure 67 and
Figure 68. These figures illustrate possible differences in input offset voltage between two different devices when
used with AVDD = 5 V. Because the exact transition region varies from device to device, the Electrical
Characteristics: VS = AVDD = DVDD = 5 V table specifies an input offset voltage above and below this input
transition region.
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Application Information (continued)
AVDD
Reference
Current
VIN-
VIN+
GND
Figure 66. PGA Rail-To-Rail Input Stage
80
Input Offset Voltage (mV)
70
60
50
40
30
20
10
AVDD = 5V
0
0
1
2
3
4
5
6
Input Voltage (V)
Figure 67. VOS Versus Input Voltage—Case 1
50
AVDD = 5V
Input Offset Voltage (mV)
40
30
20
10
0
-10
-20
-30
0
1
2
3
4
5
6
Input Voltage (V)
Figure 68. VOS Versus Input Voltage—Case 2
9.1.2 Op Amp: General Gain Equations
Figure 69 shows the basic configuration for using the PGA as a gain block. VOUT / VIN is the selected
noninverting gain, depending on the model selected, for either binary or scope gains.
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Application Information (continued)
CH1
VOUT
RI
VIN
VREF
RF
G=1
Figure 69. PGA Used as a Gain Block
VOUT = G ´ VIN
where
•
•
G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)
G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope gains)
(1)
Figure 70 shows the PGA configuration and gain equations for VREF = AVDD/2. VOUT0 is VOUT when CH0 is
selected and VOUT1 is VOUT when CH1 is selected. Notice the VREF pin has no effect for G = 1 because the
internal feedback resistor, RF, is shorted out. This configuration allows for positive and negative voltage
excursions around a midsupply virtual ground.
CH0
CH1
PGA112
PGA113
MUX
VOUT
RI
VIN0
VIN1
VREF
RF
+
G=1
VS/2
-
Figure 70. PGA112 and PGA113 Configuration for Positive and Negative Excursions Around Midsupply
Virtual Ground
VOUT0 = G ´ VIN0 - AVDD/2 ´ (G - 1)
(2)
When: G = 1
Then: VOUT0 = G × VIN0
VOUT1 = G ´ (VIN1 + AVDD/2) - AVDD/2 ´ (G - 1)
VOUT1 = G ´ VIN1 + AVDD/2, where: -AVDD/2 < G ´ VIN1 < +AVDD/2
where
•
•
G = 1, 2, 4, 8, 16, 32, 64, and 128 (binary gains)
G = 1, 2, 5, 10, 20, 50, 100, and 200 (scope gains)
(3)
Table 7 details the internal typical values for the op amp internal feedback resistor (RF) and op amp internal input
resistor (RI) for both binary and scope gains.
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Application Information (continued)
Table 7. Typical RF and RI Versus Gain
BINARY GAIN (V/V)
RF (Ω)
RI (Ω)
SCOPE GAIN (V/V)
RF (Ω)
RI (Ω)
1
0
3.25 k
1
0
3.25 k
2
3.25 k
3.25 k
2
3.25 k
3.25 k
4
9.75 k
3.25 k
5
13 k
3.25 k
8
22.75 k
3.25 k
10
29.25 k
3.25 k
16
48.75 k
3.25 k
20
61.75 k
3.25 k
32
100.75 k
3.25 k
50
159.25 k
3.25 k
64
204.75 k
3.25 k
100
321.75 k
3.25 k
128
412.75 k
3.25 k
200
646.75 k
3.25 k
9.1.3 Op Amp: Frequency Response Versus Gain
Table 8 documents how small-signal bandwidth and slew rate change correspond to changes in PGA gain.
Full power bandwidth (that is, the highest frequency that a sine wave can pass through the PGA for a given gain)
is related to slew rate by Equation 4:
SR (V/ms) = 2pf ´ VOP (1 ´ 10-6)
where
•
•
•
SR = Slew rate in V/μs
f = Frequency in Hz
VOP = Output peak voltage in volts
(4)
9.1.3.1 Example:
For G = 8, then SR = 10.6 V/μs (slew rate rise is minimum slew rate).
For a 5-V system, choose 0.1 V < VOUT < 4.9 V or VOUTPP = 4.8 V or VOUTP = 2.4 V.
SR (V/μs) = 2πf × VOP (1 × 10–6).
10.6 = 2πf (2.4) (1 × 10–6) → f = 702.9 kHz
This example shows that a G = 8 configuration can produce a 4.8-VPP sine wave with frequency up to 702.9 kHz.
This computation only shows the theoretical upper limit of frequency for this example, but does not indicate the
distortion of the sine wave. The acceptable distortion depends on the specific application. As a general guideline,
maintain two to three times the calculated slew rate to minimize distortion on the sine wave. For this example,
the application should only use G = 8, 4.8 VPP, up to a frequency range of 234 kHz to 351 kHz, depending upon
the acceptable distortion. For a given gain and slew rate requirement, check for adequate small-signal bandwidth
(typical –3-dB frequency) to assure that the frequency of the signal can be passed without attenuation.
9.1.4 Analog MUX
The analog input MUX provides two input channels for the PGA112 and PGA113 devices and 10 input channels
for the PGA116 and PGA117 devices. The MUX switches are designed to be break-before-make and thereby
eliminate any concerns about shorting the two input signal sources together.
Four internal MUX CAL channels are included in the analog MUX for ease of system calibration. These CAL
channels allow ADC gain and offset errors to be calibrated out. This calibration does not remove the offset and
gain errors of the PGA for gains greater than 1, but most systems should see a significant increase in the ADC
accuracy. In addition, these CAL channels can be used by the ADC to read the minimum and maximum possible
voltages from the PGA. With these minimum and maximum levels known, the system architecture can be
designed to indicate an out-of-range condition on the measured analog input signals if these levels are ever
measured.
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To use the CAL channels, VCAL/CH0 must be permanently connected to the system ADC reference. There is a
typical 100-kΩ load from VCAL/CH0 to ground. Table 9 illustrates how to use the CAL channels with VREF =
ground. Table 10 describes how to use the CAL channels with VREF = AVDD/2. The VREF pin must be connected
to a source that is low-impedance for both DC and AC to maintain gain and nonlinearity accuracy. Worst-case
current demand on the VREF pin occurs when G = 1 because there is a 3.25-kΩ resistor between VOUT and VREF.
For a 5-V system with AVDD/2 = 2.5 V, the VREF pin buffer must source and sink 2.5 V/3.25 kΩ = 0.7 mA
minimum for a VOUT that can swing from ground to 5 V.
Table 8. Frequency Response versus Gain (CL = 100 pf, RL= 10 kω)
TYPICAL
BINARY
–3dB
GAIN (V/V) FREQUENCY
(MHz)
SLEW
RATEFALL
(V/μs)
SLEW
RATERISE
(V/μs)
0.1%
SETTLING
TIME:
4VPP
(μs)
0.01%
SETTLING
TIME:
4VPP
(μs)
SCOPE
GAIN
(V/V)
TYPICAL
–3dB
FREQUENCY
(MHz)
SLEW
RATEFALL
(V/μs)
SLEW
RATERISE
(V/μs)
0.1%
SETTLING
TIME:
4VPP
(μs)
0.01%
SETTLING
TIME:
4VPP
(μs)
1
10
8
3
2
2.55
1
10
8
3
2
2.55
2
3.8
9
6.4
2
2.6
2
3.8
9
6.4
2
2.6
4
2
12.8
10.6
2
2.6
5
1.8
12.8
10.6
2
2.6
8
1.8
12.8
10.6
2
2.6
10
1.8
12.8
10.6
2.2
2.6
16
1.6
12.8
12.8
2.3
2.6
20
1.3
12.8
9.1
2.3
2.8
32
1.8
12.8
13.3
2.3
3
50
0.9
9.1
7.1
2.4
3.8
64
0.6
4
3.5
3
6
100
0.38
4
3.5
4.4
7
128
0.35
2.5
2.5
4.8
8
200
0.23
2.3
2
6.9
10
+3V
+3V
CBYPASS
0.1mF
CBYPASS
0.1mF
CBYPASS
0.1mF
DVDD
AVDD
REF3225
PGA112
PGA113
VCAL/CH0
MUX
Output
Stage
CH1
VOUT
2.5V
ADC Ref
ADC
CAL1
10kW
RF
G=1
0.9VCAL
0.1VCAL
80kW
CAL3
CAL4
10kW
MSP430
Microcontroller
CAL2
RI
VREF
CAL2/3
GND
SCLK
SPI
Interface
DIO
CS
VREF
Figure 71. Using CAL Channels With VREF = Ground
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Table 9. Using the MUX CAL Channels With VREF = GND
(AVDD = 3 V, DVDD = 3 V, ADC Ref = 2.5 V, and VREF = GND)
FUNCTION
MUX
SELECT
GAIN
SELECT
MUX INPUT
OP AMP
(+In)
OP AMP
(VOUT)
DESCRIPTION
Minimum Signal
CAL1
1
GND
GND
50 mV
Minimum signal level that the
MUX, op amp, and ADC can
read. Op amp VOUT is limited
by negative saturation.
Gain Calibration
CAL2
1
0.9 ×
(VCAL/CH0)
2.25 V
2.25 V
90% ADC Ref for system fullscale or gain calibration of
the ADC.
Maximum Signal
CAL2
2
0.9 ×
(VCAL/CH0)
2.25 V
2.95 V
Maximum signal level that
the MUX, op amp, and ADC
can read. Op amp VOUT is
limited by positive saturation.
System is limited by ADC
max input of 2.5 V (ADC Ref
= 2.5 V).
Offset Calibration
CAL3
1
0.1 ×
(VCAL/CH0)
0.25 V
0.25 V
10% ADC Ref for system
offset calibration of the ADC.
50 mV
Minimum signal level that the
MUX, op amp, and ADC can
read. Op amp VOUT is limited
by negative saturation.
Minimum Signal
CAL4
1
VREF
GND
+3V
+3V
AVDD
CBYPASS
0.1mF
CBYPASS
0.1mF
CBYPASS
0.1mF
DVDD
PGA112
PGA113
VCAL/CH0
ADC Ref
MUX
Output
Stage
CH1
CAL1
10kW
MSP430
Microcontroller
CAL2
0.1VCAL
CAL3
80kW
ADC
RF
G=1
0.9VCAL
VOUT
RI
VREF
CAL4
CAL2/3
10kW
SCLK
SPI
Interface
GND
DIO
CS
VREF
RF
10kW
CF
2.7nF
+3V
CBYPASS
0.1mF
+3V
RX
100kW
RY
100kW
(1.5V)
OPA364
0.1mF
CL2
0.1mF
Figure 72. Using CAL Channels With VREF = AVDD/2
Table 10. Using the MUX CAL Channels With VREF = AVDD/2
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Table 10. Using the MUX CAL Channels With VREF = AVDD/2
(AvDD = 3 V, DVDD = 3 V, ADC Ref = 3 V, and VREF = 1.5 V) (continued)
(AvDD = 3 V, DVDD = 3 V, ADC Ref = 3 V, and VREF = 1.5 V)
FUNCTION
MUX
SELECT
GAIN
SELECT
MUX INPUT
OP AMP
(+In)
OP AMP
(VOUT)
DESCRIPTION
Minimum Signal
CAL1
1
GND
GND
50 mV
Minimum signal level that the MUX,
op amp, and ADC can read. Op amp
VOUT is limited by negative saturation.
Gain Calibration
CAL2
1
0.9 ×
(VCAL/CH0)
2.7 V
2.7 V
90% ADC Ref for system full-scale or
gain calibration of the ADC.
Maximum Signal
CAL2
4 or 5
0.9 ×
(VCAL/CH0)
2.25 V
2.95 V
Maximum signal level that the MUX,
op amp, and ADC can read. Op amp
VOUT is limited by positive saturation.
Offset Calibration
CAL3
1
0.1 ×
(VCAL/CH0)
0.3 V
0.3 V
10% ADC Ref for system offset
calibration of the ADC.
VREF Check
CAL4
1
VREF
1.5 V
1.5 V
Midsupply voltage used as VREF.
9.1.5 System Calibration Using The PGA
Analog-to-digital converters (ADCs) contain two major errors that can be easily removed by calibration at a
system level. These errors are gain error and offset error, as shown in Figure 73. Figure 73 shows a typical
transfer function for a 12-bit ADC. The analog input is on the x-axis with a range from 0 V to (VREF_ADC – 1LSB),
where VREF_ADC is the ADC reference voltage. The y-axis is the hexadecimal equivalent of the digital codes that
result from ADC conversions. The dotted red line represents an ideal transfer function with 0000h representing 0
V analog input and 0FFFh representing an analog input of (VREF_ADC – 1LSB). The solid blue line illustrates the
offset error. Although the solid blue line includes both offset error and gain error, at an analog input of 0 V the
offset error voltage, VZ_ACTUAL, can be measured. The dashed black line represents the transfer function with gain
error. The dashed black line is equivalent to the solid blue line without the offset error, and can be measured and
computed using VZ_ACTUAL and VZ_IDEAL. The difference between the dashed black line and the dotted red line is
the gain error. Gain and offset error can be computed by taking zero input and full-scale input readings. Using
these error calculations, compute a calibrated ADC reading to remove the ADC gain and offset error.
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VFS_ACTUAL
Gain Error
0FFFh
VFS_IDEAL
Transfer Function
with Offset Error + Gain Error
Id
ea
lT
ra
ns
fe
rF
un
ct
io
n
Digital Output
Transfer Function
with Gain Error Only
VZ_ACTUAL
0000h
VZ_IDEAL
Offset Error
0V
Analog Input
VREF_ADC - 1LSB
Figure 73. ADC Offset and Gain Error
In practice, the zero input (0 V) or full-scale input (VREF_ADC – 1LSB) of ADCs cannot always be measured
because of internal offset error and gain error. However, if measurements are made very close to the full-scale
input and the zero input, both zero and full-scale can be calibrated very accurately with the assumption of
linearity from the calibration points to the desired end points of the ADC ideal transfer function. For the zero
calibration, choose 10%VREF_ADC; this value should be above the internal offset error and sufficiently out of the
noise floor range of the ADC. For the gain calibration, choose 90%VREF_ADC; this value should be less than the
internal gain error and sufficiently below the tolerance of VREF. These key points can be summarized in this way:
For zero calibration:
• The ADC cannot read the ideal zero because of offset error
• Must be far enough above ground to be above noise floor and ADC offset error
• Therefore, choose 10%VREF_ADC for zero calibration
For gain calibration:
• The ADC cannot read the ideal full-scale because of gain error
• Must be far enough below full-scale to be below the VREF tolerance and ADC gain error
• Therefore, choose 90%VREF_ADC for gain calibration
The 12-bit ADC example in Figure 74 illustrates the technique for calibrating an ADC using a 10%VREF_ADC and
90%VREF_ADC reading where VREF_ADC is the ADC reference voltage. The 10%VREF reading also contains a gain
error because it is not a VIN = 0 calibration point. First, use the 90%VREF and 10%VREF points to compute the
measured gain error. The measured gain error is then used to remove the gain error from the 10%VREF reading,
giving a measured 10%VREF number. The measured 10%VREF number is used to compute the measured offset
error.
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VREF = +5V
Offset Error = +4LSB
Gain Error = +6LSB
Digital Output (VAD_MEAS)
0FFFh (4.99878V)
(4.5114751443V)
Id
ea
lT
ra
ns
fe
rF
un
ct
io
n
Transfer Function
with Offset Error + Gain Error
(0.5056191443V)
0000h (0V)
0.5V
(0.1 ´ VREF_ADC)
0V
VIN
4.5V
(0.9 ´ VREF_ADC)
4.99878V
(VREF_ADC - 1LSB)
Figure 74. 12-Bit Example of ADC Calibration for Gain and Offset Error
The gain error and offset error in ADC readings can be calibrated by using 10%VREF_ADC and 90%VREF_ADC
calibration points. Because the calibration is ratiometric to VREF_ADC, the exact value of VREF_ADC does not need
to be known in the end application.
Follow these steps to compute a calibrated ADC reading:
1. Take the ADC reading at VIN = 90% × VREF and VIN = 10% × VREF. The ADC readings for 10%VREF and
90%VREF are taken.
VREF90 = 0.9(VREF_ADC)
(5)
VREF10 = 0.1(VREF_ADC)
(6)
VMEAS90 = ADCMEASUREMENT at VREF90
(7)
VMEAS10 = ADCMEASUREMENT at VREF10
(8)
2. Compute the ADC measured gain. The slope of the curve connecting the measured 10%VREF and measured
90%VREF point is computed and compared to the slope between the ideal 10%VREF and ideal 90%VREF. This
result is the measured gain.
VMEAS90 - VMEAS10
GMEAS =
VREF90 - VREF10
(9)
3. Compute the ADC measured offset. The measured offset is computed by taking the difference between the
measured 10%VREF and the (ideal 10%VREF) × (measured gain).
OMEAS = VMEAS10 - (VREF10 ´ GMEAS)
(10)
4. Compute the calibrated ADC readings.
VAD_MEAS = Any VIN ADCMEASUREMENT
(11)
VADC_CAL =
VAD_MEAS - OMEAS
GMEAS
(12)
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Any ADC reading can therefore be calibrated by removing the gain error and offset error. The measured offset is
subtracted from the ADC reading and then divided by the measured gain to give a corrected reading. If this
calibration is performed on a timed basis, relative to the specific application, gain and offset error over
temperature are also removed from the ADC reading by calibration.
For example; given:
• 12-Bit ADC
• ADC Gain Error = 6 LSB
• ADC Offset Error = 4 LSB
• ADC Reference (VREF_ADC) = 5 V
• Temperature = 25°C
Table 11 shows the resulting system accuracy.
Table 11. Bits of System Accuracy (1) (To 0.5 LSB)
(1)
VIN
ADC ACCURACY WITHOUT
CALIBRATION
ADC ACCURACY WITH PGA112
CALIBRATION
10%VREF_ADC
8.80 Bits
12.80 Bits
90%VREF_ADC
7.77 Bits
11.06 Bits
Difference in maximum input offset voltage for VIN = 10%VREF_ADC and VIN = 90%VREF_ADC is the reason for different accuracies.
9.1.6 Driving and Interfacing to ADCs
CDAC SAR ADCs contain an input sampling capacitor, CSH, to sample the input signal during a sample period as
shown in Figure 75. After the sample period, CSH is removed from the input signal. Subsequent comparisons of
the charge stored on CSH are performed during the ADC conversion process. To achieve optimal op amp
stability, input signal settling, and the demands for charge from the input signal conditioning circuitry, most ADC
applications are optimized by the use of a resistor (RFILT) and capacitor (CFILT) filter placed between the op amp
output and ADC input. For the PGA112 and PGA113 devices, or the PGA116 and PGA117 devices, setting CFILT
= 1 nF and RFILT = 100 Ω yields optimum system performance for sampling converters operating at speeds up to
500 kHz, depending upon the application settling time and accuracy requirements.
+3V
+5V
CBYPASS
0.1mF
CBYPASS
0.1mF
10
1
VCAL/CH0
CH1
3
CBYPASS
0.1mF
DVDD
AVDD
PGA112
PGA113
(MSOP-10)
MUX
2
Output
Stage
5
VOUT
RFILT
100W
CFILT
(1nF)
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
CAL2
CDAC SAR
ADC
CAL3
CAL4
10kW
RF
G=1
CSH
40pF
VREF
RI
SPI
Interface
CAL2/3
6
4
GND
VREF
7
SCLK
8
DIO
9
CS
12-Bit Settling ® 500kHz
16-Bit Settling ® 300kHz
Figure 75. Driving and Interfacing to ADCs
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9.1.7 Power Supplies
Figure 76 shows a typical mixed-supply voltage system where the analog supply, AVDD, is 5 V and the digital
supply voltage, DVDD, is 3 V. The analog output stage of the PGA and the SPI interface digital circuitry are both
powered from DVDD. When considering the power required for DVDD, use the Electrical Characteristics: VS =
AVDD = DVDD = 5 V table and add any load current anticipated on VOUT; this load current must be provided by
DVDD. This split-supply architecture ensures compatible logic levels with the microcontroller. It also ensures that
the PGA output cannot run the input for the onboard ADC into an overvoltage condition; this condition could
cause device latch-up and system lock-up, and require power-supply sequencing. Each supply pin should be
individually bypassed with a 0.1 μF ceramic capacitor directly at the device to ground. If there is only one power
supply in the system, AVDD and DVDD can both be connected to the same supply; however, TI recommends
using individual bypass capacitors directly at each respective supply pin to a single point ground. VOUT is diodeclamped to AVDD (as shown in Figure 76); therefore, set DVDD less than or equal to AVDD + 0.3 V. DVDD and
AVDD must be within the operating voltage range of 2.2 V to 5.5 V.
At initial power-on, the state of the PGA is G = 1 and Channel 0 active.
NOTE
For most applications, set AVDD ≥ DVDD to prevent VOUT from driving current into AVDD
and raising the voltage level of AVDD
9.1.8 Shutdown and Power-On-Reset (POR)
The PGA112 and PGA113 devices have a software shutdown mode, and the PGA116 and PGA117 devices offer
both a hardware and software shutdown mode. When the PGA11x is shut down, it goes into a low-power
standby mode. The Electrical Characteristics: VS = AVDD = DVDD = 5 V table details the current draw in shutdown
mode with and without the SPI interface being clocked. In shutdown mode, RF and RI remain connected between
VOUT and VREF.
When DVDD is less than 1.6 V, the digital interface is disabled and the channel and gain selections are held to
the respective POR states of Gain = 1 and Channel = VCAL/CH0. When DVDD is above 1.8 V, the digital interface
is enabled and the POR gain and channel states remain unchanged until a valid SPI communication is received.
+3V
+5V
VCAL/CH0
CH1
3
AVDD
DVDD
1
10
PGA112
PGA113
(MSOP-10)
MSP430
Microcontroller
MUX
2
Output
Stage
5
VOUT
7
SCLK
8
DIO
9
CS
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
RF
G=1
CAL2
CAL3
CAL4
VREF
RI
SPI
Interface
CAL2/3
10kW
6
4
GND
VREF
Figure 76. Split Power-Supply Architecture: AVDD ≠ DvDD
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+3V
+5V
CBYPASS
0.1mF
CBYPASS
0.1mF
AVDD
CBYPASS
0.1mF
DVDD
1
10
MSP430
Microcontroller
PGA112
PGA113
3
VCAL/CH0
MUX
2
CH1
Output
Stage
5
VOUT
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
RF
G=1
CAL2
CAL3
VREF
CAL4
RI
SPI
Interface
CAL2/3
10kW
6
4
GND
VREF
7
SCLK
8
DIO
9
CS
Figure 77. PGA112, PGA113 (VSSOP-10) Typical Application Schematic
9.1.9
Typical Connections: PGA116, PGA117 (TSSOP-20)
+5V
CBYPASS
0.1mF
AVDD
VCAL/CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
1
7
+3V
6
19
5
DVDD
CBYPASS
0.1mF
PGA116
PGA117
4
CBYPASS
0.1mF
3
2
MSP430
Microcontroller
20
10
MUX
11
12
Output
Stage
9
VOUT
ADC
CAL1
10kW
0.9VCAL
0.1VCAL
80kW
G=1
RF
CAL2
CAL3
CAL4
VREF
RI
SPI
Interface
CAL2/3
10kW
14
8
GND
VREF
15
SCLK
16
DIN
18
CS
17
DOUT
13
ENABLE
Figure 78. PGA116, PGA117 (TSSOP-20)
42
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9.2 Typical Applications
9.2.1 Bipolar Input to Single-Supply Scaling
VREF_ADC
(2.5V)
+
RB
10kW
VIN1
(+5V, -5V)
RX
4.81kW
CH1 Input
(2.447817V,
0.0474093V)
RA
9.2kW
Figure 79. Bipolar to Single-Ended Input Algorithm
9.2.1.1 Design Requirements
Table 12. Bipolar to Single-Ended Input Scaling (1) (2)
VREF_ADC (V)
VIN1 (V)
CH1 INPUT
RA (kΩ)
RX (Ω)
RB (kΩ)
2.5
–5
0.047613
9.2
4.81 k
10
0
1.247613
3.16
2.4 k
10
13.5
5.76 k
10
4.02
2.87 k
10
37
7.87 k
10
6.49
3.92 k
10
24
965
10
9.2
4.81 k
10
2.5
3
3
4.096
4.096
5
5
(1)
(2)
5
2.447613
–10
0.050317
0
1.250317
10
2.450317
–5
0.058003
0
1.498003
5
2.938003
–10
0.059303
0
1.499303
10
2.939303
–5
0.082224
0
2.048304
5
4.014384
–10
0.086018
0
2.052098
10
4.018178
–5
0.093506
0
2.493506
5
4.893506
–10
0.095227
0
2.495227
10
4.895227
Scaling is based on 0.02(VREF_ADC) to 0.98(VREF_ADC), using standard 0.1% resistor values.
Assumes symmetrical VIN and symmetrical scaling for CH1 input minimum and maximum.
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9.2.1.2 Detailed Design Procedure
This process assumes a symmetrical VIN1 and that symmetrical scaling is used for CH1 input minimum and
maximum values. The following steps give the algorithm to compute resistor values for references not listed in
Table 12.
Step 1: Choose the following:
a. VREF_ADC = 2.5 V (ADC reference voltage)
b. | VIN1 | = 5
(magnitude of VIN, assuming scaling is for ±VIN1)
c. Choose RB as a standard resistor value. The input on-channel current multiplied by RB should be less than
the input offset voltage, such that RB is not a major source of inaccuracy.
RB = 10 kΩ (select as a starting value for resistors)
d. For the most negative VIN1, choose the percentage (in decimal format) of VREF_ADC desired at the ADC input.
kVO– = 0.02
(CH1 input = kVO– × VREF_ADC when VIN1 = –VIN1)
e. For the most positive VIN1, choose the percentage (in decimal format) of VREF_ADC desired at the ADC input.
Because this scaling is based on symmetry, kVO+ must be the same percentage away from VREF_ADC at the
upper limit as at the lower limit where kVO– is computed.
kVO+ = 1 – kVO–
kVO+ = 1 – 0.02 = 0.98
(CH1 input = kVO+ × VREF_ADC when VIN1 = +VIN1)
Step 2: Compute the following:
a. To simplify analysis, create one constant called kVO.
kVO = kVO+ - kVO0.96 = 0.98 - 0.02
b. A constant, g, is created to simplify resistor value computations.
kVO ´ VREF_ADC
g=
2 ´ |VIN1| - kVO ´ VREF_ADC
(13)
0.96 ´ 2.5
2 ´ 5 - 0.96 ´ 2.5
c. RA is now selected from the starting value of RB and the g constant.
2 ´ RB ´ g
RA =
1-g
0.315789474 =
(14)
2 ´ 10kW ´ 0.315789474
1 - 0.315789474
d. RX can now be computed from the starting value of RB and the computed value for RA.
RB ´ RA
RX =
R B + RA
9.23077kW =
4.81kW =
44
10kW ´ 9.23077kW
10kW + 9.23077kW
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(15)
(16)
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9.2.1.3 Application Curve
5
Voltage (V)
2.5
0
-2.5
Vin
Vin Bias
Vout
-5
0
0.0003
0.0006
0.0009
Time (s)
0.0012
0.0015
Figure 80. Voltage (V) vs Time (s)
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9.2.2 Typical Application: General-Purpose Input Scaling
Figure 81 is an example application that demonstrates the flexibility of the PGA for general-purpose input scaling.
VIN0 is a ±100-mV input that is ac-coupled into CH0. The PGA112 and PGA113 are powered from a 5-V supply
voltage, VS, and configured with the VREF pin connected to VS/2 (2.5 V). VCH0 is the ±100-mV input, level-shifted
and centered on VS/2 (2.5 V). A gain of 20 is applied to CH0, and because of the PGA113 configuration, the
output voltage at VOUT is ±2 V centered on VS/2 (2.5 V).
CH1 is set to G = 1; through a resistive divider and scalar network, we can read ±5 V or 0 V. This setting
provides bipolar to single-ended input scaling. Table 12 summarizes the scaling resistor values for RA, RX, and
RB for different ADC Ref voltages. VREF_ADC is the reference voltage used for the ADC connected to the PGA112
and PGA113 output. It is assumed the ADC input range is 0 V to VREF_ADC. The Table 12 section gives the
algorithm to compute resistor values for references not listed in Table 12. As a general guideline, RB should be
chosen such that the input on-channel current multiplied by RB is less than or equal to the input offset voltage.
This value ensures that the scaling network contributes no more error than the input offset voltage. Individual
applications may require other design trade-offs.
VCH0
VIN0
+2.6V
+100mV
+2.5V
0
+2.4V
CA
-100mV
VIN0
200mVPP
PGA112
PGA113
CH0
RA
+4.5V
+2.5V
AVDD
MUX
CH1
VOUT0
VS
(+5V)
DVDD
RI
+0.5V
VOUT
G = 20
VREF
VOUT1
RF
VREF_ADC
RX
VS/2
(+2.5V)
+4.9625V
+
+37.5mV
G=1
RA
VIN1
RB
Figure 81. General-Purpose Input Scaling
10 Power Supply Recommendations
Power-supply bypass: Bypass each power-supply pin separately. Use a ceramic capacitor connected directly
from the power-supply pin to the ground pin of the IC on the same PCB plane. Vias can then be used to connect
to ground and voltage planes. This configuration keeps parasitic inductive paths out of the local bypass for the
PGA. Good analog design practice dictates the use of a large value tantalum bypass capacitor on the PCB for
each respective voltage.
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11 Layout
11.1 Layout Guidelines
11.1.1 High Gain and Wide Bandwidth Considerations
As a result of the combination of wide bandwidth and high gain capability of the PGA112 and PGA113 devices
and PGA116 and PGA117 devices, there are several printed-circuit-board (PCB) design and system
recommendations to consider for optimum application performance.
1. Power-supply bypass: Refer to Power Supply Recommendations.
2. Signal trace routing: Keep VOUT and other low impedance traces away from MUX channel inputs that are
high impedance. Poor signal routing can cause positive feedback, unwanted oscillations, or excessive
overshoot and ringing on step-changing signals. If the input signals are particularly noisy, separate MUX
input channels with guard traces on either side of the signal traces. Connect the guard traces to ground near
the PGA and at the signal entry point into the PCB. On multilayer PCBs, ensure that there are no parallel
traces near MUX input traces on adjacent layers; capacitive coupling from other layers can be a problem.
Use ground planes to isolate MUX input signal traces from signal traces on other layers.
Additionally, group and route the digital signals into the PGA as far away as possible from the analog MUX
input signals. Most digital signals are fast rise and fall time signals with low-impedance drive capability that
can easily couple into the high-impedance inputs of the input MUX channels. This coupling can create
unwanted noise that gains up to VOUT.
3. Input MUX channels and source impedance: Input MUX channels are high-impedance; when combined
with high gain, the channels can pick up unwanted noise. Keep the input signal sources low-impedance
(< 10 kΩ). Also, consider bypassing input MUX channels with a ceramic bypass capacitor directly at the MUX
input pin. Bypass capacitors greater than 100 pF are recommended. Lower impedances and a bypass
capacitor placed directly at the input MUX channels keep crosstalk between channels to a minimum as a
result of parasitic capacitive coupling from adjacent PCB traces and pin-to-pin capacitance.
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11.2 Layout Example
AVDD
DVDD
C1
C2
R1
CH1
VCAL/CH0
R2
R3
AVDD
DVDD
CH1
/CS
/CS
VCAL/CH0
DIO
DIO
VREF
SCLK
SCLK
R4
VOUT
VOUT
GND
PGA112/PGA113
DVDD
AVDD
C1
C2
R1
R2
R3
R4
AVDD
CH6
CH5
CH5
DVDD
CH4
CH4
/CS
CH3
CH3
DOUT
CH2
CH2
DIN
CH1
CH1
SCLK
VCAL/CH0
GND
VREF
ENABLE
VOUT
VOUT
CH9
CH9
CH7
CH7
CH8
CH8
VCAL/CH0
CH6
/CS
DOUT
DIN
SCLK
ENABLE
R5
PGA116/PGA117
Figure 82. PGA11x Layout Example
48
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Shelf-Life Evaluation of Lead-Free Component Finishes, SZZA046.
• PGA112/113EVM Users Guide, SBOU073.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 13. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PGA112
Click here
Click here
Click here
Click here
Click here
PGA113
Click here
Click here
Click here
Click here
Click here
PGA116
Click here
Click here
Click here
Click here
Click here
PGA117
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
PGA112AIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
P112
PGA112AIDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
P112
PGA112AIDGSTG4
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
P112
PGA113AIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
P113
PGA113AIDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
P113
PGA113AIDGSTG4
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
P113
PGA116AIPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA116
PGA116AIPWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA116
PGA116AIPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA116
PGA117AIPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA117
PGA117AIPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA117
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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