PGA207UA/1K

® PG PGA206 PGA207 A20 PG 6 A2 07 High-Speed Programmable Gain INSTRUMENTATION AMPLIFIER FEATURES DESCRIPTION ● DIGITALLY PROGRAMMABLE GAINS: PGA206: G=1, 2, 4, 8V/V PGA207: G=1, 2, 5, 10V/V The PGA206 and PGA207 are digitally programmable gain instrumentation amplifiers that are ideally suited for data acquisition systems. ● TRUE INSTRUMENTATION AMP INPUT The PGA206 and PGA207’s fast settling time allows multiplexed input channels for excellent system efficiency. FET inputs eliminate IB errors due to analog multiplexer series resistance. ● FAST SETTLING: 3.5µs to 0.01% ● FET INPUT: IB = 100pA max ● INPUT PROTECTION: ±40V Gains are selected by two CMOS/TTL-compatible address lines. Analog inputs are internally protected for overloads up to ±40V, even with the power supplies off. The PGA206 and PGA207 are laser-trimmed for low offset voltage and low drift. ● LOW OFFSET VOLTAGE: 1.5mV max ● 16-PIN DIP, SOL-16 SOIC PACKAGES APPLICATIONS The PGA206 and PGA207 are available in 16-pin plastic DIP and SOL-16 surface-mount packages. Both are specified for –40°C to +85°C operation. ● MULTIPLE-CHANNEL DATA ACQUISITION ● MEDICAL, PHYSIOLOGICAL AMPLIFIER ● PC-CONTROLLED ANALOG INPUT BOARDS VO1 1 – VIN 4 V+ 13 PGA206 PGA207 Over-Voltage Protection A1 10kΩ A1 A0 Digital Ground + VIN 10kΩ Feedback 12 16 Digitally Selected Feedback Network 15 A3 11 VO 14 5 A2 Over-Voltage Protection 10kΩ 7 6 VOS Adj 9 VO2 10kΩ 10 Ref 8 V– International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © SBOS033 1994 Burr-Brown Corporation PDS-1241B Printed in U.S.A. May, 1995 SPECIFICATIONS At TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise noted. PGA206P, U PGA207P, U PARAMETER CONDITIONS MIN TYP INPUT Offset Voltage, RTI All Gains Initial TA = +25°C vs Temperature TA = TMIN to TMAX, G = 8, 10 vs Power Supply VS = ±4.5V to ±18V Long-Term Stability Impedance, Differential Common-Mode Common-Mode Voltage Range(1) VO = 0V ±(|VS|–4) Safe Input Voltage Common-Mode Rejection VCM = ±11V, ∆RS = 1kΩ G=1 80 G=2 85 G = 4 or 5 90 G = 8 or 10 95 INPUT BIAS CURRENT vs Temperature Offset Current vs Temperature VIN = 0 NOISE VOLTAGE, RTI f = 10Hz f = 100Hz f = 1kHz fB = 0.1Hz to 10Hz Noise Current f = 1kHz G = 8,10; RS = 0Ω GAIN Gain Error Gain vs Temperature(2) Nonlinearity All Gains, VO = ±11V OUTPUT Voltage, Positive Negative Load Capacitance Stability Short-Circuit Current FREQUENCY RESPONSE Bandwidth, –3dB Slew Rate Settling Time, 0.1% 0.01% Output Overload Recovery ±0.5 ±2 ±5 4.5 1013 || 1 1012 || 4 ±(|VS| –2.5) MIN ±1.5 ±20 ✻ ±1 ✻ ±10 ✻ ✻ ✻ ✻ ±2.5 mV µV/°C µV/V µV/mo Ω || pF Ω || pF V V ±40 75 80 84 84 86 90 94 94 ✻ ✻ ✻ ✻ 100 100 dB dB dB dB ✻ pA ✻ pA ✻ ✻ ✻ ✻ nV/√Hz nV/√Hz nV/√Hz µVp-p 1.5 ✻ fA/√Hz ±0.05 ±10 ±0.002 ✻ ✻ ✻ ✻ ✻ (V+) –2.3 (V–) +1.5 1000 ±17 V– V– (V+) –4 VDG + 0.8V ✻ ✻ V+ ✻ –40 –40 ±18 ±13.5 ✻ +85 +125 ✻ ✻ 80 % ppm/°C % of FSR ✻ ✻ ✻ ✻ V V pF mA ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ MHz MHz MHz kHz V/µs µs µs µs ✻ ✻ ✻ ✻ 500 ±15 +12.4/–11.2 ±0.1 ✻ ±0.005 ✻ 1 VDG+2 TEMPERATURE RANGE Specification Operating Thermal Resistance, θJA UNITS ✻ 5 4 1.3 600 25 2 3.5 1.5 ±4.5 MAX 30 20 18 1 ±0.01 ±1 ±0.0003 VIN = 0V TYP ±40 92 96 100 100 G=1 G=2 G = 4, 5 G = 8, 10 VO = ±10V, G = 1 to 10 20V Step, All Gains 20V Step, All Gains 50% Overdrive POWER SUPPLY Voltage Range Current MAX 2 See Typical Curve 1 See Typical Curve (V+) –4 (V–) +4 DIGITAL LOGIC INPUTS Digital Ground Voltage, VDG Digital Low Voltage Digital Input Current Digital High Voltage Gain Switching Time PGA206PA, UA PGA207PA, UA ✻ ✻ ✻ V V pA V ns ✻ V mA ✻ ✻ °C °C °C/W ✻ Specification same as PGA206P or PGA207P. NOTES: (1) Input common-mode range varies with output voltage—see typical curves. (2) Guaranteed by wafer test. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PGA206/207 2 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Top View Supply Voltage .................................................................................. ±18V Analog Input Voltage Range ............................................................. ±40V Logic Input Voltage Range .................................................................. ±VS Output Short-Circuit (to ground) .............................................. Continuous Operating Temperature ................................................. –40°C to +125°C Storage Temperature ..................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering –10s) .............................................. +300°C DIP SOL-16 VO1 1 16 A1 NC 2 15 A0 NC 3 14 Dig. Ground – VIN 4 13 V+ + VIN 5 12 Sense VOS Adjust 6 11 VO VOS Adjust 7 10 Ref V– 8 9 ORDERING INFORMATION PRODUCT VO2 NC: No Internal Connection GAINS PACKAGE TEMPERATURE RANGE PGA206PA PGA206P PGA206UA PGA206U 1, 1, 1, 1, 2, 2, 2, 2, 4, 4, 4, 4, 8V/V 8V/V 8V/V 8V/V 16-Pin Plastic DIP 16-Pin Plastic DIP SOL-16 Surface-Mount SOL-16 Surface-Mount –40°C –40°C –40°C –40°C to to to to +85°C +85°C +85°C +85°C PGA207PA PGA207P PGA207UA PGA207U 1, 1, 1, 1, 2, 2, 2, 2, 5, 5, 5, 5, 10V/V 16-Pin Plastic DIP 10V/V 16-Pin Plastic DIP 10V/V SOL-16 Surface-Mount 10V/V SOL-16 Surface-Mount –40°C –40°C –40°C –40°C to to to to +85°C +85°C +85°C +85°C PACKAGE INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) PGA206PA PGA206P PGA206UA PGA206U 16-Pin Plastic 16-Pin Plastic SOL-16 Surface SOL-16 Surface DIP DIP Mount Mount 180 180 211 211 PGA207PA PGA207P PGA207UA PGA207U 16-Pin Plastic 16-Pin Plastic SOL-16 Surface SOL-16 Surface DIP DIP Mount Mount 180 180 211 211 ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 PGA206/207 TYPICAL PERFORMANCE CURVES At TA = +25°C, and VS = ±15V, unless otherwise noted. GAIN vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY 30 120 G=5 Gain (dB) G=8 10 G = 10V/V Common-Mode Rejection (dB) G = 10 20 G=4 G=2 0 G=1 –10 100 80 40 20 –20 10k 100k 1M 1k 10M 10k 10M POWER SUPPLY REJECTION vs FREQUENCY INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE Common-Mode Voltage (V) G = 10V/V 100 80 60 G = 1V/V 40 +PSR –PSR 10 100 1k 10k 100k 1M 10M Limit + Ou ed by A tput Swin2 g y A1 ed b Limit ut Swing tp + Ou 10 – VD/2 5 + + 0 –5 –10 VO + – VD/2 VCM (Any Gain) A3 + Output Swing Limit A3 – Output Swing Limit Lim it – O ed by utpu A t Sw 2 ing –15 –15 0 –10 by A 1 g in ited Lim put Sw ut O – –5 0 5 10 15 Output Voltage (V) Frequency (Hz) INPUT VOLTAGE NOISE vs FREQUENCY INPUT BIAS CURRENT vs TEMPERATURE 1k 10n 1n Input Bias Current (A) Voltage Noise Density nV/√Hz 1M Frequency (Hz) 15 20 100k Frequency (Hz) 120 Power Supply Rejection (dB) G = 1V/V 60 100 G=1 100p IB 10p 1p IOS 100f G = 10 10 10f 1 10 100 1k 10k 100k –75 Frequency (Hz) –25 0 25 50 Temperature (°C) ® PGA206/207 –50 4 75 100 125 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. OFFSET VOLTAGE WARM-UP TIME INPUT OVER-VOLTAGE V/I CHARACTERISTIC 100 6 +15V Input Current (mA) Offset Voltage Change (µV) I 4 V 2 –15V 0 –2 Input current increases when the applied voltage exceeds the power supply voltage. This V/I characteristic does not vary with the voltage applied to the other input. –4 50 0 –50 –100 –6 –40 –30 –20 –10 0 10 20 30 0 40 2 3 Time After Turn-On (minutes) OFFSET VOLTAGE TEMPERATURE DRIFT PRODUCTION DISTRIBUTION QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE 4 14 Typical production distribution of packaged units. G = 8, 10V/V 30 25 20 15 10 Quiescent Current (mA) 35 Units (%) 1 Input Voltage (V) 13 +IQ –55°C +25°C 12 –IQ +125°C –55°C +25°C +125°C 11 10 5 9 0 –10 –8 –6 –4 –2 0 2 4 6 8 0 10 ±5 ±10 ±15 ±20 Offset Voltage Drift (µV/°C) Power Supply Voltage (V) MAXIMUM OUTPUT VOLTAGE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VO = 6Vrms RL = 2kΩ G = 10V/V G=1 30 20 THD + N (%) Maximum Output Voltage (Vp-p) 0.1 G = 2V/V 10 Maximum output voltage without slew-rate limiting or other large-signal distortion. Dotted region is beyond small signal bandwidth. 1 100k G = 1V/V RL = 2kΩ RL = ∞ 0.01 G = 10V/V G = 1V/V 0.001 1M 10 10M 100 1k 10k 100k Frequency (Hz) Frequency (Hz) ® 5 PGA206/207 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. SMALL SIGNAL RESPONSE G = 10, CL = 50pF SMALL SIGNAL RESPONSE G = 1, CL = 50pF 100mV/div 100mV/div 1µs/div 1µs/div LARGE SIGNAL RESPONSE G = 1, CL = 50pF LARGE SIGNAL RESPONSE G = 10, CL = 50pF 5V/div 5V/div 1µs/div 1µs/div ® PGA206/207 6 +15V 1µF VO1 1 – 4 VIN 13 PGA206 PGA207 Over-Voltage Protection Sense A1 10kΩ 12 10kΩ 16 Digitally Selected Feedback Network 15 A3 11 VO 14 + – – VIN ) VO = G (VIN + 5 VIN Digital Ground GAIN PGA206 PGA207 1 2 4 8 1 2 5 10 Ref A2 Over-Voltage Protection 10kΩ 6 7 VOS Adj 9 8 Sometimes shown in simplified form: 1µF VO2 – VIN A 1 A0 0 0 1 1 10 10kΩ 0 1 0 1 –15V PGA206 + VIN VO A1 A0 FIGURE 1. Basic Connections. APPLICATIONS INFORMATION The digital inputs, A0 and A1, are not latched. A change in logic input immediately selects a new gain. Switching time of the logic is approximately 500ns. The time to respond to gain change is equal to switching time, plus the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to acquire gain control data from a high speed digital bus. Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the digital latch as far as practical from analog circuitry to avoid coupling digital noise into analog input circuitry. Figure 1 shows the circuit diagram for basic operation of the PGA206 or PGA207. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of 2Ω in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G = 1). The output sense connection (pin 12) must be connected to the output terminal (pin 11) for proper operation. This connection can be made at the load for best accuracy. OFFSET VOLTAGE ADJUSTMENT The PGA206 and PGA207 are laser trimmed for very low offset voltage and drift. Many applications require no external offset adjustment. Multiplexed data acquisition systems generally correct offset by grounding the inputs of one channel to measure offset voltage. Stored offset values for each gain are then subtracted from subsequent readings of other channels. Figure 2 shows optional offset voltage trim circuits. Offset voltage changes with the selected gain. To adjust for low offset voltage in all gains, both input and output offsets must be trimmed. DIGITAL INPUTS The digital inputs A0 and A1 select the gain according to the logic table in Figure 1. Logic “1” is defined as a voltage greater than 2V above digital ground potential (pin 14). Digital ground can be connected to any potential ranging from the V– power supply to 4V less than V+. Digital ground is usually equal to analog ground potential and the two grounds are connected at the power supply. The digital inputs interface directly to CMOS and TTL logic. A nearly constant current of approximately 1.2mA flows in the digital ground pin. It is good practice to return digital ground through a separate connection path so that analog ground is not affected by the digital ground current. ® 7 PGA206/207 VO1 1 – VIN 4 13 PGA206 PGA207 Over-Voltage Protection A1 10kΩ A1 A0 Digital Ground V+ Manual output offset trim circuit. V+ Resistors can be substituted for REF200. Power supply 100µA rejection will be degraded. 1/2 REF200 V+ 10kΩ 100Ω 12 R2 10kΩ 100Ω 16 Digitally Selected Feedback Network 15 A3 VO 11 100µA 1/2 REF200 14 5 IN VREF A2 Over-Voltage Protection 10kΩ 7 6 10kΩ 9 VO2 V– 10 Offset control with digital/analog converter OPA131 8 V– D/A Optional Input Offset Adjustment R1 200kΩ (100kΩ to 500kΩ) V+ FIGURE 2. Optional Offset Voltage Trim Circuits. R1 adjusts the offset of the input amplifiers. Output stage offset is adjusted with R2. A buffer op amp is required in the output offset adjustment circuit, as shown, to assure that the Ref pin is driven by a low source impedance. To adjust for low offset voltage in all gains, first adjust the input stage offset in the highest gain. Then adjust the output stage offset (R2) in G = 1. Iterate the adjustments for lowest offset in all gains. Microphone, Hydrophone etc. Offset can also be adjusted under processor control with a D/A converter as shown in Figure 2. The D/A’s output voltage can be reduced with a resistor divider for better adjustment resolution, but an op amp buffer following the divider is required to provide a low source impedance to the ref terminal. A different offset value is required for each amplifier gain. Thermocouple PGA 47kΩ 47kΩ PGA 10kΩ INPUT BIAS CURRENT RETURN PATH The FET inputs of the PGA206 and PGA207 provide extremely high input impedance. Still, a path must be provided for the bias current of each input. Figure 3 shows provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the linear input voltage range and the input amplifiers will saturate. If the differential source resistance is low, a bias current return path can be connected to only one input (see thermocouple example in Figure 3). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better common-mode rejection. Many sources or sensors inherently provide a path for input bias current (e.g. the bridge sensor shown in Figure 3). These applications do not require additional resistor(s) for proper operation. PGA VR Bridge PGA Bias current return inherrently provided by source. FIGURE 3. Providing an Input Bias Current Path. ® PGA206/207 Center-tap provides bias current return. 8 +15V 14 Input Filter See Text – VIN Channel 1 + VIN 1kΩ 1kΩ 2 HI-509 1nF 4 5 10nF 8 6 7 1nF PGA207 13 A/D Converter ADS7807 12 9 11 10 15 Channel 4 Software-Zero 3 1 16 –15V 74HC574 CK To Address Logic Data Bus FIGURE 4. Multiplexed-Input Signal Acquisition System. INPUT COMMON-MODE RANGE The linear input voltage range of the PGA206 and PGA207 is from approximately 2.3V below the positive supply voltage to 1.5V above the negative supply. As a differential input voltage causes output voltage to increase, however, the linear input range is limited by the output voltage swing of amplifiers A1 and A2. So the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage— see performance curves “Input Common-Mode Range vs Output Voltage”. Input overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier will be near zero. The output of the PGA206 or PGA207 will be near 0V even though both inputs are overloaded. This condition can be detected by sensing the voltage on the V01 and V02 pins to determine whether they are within their linear operating range. MULTIPLEXED INPUTS The PGA206 and PGA207 are ideally suited for multiple channel data acquisition. Figure 4 shows a typical application with an analog multiplexer used to connect one of four differential input signals to a single PGA207. Careful circuit layout will help preserve accuracy of multiplexed signals. Run the inverting and non-inverting connections of each channel parallel to each other over a ground plane, or directly adjacent on top and bottom of the circuit board. Grounded guard traces between channels help reduce stray signal pick-up. Multiplexed signals from high impedance sources require special care. As inputs are switched by the multiplexer, charge can be injected into the source, disturbing the input signal. Since many such sources involve slow signals, a simple R/C filter at the input can be used to dramatically reduce this effect. The arrangement shown filters both the differential signal and common-mode noise. INPUT PROTECTION The inputs of the PGA206 and PGA207 are individually protected for voltages up to ±40V. For example, a condition of -40V on one input and +40V on the other input will not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is overloaded, the protection circuitry limits the input current to a safe value. The typical performance curve “Input Overload V/I Characteristic” shows this behavior. The inputs are protected even if no power supply voltage is applied. ® 9 PGA206/207 VO1 – VIN PGA207 + VIN VO Ref VO2 A1 A0 220Ω OPA131 20kΩ 20kΩ Equal to input common-mode voltage. FIGURE 5. Shield Drive Circuit. G = 1, 2, 5, 10 G = 1, 10, 100 – VIN PGA207 + VIN 4 PGA103 7 VO 3 2 A1 A0 1 A 3 A2 FIGURE 6. Wide Gain Range Programmable IA. ® PGA206/207 10 GAIN (V/V) A1 A0 A3 A2 1 2 5 10 20 50 100 200 500 1000 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PGA206PA ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 PGA206PA PGA206UA ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA206UA PGA206UAG4 ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA206UA PGA207UA ACTIVE SOIC DW 16 40 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA207UA PGA207UA/1K ACTIVE SOIC DW 16 1000 RoHS & Green NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA207UA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of