PGA281
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SBOS664A – MARCH 2013 – REVISED JUNE 2013
Precision, Zero-Drift, High-Voltage,
Programmable Gain Instrumentation Amplifier
Check for Samples: PGA281
FEATURES
DESCRIPTION
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The PGA281 is a high-precision instrumentation
amplifier with a digitally-controllable gain and signalintegrity test capability. This device uses proprietary
autozeroing techniques to offer low offset voltage,
near-zero offset and gain drift, excellent linearity, and
nearly no 1/f noise.
1
234
Wide Input Range: ±15.5 V at ±18 V Supply
Binary Gain Steps: 128 V/V to ⅛ V/V
Additional Scaling Factor: 1 V/V and 1⅜ V/V
Low Offset Voltage: 5 μV at G = 128
Near-Zero Long-Term Drift of Offset Voltage
Near-Zero Gain Drift: 0.5 ppm/°C
Excellent Linearity: 1.5 ppm
Excellent CMRR: 140 dB
High Input Impedance
Very Low 1/f Noise
Differential Signal Output
Overload Detection
TSSOP-16 Package
APPLICATIONS
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High-Precision Signal Instrumentation
Multiplexed Data Acquisition
Medical Instrumentation
Test and Measurement Equipment
Differential or Single-Ended ADC Drivers
Strain Gauge Amplifiers
Industrial Process Control
The PGA281 is optimized to provide an excellent
common-mode rejection of greater than 110 dB (G =
1) over a wide frequency range. Superior commonmode and supply rejection supports high-resolution,
precise measurement. The 36-V supply capability and
wide, high-impedance input range comply with
requirements for universal signal measurement.
The PGA281 offers multiple internal gain options from
⅛ V/V (attenuation) to 176 V/V, making this a
universal,
high-performance,
analog
front-end
suitable for a wide variety of applications. The fully
differential, rail-to-rail output is designed to easily
interface a wide range of input signals to the lowvoltage domain of high-resolution analog-to-digital
converters (ADCs).
The PGA281 is available in a TSSOP-16 package
and is specified over a temperature range of –40°C to
+105°C.
RELATED PRODUCTS
PRODUCT
ADS1259
+15 V
VSP
+5 V
PGA281
IN-P
A1
Gain
A3
FEATURES
23-bit resolution, ΔΣ analog-to-digital converter
VSOP
INA333
Chopper-stabilized instrumentation amplifier,
RR I/O, 5-V single supply
VO-P
PGA204
High-precision PGA; G = 1, 10, 100, and 1000
PGA280
Zero-Drift, 36-V, PGA, SPI, GPIOs, input switch
matrix
VOCM
ADS1259
ADC
VO-N
A2
VSON
IN-N
15 V
VSN
G0 G1 G2 G3 G4
3V
DVDD
EF
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TINA-TI is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
PGA281
SBOS664A – MARCH 2013 – REVISED JUNE 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION (1)
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage
VALUE
UNIT
VSN to VSP
40
V
VSON to VSOP, and VSON to DVDD
6
V
Signal input terminals, voltage
(2)
Signal input terminals, current (2)
VSN – 0.5 to VSP + 0.5
V
±10
mA
Output short-circuit (3)
Continuous
Operating temperature
–55 to +140
°C
Storage temperature
–65 to +150
°C
Junction temperature
+150
°C
Electrostatic
discharge (ESD)
ratings
2000
V
(1)
(2)
(3)
Human body model (HBM)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Terminals are diode-clamped to the power-supply (VON and VOP) rails. Signals that can swing more than 0.5 V beyond the supply rails
must be current-limited.
Short-circuit to VSON or VSOP, respectively, VSON or DVDD.
THERMAL INFORMATION
PGA281
THERMAL METRIC
(1)
PW (TSSOP)
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance
92.6
θJCtop
Junction-to-case (top) thermal resistance
23.7
θJB
Junction-to-board thermal resistance
37.9
ψJT
Junction-to-top characterization parameter
1.0
ψJB
Junction-to-board characterization parameter
37.3
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP / 2 = VOCM,
G = 1 V/V, VCM = 0 V, and differential output, unless otherwise noted.
PGA281
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All gains
±(5 + 45/G)
±(20 + 235/G)
All gains
±(0.03 +
0.18/G)
±(0.17 +
0.45/G)
μV/°C
±0.3
±3
μV/V
INPUT
Offset voltage, RTI (1)
VOS
(2)
dVOS/dT
vs temperature
PSR
vs power supply, RTI
Long-term stability
CMR
VSP – VSN = 10 V and 36 V,
gain = 1 V/V, 128 V/V
(3)
μV
Gain = 128 V/V
3.5
nV/month
Input impedance
Single-ended (SE) and differential
>1
GΩ
Input capacitance
SE
12
Input voltage range
TA = –40°C to +105°C
Common-mode rejection, RTI
SINGLE-ENDED OUTPUT CONNECTION
VOS
Offset voltage, RTI, SE
dVOS/dT
vs temperature, SE
(VSN) + 2.5
pF
(VSP) – 2.5
V
Gain = 1 V/V, TA = –40°C to +105°C
110
130
dB
Gain = 128 V/V
121
142
dB
Gain = 128 V/V, TA = –40°C to +105°C
116
140
dB
±120
μV
±3
μV
Gain = 1 V/V, TA = –40°C to +105°C
0.6
μV/°C
Gain = 64 V/V, TA = –40°C to +105°C
0.05
μV/°C
Gain = 1 V/V
±0.3
±1
nA
Gain = 128 V/V
±0.8
±2
nA
Gain = 1 V/V, gain = 128 V/V,
TA = –40°C to +105°C
±0.6
±2
nA
Gain = 1 V/V, gain = 128 V/V
±0.1
±0.5
nA
Gain = 1 V/V, gain = 128 V/V,
TA = –40°C to +105°C
±0.9
±2
nA
f = 0.01 Hz to 10 Hz, gain = 128 V/V
420
nVPP
22
nV/√Hz
(4)
Gain = 1 V/V, 1.375 V/V
Gain = 64 V/V
INPUT BIAS CURRENT (5)
IB
Bias current
IOS
Offset current
NOISE
eNI
IN
(1)
(2)
(3)
(4)
(5)
Voltage noise, RTI; target
Current noise, RTI
f = 1 kHz, gain = 128 V/V
f = 0.01 Hz to 10 Hz, gain = 1 V/V
4.5
μVPP
f = 1 kHz, gain = 1 V/V
240
nV/√Hz
f = 0.01 Hz to 10 Hz, gain = 128 V/V
1.7
pAPP
f = 1 kHz, gain = 128 V/V
90
fA/√Hz
RTI: Referred to input.
Specified by design; not production tested.
300-hour life test at +150°C demonstrated randomly distributed variation in the range of measurement limits.
For single-ended (SE) output mode, see Application Information section and Typical Characteristic graphs; signal between VOP and
VOCM.
See Application Information section and Typical Characteristic graphs.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP / 2 = VOCM,
G = 1 V/V, VCM = 0 V, and differential output, unless otherwise noted.
PGA281
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
128
V/V
GAIN (Output Swing = ±4.5 V (6))
⅛
Range of input gain
Output gain
1 or 1⅜
All gains
TA = –40°C to +105°C, no load, all gains
except gain = 128 V/V (7) (8)
Gain error, all binary steps
TA = –40°C to +105°C, no load, gain = 128
V/V (7) (8)
Gain step matching
gain)
(9)
(gain to
No load, all gains
No load, all gains
Nonlinearity
V/V
±0.03%
±0.15%
-0.5
±2
ppm/°C
-1
±3
ppm/°C
10
ppm
See Typical Characteristics
(10)
1.5
No load, all gains, TA = –40°C to +105°C (7)
3
ppm
OUTPUT
Voltage output swing from rail
(9)
VSOP = 5 V, load current 2 mA
TA = –40°C to +105°C
40
VSOP = 2.7 V, load current 1.5 mA
TA = –40°C to +105°C
Capacitive load drive
ISC
100
mV
100
mV
25
mA
500
Short-circuit current
To VSOP / 2, gain = 1.375 V/V
Output resistance
Both VOP and VON outputs
Voltage range for VOCM
VSP – 2 V > VOCM, TA = –40°C to +105°C
7
15
pF
200
mΩ
VOCM
IB(VOCM)
(VSON) + 0.1
(VSOP) – 0.1
V
100
nA
Bias current into VOCM
3
VOCM input resistance
1
GΩ
Gain > 4 V/V
6
MHz
Gain = 1 V/V, 4-VPP output step, CL = 100 pF
1
V/μs
Gain = 8 V/V, 4-VPP output step, CL = 100 pF
2
V/μs
Gain = 128 V/V, 4-VPP output step, CL = 100
pF
1
V/μs
To 0.01%, gain = 8 V/V, VO = 8-VPP step
20
μs
To 0.001%, gain = 8 V/V, VO = 8-VPP step
30
μs
To 0.01%, gain = 128 V/V, VO = 8-VPP step
30
μs
To 0.001%, gain = 128 V/V, VO = 8-VPP step
40
μs
Overload recovery, input (9)
0.5 V over supply, gain = ⅛ V/V to 128 V/V
8
μs
Overload recovery, output (9)
±5.5-VPP input, gain = 1 V/V
6
μs
FREQUENCY RESPONSE
GBP
SR
tS
(6)
(7)
(8)
(9)
(10)
4
Gain bandwidth product (9)
Slew rate
(9)
Settling time (9)
Gains smaller than ½ are measured with smaller output swing.
Specified by design; not production tested.
See Figure 10 for typical gain error drift of various gain settings.
See Application Information section and Typical Characteristic graphs.
Only gain = 1 is production tested.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP / 2 = VOCM,
G = 1 V/V, VCM = 0 V, and differential output, unless otherwise noted.
PGA281
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL I/O (Supply = 2.7 V to 5.5 V)
G4:G0 pin input
Logic low threshold
Logic high threshold
0.1
0.2(DVDD)
0.8(DVDD)
DVDD
G4:G0 pin input current
Error flag (EF pin) output
Error flag (EF pin) delay
Logic high, alarm
V
μA
0.2
Logic low, disable
V
0.7
DVDD – 0.5
V
V
Alarm → disable (recovery)
5
μs
Disable → alarm (response)
30
μs
POWER SUPPLY: Input Stage (VSP – VSN)
Specified voltage range
TA = –40°C to +105°C
Operating voltage range
10 (±5)
36 (±18)
10 (±5)
38 (±19)
V
V
IQ(VSP)
Quiescent current , VSP pin
TA = –40°C to +105°C
2.4
3
mA
IQ(VSN)
Quiescent current, VSN pin
TA = –40°C to +105°C
2.1
3
mA
POWER SUPPLY: Output Stage (VSOP – VSON)
IQ(VSOP)
Specified voltage range
VSP – 1.5 V ≥ VSOP, TA = –40°C to +105°C
Voltage range for VSOP, upper
limit
(VSP – 2 V) > VOCM, (VSP – 5 V) > VSON
Voltage range for VSON
(VSP – 2 V) > VOCM, VSP ≥ VSOP
Quiescent current, VSOP pin
TA = –40°C to +105°C
2.7
5.5
(VSP)
(VSN)
V
(VSP) – 5
0.75
V
1
V
mA
POWER SUPPLY: Digital (DVDD – VSON)
Specified voltage range
IQ(DVDD)
TA = –40°C to +105°C
2.7
5.5
V
Voltage range for DVDD, upper
limit
(VSP) – 1
V
Voltage range for VSON, lower
limit
(VSN)
V
Quiescent current (11)
Static condition, no external load, DVDD = 3 V,
TA = –40°C to +105°C
0.07
0.13
mA
TEMPERATURE
Specified range
–40
+105
°C
Operating range
–55
+140
°C
(11) See Application Information section and Typical Characteristic graphs.
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PIN CONFIGURATION
TSSOP-16
PW PACKAGE
(TOP VIEW)
DVDD
1
16
VSN
EF
2
15
INN
G4
3
14
INP
G3
4
13
VSP
PGA281
G2
5
12
VSON
G1
6
11
VSOP
G0
7
10
VOCM
VON
8
9
VOP
PIN DESCRIPTIONS
PIN
PIN
NAME
NUMBER
DVDD
1
EF
DESCRIPTION
NAME
NUMBER
Digital supply
INN
15
Signal input, inverting
DESCRIPTION
2
Error flag (output)
INP
14
Signal input, noninverting
VSON
12
Negative output-stage low-voltage
supply and negative digital supply
VOCM
10
Signal input, output common-mode
voltage
G0
7
Gain option 1 (see Table 1)
VON
8
Inverting signal output
G1
6
Gain option 2 (see Table 1)
VOP
9
Noninverting signal output
G2
5
Gain option 3 (see Table 1)
VSOP
11
Positive output-stage low-voltage supply
G3
4
Gain option 4 (see Table 1)
VSN
16
Negative high-voltage supply
G4
3
Gain option 5 (see Table 1)
VSP
13
Positive high-voltage supply
Table 1. Gain Control
G3:G0
G4 = 0
G4 = 1
0000
0.125
0.172
0001
0.25
0.344
0010
0.5
0.688
0011
1
1.375
0100
2
2.75
0101
4
5.5
0110
8
11
0111
16
22
1000
32
44
1001
64
88
1010
128
176
1011
Reserved (1) (0.125)
Reserved (1) (0.172)
Reserved
(1)
(0.125)
Reserved (1) (0.172)
1101
Reserved
(1)
(0.125)
Reserved (1) (0.172)
1110
Reserved (1) (0.125)
Reserved (1) (0.172)
1100
1111
(1)
6
Reserved
(1)
(0.125)
Reserved (1) (0.172)
Reserved for test-modes. Default gain in parenthesis.
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TYPICAL CHARACTERISTICS
50
45
45
40
40
35
35
Population (%)
50
30
25
20
30
25
20
15
10
10
5
5
0
0
-300
-270
-240
-210
-180
-150
-120
-90
-60
-30
0
30
60
90
120
150
180
210
240
270
300
15
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Population (%)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP/2 = VOCM,
gain = 1 V/V, VCM = 0 V, and differential input and output, unless otherwise noted.
Offset Voltage (mV)
Offset Voltage (mV)
Figure 2. OFFSET VOLTAGE PRODUCTION DISTRIBUTION
(G = 1)
50
45
45
40
40
35
35
Population (%)
50
30
25
20
15
30
25
20
15
10
5
5
0
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
10
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.10
0.12
0.14
0.16
0.18
0.20
Population (%)
Figure 1. OFFSET VOLTAGE PRODUCTION DISTRIBUTION
(G = 128)
Offset Voltage Drift (mV/°C)
Offset Voltage Drift (mV/°C)
Figure 3. OFFSET VOLTAGE DRIFT DISTRIBUTION
(G = 128)
Figure 4. OFFSET VOLTAGE DRIFT DISTRIBUTION
(G = 1)
80
120
70
100
Population (%)
Population (%)
60
80
60
40
50
40
30
20
20
10
-3.0
-2.7
-2.4
-2.1
-1.8
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
-3.0
-2.7
-2.4
-2.1
-1.8
-1.5
-1.2
-0.9
-0.6
-0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
0
0
Common-Mode Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
Figure 5. COMMON-MODE REJECTION DISTRIBUTION
(G = 128)
Figure 6. COMMON-MODE REJECTION DISTRIBUTION
(G = 1)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP/2 = VOCM,
70
30
60
25
50
Population (%)
40
30
20
20
15
10
5
0
0
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
10
0.15
Gain Error (%)
Gain Error (%)
Figure 7. GAIN ERROR DISTRIBUTION
(G = 128)
Figure 8. GAIN ERROR DISTRIBUTION
(G = 1)
3
Gain Error Drift: Mean ±3s (ppm/°C)
Selected samples with typical performance
0.05
0
-0.05
-0.10
-0.15
2
1
0
-1
-2
64
128
Gain Setting (V/V)
64
32
128
16
32
8
8
4
16
2
2
13 8
4
1
1
1/2
1/8
1/4
13 8
-3
1/8
1/2
Gain Error (%)
0.10
1/4
Population (%)
gain = 1 V/V, VCM = 0 V, and differential input and output, unless otherwise noted.
Gain Setting (V/V)
Figure 10. GAIN ERROR DRIFT DISTRIBUTION vs
GAIN SETTING (Mean with ±3 σ)
0.20
0.15
0.15
64
128
32
8
16
64 to 128
32 to 64
16 to 32
8 to 16
4 to 8
2 to 4
1 to 2
-0.20
1 to 1 3 8
-0.20
1/2 to 1
-0.15
1/4 to 1/2
-0.15
2
-0.10
4
-0.10
-0.05
1
-0.05
0
13 8
0
0.05
1/2
0.05
0.10
1/8
0.10
1/4
Gain Error: Mean ±3s (%)
0.20
1/8 to 1/4
Gain Error: Mean ±3s (%)
Figure 9. GAIN ERROR vs GAIN SETTING
Gain Setting (V/V)
Gain Setting Change
Figure 11. MAXIMUM GAIN ERROR DEVIATION BETWEEN
SEQUENTIAL GAIN SETTINGS (Mean with ±3 σ)
8
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Figure 12. GAIN ERROR DISTRIBUTION vs
GAIN SETTING (MEAN with ±3σ)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP/2 = VOCM,
gain = 1 V/V, VCM = 0 V, and differential input and output, unless otherwise noted.
160
VSN
VSP
120
Common-Mode Rejection (dB)
Power-Supply Rejection Ratio (dB)
140
100
80
60
40
20
140
120
100
80
60
G = 1/8
40
G=1
20
G = 128
0
0
10
100
1k
10k
100k
1
10
100
Frequency (Hz)
1k
10k
100k
Frequency (Hz)
C014
Figure 13. POWER-SUPPLY REJECTION vs FREQUENCY
Figure 14. COMMON-MODE REJECTION vs FREQUENCY
100
60
50
40
G = 1/8
1
Gain (dB)
Noise (mV/ÖHz)
10
G=1
G=4
0.1
20
10
0
G = 128
-10
-20
0.01
0.1
1
10
100
1k
10k
10
100k
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 15. INPUT-REFERRED NOISE SPECTRUM
Figure 16. SMALL-SIGNAL GAIN vs FREQUENCY
2.0
3.0
1.8
2.5
2.0
Input Bias Current (nA)
Input Voltage Swing to Rail (V)
30
INP
(Voltage Range)
1.5
1.0
INP
(Voltage Range)
0.5
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
-50
-25
0
25
50
75
100
125
150
1
Temperature (°C)
2
4
8
16
32
64
128
Gain Setting (V/V)
Figure 17. INPUT VOLTAGE RANGE LIMITS vs
TEMPERATURE
Figure 18. BIAS CURRENT vs GAIN SETTING
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP/2 = VOCM,
gain = 1 V/V, VCM = 0 V, and differential input and output, unless otherwise noted.
80
90
70
80
70
Population (%)
Population (%)
60
50
40
30
20
60
50
40
30
20
0
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
10
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
10
Bias Current (nA)
Bias Current (nA)
Figure 19. INPUT BIAS CURRENT DISTRIBUTION
(G = 128)
Figure 20. INPUT BIAS CURRENT DISTRIBUTION
(G = 1)
10
70
8
6
IBIAS/IOS Current (nA)
Population (%)
60
50
40
30
20
IBIAS
4
2
0
-2
IOFFSET
IN1_IBIAS_1
IN1_IBIAS_128
IN1_IOFFSET_1
IN1_IOFFSET_128
-4
-6
10
-8
-10
0
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Input Offset Current (nA)
Figure 21. INPUT OFFSET CURRENT DISTRIBUTION
(G = 1, G = 128)
Figure 22. INPUT BIAS CURRENT AND INPUT OFFSET
CURRENT vs TEMPERATURE
3.0
90
2.5
85
Digital Supply Current (mA)
Quiescent Current (mA)
IDVDD
IQ VSP
2.0
1.5
IQ VSOP
1.0
0.5
0
75
70
65
60
-50
10
80
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 23. QUIESCENT CURRENT FROM SUPPLIES (VSP
AND VSOP) vs TEMPERATURE
Figure 24. DIGITAL SUPPLY CURRENT
vs TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP/2 = VOCM,
0
10
-1
9
-2
8
Nonlinearity (ppm)
Nonlinearity (ppm)
gain = 1 V/V, VCM = 0 V, and differential input and output, unless otherwise noted.
-3
-4
-5
-6
-7
7
6
5
4
3
2
-8
-9
1
Selected samples with typical performance
0
-10
-4
-3
-2
-1
0
1
2
-50
4
3
-25
0
25
Figure 25. GAIN NONLINEARITY WITH END-POINT
CALIBRATION (G = 1)
16
14
14
12
Population (%)
Population (%)
75
100
125
150
Figure 26. GAIN NONLINEARITY vs TEMPERATURE
12
10
8
6
10
8
6
4
4
2
0
0
8.0
8.8
9.6
10.4
11.2
12.0
12.8
13.6
14.4
15.2
16.0
16.8
17.6
18.4
19.2
20.0
20.8
21.6
22.4
23.2
24.0
8.0
8.8
9.6
10.4
11.2
12.0
12.8
13.6
14.4
15.2
16.0
16.8
17.6
18.4
19.2
20.0
20.8
21.6
22.4
23.2
24.0
2
Positive Current Limit (mA)
Negative Current Limit (mA)
Figure 27. POSITIVE OUTPUT CURRENT LIMIT
DISTRIBUTION
Figure 28. NEGATIVE OUTPUT CURRENT LIMIT
DISTRIBUTION
100
19
90
Output Swing to Rail (mV)
20
18
Current Limit (mA)
50
Temperature (°C)
Input/Output Voltage (V)
17
16
Negative
15
14
13
Positive
12
11
80
70
60
50
Positive Rail
40
30
Negative Rail
20
10
10
0
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
Figure 29. OUTPUT CURRENT LIMIT vs TEMPERATURE
Figure 30. OUTPUT SWING TO RAIL vs TEMPERATURE
(VSOP – VSON = 5 V)
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VSP = +15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = +3 V, RL = 2.5 kΩ to VSOP/2 = VOCM,
gain = 1 V/V, VCM = 0 V, and differential input and output, unless otherwise noted.
Diff Signal
Output
(Right Scale)
500 mV/div
2 V/div
5 V/div
INN
(Left Scale)
2 V/div
2 V/div
50 mV/div
Diff Signal
Output
(Right Scale)
Error Flag
INN Single-Ended
(INP to GND)
(Left Scale)
Error Flag
10 ms/div
10 ms/div
Figure 31. STEP RESPONSE (G = 128)
Figure 32. STEP RESPONSE (G = 8)
G = 1, VSOP (5 V)
Diff Signal Output
(Right Scale)
VON (1-V/div)
INN (5-V/div)
5 V/div
2 V/div
INN
(INP to GND)
(Left Scale)
VOP (1-V/div)
5 V/div
GND
Error Flag
Error Flag
10 ms/div
10 ms/div
Figure 34. OUTPUT OVERLOAD RECOVERY
180
160
160
140
140
120
120
EMIRR (dB)
EMIRR (dB)
Figure 33. STEP RESPONSE (G = 1)
100
80
60
80
60
40
40
20
20
0
10M
100
100M
1G
10G
Frequency (Hz)
0
10M
C035
Figure 35. COMMON MODE EMIRR
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100M
1G
Frequency (Hz)
10G
C036
Figure 36. DIFFERENTIAL MODE EMIRR
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APPLICATION INFORMATION
DESCRIPTION
The PGA281 is a universal high-voltage instrumentation amplifier with digital gain control. It offers excellent dc
precision and long-term stability using modern chopper technology with internal filters that minimize chopperrelated noise. The input gain extends from ⅛ V/V (attenuation) to 128 V/V in binary steps. The output stage
offers a gain multiplying factor of 1 V/V or 1⅜ V/V for optimal gain adjustment. The output stage connects to the
low-voltage (for example: 5 V or 3 V) supply. Figure 37 shows a block diagram of the PGA281.
VSP
DVDD
VSOP
IN-P
A1
G0
VO-P
G1
Gain
G2
A3
VOCM
G3
VO-N
G4
A2
IN-N
VSON
Error Detection
VSN
EF
Figure 37. Block Diagram
The supply voltage of up to ±18 V offers a wide common-mode range with high input impedance; therefore, large
common-mode noise signals and offsets can be suppressed.
The fully differential signal output is compatible with the inputs of modern high-resolution and high-accuracy
analog-to-digital converters (ADCs), including delta-sigma (ΔΣ) as well as successive-approximation register
(SAR) converters. The supply voltage for the output stage is normally connected to the converter supply, thus
preventing signal overloads from the high-voltage analog supply.
Internal error detection in the input and output stage monitors signal integrity and provides information about the
input signal condition on the EF pin output.
The gain is set using digital inputs G4:G0 (pins 3, 4, 5, 6, and 7). Select the desired gain according to the
settings in Table 1. Logic high and low levels are with respect to the voltage on DVDD (pin 1) and VSON (pin
12). The limits are specified in the Digital I/O section of the Electrical Characteristics.
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FUNCTIONAL BLOCKS
The PGA281 has two high-impedance input amplifiers (see Figure 37, A1 and A2) that are symmetrical and low
noise, with excellent dc precision. These amplifiers are connected to a resistor network and provide a gain range
from 128 V/V down to an attenuation of ⅛ V/V. The PGA281 architecture rejects common-mode offsets and
noise over a wide bandwidth.
The signal inputs are diode-clamped to the supply rails. To provide overvoltage protection, place external
resistors in series to the inputs. Limit current into the input pins to ≤ 10 mA.
The output stage (A3) provides a fully-differential symmetrical signal around the output reference pin, VOCM. The
VOCM pin is a high-impedance input and must be driven with an external voltage, typically close to midsupply.
The 3-V or 5-V supply of the converter or amplifier, following the PGA281 outputs, is normally connected to
VSOP and VSON; this configuration shares a common supply voltage and protects the circuit from overloads.
The fully-differential signal avoids coupling of noise and errors from the supply and ground, and allows large
signal swing without the risk of nonlinearities that arise when driving near the supply rails.
The PGA281 signal path has several internal nodes monitored for critical overload conditions. The input
amplifiers detect signal overvoltage and overload as a result of high gain. The output stage also detects clipping.
Input Amplifiers and Gain Network
The high-precision input amplifiers present very low dc error and drift as a result of a modern chopper technology
with an embedded synchronous filter that removes nearly all chopping noise. This topology reduces flicker (1/f)
noise to a minimum, and therefore enables the precise measurement of small dc-signals with high resolution,
accuracy, and repeatability. The chopping frequency of 250 kHz is derived from an internal 1-MHz clock.
The gain network for the binary gain steps connects to the input amplifiers, thus providing the best possible
signal-to-noise ratio (SNR) and dc accuracy up to the highest gains. Gain is digitally programmable by pins
G4:G0. The input stage provides selectable gains (in V/V): 128, 64, 32, 16, 8, 4, 2, 1, ½, ¼, and ⅛. The G4 pin
provides an additional gain multiplication factor on the output stage of 1 V/V or 1⅜ V/V. This allows for optimal
gain fine-tuning, and increases the maximum gain of the PGA281 to 176 V/V.
Programmable gain amplifiers such as the PGA281 use internal resistors to set the gain. Consequently,
quiescent current is increased by the current that passes through these resistors. The largest amplitude may
increase the supply current by ±0.4 mA. For example, in a maximum overload condition, with a gain of 128 V/V,
and with each of the inputs connected to the opposite supply voltage, a current of approximately 27 mA is
measured. External resistors in series with the input pins are normally present and help to avoid this extreme
condition. This current is only limited by the internal 600 Ω.
Digital Inputs
Digital inputs G0, G1, G2, G3, and G4, select the gain according to the settings shown in Table 1. Logic high and
low levels are with respect to the voltage on DVDD (pin 1) and VSON (pin 12). The logic limits are specified in
the Digital I/O section of the Electrical Characteristics. Approximately 0.2 µA flows out of the digital input pins
when a logic '0' is applied. Logic input current is nearly zero with a logic '1' input.
Digital inputs G4:G0 are not latched; a change in logic inputs immediately selects a new gain. Switching time of
the logic is approximately 1 µs. The time to respond to gain change is effectively the time it takes the amplifier to
settle to a new output voltage in the newly selected gain (see the settling times specified in the Frequency
Response section of the Electrical Characteristics). Many applications use an external logic latch to access gain
control data from a high-speed data bus. Using an external latch isolates the high-speed digital bus from
sensitive analog circuitry. Place the latch circuitry as far as practical from analog circuitry.
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Output Stage
The output stage power supply is usually connected to the low-voltage supply (normally 3 V or 5 V) that is used
by the subsequent signal path of the system. This design prevents overloading of the low-voltage signal path.
The output signal is fully differential around the common-mode voltage (VOCM). The VOCM input pin is typically
connected to the midsupply voltage in order to offer the widest signal amplitude range. VOCM is a highimpedance input that requires an external connection to a voltage within the supply boundaries. If the VOCM pin
is left floating, the output common-mode voltage is undefined, and the amplifier will not operate properly. The
usable voltage range for the VOCM input is specified in the Electrical Characteristics and must be observed.
The output stage can be set to a gain of 1V/V or 1⅜V/V with the G4 pin logic level. This option allows for
additional gain fine tuning.
Figure 38 shows how signal outputs VOP and VON swing symmetrically around VOCM. The signal is
represented as the voltage between the two outputs and does not require an accurate VOCM. Therefore, the
signal output does not include ground noise or grounding errors. Noise or drift on VOCM is normally rejected by
the common-mode rejection capability of the subsequent signal stage. By using a differential output stage, the
PGA281 achieves large voltage swings on a single 3-V or 5-V supply.
5
4 VPP
4
VOUT (V)
3
2 VPP
2
1
15 V
5V
0
VOP
8 VPP
PGA281
VOCM
VOCM
G = 1/4
VOP
VON
-1
+2.5 V
-15 V
VON
Differential
VOUT
-2
C037
Figure 38. Differential Output Voltage
The output signal is internally monitored for two error conditions: clipping of the signal to the supply rail and
overcurrent. In fault conditions, an error flag bit is set high until the fault is removed.
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Electrical Overstress
Designers often ask questions about the capability of an amplifier to withstand electrical overstress. These
questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin.
Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal ESD protection is built into these circuits to protect them from accidental ESD events both
before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 39 illustrates the ESD circuits contained in the PGA281. The ESD protection circuitry involves
several current-steering diodes connected from the input and output pins and routed back to the internal powersupply lines. This protection circuitry is intended to remain inactive during normal circuit operation.
VSP
DVDD
EF
DVDD
VSP
600 :
Error
Detection
IN-P
VSOP
VSOP
A1
VSON
VSN
VO-P
VSOP
VSON
A3
Gain
VOCM
VSOP
VSON
VO-N
VSP
A2
600 :
VSON
IN-N
VSN
G0
G1
G2
G3
VSON
VSON
DVDD
VSON
DVDD
DVDD
VSON
DVDD
VSN
VSON
DVDD
VSON
G4
Figure 39. Equivalent Internal ESD Circuitry
The PGA281 input terminals are protected with internal diodes connected to VSP and VSN. If the input signal
voltage exceeds the power-supply voltage (VSP and VSN), limit the current to less than 10 mA to protect the
internal clamp diodes. This current-limiting can usually be accomplished with a series input resistor.
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EMI Rejection
180
160
160
140
140
120
120
EMIRR (dB)
EMIRR (dB)
The PGA281 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications, and densely-populated boards with a mix of analog signal chain and
digital components. The PGA281 is specifically designed to minimize susceptibility to EMI by incorporating an
internal low-pass filter. Depending on the end-system requirements, additional EMI filters may be required near
the signal inputs of the system, as well as incorporating known good practices such as using short traces, lowpass filters, and damping resistors combined with parallel and shielded signal routing. Texas Instruments
developed a method to accurately measure the immunity of an amplifier over a broad frequency spectrum,
extending from 10 MHz to 6 GHz. This method uses EMI rejection ratio (EMIRR) to quantify the PGA281 ability
to reject EMI. Figure 40 and Figure 41 show the PGA281 EMIRR graph for both differential and common-mode
EMI rejection across this frequency range. Table 2 shows the EMIRR values for the PGA281 at frequencies
commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated
near the particular frequency shown.
100
80
60
100
80
60
40
40
20
20
0
10M
100M
1G
0
10M
10G
Frequency (Hz)
100M
1G
10G
Frequency (Hz)
C035
Figure 40. Common Mode EMIRR Testing
C036
Figure 41. Differential Mode (IN-P) EMIRR Testing
Table 2. PGA281 EMIRR for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
DIFFERENTIAL
(IN-P) EMIRR
COMMON-MODE
EMIRR
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar,
ultra-high frequency (UHF) applications
84.3 dB
101.8 dB
900 MHz
Global system for mobile communications (GSM) applications,
radio communication, navigation, GPS (to 1.6 GHz), GSM,
aeronautical mobile, UHF applications
103.3 dB
125.6 dB
1.8 GHz
GSM applications, mobile personal communications, broadband,
satellite, L-band (1 GHz to 2 GHz)
112.5 dB
131.8 dB
®
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth , mobile personal
communications, industrial, scientific and medical (ISM) radio band,
amateur radio and satellite, S-band (2 GHz to 4 GHz)
114.6 dB
122.4 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite,
mobile, S-band
108.9 dB
113.5 dB
5.0 GHz
802.11a, 802.11n, aero communication and navigation, mobile
communication, space and satellite operation, C-band (4 GHz to 8
GHz)
118.7 dB
123.3 dB
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Output Filter
The PGA281 uses a chopper-stabilized architecture for excellent dc stability over temperature and life of
operation. The device also removes 1/f frequency (flicker) noise, and therefore enables both high resolution and
high repeatability for dc measurements. Although the chopper noise components are internally filtered, a minimal
residual amount of high-frequency switching noise appears at the signal outputs. Placing an external, passive,
low-pass filter after the output stage is recommended to remove this switching noise; Figure 42 shows two
examples. This filter can also be used to isolate or decouple the charge switching pulses of an ADC input.
R1
50 W
R3
100 W
VOP
VOP
C1
10 nF
R2
50 W
VON
R4
100 W
VON
C2
10 nF
C3
10 nF
Figure 42. Typical Examples of Recommended Output Filters
Single-Ended Output
The output stage of the PGA281 is designed for highest precision. The fully-differential output avoids grounding
errors and noise, and delivers twice the signal amplitude compared to single-ended signals. However, if desired,
a single-ended output (VOP or VON) can be measured, referred to the voltage at the VOCM pin. The output
stage errors now relate to half the signal amplitude and half the signal gain. Figure 43 shows how the unused
output is unconnected, but not disconnected from error detection. The usable voltage range for the VOCM input
is specified in the Electrical Characteristics and must be observed; that is, the output swing (of both outputs)
should not saturate to the supply. Separate specifications for offset voltage and drift indicate higher offset voltage
at lower gains because some error sources are not cancelled in the output stage connected in single-ended
mode. Note that the gain is one-half of the gain set in reference to the gain table (see Table 1).
15 V
DVDD
VSOP
+
+5 V
In
PGA281
2.5 V
ADC
15 V
Figure 43. Single-Ended Connection Example
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ERROR INDICATORS
Error Flag Detection
The PGA281 is designed for high dc precision and universal use, but it also allows monitoring of signal integrity.
This error flag pin (EF, pin 2) alerts if an error is detected in one of the diagnostic areas specified in Figure 44.
The error flag is a logic low during normal operation, but alarms to a logic high level when in an error state. The
pin returns to normal operation (logic low) after the error state is removed. This added feature supports fully
automated system setup and diagnostic capability while maintaining signal integrity. Figure 44 illustrates the
diagnostic points available for error detection in the device architecture.
VSOP
VSP
VSP
VSP
VSN
VSOP
VSN
Error:
Input overvoltage
Error:
Input amplifier saturation
VSON
Error:
Output amplifier
Error:
Clamp condition
Clamp
A1
Gain
Clamp
A3
A2
VSN
Error:
Gain
network
overload
VSON
Figure 44. Diagnostic Points for Error Detection
Input Clamp Conduction
The input clamp protects the precision input amplifier from large voltages between the inputs caused by a fast
signal slew rate in the input. This clamp circuit conducts current from the input pins during overload. Current
flowing through the clamp can influence the signal source and cause long settling delays on passive input signal
filters. The current is limited by internal resistors of approximately 600 Ω. Note that dynamic overload can result
from the difference signal as well as the common-mode signal.
The input clamp turns on when the input signal slew rate is greater than ±1 V/µs and faster than the amplifier
slew rate (specified in the Frequency Response section of the Electrical Characteristics). Appropriate input
filtering avoids input clamp activation.
Input Overvoltage
The input amplifier can only operate at high performance within a certain input voltage range inside the supply
rail. The error flag (EF pin) alarm indicates a loss of performance as a result of the input voltage or the amplifier
output approaching the rail.
Gain Network Overload
The gain setting network is protected against overcurrent conditions that occur because of an improper gain
setting. The current into the resistors is proportional to the voltage between both inputs and the internal resistor;
a low resistor value results in high gains. The error flag alarms if such an overload condition results from an
improper gain setting.
Output Amplifier
The output stage is monitored for signal clipping to the supply rail and for overcurrent conditions.
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POWER SUPPLY
The PGA281 requires three supply voltages: the high-voltage analog supply, the low-voltage output amplifier
supply, and the digital I/O supply. This architecture allows an optimal interface (level-shift) to the different supply
domains.
The high-voltage analog supplies, VSP and VSN, power the high-voltage input stage section. The substrate of
the device is connected to VSN; therefore, it must be connected to the most negative potential.
The low-voltage analog output supplies, VSOP and VSON, operate within the high-voltage supply boundaries
with two minimal limitations:
1. The usable range for VSON is from a minimum 5 V below VSP to as low as VSN. This 5 V provides the
headroom for the output supply voltage of +2.7 V to +5 V. Even with less than a 5-V supply, this voltage
difference is required for proper operation.
2. The common-mode control input, VOCM, requires a voltage at least 2 V less than VSP in order to support
internal rail-to-rail performance.
These limitations are applicable when using a minimum supply or an extremely asymmetrical high-voltage
supply. In most practical cases, VSON is connected to the ground of the system 3-V or 5-V supply.
VSOP can be turned on first or can be higher than VSP without harm, but operation fails if VSP and VSN are not
present.
Observe the maximum voltage applied between VSOP and VSON because there is no internal protection.
Positive digital supply DVDD and digital ground VSON can also be set within the boundaries of VSP and VSN.
However, DVDD must be 1 V less than VSP. DVDD can be turned on without the analog supply being present
and is operational. Observe the maximum supply voltage because there is no internal protection. VSOP can be
connected with DVDD if desired.
The negative digital supply is connected to the VSON pin. Take care if using split supplies on the VSOP and
VSON pin because the logic low and high thresholds are determined by DVDD and VSON. In normal operation,
VSON is connected to the system ground.
VSN is connected to the substrate; therefore, the voltage at VSON must not turn on the substrate diode to VSN.
Use external Schottky diodes from VSON to VSN to prevent this condition.
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The PGA281 uses an internal chopper-stabilized architecture, and requires good supply decoupling. RC
decoupling using series resistors in the supply is recommended. Series resistors can be in the range of 15 Ω to
22 Ω. RC decoupling also prevents a very fast rise time of the supply voltage, thus avoiding parasitic currents in
the device. Connecting supply wires into an already turned-on supply (very fast rise time) without such a filter
can damage the device as a result of voltage overshoot and parasitic charge currents. Figure 45 shows an
example of a supply connection using RC bypass filters. DVDD may not need decoupling, but if the digital supply
is noisy, a filter is recommended.
NOTE
Rise and fall times for the high-voltage supplies must be slower than 1 V/μs.
5 V to 18 V
IQVSP =
2.4 mA
(typ)
22
470 nF
2.7 V to 5.5 V
5 V to 18 V
22
IQVSN =
2.1 mA
(typ)
470 nF
VSP
VSN
10
IQVSOP =
0.75 mA
(typ)
PGA281
470 nF
VSOP
2.7 V to 5.5 V
IQVDD =
0.07 mA
(typ)
100 nF
DVDD
Supply Connections
VSON
NOTE: The supply voltages shown are only example values.
Figure 45. Supply Connection Example Using RC Bypass Filters for Good Decoupling
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Quiescent Current
The PGA281 uses internal resistor networks and switches to set the signal gain. Consequently, the current
through the resistor network may vary with the gain and signal amplitude. Under normal operation, the gainrelated current is low (less than 400 μA). However, in signal overload conditions while a high gain is selected,
this amount of current may increase.
Settling Time
The PGA281 provides very low drift and low noise, and therefore allows repeatable settling to a precise value.
Signal-related load and power-dissipation variables have minimal effect on device accuracy.
Overload Recovery
Overload conditions can vary widely and there are multiple points in an instrumentation amplifier that can be
overloaded. During input overload, the PGA281 folds the output signal partially back as a result of the differential
signal structure and summing, but the error flag indicates such fault conditions. The amplifier recovers safely
after removing the overload condition, as long as it is within the specified operating range as shown in Figure 46.
Overload Error Flag
Ch 4, 2-V/div
Output Signal
Ch 3, 2-V/div
VSN
Ch 2, 5-V
INN Clipped to VSN
Ch 1, 5-V/div
25 ms/div
Figure 46. Input Clipping: Negative Side
Avoid dynamic overload by using adequate signal filtering that reduces the input slew rate to the slew rate of the
amplifier.
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Input Bias Current Return Path
The input impedance of the PGA281 is extremely high; greater than 1 GΩ. However, make sure to provide a
path for the input bias current of both inputs. This input bias current is typically 300 pA. A high input impedance
means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 47 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the common-mode range of the PGA281, and the input amplifiers saturate. If the differential source resistance is
low, connect the bias current return path to one input (as shown in the thermocouple example in Figure 47). With
higher source impedance, using two equal resistors provides a balanced input with the possible advantage of
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
hydrophone,
and so on.
PGA281
47 k
47 k
Thermocouple
PGA281
10 k
PGA281
Center-tap provides
bias current return.
Figure 47. Providing an Input Common-Mode Current Path
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PGA281
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Application Examples
Multiplexed Data Acquisition
Figure 48 shows the PGA281 used in a multiplexed data-acquisition application.
Low-Pass
Filters
S1
Ch 1
15 V
+5 V
DVDD
S3
Ch 2
+
Ch 3
Mux
50
In+
VSOP
S2
2.5 V
PGA281
10 nF
Ref
Out
2.5 V
ADS1259
Controller
In
0
:G
G4
50
15 V
Sx
Ch x
Figure 48. Typical Block Diagram for Multiplexed Data Acquisition
Programmable Logic Controller (PLC) Input
An example of the PGA281 used in a programmable logic controller (PLC) input application is shown in
Figure 49 .
±10 V
100 k
+
4.87 k
4 mA to 20 mA
±20 mA
VOP
PGA281 VOCM
VON
2.5 V VOUT = 2.5 V ± 1.8 V at G = 4
0
:G
G4
20
µC
Figure 49. ±10-V, 4-mA to 20-mA PLC Input
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SAR ADC Driver
An example of the PGA281 used as a SAR ADC driver with the THS4031 used as input buffers to maximize
SNR and THD is shown in Figure 50 .
Buffering
RC
Low-Pass
Filter
ADC-Side
Filtering
RB
+
RA
THS4031
+
VOP
PGA281 VOCM
RA
RB
+
VON
ADS8318
SAR ADC
CD
CA
THS4031
RC
Figure 50. SAR Driver with Input Buffer
Using TINA-TI™ SPICE-Based Analog Simulation Program with the PGA281
TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range
of both passive and active models. It provides all the conventional dc, transient, and frequency-domain analysis
of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways.
Virtual instruments offer users the ability to select input waveforms and probe circuit nodes, voltages, and
waveforms, creating a dynamic quick-start tool.
NOTE
NOTE: These files require that either the TINA software (from DesignSoft) or TINA-TI
software be installed. Download the free TINA-TI software from the TINA-TI folder.
Two-Terminal Programmable Logic Controller
The circuit in Figure 51 is used to convert inputs of ±10 V, ±5 V, or ±20 mA to an output voltage range from 0 V
to 5 V. The input selection depends on the settings of the switch and the PGA281 gain. Further explanation, as
well as the TINA-TI simulation circuit, is provided in the compressed file that can be downloaded at the following
link: PGA281 PLC Circuit.
±10 V, ±5 V,
or ±20 mA
+
VOP
PGA281
VOCM
VON
250
2.5 V
0
:G
G4
µC
Figure 51. Two-Terminal, Programmable Logic Controller (PLC) Input
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PGA281
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RTD Amplifier
An example of the PGA281 used in an RTD-amplification application is shown in Figure 52. Click the following
link to download the TINA-TI file: PGA281 RTD.
15 V
Out
In
REF5010
1 µF
T emp er at ur e
( qC )
V
O U T at
G = ½
-200
R1
4.99 k:
RTD
Pt100
VOP
PGA281 VOCM
VON
NOTE: Avoid ground
errors by using a Kelvin
sense connection.
V
O U T at
G = 1
V
O U T at
G = 2
V
O U T at
G = 4
0.03
0.06
0.11
0.22
0
0.15
0.29
0.59
1.18
200
0.26
0.51
1.02
2.04
VOUT
Figure 52. RTD Amplifier
High-Side Current Sensing
Figure 53 shows an example of how the PGA281 can be used for high-side current sensing. The load current
(ILOAD) creates a voltage drop across the shunt resistor (RSHUNT). This voltage can be amplified or attenuated by
the PGA281. The wide gain options and excellent common-mode rejection of the PGA281 make it ideal for this
type of application. Click the following link to download the TINA-TI file: PGA281 Current Sense.
10 V
+
ILOAD
100 m
VOP
PGA281 VOCM
VON
0
:G
4
G
To ADC or µC
µC
Load
Figure 53. High-Side Current Sensing
Bridge Amplifier
An example of the PGA281 used in a bridge or strain gauge amplification application is shown in Figure 54. Click
the following link to download the TINA-TI file: PGA281 Bridge Amplifier.
10 V
Bridge
+
VOP
PGA281 VOCM
VON
Figure 54. Programmable Bridge Amplifier
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Evaluation Module
The PGA281EVM provides basic functional evaluation of the PGA281. A picture of the PGA281EVM is provided
in Figure 55.
Figure 55. PGA281 Evaluation Module
The PGA281 evaluation module provides the following features:
• Easy access to nodes with surface-mount test points
• Convenient input and output filtering
• Simple gain setting and error flag indication
The PGA281EVM User Guide (SBOU130, available for download at www.ti.com) provides instructions on how to
set up the device for evaluation. The user guide also includes schematics, layout, and a bill of materials (BOM).
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27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PGA281AIPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA
281
PGA281AIPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PGA
281
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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