PLL1705

PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) APPLICATIONS D DVD Players D DVD Add-On Cards for Multimedia PCs D Digital HDTV Systems D Set-Top Boxes DESCRIPTION The PLL1705† and PLL1706† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1705 can be controlled by sampling frequency-control pins and those of the PLL1706 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1705 and PLL1706 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. D Zero PPM Error Output Clocks D Low Clock Jitter: 50 ps (Typical) D Multiple Sampling Frequencies: – fS = 32, 44.1, 48, 64, 88.2, 96 kHz D 3.3-V Single Power Supply D PLL1705: Parallel Control PLL1706: Serial Control D Package: 20-Pin SSOP (150 mil), Lead-Free Product FUNCTIONAL BLOCK DIAGRAM (ML) SR (MC) FS2 (MD) FS1 CSEL VCC AGND VDD1–3 DGND1–3 Mode Control Interface Reset PLL2 XT1 OSC XT2 PLL1 Power Supply Divider Divider Divider ( ): PLL1706 MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE –25°C to 85°C –25°C to 85°C PACKAGE MARKING PLL1705 PLL1706 ORDERING NUMBER PLL1705DBQ PLL1705DBQR PLL1706DBQ PLL1706DBQR TRANSPORT MEDIA Tube Tape and reel Tube Tape and reel PLL1705DBQ PLL1706DBQ SSOP 20 SSOP 20 20DBQ 20DBQ ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PLL1705 AND PLL1706 Supply voltage: VCC, VDD1–3 Supply voltage differences: VCC, VDD1–3 Ground voltage differences: AGND, DGND1–3 Digital input voltage: FS1 (MD), FS2 (MC), SR (ML), CSEL Analog input voltage, XT1, XT2 Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) 4V ±0.1 V ±0.1 V – 0.3 V to (VDD + 0.3) V – 0.3 V to (VCC + 0.3) V ±10 mA –40°C to 125°C –55°C to 150°C 150°C 260°C, 5 s Package temperature (IR reflow, peak) 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT Logic input VIH (1) VIL (1) IIH (1) IIL (1) VOH (2) VOL (2) Input Input logic level Input Input logic current Logic output Output Output logic level Sampling frequency Samplingfrequency IOH = –4 mA IOL = 4 mA Standard fS Double fS VIN = VDD VIN = 0 V CMOS VDD – 0.4 V 0.4 32 64 44.1 88.2 48 96 27.27 0.3 VCC VIN = VCC VIN = 0 V 3.5 20% to 80% of VDD 80% to 20% of VDD For crystal oscillation For external clock 45% 2.0 2.0 48% 50% 50 0.5 33.8688 16.9344 8.192 12.288 12.288 18.432 2.0 2.0 45 PLL1705, to stated output frequency PLL1706, to stated output frequency To stated output frequency 50 50 50 80 3 55 100 150 200 6 33.8688 24.576 36.864 ns ns % ps ns ns ms MHz 1.5 ps ms 55% ±10 ±10 Vdc Vdc kHz CMOS compatible 0.7VDD 65 3.6 0.3 VDD 100 ±10 Vdc µA TEST CONDITIONS MIN TYP MAX UNIT MASTER CLOCK (MCKO1, 2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin) Master clock frequency 26.73 27 VIH VIL IIH IIL Input Input level(3) Input Input current(3) Output voltage (4) Output rise time Output fall time Duty cycle Clock jitter (5) Power-up time (6) PLL AC CHARACTERISTICS (SCKO0–3) (fM = 27 MHz, CL = 20 pF on measurement pin) SCKO0 Fixed SCKO1 SCKO2 SCKO3 Output rise time Output fall time Output duty cycle Output clock jitter (5) Frequency Settling Time(7) Power-up time (8) Output Output system clock frequency Selectable for 44.1 kHz 256 fS 384 fS 20% to 80% of VDD 80% to 20% of VDD 0.7 VCC MHz V µA Vp-p ns ns (1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode. 3 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com ELECTRICAL CHARACTERISTICS(continued) all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER POWER SUPPLY REQUIREMENTS VCC, VDD IDD + ICC Supply voltage range (9) Supply Supply current (9) Power dissipation TEMPERATURE RANGE Operatingtemperature –25 85 °C θJA Thermal resistance PLL1705/6DBQ: 20-pin SSOP (150 mil) 150 °C/W (1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/ML, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO1, SCKO0 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1706 goes into power-down mode. VDD = VCC = 3.3 V, fS = 48 kHz Power down(10) VDD = VCC = 3.3 V, fS = 48 kHz 2.7 3.3 19 320 63 3.6 25 500 90 Vdc mA µA mW TEST CONDITIONS MIN TYP MAX UNIT PIN ASSIGNMENTS PLL1705 (TOP VIEW) PLL1706 (TOP VIEW) 20 19 18 17 16 15 14 13 12 11 VDD1 SCKO2 SCKO3 DGND1 FS1 FS2 SR VCC AGND XT1 1 2 3 4 5 6 7 8 9 10 VDD3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL XT2 VDD1 SCKO2 SCKO3 DGND1 MD MC ML VCC AGND XT1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD3 SCKO0 SCKO1 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL XT2 4 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 Terminal Functions TERMINAL NAME AGND CSEL DGND1 DGND2 DGND3 FS1(MD) FS2(MC) MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 SR(ML) VCC VDD1 VDD2 VDD3 XT1 XT2 NO. 9 12 4 16 17 5 6 14 15 19 18 2 3 7 8 1 13 20 10 11 I/O – IN – – – IN IN OUT OUT OUT OUT OUT OUT IN – – – – IN OUT Analog ground SCKO1 frequency selection control(1) Digital ground 1 Digital ground 2 Digital ground 3 Sampling frequency group control in PLL1705, data input for serial control in PLL1706(1) Sampling frequency group control in PLL1705, bit clock input for serial control in PLL1706(1) 27-MHz master clock output 1 27-MHz master clock output 2 System clock output 0 (33.8688 MHz fixed) System clock output 1 (selectable for 44.1 kHz) System clock output 2 (256 fS) System clock output 3 (384 fS) Sampling rate control in PLL1705, load strobe input for serial control in PLL1706(1) Analog power supply, 3.3 V Digital power supply 1, 3.3 V Digital power supply 2, 3.3 V Digital power supply 3, 3.3 V 27-MHz crystal oscillator, or external clock input 27-MHz crystal oscillator, must be OPEN for external clock input mode DESCRIPTION (1) Schmitt-trigger input with internal pulldown. 5 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com TYPICAL PERFORMANCE CURVES JITTER vs SAMPLING FREQUENCY 70 70 JITTER vs LOAD CAPACITANCE 60 Jitter – psrms Jitter – psrms 60 SCKO3 SCKO0 50 50 SCKO2 40 MCKO1 MCKO2 30 30 40 50 60 70 80 90 100 fS – Sampling Frequency – kHz SCKO0 SCKO1 SCKO2 SCKO3 30 0 5 40 SCKO1 MCKO1 MCKO2 10 15 20 CL – Load Capacitance – pF Figure 1 JITTER vs SUPPLY VOLTAGE 70 70 Figure 2 JITTER vs FREE-AIR TEMPERATURE 60 SCKO0 Jitter – psrms SCKO1 50 SCKO3 Jitter – psrms 60 SCKO0 SCKO3 SCKO1 50 SCKO2 40 MCKO2 MCKO1 40 SCKO2 MCKO2 MCKO1 30 2.7 3.0 3.3 3.6 30 –50 –25 0 25 50 75 100 VCC – Supply Voltage – V TA – Free-Air Temperature – °C Figure 3 Figure 4 NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency (33.8688 MHz for SCKO0, 33.8688 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin, unless otherwise noted. 6 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 DUTY CYCLE vs SUPPLY VOLTAGE 55 55 DUTY CYCLE vs FREE-AIR TEMPERATURE 53 53 Duty Cycle – % Duty Cycle – % 51 SCKO0 SCKO2 51 SCKO2 SCKO3 SCKO1 49 SCKO1 49 SCKO0 47 SCKO3 47 MCKO2 MCKO1 45 2.7 MCKO2 MCKO1 3.0 3.3 3.6 45 –50 –25 0 25 50 75 100 VCC – Supply Voltage – V TA – Free-Air Temperature – °C Figure 5 Figure 6 NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency (33.8688 MHz for SCKO0, 33.8688 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin, unless otherwise noted. 7 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com THEORY OF OPERATION MASTER CLOCK AND SYSTEM CLOCK OUTPUT The PLL1705/6 consists of a dual PLL clock and master clock generator which generates four system clocks and two buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1705/6. The PLL is designed to accept a 27-MHz master clock. SCKO3 384 fS Counter N SCKO0–3 Frequency Control Counter M Phase Detector and Loop Filter VCO Divider Divider PLL2 PLL1 Counter M Phase Detector and Loop Filter Counter N OSC Divider VCO XT1 XT2 MCKO1 27 MHz MCKO2 27 MHz SCKO0 33.8688 MHz SCKO1 33.8688/16.9344 MHz SCKO2 256 fS Figure 7. Block Diagram 8 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options, and Figure 9 illustrates the 27-MHz master clock timing requirement. MCKO2 MCKO2 MCKO1 MCKO1 XT1 C1 Crystal Crystal OSC Circuit 27-MHz Internal Master Clock External Clock XT1 Crystal OSC Circuit XT2 27-MHz Internal Master Clock XT2 C2 PLL1705/PLL1706 C1, C2 = 10 pF to 33 pF Crystal Resonator Connection PLL1705/PLL1706 External Clock Input Connection Figure 8. Master Clock Generator Connection Diagram t(XT1H) 0.7 VCC XT1 0.3 VCC t(XT1L) DESCRIPTION Master clock pulse duration HIGH Master clock pulse duration LOW SYMBOL tXT1H tXT1L MIN 10 10 MAX UNIT ns ns Figure 9. External Master Clock Timing Requirement The PLL1705/6 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs 384 fS or 768 fS (fS = 44.1 kHz) which is selected by CSEL (pin 12) for a CD-DA DSP. The output frequency of the remaining clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3 output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency, which can be programmed. The system clock output frequencies for programmed sampling frequencies are shown in Table 3. Table 1. Generated System Clock SCKO1 Frequency CSEL LOW HIGH SCKO1 FREQUENCY 33.8688 MHz 16.9344 MHz Table 2. Sampling Frequencies SAMPLING RATE Standard sampling frequencies Double sampling frequencies SAMPLING FREQUENCY (kHz) 32 64 44.1 88.2 48 96 9 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com Table 3. Sampling Frequencies and System Clock Output Frequencies SAMPLING FREQUENCY (kHz) 32 44.1 48 64 88.2 96 SAMPLING RATE Standard Standard Standard Double Double Double SCKO2 (MHZ) 8.192 11.2896 12.288 16.384 22.5792 24.576 SCKO3 (MHZ) 12.288 16.9344 18.432 24.576 33.8688 36.864 Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from sampling frequency change to SCKO settling is 200 ns maximum. This clock transient timing is not synchronized with the SCKOx signals. Figure 10 illustrates SCKO transient timing in the PLL1706. External buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PLL1705/6. ML 200 ns 1–2 Clocks of MCKO1,2 SCKO2 SCKO3 Stable Clock Transition Region Stable SCKO0 SCKO1 33.8688 MHz, 384 or 768 of 44.1 kHz Figure 10. System Clock Transient Timing POWER-ON RESET The PLL1705/6 has an internal power-on reset circuit. The mode register of PLL1706 is initialized with default settings by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power up time. Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on reset timing is shown in Figure 11. VDD 2.4 V 2.0 V 1.6 V Reset Internal Reset Reset Removal 1024 Master Clocks Master Clock Figure 11. Power-On Reset Timing 10 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 FUNCTION CONTROL The built-in functions of the PLL1705 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1 (pin 5) and FS2 (pin 6). The PLL1706 can be controlled in the serial mode (software mode), which uses a three-wire interface by ML (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4. Table 4. Selectable Functions SELECTABLE FUNCTION Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz) Sampling rate select (standard/double) Each clock output enable/disable Power down PARALLEL MODE Yes Yes No No SERIAL MODE Yes Yes Yes Yes PLL1705 (Parallel Mode) In the parallel mode, the following functions can be selected: Sampling Frequency Group Select The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6). FS2 (PIN 6) LOW LOW HIGH HIGH FS1 (PIN 5) LOW HIGH LOW HIGH SAMPLING FREQUENCY 48 kHz 44.1 kHz 32 kHz Reserved Sampling Rate Select The sampling rate can be selected by SR (pin 7) SR (PIN 7) LOW HIGH SAMPLING RATE Standard Double PLL1706 (Serial Mode) The built-in functions of the PLL1706 are shown in Table 5. These functions are controlled using the ML, MC, and MD serial control signals. Table 5. Selectable Functions SELECTABLE FUNCTION Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz) Sampling rate select (standard/double) Each clock output enable/disable Power down DEFAULT 48-kHz group Standard Enabled Disabled 11 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com Program-Register Bit Mapping The built-in functions of the PLL1706 are controlled through a 16-bit program register. This register is loaded using MD, MC and ML. After the 16 data bits are clocked in using the rising edge of MC, ML is used to latch the data into the register. Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in Figure 12 and Figure 13, respectively. ML MC MD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 12. Serial Mode Control Format t(MHH) t(MLL) ML VDD/2 t(MLS) t(MCH) MC t(MCL) t(MLH) t(MLS) VDD/2 t(MCY) MD MSB t(MDH) t(MDS) DESCRIPTION LSB VDD/2 SYMBOL tMCY tMCL tMCH tMDH tMDS MIN 100 40 40 40 40 16 200 40 TYP MAX UNIT ns ns ns ns ns MC clocks(1) ns ns ns MC pulse cycle time MC pulse duration LOW MC pulse duration HIGH MD hold time MD setup time ML low-level time ML high-level time ML hold time(2) tMLL tMHH tMLH ML setup time(3) tMLS 40 (1) MC clocks: MC clock period (2) MC rising edge for LSB to ML rising edge (3) ML rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any ML rise time is accepted. Figure 13. Control Data Input Timing 12 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 Mode Register D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 CE6 D8 CE5 D7 CE4 D6 CE3 D5 CE2 D4 CE1 D3 RSV D2 SR D1 FS2 D0 FS1 Table 6. Register Mapping REGISTER BIT NAME CE6 CE5 CE4 CE3 Mode control control CE2 CE1 RSV SR FS[2:1] DESCRIPTION MCKO2 output enable/disable MCKO1 output enable/disable SCKO1 output enable/disable SCKO3 output enable/disable SCKO2 output enable/disable SCKO0 output enable/disable Reserved, must be 0 Sampling rate select Sampling frequency select FS[2:1]: Sampling Frequency Group Select FS2 0 0 1 1 FS1 0 1 0 1 SAMPLING FREQUENCY 48 kHz 44.1 kHz 32 kHz Reserved DEFAULT O SR: Sampling Rate Select SR 0 1 SAMPLING RATE Standard Double DEFAULT O CE [6:1]: Clock Output Control CE1–CE6 0 1 CLOCK OUTPUT CONTROL Clock output disable Clock output enable O DEFAULT While all the bits of CE [6:1] are 0, the PLL1706 goes into the power-down mode, all dynamic operation including PLLs and the oscillator halt, but serial mode control is enabled for resumption. CONNECTION DIAGRAM Figure 14 shows the typical connection circuit for the PLL1705. There are four grounds for digital and analog power supplies. However, the use of one common ground connection is recommended to avoid latch-up or other power-supply-related troubles. Power supplies should be bypassed as close as possible to the device. MPEG-2 APPLICATIONS Typical applications for the PLL1705/6 are MPEG-2 based systems such as DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1705/6 provides audio system clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, and DAC(s) from a 27-MHz video clock. 13 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com 3.3 V (2) PLL1705/6 1 2 (1) 3 4 (4) 5 6 7 8 (2) (1) 9 FS1 (MD) FS2 (MC) SR(ML) VCC AGND DGND2 MCKO2 MCKO1 VDD2 CSEL XT2 16 15 (1) 14 13 12 11 SCKO3 DGND1 SCKO1 DGND3 18 17 VDD1 SCKO2 VDD3 SCKO0 20 19 (1) 10 XT1 (3) (3) Clock Outputs (5) (1) 0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout (2) 10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout (3) 27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2 (4) This connection is for PLL1705 (parallel mode); when PLL1706 (serial mode) is to be used, control pins must be connected to serial interfaced controller. (5) For good jitter performance, minimize the load capacitance on the clock output. Figure 14. Typical Connection Diagram 14 www.ti.com PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 BLOCK DIAGRAM OF MPEG-2 BASED SYSTEM APPLICATION PLL1705/6 384 fS SCKO3 27-MHz Crystal 256 fS SCKO2 PCM1716 Front MCKO1/2 27 MHz SCKO0 or 1 PCM1716 Surround Center CD-DA/ DVD DSP MPEG/AC-3 Audio Decoder PCM1716 Subwoofer 15 PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 www.ti.com MECHANICAL DATA DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 0.025 (0,64) 24 0.012 (0,30) 0.008 (0,20) 13 0.005 (0,13) 0.157 (3,99) 0.150 (3,81) 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM Gauge Plane 1 A 0°–8° 0.069 (1,75) MAX 0.035 (0,89) 0.016 (0,40) 12 0.010 (0,25) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX 16 0.197 (5,00) 0.189 (4,80) 20 0.344 (8,74) 0.337 (8,56) 24 0.344 (8,74) 0.337 (8,56) 28 0.394 (10,01) 0.386 (9,80) A MIN D M0–137 VARIATION AB AD AE AF 4073301/F 02/02 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO–137. 16 PACKAGE OPTION ADDENDUM www.ti.com 22-May-2006 PACKAGING INFORMATION Orderable Device PLL1705DBQ PLL1705DBQG4 PLL1705DBQR PLL1705DBQRG4 PLL1706DBQ PLL1706DBQG4 PLL1706DBQR PLL1706DBQRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP Package Drawing DBQ DBQ DBQ DBQ DBQ DBQ DBQ DBQ Pins Package Eco Plan (2) Qty 20 20 20 20 20 20 20 20 56 56 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 56 56 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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