PLL1707 PLL1708
SLES065 – DECEMBER 2002
3.3 V DUAL PLL MULTICLOCK GENERATOR
FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock (PLL1707):
– SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL1708): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS, 384 fS, 256 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitter: 50 ps (Typical) Multiple Sampling Frequencies (PLL1707): – fS = 32, 44.1, 48, 64, 88.2, 96 kHz Multiple Sampling Frequencies (PLL1708): – fS = 16, 22.05, 24, 32, 44.1, 48, 64, 88.2, 96 kHz 3.3-V Single Power Supply PLL1707: Parallel Control PLL1708: Serial Control Package: 20-Pin SSOP (150 mil), Lead-Free Product
APPLICATIONS D D D D D D D
HDD + DVD Recorders DVD Recorders HDD Recorders DVD Players DVD Add-On Cards for Multimedia PCs Digital HDTV Systems Set-Top Boxes
D
DESCRIPTION
The PLL1707† and PLL1708† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1707 and PLL1708 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins and those of the PLL1708 can be controlled through serial-mode control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1707 and PLL1708 are ideal for MPEG-2 applications which use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes.
D D D D D D D
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †The PLL1707 and PLL1708 use the same die and they are electrically identical except for mode control.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
PLL1707 PLL1708
SLES065 – DECEMBER 2002
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FUNCTIONAL BLOCK DIAGRAM
(MS) SR (MC) FS2 (MD) FS1 CSEL VCC AGND VDD1–3 DGND1–3
Mode Control Interface Reset PLL2 XT1 OSC XT2 PLL1
Power Supply
Divider
Divider
Divider
( ): PLL1708
MCKO1
MCKO2
SCKO0
SCKO1
SCKO2
SCKO3
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE –25°C to 85°C –25°C to 85°C PACKAGE MARKING PLL1707 PLL1708 ORDERING NUMBER PLL1707DBQ PLL1707DBQR PLL1708DBQ PLL1708DBQR TRANSPORT MEDIA Tube Tape and reel Tube Tape and reel
PLL1707DBQ PLL1708DBQ
SSOP 20 SSOP 20
20DBQ 20DBQ
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) PLL1705 AND PLL1706 Supply voltage: VCC, VDD1–VDD3 Supply voltage differences: VCC, VDD1–VDD3 Ground voltage differences: AGND, DGND1–DGND3 Digital input voltage: FS1 (MD), FS2 (MC), SR (MS), CSEL Analog input voltage, XT1, XT2 Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) 4V ±0.1 V ±0.1 V – 0.3 V to (VDD + 0.3) V – 0.3 V to (VCC + 0.3) V ±10 mA –40°C to 125°C –55°C to 150°C 150°C 260°C, 5 s
Package temperature (IR reflow, peak) 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER DIGITAL INPUT/OUTPUT Logic input VIH (1) VIL (1) IIH (1) IIL (1) VOH (2) VOL (2) Input Input logic level Input Input logic current Logic output Output Output logic level PLL1707 Sam ling frequency Sampling frequency PLL1708 IOH = –4 mA IOL = 4 mA Standard fS Double fS Half fS Standard fS VIN = VDD VIN = 0 V CMOS VDD – 0.4 V 0.4 32 64 16 32 44.1 88.2 22.05 44.1 48 96 24 48 kHz Vdc Vdc CMOS compatible 0.7VDD 65 3.6 0.3 VDD 100 ±10 Vdc µA TEST CONDITIONS MIN TYP MAX UNIT
Double fS 64 88.2 96 MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS (fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin) Master clock frequency VIH VIL IIH IIL Input Input level(3) Input Input current(3) Output voltage (4) Output rise time Output fall time Duty cycle Clock jitter (5) Power-up time (6) PLL AC CHARACTERISTICS (SCKO0–SCKO3) (fM = 27 MHz, CL = 20 pF on measurement pin) SCKO0 Fixed SCKO1 SCKO2 SCKO3 SCKO0 SCKO1 SCKO2 SCKO3 Output rise time Output fall time Output duty cycle Out ut ystem clock Output system clock frequency q y PLL1708 PLL1707 Selectable for 48 kHz 256 fS 384 fS Fixed Selectable for 48 kHz 256 fS 384 fS 20% to 80% of VDD 80% to 20% of VDD 45 12.288 4.096 6.144 24.576 8.192 12.288 12.288 18.432 33.8688 24.576 12.288 18.432 2.0 2.0 50 55 36.864 24.576 36.864 ns ns % 20% to 80% of VDD 80% to 20% of VDD For crystal oscillation For external clock 45% VIN = VCC VIN = 0 V 3.5 2.0 2.0 51% 50% 50 0.5 33.8688 36.864 24.576 36.864 MHz 1.5 ps ms 55% 26.73 0.7 VCC 0.3 VCC ±10 ±10 27 27.27 MHz V µA Vp-p ns ns
(1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode. 3
PLL1707 PLL1708
SLES065 – DECEMBER 2002
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ELECTRICAL CHARACTERISTICS (continued)
all specifications at TA = 25°C, VDD1–VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted) PARAMETER (5) Output Output clock jitter (5) Frequency Settling Time(7) Power-up time (8) POWER SUPPLY REQUIREMENTS VCC, VDD IDD + ICC Supply voltage range (9) Supply Supply current (9) Power dissipation TEMPERATURE RANGE Operating temperature –25 85 °C θJA Thermal resistance PLL1707/8DBQ: 20-pin SSOP (150 mil) 150 °C/W (1) Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant) (2) Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1 (3) Pin 10: XT1 (4) Pin 11: XT2 (5) Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output. (6) The delay time from power on to oscillation (7) The settling time when the sampling frequency is changed (8) The delay time from power on to lockup (9) fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling frequency selection and load condition. (10) While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode. VDD = VCC = 3.3 V, fS = 48 kHz Power down(10) VDD = VCC = 3.3 V, fS = 48 kHz 2.7 3.3 19 350 63 3.6 25 550 90 Vdc mA µA mW TEST CONDITIONS SCKO0, SCKO1 SCKO2, SCKO3 PLL1707, to stated output frequency PLL1708, to stated output frequency To stated output frequency MIN TYP 58 50 50 80 3 MAX 100 100 150 300 6 UNIT ps ps ns ms
PIN ASSIGNMENTS
PLL1707 (TOP VIEW) PLL1708 (TOP VIEW) 20 19 18 17 16 15 14 13 12 11
VDD1 SCKO2 SCKO3 DGND1 FS1 FS2 SR VCC AGND XT1
1 2 3 4 5 6 7 8 9 10
VDD3 SCKO1 SCKO0 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL XT2
VDD1 SCKO2 SCKO3 DGND1 MD MC MS VCC AGND XT1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD3 SCKO1 SCKO0 DGND3 DGND2 MCKO2 MCKO1 VDD2 CSEL XT2
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
PLL1707 Terminal Functions
TERMINAL NAME AGND CSEL DGND1 DGND2 DGND3 FS1 FS2 MCKO1 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 SR VCC VDD1 VDD2 VDD3 XT1 XT2 NO. 9 12 4 16 17 5 6 14 15 18 19 2 3 7 8 1 13 20 10 11 I/O – I – – – I I O O O O O O I – – – – I O Analog ground SCKO1 frequency selection control(1) Digital ground 1 Digital ground 2 Digital ground 3 Sampling frequency group control 1(1) Sampling frequency group control 2(1) 27-MHz master clock output 1 27-MHz master clock output 2 System clock output 0 (33.8688 MHz fixed) System clock output 1 (selectable for 48 kHz) System clock output 2 (256 fS selectable) System clock output 3 (384 fS selectable) Sampling rate control(1) Analog power supply, 3.3 V Digital power supply 1, 3.3 V Digital power supply 2, 3.3 V Digital power supply 3, 3.3 V 27-MHz crystal oscillator, or external clock input 27-MHz crystal oscillator, must be OPEN for external clock input mode DESCRIPTION
(1) Schmitt-trigger input with internal pulldown.
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SLES065 – DECEMBER 2002
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PLL1708 Terminal Functions
TERMINAL NAME AGND CSEL DGND1 DGND2 DGND3 MC MCKO1 MCKO2 MD MS SCKO0 SCKO1 SCKO2 SCKO3 VCC VDD1 VDD2 VDD3 XT1 XT2 NO. 9 12 4 16 17 6 14 15 5 7 18 19 2 3 8 1 13 20 10 11 I/O – I – – – I O O I I O O O O – – – – I O Analog ground SCKO1 frequency selection control(1) Digital ground 1 Digital ground 2 Digital ground 3 Bit clock input for serial control(1) 27-MHz master clock output 1 27-MHz master clock output 2 Data input for serial control(1) Chip select input for serial control(1) System clock output 0 (33.8688 MHz fixed) System clock output 1 (selectable for 48 kHz) System clock output 2 (256 fS selectable) System clock output 3 (384 fS selectable) Analog power supply, 3.3 V Digital power supply 1, 3.3 V Digital power supply 2, 3.3 V Digital power supply 3, 3.3 V 27-MHz crystal oscillator, or external clock input 27-MHz crystal oscillator, must be OPEN for external clock input mode DESCRIPTION
(1) Schmitt-trigger input with internal pulldown.
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
TYPICAL PERFORMANCE CURVES
JITTER vs SAMPLING FREQUENCY
70 MCKO1 65 MCKO2 SCKO0 SCKO1 SCKO2 SCKO3 65 SCKO1 60 Jitter – psrms Jitter – psrms 60 SCKO3 SCKO0 70
JITTER vs LOAD CAPACITANCE
55
55 SCKO2 50
50
45
45 MCKO1 MCKO2
40 30 40 50 60 70 80 90 100 fS – Sampling Frequency – kHz
40 0 5 10 15 20 CL – Load Capacitance – pF
Figure 1
JITTER vs SUPPLY VOLTAGE
70 70
Figure 2
JITTER vs FREE-AIR TEMPERATURE
65
SCKO1 SCKO0
65 SCKO1 SCKO0 60 Jitter – psrms SCKO3
60 Jitter – psrms
55
SCKO3 MCKO2
55 MCKO2 50
50
45
SCKO2
MCKO1
45
SCKO2
MCKO1
40 2.7
3.0
3.3
3.6
40 –50
–25
0
25
50
75
100
VCC – Supply Voltage – V
TA – Free-Air Temperature – °C
Figure 3
Figure 4
NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency (33.8688 MHz for SCKO0, 36.864 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin, unless otherwise noted.
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
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DUTY CYCLE vs SUPPLY VOLTAGE
55 54 MCKO1 53 52 Duty Cycle – % 51 50 49 48 47 46 45 2.7 SCKO3 SCKO1 SCKO0 MCKO2 SCKO2 Duty Cycle – % 53 52 51 50 49 48 47 46 3.0 3.3 3.6 45 –50 55 54
DUTY CYCLE vs FREE-AIR TEMPERATURE
MCKO2 MCKO1 SCKO2 SCKO1
SCKO0
SCKO3
–25
0
25
50
75
100
VCC – Supply Voltage – V
TA – Free-Air Temperature – °C
Figure 5
Figure 6
NOTE: All specifications at TA = 25°C, VDD1–3 (= VDD) = VCC = +3.3 V, fM = 27 MHz, crystal oscillation, C1, C2 = 15 pF, default frequency (33.8688 MHz for SCKO0, 36.864 MHz for SCKO1, 256 fS and 384 fS of 48 kHz for SCKO2 and SCKO3), CL = 20 pF on measurement pin, unless otherwise noted.
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
THEORY OF OPERATION
MASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1707/8 consists of a dual PLL clock and master clock generator which generates four system clocks and two buffered 27-MHz clocks from a 27-MHz master clock. Figure 7 shows the block diagram of the PLL1707/8. The PLL is designed to accept a 27-MHz master clock.
SCKO3 384 fS
Counter N SCKO0–3 Frequency Control Counter M Phase Detector and Loop Filter VCO
Divider
Divider PLL2
PLL1
Counter M Phase Detector and Loop Filter Counter N OSC Divider VCO
XT1 XT2 MCKO1 27 MHz
MCKO2 27 MHz
SCKO0 33.8688 MHz
SCKO1 36.864/24.576 MHz (36.864/24.576 MHz) (18.432/12.288 MHz)
SCKO2 256 fS
( ): PLL1708
Figure 7. Block Diagram
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SLES065 – DECEMBER 2002
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The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options, and Figure 9 illustrates the 27-MHz master clock timing requirement.
MCKO2
MCKO2
MCKO1
MCKO1
XT1 C1 Crystal Crystal OSC Circuit
27-MHz Internal Master Clock
External Clock
XT1 Crystal OSC Circuit XT2
27-MHz Internal Master Clock
XT2 C2 PLL1707/PLL1708 C1, C2 = 10 pF to 33 pF Crystal Resonator Connection
PLL1707/PLL1708 External Clock Input Connection
Figure 8. Master Clock Generator Connection Diagram
t(XT1H) 0.7 VCC XT1 0.3 VCC t(XT1L)
DESCRIPTION Master clock pulse duration HIGH Master clock pulse duration LOW
SYMBOL t(XT1H) t(XT1L)
MIN 10 10
MAX
UNIT ns ns
Figure 9. External Master Clock Timing Requirement
The PLL1707/8 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs 256 fS, 384 fS 512 fS, or 768 fS (fS = 48 kHz) which is selected by hardware or software control. The output frequency of the remaining clocks is determined by the sampling frequency (fS) under hardware or software control. SCKO2 and SCKO3 output 256-fS and 384-fS system clocks, respectively. Table 2 shows each sampling frequency which can be programmed. The system clock output frequencies for programmed sampling frequencies are shown in Table 3. The half sampling frequencies on SCKO2 and SCKO3 and 256 fS and 384 fS on SCKO1 are supported only on the PLL1708.
Table 1. Generated System Clock SCKO1 Frequency
fS 256 fS† 384 fS† 512 fS 768 fS † PLL1708 only 10 SCKO1 FREQUENCY 12.288 MHz 18.432 MHz 24.576 MHz 36.864 MHz
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
Table 2. Sampling Frequencies
SAMPLING RATE Half sampling frequencies† Standard sampling frequencies Double sampling frequencies † PLL1708 only SAMPLING FREQUENCY (kHz) 16 32 64 22.05 44.1 88.2 24 48 96
Table 3. Sampling Frequencies and System Clock Output Frequencies
SAMPLING FREQUENCY (kHz) 16† 22.05† 24† 32 44.1 48 64 88.2 96 † PLL1708 only SAMPLING RATE Half Half Half Standard Standard Standard Double Double Double 256 fS SCKO2 (MHZ) 4.096 5.6448 6.144 8.192 11.2896 12.288 16.384 22.5792 24.576 384 fS SCKO3 (MHZ) 6.144 8.4672 9.216 12.288 16.9344 18.432 24.576 33.8688 36.864
Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the PLL1708.
MS
300 ns 1–2 Clocks of MCKO1, 2 SCKO2 SCKO3 Stable Clock Transition Region Stable
SCKO0 SCKO1
33.8688 , 36.864, or 24.576 MHz
Figure 10. System Clock Transient Timing
The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.
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SLES065 – DECEMBER 2002
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SR FS2, 1 CSEL 150 ns 50 ns SCKO1 SCKO2 SCKO3 Stable Clock Transition Region Stable
SCKO0
33.8688 MHz
Figure 11. SCKO Transient Timing
POWER-ON RESET
The PLL1707/8 has an internal power-on reset circuit. The mode register of the PLL1708 is initialized with default settings by power-on reset. Throughout the reset period, all clock outputs are enabled with the default settings after power-up time. Initialization by internal power-on reset is done automatically during 1024 master clocks at VDD > 2.0 V (TYP). Power-on reset timing is shown in Figure 12.
VDD 2.4 V 2.0 V 1.6 V
Reset Internal Reset
Reset Removal
1024 Master Clocks Master Clock
Figure 12. Power-On Reset Timing
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
FUNCTION CONTROL
The built-in functions of the PLL1707 can be controlled in the parallel mode (hardware mode), which uses SR (pin 7), FS1 (pin 5) and FS2 (pin 6). The PLL1708 can be controlled in the serial mode (software mode), which has a three-wire interface using MS (pin 7), MC (pin 6), and MD (pin 5). The selectable functions are shown in Table 4.
Table 4. Selectable Functions
SELECTABLE FUNCTION Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz) Sampling rate select (standard/double) Sampling rate select (half) Each clock output enable/disable Power down SCKO1 configuration PARALLEL MODE Yes Yes No No No No SERIAL MODE Yes Yes Yes Yes Yes Yes
PLL1707 (Parallel Mode)
In the parallel mode, the following functions can be selected:
Sampling Frequency Group Select
The sampling frequency group can be selected by FS1 (pin 5) and FS2 (pin 6).
FS2 (PIN 6) LOW LOW HIGH HIGH FS1 (PIN 5) LOW HIGH LOW HIGH SAMPLING FREQUENCY 48 kHz 44.1 kHz 32 kHz Reserved
Sampling Rate Select
The sampling rate can be selected by SR (pin 7)
SR (PIN 7) LOW HIGH SAMPLING RATE Standard Double
System Clock SCKO1 Frequency Select
System clock SCKO1 frequency can be selected by CSEL (pin 12).
CSEL (PIN 12) LOW HIGH SCKO1 FREQUENCY 36.864 MHz 24.576 MHz
PLL1708 (Serial Mode)
The built-in functions of the PLL1708 are shown in Table 5. These functions are controlled using the MS, MC, and MD serial control signals.
Table 5. Selectable Functions
SELECTABLE FUNCTION Sampling frequency select (32 kHz, 44.1 kHz, 48 kHz) Sampling rate select (half, standard, double) Each clock output enable/disable Power down SCKO1 configuration DEFAULT 48-kHz group Standard Enabled Disabled 36.864 MHz, 24.576 MHz 13
PLL1707 PLL1708
SLES065 – DECEMBER 2002
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Program-Register Bit Mapping
The built-in functions of the PLL1708 are controlled through a 16-bit program register. This register is loaded using MD, MC and MS. After the 16 data bits are clocked in using the rising edge of MC, MS is used to latch the data into the register. Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in Figure 13 and Figure 14, respectively.
MS
MC
MD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 13. Serial Mode Control Format
t(MHH) t(MSL) MS VDD/2
t(MSS) t(MCH) MC
t(MCL) t(MSH)
t(MSS)
VDD/2 t(MCY)
MD
MSB t(MDH) t(MDS) DESCRIPTION
LSB
VDD/2
SYMBOL t(MCY) t(MCL) t(MCH) t(MDH) t(MDS) t(MSL) t(MHH) t(MSH)
MIN 100 40 40 40 40 16 200 40
TYP
MAX
UNIT ns ns ns ns ns MC clocks(1) ns ns ns
MC pulse cycle time MC pulse duration LOW MC pulse duration HIGH MD hold time MD setup time MS low-level time MS high-level time MS hold time(2)
MS setup time(3) t(MSS) 40 (1) MC clocks: MC clock period (2) MC rising edge for LSB to MS rising edge (3) MS rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any MS rise time is accepted.
Figure 14. Control Data Input Timing
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
Mode Register
D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 CE6 D8 CE5 D7 CE4 D6 CE3 D5 CE2 D4 CE1 D3 SR2 D2 SR1 D1 FS2 D0 FS1
Table 6. Mode Register Mapping
REGISTER BIT NAME CE6 CE5 CE4 CE3 Mode control CE2 CE1 SR[2:1] FS[2:1] DESCRIPTION MCKO2 output enable/disable MCKO1 output enable/disable SCKO1 output enable/disable SCKO3 output enable/disable SCKO2 output enable/disable SCKO0 output enable/disable Sampling rate select Sampling frequency select
FS[2:1]: Sampling Frequency Group Select
FS2 0 0 1 1 FS1 0 1 0 1 SAMPLING FREQUENCY 48 kHz (default) 44.1 kHz 32 kHz Reserved
SR[2:1]: Sampling Rate Select
SR2 0 0 1 1 SR1 0 1 0 1 SAMPLING RATE Standard (default) Double Half Reserved
CE [6:1]: Clock Output Control
CE1–CE6 0 1 CLOCK OUTPUT CONTROL Clock output disable Clock output enable (default)
While all the bits of CE [6:1] are 0, the PLL1708 goes into the power-down mode, all dynamic operation including PLLs and the oscillator halts, but serial mode control is enabled for resumption.
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SLES065 – DECEMBER 2002
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Configuration Register
D15 0 D14 1 D13 1 D12 0 D11 1 D10 1 D9 RSV D8 RSV D7 RSV D6 RSV D5 RSV D4 CFG1 D3 RSV D2 RSV D1 RSV D0 RSV
Table 7. Configuration Register Mapping
REGISTER Configuration BIT NAME RSV CFG1 DESCRIPTION Reserved, must be 0 SCKO1 configuration
CFG1: SCKO1 Configuration Control
CFG1 0 1 CONFIGURATION 1 36.864 MHz, 24.576 MHz for SCKO1 (default) 18.432 MHz, 12.288 MHz for SCKO1
The system clock SCKO1 frequency can be selected by CSEL (pin 12) and CFG1 (register).
CFG1 (REGISTER) 0 0 1 1 CSEL (PIN 12) LOW HIGH LOW HIGH SCKO1 36.864 MHz 24.576 MHz 18.432 MHz 12.288 MHz
CONNECTION DIAGRAM
Figure 15 shows the typical connection circuit for the PLL1707. There are four grounds for digital and analog power supplies. However, the use of one common ground connection is recommended to avoid latch-up or other power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.
MPEG-2 APPLICATIONS
Typical applications for the PLL1707/8 are MPEG-2 based systems such as DVD recorders, HDD recorders, DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1707/8 provides audio system clocks for a CD-DA DSP, DVD DSP, Karaoke DSP, ADC(s), and DAC(s) from a 27-MHz video clock.
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
3.3 V
(2) PLL1707/8 1 2 (1) 3 4 (4) 5 6 7 8 (2) (1) 9 FS1 (MD) FS2 (MC) SR(MS) VCC AGND DGND2 MCKO2 MCKO1 VDD2 CSEL XT2 16 15 (1) 14 13 12 11 SCKO3 DGND1 SCKO0 DGND3 18 17 VDD1 SCKO2 VDD3 SCKO1 20 19 (1)
10 XT1
(3)
(3)
Clock Outputs (5) (1) 0.1-µF ceramic capacitor typical, depending on quality of power supply and pattern layout (2) 10-µF aluminum electrolytic capacitor typical, depending on quality of power supply and pattern layout (3) 27-MHz quartz crystal and 10–33 pF × 2 ceramic capacitors, which generate the appropriate amplitude of oscillation on XT1/XT2 (4) This connection is for PLL1707 (parallel mode); when PLL1708 (serial mode) is to be used, control pins must be connected to serial interfaced controller. (5) For good jitter performance, minimize the load capacitance on the clock output. It is recommended to drive the clock outputs through buffers, especially if there are heavy loads on SCKO0 and SCKO1, and to minimize mutual interference by separating them or inserting a guard pattern between them.
Figure 15. Typical Connection Diagram
17
PLL1707 PLL1708
SLES065 – DECEMBER 2002
www.ti.com
BLOCK DIAGRAM OF DVD PLAYER APPLICATION
PLL1707/8 SCKO3 384 fS
27 MHz Crystal
SCKO2 MCKO1/2 SCKO0
256 fS 27 MHz
Front CD-DA/ DVD DSP MPEG/AC-3 Audio Decoder Surround PCM/DSD1608 Center, Subwoofer Down Mix
BLOCK DIAGRAM OF HDD+DVD RECORDER APPLICATION
MPEG Encoder
PCM1802
SCKO1 PLL1707/8 MCKO1/2 XTI
SCKO2, 3
MPEG Decoder
PCM1742
27-MHz Master Clock
18
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PLL1707 PLL1708
SLES065 – DECEMBER 2002
MECHANICAL DATA
DBQ (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
0.025 (0,64) 24
0.012 (0,30) 0.008 (0,20) 13
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane 1 A 0°–8° 0.069 (1,75) MAX 0.035 (0,89) 0.016 (0,40) 12 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
16 0.197 (5,00) 0.189 (4,80)
20 0.344 (8,74) 0.337 (8,56)
24 0.344 (8,74) 0.337 (8,56)
28 0.394 (10,01) 0.386 (9,80)
A MIN
D
M0–137 VARIATION
AB
AD
AE
AF
4073301/F 02/02 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO–137.
19
MECHANICAL DATA
MSOI004E JANUARY 1995 – REVISED MAY 2002
DBQ (R–PDSO–G**)
PLASTIC SMALL–OUTLINE PACKAGE
0.025 (0,64) 24
0.012 (0,30) 0.008 (0,20) 13
0.005 (0,13)
0.157 (3,99) 0.150 (3,81)
0.244 (6,20) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane 1 A 0°–8° 0.069 (1,75) MAX 0.035 (0,89) 0.016 (0,40) 12 0.010 (0,25)
Seating Plane 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
16 0.197 (5,00) 0.189 (4,80)
20 0.344 (8,74) 0.337 (8,56)
24 0.344 (8,74) 0.337 (8,56)
28 0.394 (10,01) 0.386 (9,80)
A MIN
D
M0–137 VARIATION
AB
AD
AE
AF
4073301/F 02/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO–137.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0°– 8° 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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