PT4855A

PT4850 Series 25-A Triple Output Isolated DC/DC Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 Features • Triple Logic Voltage Outputs (Independently Regulated !) • Input Voltage Range: 36V to 75V • 1500VDC Isolation • Over-Current Protection • Over-Voltage Protection • Over-Temperature Shutdown • Under-Voltage Lockout • Independently Adjustable Outputs Description • Dual Logic On/Off Control • Fixed Frequency Operation • Solderable Space Saving Package: 1.97 sq. in. PCB Area (suffix N) • IPC Lead Free 2 • Safety Approvals Pending: UL60950 CSA 22.2 950 VDE EN60950 Ordering Information The PT4850 Excalibur™ power modules are a series of isolated tripleoutput DC/DC converters that operate from a standard (–48V) central office supply. These modules are rated for a combined output of up to 25A, and were designed for powering mixed logic applications. The triple-output voltage provides a compact multiple-output power supply in a single DC/DC module. Output voltage options include a low-voltage output for a DSP or ASIC core, and two additional supply voltages for the I/O, and other functions. The PT4850 series incorporates many features to simplify system integration. These include a flexible On/Off enable control, input undervoltage lockout and over-temperature protection. All outputs are current limited and short-circuit protected, and are internally sequenced to meet the power-up and power-down requirements of popular DSP ICs. The PT4850 series is housed in a space-saving solderable case. The module requires no external heat sink. Both vertical and horizontal pin configurations are available, including surface mount. PT4851o PT4852o PT4853o PT4854o PT4855o PT4856o = = = = = = +3.3/+2.5/+1.5V +3.3/+1.8/+1.5V +3.3/+2.5/+1.2V +3.3/+1.8/+1.2V +3.3/+1.5/+1.2V +5.0/+3.3/+1.5V PT Series Suffix (PT1234 x ) Case/Pin Configuration Vertical Horizontal SMD Order Suffix Package Code N A C (EKD) (EKA) (EKC) (Reference the applicable package code drawing for the dimensions and PC layout) Standard Application PT4850 I/O +Vo1 9,10,11 +VIN 1 +VIN V1 Adj 8 + Co1 COM 12,13,14 V2Sense +Vo2 + CIN 4 Q1 3 EN 2 V2 Adj 1 =Inhibit 2 Logic 15,16 17 + DSL, DSP, or ASIC Chipset Co2 EN 1 V3Sense –VIN 25 24 Core +Vo3 22,23 –VIN V3 Adj 21 + Co3 COM 18,19,20 Cin =Optional Co1 , Co2 , Co3 =Optional. See specifications EN1 & EN2 operation: See application notes For technical support and more information, see inside back cover or visit www.ti.com PT4850 Series 25-A Triple Output Isolated DC/DC Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 Environmental Specifications Characteristics Symbols Operating Temperature Range Case Temperature Storage Temperature Over Temperature Protection Mechanical Shock Ta Tc Ts OTP Mechanical Vibration Weight Flammability — — Conditions Min Typ Max Units Over Vin Range –40 — –40 — — — — 110 +85 (i) 105 +125 125 °C °C °C °C — 500 — G’s — — — 10 (ii) 20 (ii) 90 — — — grams — Case temperature Per Mil-STD-883D, Method 2002.3 1 msec, ½ Sine, mounted Mil-STD-883D, Method 2007.2 20-2000 Hz Vertical/Horizontal Meets UL 94V-O Suffix N Suffix A, C G’s Notes: (i) See SOA curves or consult factory for appropriate derating. (ii) The case pins on through-hole pin configurations (N & A) must be soldered. For more information see the applicable package outline drawing. Pin Configuration On/Off Enable Logic Pin Function Pin Function Pin Function Pin 3 Pin 4 Output Status 1 +Vin 10 +Vo1 19 COM 1 × Off 2 –Vin 11 +Vo1 20 COM 0 1 On 3 EN 1 12 COM 21 Vo3 Adjust 4 EN 2 13 COM 22 +Vo3 × 0 Off 5 TEMP 14 COM 23 +Vo3 6 Pin Not Present 15 +Vo2 24 Vo3 Rem Sense 7 Do Not Connect 16 +Vo2 25 Vo2 Rem Sense 8 Vo1 Adjust 17 Vo2 Adjust 26 Do Not Connect 9 +Vo1 18 COM Notes: Logic 1 =Open circuit Logic 0 = –Vin (pin 2) potential For positive Enable function, connect pin 3 to pin 2 and use pin 4. For negative Enable function, leave pin 4 open and use pin 3. Note: Shaded functions indicate those pins that are at primary-side potential. Pin Descriptions +Vin: The positive input supply for the module with respect to –Vin. When powering the module from a –48V telecom central office supply, this input is connected to the primary system ground. –Vin: The negative input supply for the module, and the 0VDC reference for the EN 1, and EN 2 inputs. When powering the module from a +48V supply, this input is connected to the 48V(Return). EN 1: The negative logic input that activates the module output. This pin must be connected to –Vin to enable the module’s outputs. A high impedance disables the module’s outputs. EN 2: The positive logic input that activates the module output. If not used, this pin should be left open circuit. Connecting this input to –Vin disables the module’s outputs. TEMP: This pin produces an output signal that tracks a temperature that is approximately the module’s metal case. The output voltage is referenced to –Vin and rises approximately 10mV/°C from an intital value of 0.1VDC at –40°C. The signal is available whenever the module is supplied with a valid input voltage, and is independant of the enable logic status. (Note: A load impedance of less than 1MΩ will adversly affect the module’s over-temperature shutdown threshold. Use a high-impedance input when monitoring this signal.) Vo 1: The highest regulated output voltage, which is referenced to the COM node. Vo 2: The regulated output that is designed to power logic circuitry. It is referenced to the COM node. Vo 3: The low-voltage regulated output that provides power for a µ-processor or DSP core, and is referenced to the COM node. COM: The secondary return reference for the module’s three regulated output voltages. It is DC isolated from the input supply pins. Vo(n) Adjust: Using a single resistor, this pin allows the associated output Vo(n) to be adjusted higher or lower than the preset value. If not used, this pin should be left open circuit. Vo(n) Rem Sense: An external remote sense input is provided for the two lowest voltage outputs, +Vo2 and +Vo3. Connecting the remote sense pins improves the load regulation of the applicable output by allowing the regulation circuit to compensate for voltage drop between the converter and load. If desired these inputs may be left disconnected. For technical support and more information, see inside back cover or visit www.ti.com PT4850 Series 25-A Triple Output Isolated DC/DC Converter For Logic Applications Electrical Specifications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 (Unless otherwise stated, the operating conditions are:- Ta =25°C, V in =48V, and I o =0.5Io max) Characteristics Symbols Output Current Io Each output Input Voltage Range Iotot Vin Total (all three outputs) Continuous Surge (1 minute) Set-Point Voltage Tolerance Temperature Variation Line Regulation Load Regulation Cross Regulation Total Output Voltage Variation Votol ∆Regtemp ∆Regline ∆Regload ∆Regcross ∆Vo tol Efficiency Vo Ripple (pk-pk) η Vr PT4850 Series (Except PT4856) Min Typ Max Conditions Io1 Io2 Io3 Output Adjust Range Current Limit Threshold ttr Vos Voadj ILIM Output Over-Voltage Protection Switching Frequency OVP ƒs –40°C ≤Ta ≤+85°C, Io1 =Io2 =Io3 =Iomin All outputs, Over Vin range Each output, 0≤Io≤Iomax Any output vs. another Includes set-point, line, load, –40°C ≤Ta ≤+85°C Io1 =10A, Io2 =5A, Io3 =5A 20MHz bandwidth, Vo =5.0V Vo =3.3V Io1 =Io2 =Io3 =5A Vo =1.8V/2.5V Vo ≤1.5V 0.1A/µs load step, 50% to 75% Iomax Vo over/undershoot Vo1/Vo2/Vo3 ∆Vo = –1% Vo1 Vo2 Vo3 All outputs; module shutdown and latch off Over Vin and Io ranges Under Voltage Lockout Von Voff Vin increasing Vin decreasing Transient Response Enable Control (pins 3 & 4) High-Level Input Voltage Low-Level Input Voltage Low-Level Input Current VIH VIL IIL Standby Input Current Iin standby — — — — — — — ±0.5 ±0.2 ±5 — 15 10 10 25 75 80 1.5 — ±0.5 ±10 ±10 — ±2 ±3 — — — — — — — — — — — — 280 85 50 20 20 15 200 5 ±10 20 15 15 125 (2) 320 — 75 50 30 25 — — — — — — — 340 — 30 34 32 36 — 3.5 –0.2 — — Units A A V %Vo %Vo %Vo mV mV (1) %Vo % mVpp µSec %Vo %Vo A %Vo kHz V Referenced to –Vin (pin 2) Internal Input Capacitance Cint External Output Capacitance Primary/Secondary Isolation Cout V iso C iso R iso Vtemp Temperature Sense 0 0 0 — 36 — — — — — — Open (3) 0.8 (3) V — 0.5 — mA pins 3 & 4 open circuit — 2.5 4 mA — 2 Per each output 0 1500 — 10 — — — — 2,200 — 0.1 (4) 1.5 (4) Output voltage at temperatures:- –40°C 100°C (1) — µF 5,000 — — — — — µF V pF MΩ V Notes: (1) Limits are specified by design. (2) This is a fixed parameter. Adjusting Vo1 or Vo2 higher will increase the module’s sensitivity to over-voltage detection. For more information, see the application note on output voltage adjustment. (3) The Enable inputs (pins 3 & 4) have internal pull-ups. Leaving pin 4 open-circuit and connecting pin 3 to –V in (pin 2) allows the the converter to operate when input power is applied. The maximum open-circuit voltage for the Enable inputs is 5.4V. (4) Voltage output at “TEMP” pin is defined by the equation:- VTEMP = 0.5 + 0.01·T, where T is in °C. See pin descriptions for more information. For technical support and more information, see inside back cover or visit www.ti.com Typical Characteristics PT4850 Series 25-A Triple Output Isolated DC/DC Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 PT4851 Performance Characteristics (See Note A) (Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load) PT4852 Performance Characteristics Efficiency vs Output Load Efficiency vs Output Load 90 90 80 80 VIN Efficiency - % Efficiency - % (See Note A) (Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load) 36V 48V 75V 70 60 VIN 36V 48V 75V 70 60 50 50 0 20 40 60 80 0 100 20 Output Load (%) 40 60 80 100 Output Load (%) Power Dissipation vs Output Load Power Dissipation vs Output Load 16 16 12 12 VIN Pd - Watts Pd - Watts VIN 75V 48V 36V 8 4 36V 48V 75V 8 4 0 0 0 20 40 60 80 100 0 20 Output Load (%) PT4851 Safe operating Area Curves (See Note B) (Io1 + Io2 + Io3 =25A, represents 100% load) 60 80 PT4852 Safe operating Area Curves 100 (See Note B) (Io1 + Io2 + Io3 =25A, represents 100% load) SOA vs Output Power @Vin =48V SOA vs Output Power @Vin =48V 90 90 80 80 Airflow 70 500LFM 400LFM 300LFM 200LFM 100LFM Nat conv 60 50 40 30 Ambient Temperature (°C) Ambient Temperature (°C) 40 Output Load (%) Airflow 70 500LFM 400LFM 300LFM 200LFM 100LFM Nat conv 60 50 40 30 20 20 0 20 40 60 Output Load (%) 80 100 0 20 40 60 80 100 Output Load (%) Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures. For technical support and more information, see inside back cover or visit www.ti.com Typical Characteristics PT4850 Series 25-A Triple Output Isolated DC/DC Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 PT4853 Performance Characteristics (See Note A) (Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load) PT4854 Performance Characteristics Efficiency vs Output Load Efficiency vs Output Load 90 90 80 VIN 36V 48V 75V 70 Efficiency - % 80 Efficiency - % (See Note A) (Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load) 60 VIN 36V 48V 75V 70 60 50 50 0 20 40 60 80 100 0 20 Output Load (%) 40 60 80 100 Output Load (%) Power Dissipation vs Output Load Power Dissipation vs Output Load 16 16 12 12 36V 48V 75V 8 VIN Pd - Watts Pd - Watts VIN 4 75V 48V 36V 8 4 0 0 0 20 40 60 80 100 0 20 Output Power (%) PT4853 Safe operating Area Curves (See Note B) (Io1 + Io2 + Io3 =25A, represents 100% load) 60 80 PT4854 Safe operating Area Curves 100 (See Note B) (Io1 + Io2 + Io3 =25A, represents 100% load) SOA vs Output Power @Vin =48V SOA vs Output Power @Vin =48V 90 90 80 Airflow 70 500LFM 400LFM 300LFM 200LFM 100LFM Nat conv 60 50 40 30 Ambient Temperature (°C) 80 Ambient Temperature (°C) 40 Output Load (%) Airflow 70 500LFM 400LFM 300LFM 200LFM 100LFM Nat conv 60 50 40 30 20 20 0 20 40 60 80 100 0 Output Load (%) 20 40 60 80 100 Output Load (%) Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures. For technical support and more information, see inside back cover or visit www.ti.com Typical Characteristics PT4850 Series 25-A Triple Output Isolated DC/DC Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 PT4855 Performance Characteristics (See Note A) (Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load) Efficiency vs Output Load 90 Efficiency - % 80 VIN 36V 48V 75V 70 60 50 0 20 40 60 80 100 Output Load (%) Power Dissipation vs Output Load 16 12 Pd - Watts VIN 75V 48V 36V 8 4 0 0 20 40 60 80 100 Output Load (%) PT4855 Safe operating Area Curves (See Note B) (Io1 + Io2 + Io3 =25A, represents 100% load) SOA vs Output Power @Vin =48V 90 Ambient Temperature (°C) 80 Airflow 70 500LFM 400LFM 300LFM 200LFM 100LFM Nat conv 60 50 40 30 20 0 20 40 60 80 100 Output Load (%) Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures. For technical support and more information, see inside back cover or visit www.ti.com PT4856 25-A Triple Output Isolated DC/DC Converter For Logic Applications PT4856 Electrical Specifications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 (Unless otherwise stated, the operating conditions are:- Ta =25°C, V in =48V, and I o =0.5Io max) Characteristics Symbols Output Current Io Each output Input Voltage Range Iotot Vin Total (all three outputs) Continuous Surge (1 minute) Set-Point Voltage Tolerance Temperature Variation Line Regulation Load Regulation Cross Regulation Total Output Voltage Variation Votol ∆Regtemp ∆Regline ∆Regload ∆Regcross ∆Vo tol Efficiency Vo Ripple (pk-pk) η Vr Transient Response Output Adjust Range Current Limit Threshold ttr Vos Voadj ILIM Output Over-Voltage Protection Switching Frequency OVP ƒs –40°C ≤Ta ≤+85°C, Io1 =Io2 =Io3 =Iomin All outputs, Over Vin range Each output, 0≤Io≤Iomax Any output vs. another Includes set-point, line, load, –40°C ≤Ta ≤+85°C Io1 =7A, Io2 =5A, Io3 =5A 20MHz bandwidth, Vo =5.0V Vo =3.3V Io1 =Io2 =Io3 =5A Vo =1.5V 0.1A/µs load step, 50% to 75% Iomax Vo over/undershoot Vo1/Vo2/Vo3 ∆Vo = –1% Vo1 Vo2 Vo3 All outputs; module shutdown and latch off Over Vin and Io ranges Under Voltage Lockout Von Voff Vin increasing Vin decreasing Enable Control (pins 3 & 4) High-Level Input Voltage Low-Level Input Voltage Low-Level Input Current VIH VIL IIL Standby Input Current Iin standby Min Io1 Io2 Io3 PT4856 (Only) Typ Max 0 0 0 — 36 — — — — — — — — — — — — — ±0.5 ±0.2 ±5 — 10 10 10 25 75 80 1.5 — ±0.5 ±10 ±10 — ±2 ±3 — — — — — — — — — — — 280 88 50 20 15 200 5 ±10 20 15 15 125 (2) 320 — 75 50 25 — — — — — — — 340 — 30 34 32 36 — 3.5 –0.2 — — Units A A V %Vo %Vo %Vo mV mV (1) %Vo % mVpp µSec %Vo %Vo A %Vo kHz V Referenced to –Vin (pin 2) Internal Input Capacitance Cint External Output Capacitance Primary/Secondary Isolation Cout V iso C iso R iso Vtemp Temperature Sense Conditions Open (3) 0.8 (3) V — 0.5 — mA pins 3 & 4 open circuit — 2.5 4 mA — 2 Per each output 0 1500 — 10 — — — — 2,200 — 0.1 (4) 1.5 (4) Output voltage at temperatures:- –40°C 100°C (1) — µF 5,000 — — — — — µF V pF MΩ V Notes: (1) Limits are specified by design. (2) This is a fixed parameter. Adjusting Vo1 or Vo2 higher will increase the module’s sensitivity to over-voltage detection. For more information, see the application note on output voltage adjustment. (3) The Enable inputs (pins 3 & 4) have internal pull-ups. Leaving pin 4 open-circuit and connecting pin 3 to –V in (pin 2) allows the the converter to operate when input power is applied. The maximum open-circuit voltage for the Enable inputs is 5.4V. (4) Voltage output at “TEMP” pin is defined by the equation:- VTEMP = 0.5 + 0.01·T, where T is in °C. See pin descriptions for more information. For technical support and more information, see inside back cover or visit www.ti.com Typical Characteristics PT4856 25-A Triple Output Isolated DC/DC Converter For Logic Applications SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003 PT4856 Performance Characteristics (See Note A) (Io1 =10A, Io2 =7.5A, Io3 =7.5A represents 100% Load) Efficiency vs Output Load 100 Efficiency - % 90 VIN 80 36V 48V 75V 70 60 50 0 20 40 60 80 100 Output Load (%) Power Dissipation vs Output Load 25 20 Pd - Watts VIN 15 75V 48V 36V 10 5 0 0 20 40 60 80 100 Output Load (%) PT4856 Safe operating Area Curves (See Note B) (Io1 + Io2 + Io3 =24A, represents 100% load) SOA vs Output Power @Vin =48V 90 Ambient Temperature (°C) 80 Airflow 70 300LFM 200LFM 100LFM Nat Conv 60 50 40 30 20 0 20 40 60 80 100 Output Power (W) Note A: All Characteristic data in the above graphs has been developed from actual products tested at 25°C. This data is considered typical data for the ISR. Note B: SOA curves represent operating conditions at which the internal components are at or below the manufacturer’s maximum rated operating temperatures. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT4850 Series Operating Features of the PT4850 Triple-Output DC/DC Converters Over-Current Protection Primary-Secondary Isolation The PT4850 series of DC/DC converters provide three independently regulated logic output voltages, Vo1, Vo2, and Vo3. Each output is current limited to protect against load faults. The module will not be damaged by a continuous load fault applied to any output. Current will continue to flow into the fault but is reduced as the voltage across the fault decreases towards zero. The PT4850 series of DC/DC converters incorporate electrical isolation between the input terminals (primary) and the output terminals (secondary). All converters are production tested to a withstand voltage of 1500VDC. The isolation complies with UL60950 and EN60950, and the requirements for operational isolation. This allows the converter to be configured for either a positive or negative input voltage source. Applying a load fault above the current limit threshold to any output causes the affected output to significantly drop. Also load faults applied to Vo1 will affect Vo2 and Vo3, once Vo 1 drops to within 0.2V of either of these voltages. However, load faults applied to Vo2 or Vo3 will not affect the other outputs. Over-Temperature Protection The PT4850 DC/DC converter series have an internal temperature sensor, which monitors the temperature of the module’s metal case. If the case temperature exceeds the specified limit the converter will shut down. The converter will automatically restart when the sensed temperature returns to within the normal operating range. The analog voltage generated by the sensor is also made available at the ‘TEMP’ output (pin 5), and can be monitored by the host system for diagnostic purposes. Consult the ‘Pin Descriptions’ section of the data sheet for more information on this feature. The regulation control circuitry for these modules is located on the secondary (output) side of the isolation barrier. Control signals are passed between the primary and secondary sides of the converter via a proprietory magnetic coupling scheme. This eliminates the use of opto-couplers. The data sheet ‘Pin Descriptions’ and ‘Pin-Out Information’ provides guidance as to which reference (primary or secondary) that must be used for each of the external control signals. Fuse Recommendations If desired an input fuse may be added to protect against the application of a reverse input voltage. Under-Voltage Lock-Out The Under-Voltage Lock-Out (UVLO) circuit prevents operation of the converter whenever the input voltage to the module is insufficient to maintain output regulation. The UVLO has approximately 2V of hysterisis. This is to prevent oscillation with a slowly changing input voltage. Below the UVLO threshold the module is off and the enable control inputs, EN1 and EN2 are inoperative. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT4850 Series Using the On/Off Enable Controls on the PT4850 Series of Triple Output DC/DC Converters The PT4850 (48V input) series of 25-A, triple-output DC/DC converters incorporate two output enable controls. EN1 (pin 3) is the Negative Enable input, and EN2 (pin 4) is the Positive Enable input. Both inputs are electrically referenced to -Vin (pin 2) on the primary or input side of the converter. A pull-up resistor is not required, but may be added if desired. Voltages of up to 70V can be safely applied to the either of the Enable pins. pin 3 in order to enable the outputs of the converter. An example of this configuration is detailed in Figure 2. Note: The converter will only produce and output voltage if a valid input voltage is applied to ±Vin. Figure 2; Negative Enable Configuration DC/DC Module 4 3 EN 2 EN 1* BSS138 Automatic (UVLO) Power-Up Connecting EN1 (pin 3) to -Vin (pin 2) and leaving EN2 (pin 4) open-circuit configures the converter for automatic power up. (See data sheet “Typical Application”). The converter control circuitry incorporates an “Under Voltage Lockout” (UVLO) function, which disables the converter until the minimum specified input voltage is present at ±Vin. (See data sheet Specifications). The UVLO circuitry ensures a clean transition during power-up and power-down, allowing the converter to tolerate a slowrising input voltage. For most applications EN1 and EN2, can be configured for automatic power-up. Positive Output Enable (Negative Inhibit) To configure the converter for a positive enable function, connect EN1 (pin 3) to -Vin (pin 2), and apply the system On/Off control signal to EN2 (pin 4). In this configuration, a low-level input voltage (-Vin potential) applied to pin 4 disables the converter outputs. Figure 1 is an example of this configuration. 1 =Outputs On –VIN 2 –Vin On/Off Output Voltage Sequencing The power-up characteristic of the PT4850 series of DC/DC converters meets the requirements of microprocessor and DSP chipsets. All three outputs from the converter are internally sequenced to power up in unison. Figure 3 shows the waveforms from a PT4851 after power is applied to the input of the converter. During power-up, all three output voltages rise together until each reaches their respective output voltage. The waveforms of Figure 3 were measured with loads of approximately 50% on each output, with an input source of 48VDC. The converter typically produces a fully regulated output within 150ms. Figure 3; Vo1, Vo2, Vo3 Power-Up Sequence Vo1 (1V/Div) Figure 1; Positive Enable Configuration V02 (1V/Div) Vo3 (1V/Div) DC/DC Module 4 3 BSS138 EN 2 EN 1* 1 =Outputs Off –VIN 2 –Vin HORIZ SCALE: 20ms/Div Negative Output Enable (Positive Inhibit) To configure the converter for a negative enable function, EN2 (pin 4) is left open circuit, and the system On/Off control signal is applied to EN1 (pin 3). A low-level input voltage (-Vin potential) must then be applied to During turn-off, all outputs drop rapidly due to the discharging effect of actively switched rectifiers. The voltage at Vo 2 remains higher than Vo3 during this period. The discharge time is typically 100µs, but will vary with the amount of external load capacitance. For technical support and more information, see inside back cover or visit www.ti.com Application Notes PT4850 Series Adjusting the Output Voltages of the PT4850 Triple-Output DC/DC Converters The output voltages of the PT4850 series of triple-output DC/DC converters, Vo1, Vo2 and Vo3, are independently adjustable. The adjustment method uses a single external resistor, 1 which may be used to adjust a selected output by up to ±10% from the factory preset value. The value of the resistor determines the magnitude of adjustment, and the placement of the resistor determines the direction of adjustment (up or down). The resistor values can be calculated using the appropriate formula (see below), using the constants provided in Table 3-2. Alternatively the resistor value may be selected directly from Table 3-3 and Table 3-4, for Vo1 and Vo2/Vo3 respectively. The placement of each resistor is as follows. Table 3-1; Adjust Resistor Pin Connections To Adjust Up Connect R1 from to Vox Adj To Adjust Down Connect (R2) from to COM Vox Adj Vox Vo1 8 12 8 9 Vo2 17 18 17 16 Vo3 21 18 21 22 Calculation of Adjust Values Adjust Up: To increase a specific output, add a resistor R1 between the appropriate Vx Adj (V1 Adj, V2 Adj, or V3 Adj) and the output common (COM). See Figure 3-1(a) and Table 3-1 for the resistor placement and pin connections. The adjust resistor value may also be calculated using an equation. In each case, the equation for R1 [Adjust Up] is different to that for (R2) [Adjust Down]. For the PT4850 series, the following points should be noted. • Vo1 uses different equations to Vo2 and Vo3. The equations are defined for the desired output voltage. Figure 3-1a PT4850 +Vo x # +Vox • The equations for Vo 2 and Vo3 are based on the percentage of desired adjustment. Both Vo2 and Vo3 use the same constants, which are common for all output voltages. (Adjusted Up) Vo1 Adjust: +Vx Adj # R1 [Adjust Up] 3 = (R2) [Adjust Down] 3 = 2.5 Ro Va – Vo – Rs kΩ Ro (Va – 2.5 ) – Rs Vo – Va kΩ R1 COM Output Common # # - See Table 3-1 for pin connections, where Vo x equals Vo 1, Vo 2, or Vo 3 Adjust Down: Add a resistor (R2), between the appropriate Vx Adj (V1 Adj, V2 Adj, or V3 Adj) and the output being adjusted, +Vox. See Figure 3-1(b) and Table 3-1 for the resistor placement and pin connections. Figure 3-1b Where: Vo Va Ro Rs = = = = Vo2 / Vo3 Adjust: R1 [Adjust Up] 3 PT4850 +Vo x # +Vox (R2) +Vx Adj COM = (R2) [Adjust Down] 3 = (Adjusted Down) 50 · Ro n% Ro · –Rs (50 – n%) –Rs n% kΩ kΩ Where: R o = The resistance value in Table 3-2 R s = The series resistance from Table 3-2 n% = The desired adjustment from the nominal (in percent) # # Original output voltage Adjusted output voltage The resistance value in Table 3-2 The series resistance from Table 3-2 Output Common # - See Table 3-1 for pin connections, where Vo x equals Vo 1, Vo 2, or Vo 3 For technical support and more information, see inside back cover or visit www.ti.com Application Notes continued PT4850 Series Notes: 1. Use only a single 1% (or better) tolerance resistor in either the R1 or (R2) location to adjust a specific output. Place the resistor as close to the ISR as possible. 2. Never connect capacitors to any of the ‘Vox Adj’ pins. Any capacitance added to these control pins will affect the stability of the respective regulated output. 3. Adjustments made to any output must also comply with the following limitations. ≥ (Vo2 + 0.5V), and ≥ (Vo3 + 0.5V) Vo1 Vo1 Table 3-2 ADJUSTMENT RANGE AND FORMULA PARAMETERS Vo1 Bus Vo(nom) Va(min) Va(max) Ro (kΩ) Ω) Rs (kΩ 5.0V 4.5V 5.5V 4.99 4.99 Vo2 / Vo3 Bus 3.3V 2.97V 3.63V 4.42 4.99 All Vnom – 10% Vnom + 10% 2.1 4.99 Table 3-3 ADJUSTMENT RESISTOR VALUES FOR Vo1 Bus Table 3-4 ADJUSTMENT RESISTOR VALUES FOR Vo2 / Vo3 Buses Adj. Resistors Vo (nom) % Adjust –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 Vo(nom) Va(req’d) 3.0 3.05 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6 • 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 R1/(R 2) 3.3V 5.0V (2.4)kΩ (4.7)kΩ (8.3)kΩ (14.2)kΩ (26.0)kΩ (61.3)kΩ 216.0kΩ 106.0kΩ 68.7kΩ 50.3kΩ 39.2kΩ 31.8kΩ (15.0)kΩ (21.2)kΩ (31.6)kΩ (52.4)kΩ (115.0)kΩ 120.0kΩ 57.4kΩ 36.6kΩ 26.2kΩ 20.0kΩ 3.3V 2.5V 1.8V 1.5V 1.2V ——————— Adjusted Output Voltage ——————— 2.97 2.25 1.62 1.35 1.08 3.003 2.275 1.638 1.365 1.092 3.036 2.3 1.656 1.38 1.104 3.069 2.325 1.674 1.395 1.116 3.102 2.35 1.692 1.41 1.128 3.135 2.375 1.71 1.425 1.14 3.168 2.4 1.728 1.44 1.152 3.201 2.425 1.746 1.455 1.64 3.234 2.45 1.764 1.47 1.176 3.267 2.475 1.782 1.485 1.188 3.3 2.5 1.8 1.5 1.2 3.333 2.525 1.818 1.515 1.212 3.366 2.55 1.836 1.53 1.224 3.399 2.575 1.854 1.545 1.236 3.432 2.6 1.872 1.56 1.248 3.465 2.625 1.89 1.575 1.26 3.498 2.65 1.908 1.58 1.272 3.531 2.675 1.926 1.605 1.284 3.564 2.7 1.944 1.62 1.296 3.597 2.725 1.962 1.635 1.308 3.630 2.75 1.98 1.65 1.32 R1 = Black, R2 = (Blue) R1 = Black, R2 = (Blue) For technical support and more information, see inside back cover or visit www.ti.com R1/(R 2) (3.4)kΩ (4.6)kΩ (6.0)kΩ (7.9)kΩ (10.4)kΩ (13.9)kΩ (19.2)kΩ (27.9)kΩ (45.4)kΩ (97.9)kΩ 100.0kΩ 47.5kΩ 30.0kΩ 21.3kΩ 16.0kΩ 12.5kΩ 10.0kΩ 8.1kΩ 6.7kΩ 5.5kΩ PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) PT4851A NRND SIP MODULE EKA 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4851C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available PT4851N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4852A NRND SIP MODULE EKA 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4852C NRND SIP MODULE EKC 26 TBD Call TI Level-3-215C-168HRS Samples Not Available PT4852N NRND SIP MODULE EKD 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4853A NRND SIP MODULE EKA 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4853C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available PT4853N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4854A NRND SIP MODULE EKA 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4854C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available PT4854N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4855A NRND SIP MODULE EKA 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4855C NRND SIP MODULE EKC 26 TBD Call TI Level-3-215C-168HRS Samples Not Available PT4855N NRND SIP MODULE EKD 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available 6 PT4856A NRND SIP MODULE EKA 26 TBD Call TI Level-1-215C-UNLIM Samples Not Available PT4856C NRND SIP MODULE EKC 26 6 TBD Call TI Level-3-215C-168HRS Samples Not Available PT4856N NRND SIP MODULE EKD 26 6 TBD Call TI Level-1-215C-UNLIM Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2010 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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