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THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3A – MAY 2018 – REVISED MAY 2018
THVD14xx 3.3-V to 5-V RS-485 Transceivers With ±18-kV IEC ESD Protection
1 Features
•
1
•
•
•
•
•
•
•
•
•
•
•
Meets or Exceeds the Requirements of the
TIA/EIA-485A Standard
3 V to 5.5 V Supply Voltage
Bus I/O ESD Protection
– ±30 kV HBM
– ±18 kV IEC 61000-4-2 Contact Discharge
– ±18 kV IEC 61000-4-2 Air-Gap Discharge
– ±4 kV IEC 61000-4-4 Fast Transient Burst
Extended Operational Common-mode
Range: ±15 V
Low EMI 500 kbps and 50 Mbps Data Rates
Large Receiver Hysteresis for Noise Rejection
Low Power Consumption
– Standby Supply Current: < 1 µA
– Current During Operation: < 3 mA
Extended Ambient Temperature
Range: –40°C to 125°C
Glitch-Free Power-Up/Down for Hot Plug-in
Capability
Open, Short, and Idle Bus Failsafe
1/8 Unit Load (Up to 256 Bus Nodes)
Small-Size VSON and VSSOP Packages Save
Board Space or SOIC for Drop-in Compatibility
Each of these devices operates from a single supply
between 3 V and 5.5 V. The devices in this family
feature an extended common-mode voltage range
which makes them suitable for multi-point
applications over long cable runs.
THVD14xx family of devices is available in small
VSON and VSSOP packages for space constrained
applications. These devices are characterized over
ambient free-air temperatures from –40°C to 125°C.
Device Information(1)
PART NUMBER
THVD1410
THVD1450
THVD1451
THVD1452
PACKAGE
BODY SIZE (NOM)
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSON (8)
3.00 mm × 3.00 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (8)
4.90 mm × 3.91 mm
VSON (8)
3.00 mm × 3.00 mm
VSSOP (10)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
THVD1410 and THVD1450 Simplified Schematic
R
RE
DE
D
1
2
7
3
6
B
A
4
2 Applications
•
•
•
•
•
•
•
•
Motor Drives
Factory Automation & Control
Grid Infrastructure
Building Automation
HVAC Systems
Video Surveillance
Process Analytics
Wireless Infrastructure
THVD1451 Simplified Schematic
R
D
THVD14xx is a family of noise-immune RS-485/RS422 transceivers designed to operate in rugged
industrial environments. The bus pins of these
devices are robust to high levels of IEC electrical fast
transients (EFT) and IEC electrostatic discharge
(ESD) events, eliminating the need for additional
system level protection components.
8
A
7
B
3
6
Z
5
Y
THVD1452 Simplified Schematic
R
RE
3 Description
2
DE
D
2 (1)
3 (2)
(9 ) 12
A
(8 ) 11
B
4 (3)
5 (4)
(7 ) 10
Z
(6) 9
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3A – MAY 2018 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
9
1
1
1
2
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
ESD Ratings [IEC] .................................................... 7
Recommended Operating Conditions....................... 8
Thermal Information .................................................. 8
Power Dissipation ..................................................... 8
Electrical Characteristics........................................... 9
Switching Characteristics ........................................ 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 13
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagrams ..................................... 15
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 19
10.1 Application Information...................................... 19
10.2 Typical Application ............................................... 19
11 Power Supply Recommendations ..................... 25
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 26
13 Device and Documentation Support ................. 27
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support......................................................
Third-Party Products Disclaimer ...........................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Original (November 2017) to Revision A
•
2
Page
Changed the device status From: Advanced Information To: Production data ..................................................................... 1
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SLLSEY3A – MAY 2018 – REVISED MAY 2018
5 Device Comparison Table
PART NUMBER
DUPLEX
ENABLES
SIGNALING RATE
THVD1410
Half
DE, RE
up to 500 kbps
THVD1450
Half
DE, RE
THVD1451
Full
None
THVD1452
Full
DE, RE
Copyright © 2018, Texas Instruments Incorporated
up to 50 Mbps
NODES
256
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THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3A – MAY 2018 – REVISED MAY 2018
www.ti.com
6 Pin Configuration and Functions
THVD1410, THVD1450 Devices
8-Pin D Package (SOIC)
Top View
THVD1410, THVD1450 Devices
8-Pin DGK Package (VSSOP)
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Not to scale
THVD1450 Device
8-Pin DRB Package (VSON)
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D
DGK
DRB
A
6
6
6
Bus input/output
Bus I/O port, A (complementary to B)
B
7
7
7
Bus input/output
Bus I/O port, B (complementary to A)
D
4
4
4
Digital input
Driver data input
DE
3
3
3
Digital input
Driver enable, active high (2-MΩ internal pull-down)
GND
5
5
5
Ground
R
1
1
1
Digital output
Receive data output
VCC
8
8
8
Power
3.3-V to 5-V supply
RE
2
2
2
Digital input
4
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Device ground
Receiver enable, active low (2-MΩ internal pull-up)
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Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
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SLLSEY3A – MAY 2018 – REVISED MAY 2018
THVD1451 Device
8-Pin DRB Package (VSON)
Top View
VCC
1
8
A
R
2
7
B
D
3
6
Z
GND
4
5
Y
Not to scale
Pin Functions
PIN
NAME
I/O
DRB
A
8
B
D
DESCRIPTION
Bus input
Bus input, A (complementary to B)
7
Bus input
Bus input, B (complementary to A)
3
Digital input
GND
4
Ground
R
2
Digital output
Receive data output
VCC
1
Power
3.3-V to 5-V supply
Y
5
Bus output
Digital bus output, Y (Complementary to Z)
Z
6
Bus output
Digital bus output, Z (Complementary to Y)
Copyright © 2018, Texas Instruments Incorporated
Driver data input
Device ground
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THVD1450, THVD1451, THVD1452
SLLSEY3A – MAY 2018 – REVISED MAY 2018
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THVD1452 Device
14-Pin D Package (SOIC)
Top View
THVD1452 Device
10-Pin DGS Package (VSSOP)
Top View
NC
1
14
VCC
R
2
13
VCC
RE
3
12
A
DE
4
11
B
D
5
10
Z
GND
6
9
Y
GND
7
8
NC
R
1
10
VCC
RE
2
9
A
DE
3
8
B
D
4
7
Z
GND
5
6
Y
Not to scale
Not to scale
NC – No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
D
DGS
A
12
9
Bus input
Bus input, A (complementary to B)
B
11
8
Bus input
Bus input, B (complementary to A)
D
5
4
Digital input
Driver data input
DE
4
3
Digital input
Driver enable, active high (2-MΩ internal pull-down)
6, 7 (1)
5
Ground
1, 8
—
—
2
1
Digital output
Receive data output
13, 14 (1)
10
Power
3.3-V to 5-V supply
Y
9
6
Bus output
Digital bus output, Y (Complementary to Z)
Z
10
7
Bus output
Digital bus output, Z (Complementary to Y)
RE
3
2
Digital input
Receiver enable, active low (2-MΩ internal pull-up)
GND
NC
R
VCC
(1)
6
Device ground
Internally not connected
These pins are internally connected
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SLLSEY3A – MAY 2018 – REVISED MAY 2018
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
Supply voltage
VCC
-0.5
7
V
Bus voltage
Range at any bus pin (A, B, Y, or Z) as differential
or common-mode with respect to GND
-18
18
V
Input voltage
Range at any logic pin (D, DE, or RE)
-0.3
5.7
V
Receiver output
current
IO
-24
24
mA
-65
150
℃
Storage temperature range
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001 (1)
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Bus pins and
GND
±30
kV
All other pins
±4
kV
Charged device model (CDM), per
JEDEC JESD22-C101 (2)
All pins
±1.5
kV
Machine model (MM), per JEDEC
JESD22-A115-A
All pins
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings [IEC]
V(ESD)
V(EFT)
Electrostatic discharge
Electrical fast transient
Copyright © 2018, Texas Instruments Incorporated
VALUE
UNIT
±18
kV
Air-gap discharge, per IEC 61000-4- Bus pins and
2
GND
±18
kV
Bus pins and
GND
±4
kV
Contact discharge, per IEC 610004-2
Per IEC 61000-4-4
Bus pins and
GND
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THVD1450, THVD1451, THVD1452
SLLSEY3A – MAY 2018 – REVISED MAY 2018
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7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VCC
Supply voltage
VI
Input voltage at any bus terminal (1)
NOM
MAX
UNIT
3
5.5
V
-15
15
V
VIH
High-level input voltage (driver, driver
enable, and receiver enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver
enable, and receiver enable inputs)
0
0.8
V
VID
Differential input voltage
-15
15
V
IO
Output current, driver
-60
60
mA
IOR
Output current, receiver
-8
8
mA
RL
Differential load resistance
54
1/tUI
Signaling rate: THVD1410
1/tUI
Signaling rate: THVD1450, THVD1451,
THVD1452
TA
Operating ambient temperature
TJ
Junction temperature
(1)
Ω
500
kbps
50
Mbps
-40
125
℃
-40
150
℃
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.5 Thermal Information
THERMAL METRIC
RθJA
(1)
Junction-to-ambient thermal
resistance
RθJC(to Junction-to-case (top) thermal
resistance
p)
THVD1410
THVD1450
THVD1452
THVD1410
THVD1450
THVD1452
THVD1450
THVD1451
D (SOIC)
D (SOIC)
DGK (VSSOP)
DGS (VSSOP)
DRB (VSON)
8 PINS
14 PINS
8 PINS
10 PINS
8 PINS
114.3
86.4
155.2
155.6
48.6
°C/W
56.7
43.7
47.2
49.3
49.1
°C/W
UNIT
RθJB
Junction-to-board thermal
resistance
57.7
42.5
76.1
77.1
21.1
°C/W
ΨJT
Junction-to-top characterization
parameter
12.8
10.2
3.9
4.5
0.8
°C/W
ΨJB
Junction-to-board
characterization parameter
57
42.2
74.8
75.7
21.1
°C/W
RθJC(b
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
2.7
°C/W
ot)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Power Dissipation
PARAMETE
R
PD
8
Description
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver and receiver enabled, VCC = 5.5 Unterminated: RL = 300 Ω, CL = 50 pF
V, TA = 1250C, 50% duty cycle square
RS-422 load: RL = 100 Ω, CL = 50 pF
wave at 500kbps signaling rate,
RS-485 load: RL = 54 Ω, CL = 50 pF
THVD1410
210
mW
220
mW
250
mW
Driver and receiver enabled, VCC = 5.5 Unterminated: RL = 300 Ω, CL = 50 pF
V, TA = 1250C, 50% duty cycle square
RS-422 load: RL = 100 Ω, CL = 50 pF
wave at 50Mbps signaling rate,
RS-485 load: RL = 54 Ω, CL = 50 pF
THVD145x devices
360
mW
320
mW
330
mW
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SLLSEY3A – MAY 2018 – REVISED MAY 2018
7.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC =
5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V (See Figure 8) (1)
1.5
3.5
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V, 4.5 V ≤ VCC ≤
5.5 V, (See Figure 8)
2.1
MAX
UNIT
Driver
|VOD|
Driver differential output voltage
magnitude
RL = 100 Ω (See Figure 9)
RL = 54 Ω (See Figure 9)
Δ|VOD|
Change in differential output
voltage
VOC
Common-mode output voltage
ΔVOC(SS)
Change in steady-state commonmode output voltage
IOS
Short-circuit output current
V
2
4
V
1.5
3.5
V
-200
RL = 54 Ω (See Figure 9)
1
DE = VCC, -7 V ≤ VO ≤ 12 V
V
200
VCC/2
mV
3
V
-200
200
mV
-250
250
mA
125
µA
Receiver
DE = 0 V, VCC = 0 V or 5.5 V
II
Bus input current
DE = 0 V, VCC = 0 V or 5.5 V
VTH+
Positive-going input threshold
voltage
VTH-
Negative-going input threshold
voltage
VHYS
Input hysteresis
VOH
Output high voltage
IOH = -8 mA
VOL
Output low voltage
IOL = 8 mA
IOZR
Output high-impedance current
VO = 0 V or VCC, RE = VCC
Input current (D, DE, RE)
3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC
VI = 12V
50
VI = -7V
-100
-65
-200
-130
See (2)
-100
-20
mV
-200
-130
See (2)
mV
VI = 15V
60
VI = -15V
Over common-mode range of ± 15 V
µA
125
µA
30
VCC –
0.4
µA
mV
VCC –
0.2
0.2
V
0.4
V
-1
1
µA
-6.2
6.2
µA
Logic
IIN
Device
ICC
TSD
(1)
(2)
Driver and receiver enabled
RE = 0 V ,
DE = VCC,
No load
2.4
3
mA
Driver enabled, receiver disabled
RE = VCC,
DE = VCC,
No load
2
2.5
mA
Driver disabled, receiver enabled
RE = 0 V,
DE = 0 V,
No load
700
960
µA
Driver and receiver disabled
RE = VCC,
DE = 0 V, D
= open, No
load
0.1
1
µA
Supply current (quiescent)
Thermal shutdown temperature
170
℃
|VOD| ≥ 1.4 V when TA > 85 ℃, Vtest < -7 V and VCC < 3.135 V.
Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–.
Copyright © 2018, Texas Instruments Incorporated
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7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC =
5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
400
600
ns
250
500
ns
10
ns
80
200
ns
RE = 0 V, See Figure 11 and
Figure 12
100
600
ns
RE = VCC, See Figure 11 and
Figure 12
4
11
µs
13
20
ns
60
110
ns
7
ns
30
60
ns
DE = VCC, See Figure 14
60
140
ns
DE = 0 V, See Figure 15
6
14
µs
1
3
6
ns
3
10
Driver: THVD1410
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF, See Figure 10
Enable time
Receiver: THVD1410
tr, tf
Output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
CL = 15 pF, See Figure 13
tPZH(1), tPZL(1),
tPZH(2),
Enable time
tPZL(2),
Driver: THVD1450, THVD1451, THVD1452
tr, tf
Differential output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH, tPZL
RL = 54 Ω, CL = 50 pF, See Figure 10
Enable time
20
ns
3.5
ns
15
25
ns
RE = 0 V, See Figure 11 and
Figure 12
20
50
ns
RE = VCC, See Figure 11 and
Figure 12
2.5
10
µs
2
6
ns
CL = 15 pF, See Figure 13
25
40
ns
Receiver: THVD1450, THVD1451, THVD1452
tr, tf
Output rise/fall time
tPHL, tPLH
Propagation delay
tSK(P)
Pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Disable time
tPZH(1), tPZL(1),
tPZH(2),
Enable time
tPZL(2),
10
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3.5
ns
14
28
ns
DE = VCC, See Figure 14
50
110
ns
DE = 0V, See Figure 15
4
14
µs
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SLLSEY3A – MAY 2018 – REVISED MAY 2018
7.9 Typical Characteristics
6
VO Driver Differential Output Voltage (V)
VO Driver Output Voltage (V)
6
VOL
VOH
5
4
3
2
1
0
4
3
2
1
0
0
10
20
30 40 50 60 70 80
IO Driver Output Current (mA)
VCC = 5 V
90
100 110
0
10
DE = VCC
D=0V
30 40 50 60 70 80
IO Driver Output Current (mA)
VCC = 5 V
90
100 110
D002
DE = VCC
D=0V
Figure 2. Driver Differential Output voltage vs Driver Output
Current
80
7
VO Driver Rise and Fall Time (ns)
70
60
50
40
30
20
10
0
0
0.5
1
1.5
2 2.5 3 3.5 4 4.5
VCC Supply Voltage (V)
TA = 25°C
RL = 54 Ω
5
5.5
6
5
4
3
2
1
0
-40
6
-20
0
D003
DE = VCC
20
40
60
80
Temperature (qC)
100
120
140
D004
D = VCC
Figure 3. Driver Output Current vs Supply Voltage
Figure 4. Driver Rise or Fall Time vs Temperature
16
120
14
100
ICC Supply Current (mA)
VO Driver Propagation Delay (ns)
20
D001
Figure 1. Driver Output Voltage vs Driver Output Current
IO Driver Output Current (mA)
5
12
10
8
6
4
80
60
40
20
2
0
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
5
10
D005
15
20
25
30
35
SIgnaling Rate (Mbps)
40
45
50
D006
RL = 54 Ω
Figure 5. Driver Propagation Delay vs Temperature
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Figure 6. Supply Current vs Signal Rate
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Receiver Output (V)
Typical Characteristics (continued)
6
6
5
5
4
4
3
3
2
2
1
VTH ( 7 V) 1
VTH (0 V)
VTH (12 V)
0
-170 -160 -150 -140 -130 -120 -110 -100 -90
-80
-70
VID Differential Input Voltage (mV)
-60
0
-50
D007
Figure 7. Receiver Output vs Input
12
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8 Parameter Measurement Information
375 Ÿ
Vcc
DE
A
D
0V or Vcc
VOD
Vtest
RL
B
375 Ÿ
Figure 8. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
0V or Vcc
A
D
RL/2
VA
B
VB
VOD
RL/2
B
CL
VOC(PP)
VOC
ûVOC(SS)
VOC
Figure 9. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
Vcc
Vcc
DE
A
D
Input
Generator
VI
50%
VI
VOD
50 Ÿ
0V
tPHL
tPLH
RL=
54 Ÿ
CL= 50 pF
90%
50%
10%
B
VOD
tr
tf
~2 V
~ ±2V
Figure 10. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
D
S1
Vcc
VO
50%
VI
B
DE
Input
Generator
VI
RL =
110 Ÿ
CL =
50 pF
50 Ÿ
0V
tPZH
90%
VO
VOH
50%
~
~ 0V
tPHZ
Figure 11. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
Vcc
Vcc
A
S1
VO
B
D
DE
Input
Generator
RL= 110 Ÿ
CL=
50 pF
50%
VI
0V
tPZL
tPLZ
§ Vcc
VO
10%
50 %
VI
VOL
50 Ÿ
Figure 12. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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Parameter Measurement Information (continued)
3V
A
Input
Generator
R VO
VI
50 Ÿ
1.5V
0V
50 %
VI
B
0V
tPLH
tPHL
VOH
90%
CL=15 pF
50%
RE
VOD
10 %
tr
VOL
tf
Figure 13. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
Vcc
Vcc
Vcc
VI
50 %
DE
0V or Vcc
0V
A
D
R
B
1 kŸ
VO
tPZH(1)
tPHZ
S1
VO
CL=15 pF
90 %
50 %
tPZL(1)
VI
D at Vcc
S1 to GND
§ 0V
RE
Input
Generator
VOH
50 Ÿ
tPLZ
VO
50 %
VCC D at 0V
S1 to Vcc
10 %
VOL
Figure 14. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
V or 1.5V
R
1.5 V or 0V
B
VO
1 NŸ
S1
CL=15 pF
RE
tPZH(2)
VOH
50%
VO
§ 0V
A at 1.5 V
B at 0 V
S1 to GND
tPZL(2)
Input
Generator
VI
VCC
50 Ÿ
VO
50%
VOL
A at 0V
B at 1.5V
S1 to VCC
Figure 15. Measurement of Receiver Enable Times With Driver Disabled
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9 Detailed Description
9.1 Overview
THVD1410 and THVD1450 are low-power, half duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 500 kbps and 50 Mbps respectively.
THVD1451 is fully enabled with no external enabling pins. THVD1452 has active-high driver enable and activelow receiver enable. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagrams
VCC
R
RE
A
DE
B
D
GND
Figure 16. THVD1410 and THVD1450
VCC
A
R
R
B
VCC
D
Z
D
Y
GND
Figure 17. THVD1451
VCC
A
R
R
B
RE
DE
D
Z
D
Y
GND
Figure 18. THVD1452
9.3 Feature Description
Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±18 kV and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to ±4 kV.
With careful system design, one could achieve ±4 kV EFT Criterion A (no data loss when transient noise is
present).
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Feature Description (continued)
The THVD14xx device family provides internal biasing of the receiver input thresholds in combination with large
input-threshold hysteresis. The receiver output remains logic high under a bus-idle or bus-short conditions
without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient
temperature range from –40°C to 125°C.
9.4 Device Functional Modes
9.4.1 Device Functional Modes for THVD1410 and THVD1450
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 1. Driver Function Table for THVD1410 and THVD1450
INPUT
ENABLE
D
DE
A
OUTPUTS
B
H
H
H
L
Actively drive bus high
Actively drive bus low
FUNCTION
L
H
L
H
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 2. Receiver Function Table for THVD1410 and THVD1450
16
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
VID < VTH-
L
L
Receive valid bus low
X
H
Z
Receiver disabled
FUNCTION
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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9.4.2 Device Functional Modes for THVD1451
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic
states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the
differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns
high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left
open while the driver is enabled, output Y turns high and Z turns low.
Table 3. Driver Function Table for THVD1451
INPUT
OUTPUTS
FUNCTIONS
D
Y
Z
H
H
L
L
L
H
Actively drive bus low
OPEN
H
L
Actively drive bus High by default
Actively drive bus high
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the
receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R,
turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs
causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus
lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
Table 4. Receiver Function Table for THVD1451
DIFFERENTIAL INPUT
OUTPUT
VID = VA – VB
R
VTH+ < VID
H
Receive valid bus high
VTH- < VID < VTH+
?
Indeterminate bus state
FUNCTION
VID < VTH-
L
Receive valid bus low
Open-circuit bus
H
Fail-safe high output
Short-circuit bus
H
Fail-safe high output
Idle (terminated) bus
H
Fail-safe high output
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9.4.3 Device Functional Modes for THVD1452
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
Y turns high and Z turns low.
Table 5. Driver Function Table for THVD1452
INPUT
ENABLE
OUTPUTS
D
DE
Y
H
H
H
L
Actively drive bus high
L
H
L
H
Actively drive bus low
X
L
Z
Z
Driver disabled
X
OPEN
Z
Z
Driver disabled by default
OPEN
H
H
L
Actively drive bus high by default
Z
FUNCTION
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 6. Receiver Function Table for THVD1452
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VTH+ < VID
L
H
Receive valid bus high
VTH- < VID < VTH+
L
?
Indeterminate bus state
Receive valid bus low
18
FUNCTION
VID < VTH-
L
L
X
H
Z
Receiver disabled
X
OPEN
Z
Receiver disabled by default
Open-circuit bus
L
H
Fail-safe high output
Short-circuit bus
L
H
Fail-safe high output
Idle (terminated) bus
L
H
Fail-safe high output
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The THVD14xx family consists of half-duplex and full-duplex RS-485 transceivers commonly used for
asynchronous data transmissions. For half-duplex devices, the driver and receiver enable pins allow for the
configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires), and
allows each node to transmit data on one pair while simultaneously receiving data on the other pair.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates
over longer cable length.
R
R
R
A
RE
D
RT
B
DE
R
A
RT
D
A
R
B
A
R
D
R RE DE D
RE
B
DE
D
B
D
D
R RE DE D
Figure 19. Typical RS-485 Network With Half-Duplex Transceivers
Y
R
D
Z
A
RT
RT
B
R
R
DE
RE
Master
RE
D
Slave
B
R
A
DE
Z
RT
RT
A
B
Z
Y
D
D
Y
R Slave
D
R RE DE D
Figure 20. Typical RS-485 Network With Full-Duplex Transceivers
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Typical Application (continued)
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 21. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 50 Mbps for the THVD1450, THVD1451 and THVD1452) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections of varying phase as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12 kΩ. Because the THVD14xx family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
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Typical Application (continued)
10.2.1.4 Receiver Failsafe
The differential receivers of the THVD14xx family are failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VTH+, VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the table, differential signals more
negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200
mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output will
be High. Only when the differential input is more than VHYS below VTH+ will the receiver output transition to a Low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VTH+.
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Typical Application (continued)
10.2.1.5 Transient Protection
The bus pins of the THVD14xx transceiver family include on-chip ESD protection against ±30-kV HBM and ±18kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
High-Voltage
Pulse
Generator
330 Ω
(1.5 kΩ)
Device
Under
Test
150 pF
(100 pF)
C(S)
Current (A)
50 M
(1 M)
40
35
30 10-kV IEC
25
20
15
10
5
0
0
50
100
10-kV HBM
150
200
250
300
Time (ns)
Figure 22. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 23 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
22
20
18
16
14
12
10
8
6
4
2
0
Pulse Power (MW)
Pulse Power (kW)
The right hand diagram shows the pulse power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
Time (µs)
30
35
40
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
5
10
15
20
25
30
35
40
Time (µs)
Figure 23. Power Comparison of ESD, EFT, and Surge Transients
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Typical Application (continued)
If the surge transients, high-energy content is characterized by long pulse duration and slow decaying pulse
power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver is
converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
Figure 24 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT
pulse train that is commonly applied during compliance testing.
1000
100
Surge
10
1
Pulse Energy (J)
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 24. Comparison of Transient Energies
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Typical Application (continued)
10.2.2 Detailed Design Procedure
Figure 25 and Figure 26 suggest a protection circuit against 1 kV surge (IEC 61000-4-5) transients. Table 7
shows the associated bill of materials.
5V
100nF
100nF
10k
VCC
R1
R
RxD
MCU/
UART
DIR
RE
A
DE
B
TVS
D
TxD
R2
GND
10k
Figure 25. Transient Protection Against Surge Transients for Half-Duplex Devices
5V
100nF
R1
10k
VCC
A
TVS
R
RxD
B
RE
DIR
R2
R1
MCU/
UART
DE
DIR
Z
TVS
D
TxD
Y
10k
GND
R2
Figure 26. Transient Protection Against Surge Transients for Full-Duplex Devices
Table 7. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
RS-485 transceiver
THVD14xx
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
Vishay
Bidirectional 400-W transient suppressor
CDSOT23-SM712
Bourns
R1
R2
TVS
24
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10.2.3 Application Curves
50 Mbps
VCC = 5 V
Figure 27. THVD1450 Waveforms with 54-Ω Termination
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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12 Layout
12.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
12.2 Layout Example
5
Via to ground
C
R
Via to VCC
R
1
JMP
6
4
R
MCU
5
6
R
TVS
5
THVD14x0
Figure 28. Half-Duplex Layout Example
26
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com
SLLSEY3A – MAY 2018 – REVISED MAY 2018
13 Device and Documentation Support
13.1 Device Support
13.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
THVD1410
Click here
Click here
Click here
Click here
Click here
THVD1450
Click here
Click here
Click here
Click here
Click here
THVD1451
Click here
Click here
Click here
Click here
Click here
THVD1452
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document..
13.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2018, Texas Instruments Incorporated
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27
THVD1410
THVD1450, THVD1451, THVD1452
SLLSEY3A – MAY 2018 – REVISED MAY 2018
www.ti.com
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: THVD1410 THVD1450 THVD1451 THVD1452
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
THVD1410D
PREVIEW
SOIC
D
8
75
TBD
Call TI
Call TI
-40 to 125
THVD1410DGK
PREVIEW
VSSOP
DGK
8
80
TBD
Call TI
Call TI
-40 to 125
THVD1410DGKR
PREVIEW
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
THVD1410DR
PREVIEW
SOIC
D
8
2500
TBD
Call TI
Call TI
-40 to 125
THVD1450D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
THVD1450DGK
PREVIEW
VSSOP
DGK
8
80
TBD
Call TI
Call TI
-40 to 125
THVD1450DGKR
PREVIEW
VSSOP
DGK
8
2500
TBD
Call TI
Call TI
-40 to 125
THVD1450DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
THVD1450DRB
PREVIEW
SON
DRB
8
250
TBD
Call TI
Call TI
-40 to 125
THVD1450DRBR
PREVIEW
SON
DRB
8
3000
TBD
Call TI
Call TI
-40 to 125
THVD1451DRB
PREVIEW
SON
DRB
8
121
TBD
Call TI
Call TI
-40 to 125
THVD1451DRBR
PREVIEW
SON
DRB
8
3000
TBD
Call TI
Call TI
-40 to 125
THVD1452D
PREVIEW
SOIC
D
14
75
TBD
Call TI
Call TI
-40 to 125
THVD1452DGS
PREVIEW
VSSOP
DGS
10
1040
TBD
Call TI
Call TI
-40 to 125
THVD1452DGSR
PREVIEW
VSSOP
DGS
10
2500
TBD
Call TI
Call TI
-40 to 125
THVD1452DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
-40 to 125
VD1450
VD1450
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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