REF20-Q1
SBOSA80 – DECEMBER 2021
REF20xx-Q1 Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References
1 Features
3 Description
•
Applications with only a positive supply voltage often
require additional stable voltage in the middle of the
analog-to-digital converter (ADC) input range to bias
input bipolar signals. The REF20xx-Q1 provides a
reference voltage (VREF) for the ADC and a second
highly-accurate voltage (VBIAS) that can be used to
bias the input bipolar signals.
•
•
•
•
•
•
•
•
•
•
2 Applications
Telematics control
Battery management systems
Inverter and motor control
Automotive gateway
Power distribution box
Power steering
On board chargers
Both the VREF and VBIAS voltages have the same
excellent specifications and can sink and source
current equally well. Very good long-term stability and
low noise levels make these devices ideally-suited for
high-precision applications.
Device Information
(1)
PART NAME
PACKAGE (1)
BODY SIZE (NOM)
REF20xx-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
Power
Supply
0.05
0.04
LOAD
•
•
•
•
•
•
•
The REF20xx-Q1 offers excellent temperature drift
(8 ppm/°C, maximum) and initial accuracy (0.05%)
on both the VREF and VBIAS outputs while operating
at a quiescent current less than 430 µA. In addition,
the VREF and VBIAS outputs track each other with
a precision of 7 ppm/°C (maximum) across the
temperature range of –40°C to 125°C. All these
features increase the precision of the signal chain and
decrease board space, while reducing the cost of the
system as compared to a discrete solution. Extremely
low dropout voltage of only 10 mV allows operation
from very low input voltages, which can be very useful
in battery-operated systems.
VIN+
RSHUNT
VOUT
INA240-Q1
ISENSE
ADC
VINREF1
REF2
VBIAS = 1.5 V
VREF = 3.0 V
EN
Application Example
0.03
VBIAS
0.02
0.01
0
-0.01
-0.02
VREF
-0.03
-0.04
-0.05
REF20-Q1
GND
Output Voltage Accuracy (%)
•
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature
– Device HBM ESD classification level 2
– Device CDM ESD classification level C7B
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Two Outputs, VREF and VREF / 2, for convenient
use in single-supply systems
Excellent temperature drift performance:
– 8 ppm/°C (maximum) from –40°C to 125°C
High initial accuracy: ±0.05% (maximum)
VREF and VBIAS tracking overtemperature:
– 7 ppm/°C (maximum) from –40°C to 125°C
Microsize package: SOT23-5
Low dropout voltage: 10 mV
High output current: ±20 mA
Low quiescent current: 360 μA
Line regulation: 3 ppm/V
Load regulation: 8 ppm/mA
±75
VIN
±50
±25
0
25
50
75
100
Temperature (ƒC)
125
150
C001
VREF and VBIAS vs Temperature
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF20-Q1
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SBOSA80 – DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................ 7
8 Parameter Measurement Information.......................... 14
8.1 Solder Heat Shift.......................................................14
8.2 Long-Term Stability................................................... 15
8.3 Thermal Hysteresis................................................... 16
8.4 Noise Performance................................................... 17
9 Detailed Description......................................................18
9.1 Overview................................................................... 18
9.2 Functional Block Diagram......................................... 18
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................19
10 Applications and Implementation.............................. 20
10.1 Application Information........................................... 20
10.2 Typical Application.................................................. 20
11 Power-Supply Recommendations..............................26
12 Layout...........................................................................27
12.1 Layout Guidelines................................................... 27
12.2 Layout Example...................................................... 27
13 Device and Documentation Support..........................28
13.1 Documentation Support.......................................... 28
13.2 Receiving Notification of Documentation Updates..28
13.3 Support Resources................................................. 28
13.4 Trademarks............................................................. 28
13.5 Electrostatic Discharge Caution..............................28
13.6 Glossary..................................................................28
14 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2021
*
Initial Release
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5 Device Comparison Table
PRODUCT
VREF
VBIAS
REF2025-Q1
2.5 V
1.25 V
REF2030-Q1
3.0 V
1.5 V
REF2033-Q1
3.3 V
1.65 V
REF2041-Q1
4.096 V
2.048 V
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6 Pin Configuration and Functions
VBIAS
1
GND
2
EN
3
5
VREF
4
VIN
Figure 6-1. DDC Package
SOT23-5
(Top View)
Table 6-1. Pin Functions
PIN
4
I/O
DESCRIPTION
NO.
NAME
1
VBIAS
2
GND
—
3
EN
Input
Enable (EN ≥ VIN – 0.7 V, device enabled)
Input supply voltage
Output
4
VIN
Input
5
VREF
Output
Bias voltage output (VREF / 2)
Ground
Reference voltage output (VREF)
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
VIN
–0.3
6
EN
–0.3
VIN + 0.3
Operating
–55
150
Junction, Tj
Temperature
V
150
Storage, Tstg
(1)
UNIT
–65
°C
170
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2500
Charged-device model (CDM), per AEC Q100-011
±1500
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
(1)
Supply input voltage range (IL = 0 mA, TA = 25°C)
NOM
MAX
VREF + 0.02 (1)
5.5
UNIT
V
See Figure 7-27 in Section 7.6 for minimum input voltage at different load currents and temperature
7.4 Thermal Information
REF20xx-Q1
THERMAL METRIC (1)
DDC (SOT23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
193.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
40.2
°C/W
RθJB
Junction-to-board thermal resistance
34.5
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
34.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy
–0.05%
Output voltage temperature coefficient (1)
0.05%
–40°C ≤ TA ≤ 125°C
±3
±8
ppm/°C
–40°C ≤ TA ≤ 125°C
±2
±7
ppm/°C
VREF + 0.02 V ≤ VIN ≤ 5.5 V
3
35
ppm/V
Sourcing
0 mA ≤ IL ≤ 20 mA ,
VREF + 0.6 V ≤ VIN ≤ 5.5 V
8
20
Sinking
0 mA ≤ IL ≤ –20 mA,
VREF + 0.02 V ≤ VIN ≤ 5.5 V
8
20
360
430
VREF and VBIAS tracking over temperature
(2)
LINE AND LOAD REGULATION
ΔVO(ΔVI)
ΔVO(ΔIL)
Line regulation
Load regulation
ppm/mA
POWER SUPPLY
Active mode
ICC
–40°C ≤ TA ≤ 125°C
Supply current
Shutdown mode
Enable voltage
Dropout voltage
460
3.3
–40°C ≤ TA ≤ 125°C
Device in active mode (EN = 1)
0
0.7
VIN – 0.7
VIN
10
IL = 20 mA
Short-circuit current
ton
Turn-on time
0.1% settling, CL = 1 µF
Low-frequency noise (3)
0.1 Hz ≤ f ≤ 10 Hz
Output voltage noise density
f = 100 Hz
µA
9
Device in shutdown mode (EN = 0)
ISC
5
20
600
V
mV
50
mA
500
µs
NOISE
12
ppmPP
0.25
ppm/√ Hz
CAPACITIVE LOAD
Stable output capacitor range
0
10
µF
HYSTERESIS AND LONG TERM STABILITY
(1)
(2)
(3)
(4)
(5)
6
Long-term stability (4)
0 to 1000 hours
Output voltage hysteresis (5)
25°C, –40°C, 125°C, 25°C
25
Cycle 1
60
Cycle 2
35
ppm
ppm
Temperature drift is specified according to the box method. See the Section 9.3 section for more details.
The VREF and VBIAS tracking over temperature specification is explained in more detail in the Section 9.3 section.
The peak-to-peak noise measurement procedure is explained in more detail in the Section 8.4 section.
Long-term stability measurement procedure is explained in more in detail in the Section 8.2 section.
The thermal hysteresis measurement procedure is explained in more detail in the Section 8.3 section.
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7.6 Typical Characteristics
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
70
50
60
40
Population (%)
Population (%)
50
40
30
30
20
20
10
0
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
0
-0.05
10
VREF Initial Accuracy (%)
0
1
2
3
4
5
6
7
8
VREF Drift Distribution (ppm/ƒC)
C010
C015
–40°C ≤ TA ≤ 125°C
Figure 7-1. Initial Accuracy Distribution (VREF)
Figure 7-2. Drift Distribution (VREF)
50
80
70
40
Population (%)
Population (%)
60
50
40
30
20
30
20
10
0
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
0
-0.05
10
VBIAS Initial Accuracy (%)
0
1
2
3
4
5
6
7
8
VBIAS Drift Distribution (ppm/ƒC)
C015
C008
–40°C ≤ TA ≤ 125°C
Figure 7-4. Drift Distribution (VBIAS)
Figure 7-3. Initial Accuracy Distribution (VBIAS)
60
40
50
Population (%)
Population (%)
30
20
40
30
20
10
0
80
60
40
20
0
±20
±40
±60
±80
0
±100
10
0
1
2
3
4
5
6
7
VREF and VBIAS Tracking Over Temperature (ppm/ƒC)
VREF and VBIAS Matching (ppm)
C017
C004
–40°C ≤ TA ≤ 125°C
Figure 7-5. VREF – 2 × VBIAS Distribution
Figure 7-6. Distribution of VREF – 2 × VBIAS Drift Tracking Over
Temperature
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
60
50
50
Population (%)
Population (%)
40
30
20
10
0
40
30
20
10
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0
0.0025
-0.0125 -0.01 -0.0075 -0.005 -0.0025
Solder Heat Shift Histogram - VREF (%)
0
0.0025
Solder Heat Shift Histogram - VBIAS (%)
C040
C041
Refer to the Section 8.1 section for more information.
Refer to the Section 8.1 section for more information.
Figure 7-8. Solder Heat Shift Distribution (VBIAS)
0.05
1000
0.04
750
0.03
VREF - 2 x VBIAS (ppm)
Output Voltage Accuracy (%)
Figure 7-7. Solder Heat Shift Distribution (VREF)
VBIAS
0.02
0.01
0
-0.01
-0.02
VREF
-0.03
500
250
0
±250
±500
±750
-0.04
-0.05
±1000
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
Figure 7-9. Output Voltage Accuracy (VREF) vs Temperature
C003
Figure 7-10. VREF – 2 × VBIAS Tracking vs Temperature
1.2503
2.5005
-40°C
-40°C
2.4995
1.2501
VBIAS (V)
VREF (V)
2.5000
25°C
2.4990
1.2499
1.2497
25°C
125°C
125°C
1.2495
2.4985
1.2493
2.4980
±20
±15
±10
±5
0
5
10
Load Current (mA)
15
20
±20
±10
±5
0
5
10
15
20
C039
VBIAS output
VREF output
Figure 7-11. Output Voltage Change vs Load Current (VREF)
8
±15
Load Current (mA)
C038
Figure 7-12. Output Voltage Change vs Load Current (VBIAS)
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7.6 Typical Characteristics (continued)
11
10
9
8
7
6
5
4
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
VREF output
150
VREF - Load Regulation Sinking (ppm/mA)
10
9
8
7
6
5
4
0
25
50
75
100
125
Temperature (ƒC)
VREF output
150
9
8
7
6
5
4
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C020
IL = 20 mA
Figure 7-14. Load Regulation Sourcing vs Temperature (VBIAS)
12
11
10
9
8
7
6
5
4
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C021
IL = –20 mA
VBIAS output
Figure 7-15. Load Regulation Sinking vs Temperature (VREF)
150
C022
IL = –20 mA
Figure 7-16. Load Regulation Sinking vs Temperature (VBIAS)
5
5
VBIAS Line Regulation (ppm/V)
VREF Line Regulation (ppm/V)
10
IL = 20 mA
11
±25
11
VBIAS output
12
±50
12
C025
Figure 7-13. Load Regulation Sourcing vs Temperature (VREF)
±75
VBIAS - Load Regulation Sourcing (ppm/mA)
12
VBIAS - Load Regulation Sinking (ppm/mA)
VREF - Load Regulation Sourcing (ppm/mA)
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
4.5
4
3.5
3
2.5
2
4.5
4
3.5
3
2.5
2
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C019
VREF output
150
C018
VBIAS output
Figure 7-17. Line Regulation vs Temperature (VREF)
Figure 7-18. Line Regulation vs Temperature (VBIAS)
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
100
100
VBIAS
VBIAS
80
PSRR (dB)
PSRR (dB)
80
VREF
60
40
VREF
60
40
20
20
1
10
100
1k
10k
1
100k
Frequency (Hz)
10
CL = 0 µF
500 mV/div
1k
10k
100k
C027
CL = 10 µF
Figure 7-19. Power-Supply Rejection Ratio vs Frequency
VIN + 0.25 V
100
Frequency (Hz)
C026
Figure 7-20. Power-Supply Rejection Ratio vs Frequency
VIN + 0.25 V
VIN + 0.25 V
500 mV/div
VIN - 0.25 V
VIN + 0.25V
VIN - 0.25V
VREF
VREF
40 mV/div
40 mV/div
Time (500 µs/div)
Time (500 µs/div)
C006
C006
CL = 1 µF
CL = 10 µF
Figure 7-21. Line Transient Response
+1 mA
Figure 7-22. Line Transient Response
+1 mA
2 mA/div
+1 mA
+1 mA
2 mA/div
- 1 mA
- 1 mA
VREF
VREF
20 mV/div
20 mV/div
Time (500 µs/div)
Time (500 µs/div)
C032
CL = 1 µF
IL = ±1-mA step
Figure 7-23. Load Transient Response
10
C037
CL = 10 µF
IL = ±1-mA step
Figure 7-24. Load Transient Response
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
+20 mA
+20 mA
40 mA/div
+20 mA
+20 mA
40 mA/div
-20 mA
-20 mA
VREF
VREF
40 mV/div
40 mV/div
Time (500 µs/div)
Time (500 µs/div)
C036
C031
CL = 1 µF
CL = 10 µF
IL = ±20-mA step
IL = ±20-mA step
Figure 7-26. Load Transient Response
Figure 7-25. Load Transient Response
400
Dropout Voltage (mV)
125°C
300
VIN
25°C
±40°C
200
2 V/div
VREF
100
0
±30
±20
±10
0
10
Load Current (mA)
20
Time (100 µs/div)
30
C033
C005
CL = 1 µF
Figure 7-28. Turn-On Settling Time
Figure 7-27. Minimum Dropout Voltage vs Load Current
500
Quiescent Current ( A)
450
VIN
2 V/div
VREF
400
350
300
250
200
Time (100 µs/div)
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C034
150
C006
CL = 10 µF
Figure 7-29. Turn-On Settling Time
Figure 7-30. Quiescent Current vs Temperature
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
500
Voltage (5 V/div)
Quiescent Current ( A)
450
400
350
300
250
200
2
3
4
5
Time (1 s/div)
6
Input Voltage (V)
C028
C007
VREF output
Figure 7-32. 0.1-Hz to 10-Hz Noise (VREF)
Figure 7-31. Quiescent Current vs Input Voltage
Voltage (5 V/div)
2XWSXW 1RLVH 6SHFWUDO 'HQVLW\ SSP ¥+]
1
Time (1 s/div)
CL = 0 µF
0.1
CL = 4.7 F
CL = 10 µF
0.01
1
10
100
1k
10k
Frequency (Hz)
C029
C030
VBIAS output
Figure 7-33. 0.1-Hz to 10-Hz Noise (VBIAS)
Figure 7-34. Output Voltage Noise Spectrum
100
100
CL = 0 F
Output Impedance ( )
Output Impedance ( )
CL = 0 F
10
CL = 1µF
1
CL = 10 F
0.1
0.01
0.01
0.1
1
10
100
1k
10k
Frequency (Hz)
100k
10
CL = 10 F
0.1
0.01
0.01
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
C024
C023
VBIAS output
VREF output
Figure 7-35. Output Impedance vs Frequency (VREF)
12
CL = 1µF
1
Figure 7-36. Output Impedance vs Frequency (VBIAS)
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7.6 Typical Characteristics (continued)
40
35
35
30
30
Thermal Hysterisis - VREF (ppm)
120
100
120
100
80
60
0
40
5
0
20
10
5
80
15
10
60
15
20
40
20
25
20
25
0
Population (%)
40
0
Population (%)
At TA = 25°C, IL = 0 mA, VIN = 5 V power supply, CL = 0 µF, and 2.5 V output, unless otherwise noted.
Thermal Hysteresis - VBIAS (ppm)
C013
Figure 7-37. Thermal Hysteresis Distribution (VREF)
C014
Figure 7-38. Thermal Hysteresis Distribution (VBIAS)
50
Output Voltage Stability (ppm)
45
40
35
30
25
20
15
10
5
0
-5
-10
0
100
200
300
400 500 600
Time (hr)
700
800
900 1000
Figure 7-39. Long-Term Stability (First 1000 Hours)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF20xx-Q1 have differing coefficients of thermal expansion,
resulting in stress on the device die when the part is heated. Mechanical and thermal stress on the device
die can cause the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow
soldering is a common cause of this error.
To illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on each
printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow profile.
The reflow profile is as shown in Figure 8-1. The printed circuit board is comprised of FR4 material. The board
thickness is 1.57 mm and the area is 171.54 mm × 165.1 mm.
The reference and bias output voltages are measured before and after the reflow process; the typical shift is
displayed in Figure 8-2 and Figure 8-3. Although all tested units exhibit very low shifts (< 0.01%), higher shifts
are also possible depending on the size, thickness, and material of the printed circuit board. An important note is
that the histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows,
as is common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias
voltage. If the PCB is exposed to multiple reflows, the device must be soldered in the second pass to minimize
its exposure to thermal stress.
300
Temperature (ƒC)
250
200
150
100
50
0
0
50
100
150
200
250
300
Time (seconds)
350
400
C01
Figure 8-1. Reflow Profile
60
50
50
Population (%)
Population (%)
40
30
20
10
0
40
30
20
10
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
0
-0.0125 -0.01 -0.0075 -0.005 -0.0025
Solder Heat Shift Histogram - VREF (%)
0
0.0025
Solder Heat Shift Histogram - VBIAS (%)
C041
C040
Figure 8-2. Solder Heat Shift Distribution, VREF (%) Figure 8-3. Solder Heat Shift Distribution, VBIAS (%)
14
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8.2 Long-Term Stability
The long term stability of the REF20xx-Q1 was collected on 32 parts that were soldered onto Printed Circuit
Boards without any slots or special layout considerations. The boards were then placed into an oven with air
temperature maintained at TA = 35°C. The Vref output of the 32 parts was measured regularly. Typical long term
stability is as shown in Figure 8-4.
50
Output Voltage Stability (ppm)
45
40
35
30
25
20
15
10
5
0
-5
-10
0
100
200
300
400 500 600
Time (hr)
700
800
900 1000
Figure 8-4. Long Term Stability – 1000 hours (VREF)
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8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF20xx-Q1 soldered to a PCB, similar to a real-world application.
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed
by Equation 1:
§ VPRE VPOST
¨¨
VNOM
©
VHYST
·
6
¸¸ x 10
¹
(ppm)
(1)
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm)
VNOM = the specified output voltage
VPRE = output voltage measured at 25°C pre-temperature cycling
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to 125°C and returns to 25°C
40
35
35
30
30
Thermal Hysterisis - VREF (ppm)
120
Thermal Hysteresis - VBIAS (ppm)
C013
Figure 8-5. Thermal Hysteresis Distribution (VREF)
16
100
120
100
0
80
5
0
60
5
40
10
20
10
80
15
60
15
20
40
20
25
20
25
0
Population (%)
40
0
Population (%)
Typical thermal hysteresis distribution is as shown in Figure 8-5 and Figure 8-6.
C014
Figure 8-6. Thermal Hysteresis Distribution (VBIAS)
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8.4 Noise Performance
Voltage (5 V/div)
Voltage (5 V/div)
Typical 0.1-Hz to 10-Hz voltage noise can be seen in Figure 8-7 and Figure 8-8. Device noise increases
with output voltage and operating temperature. Additional filtering can be used to improve output noise levels,
although care must be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak
noise measurement setup is shown in Figure 8-9.
Time (1 s/div)
Time (1 s/div)
C028
C029
Figure 8-7. 0.1-Hz to 10-Hz Noise (VREF)
Figure 8-8. 0.1-Hz to 10-Hz Noise (VBIAS)
10 k
100
40 mF
VIN
REF20-Q1
GND
10 F
+
EN
0.1 F
To scope
VREF
1 k
2-Pole High-pass
4-Pole Low-pass
0.1 Hz to 10 Hz Filter
VBIAS
Figure 8-9. 0.1-Hz to 10-Hz Noise Measurement Setup
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9 Detailed Description
9.1 Overview
The REF20xx-Q1 are a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The
Section 9.1 section provides a block diagram of the basic band-gap topology and the two buffers used to derive
the VREF and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than
that of Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature coefficient
and is forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2, which has
a negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature.
Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The resistors R1, R2
and R3, R4 are sized such that VBIAS = VREF / 2.
e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and V BIAS,
implemented during the final steps of manufacturing after the plastic molding process. This method minimizes
the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is
implemented in the REF20xx-Q1 to minimize the temperature drift and maximize the initial accuracy of both the
VREF and VBIAS outputs.
9.2 Functional Block Diagram
R2
R6
R1
R7
VREF
+
+
e-Trim
R5
+
VBE1
-
+
VBE2
-
R4
R3
Q2
Q1
VBIAS
e-Trim
+
9.3 Feature Description
9.3.1 VREF and VBIAS Tracking
Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter
(ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF20xx-Q1 are generated
from the same band-gap voltage as shown in the Section 9.2. Hence, both outputs track each other over the full
temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (maximum). The tracking error is calculated
using the box method, as described by Equation 2:
Tracking Error
VDIFF(MAX) VDIFF (MIN)
§
·
6
¨
¸ x 10
x
V
Temperature
Range
© REF
¹
(ppm)
(2)
where
•
18
VDIFF
VREF
2 ‡ VBIAS
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The tracking accuracy is as shown in Figure 9-1.
0.05
Output Voltage Accuracy (%)
0.04
0.03
VBIAS
0.02
0.01
0
-0.01
-0.02
VREF
-0.03
-0.04
-0.05
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C001
Figure 9-1. VREF and VBIAS Tracking vs Temperature
9.3.2 Low Temperature Drift
The REF20xx-Q1 is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 3:
Drift
V REF(MAX) V REF(MIN)
§
·
6
¨
¸ x 10
© V REF xTemperature Range ¹
(ppm)
(3)
9.3.3 Load Current
The REF20xx-Q1 family is specified to deliver a current load of ±20 mA per output. Both the VREF and VBIAS
outputs of the device are protected from short circuits by limiting the output short-circuit current to 50 mA. The
device temperature increases according to Equation 4:
TJ
TA
PD ‡ R
(4)
-$
where
•
•
•
•
TJ = junction temperature (°C)
TA = ambient temperature (°C)
PD = power dissipated (W)
RθJA = junction-to-ambient thermal resistance (°C/W)
The REF20xx-Q1 maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
When the EN pin of the REF20xx-Q1 is pulled high, the device is in active mode. The device must be in active
mode for normal operation. The REF20xx-Q1 can be placed in a low-power mode by pulling the ENABLE pin
low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of
the device reduces to 5 µA in shutdown mode. See the Section 7.5 for logic high and logic low voltage levels.
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10 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The low-drift, bidirectional, single-supply, low-side, current-sensing solution, described in this section, can
accurately detect load currents from –2.5 A to 2.5 A. The linear range of the output is from 250 mV to 2.75 V.
Positive current is represented by output voltages from 1.5 V to 2.75 V, whereas negative current is represented
by output voltages from 250 mV to 1.5 V. The difference amplifier is the INA240-Q1 current-shunt monitor, whose
supply and reference voltages are supplied by the low-drift REF2030-Q1.
10.2 Typical Application
10.2.1 Low-Side, Current-Sensing Application
REF20-Q1
VREF
+
VIN
Reference
EN
+
VCC
VBIAS
+
–
GND
REF1
VS
±ILOAD
REF2
VBUS
+
–
IN+
VREF
+
OUT
ADC
RSHUNT
VOUT
INGND
INA240-Q1
Figure 10-1. Low-Side, Current-Sensing Application
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10.2.1.1 Design Requirements
The design requirements are as follows:
1. Supply voltage: 5.0 V
2. Load current: ±2.5 A
3. Output: 250 mV to 2.75 V
4. Maximum shunt voltage: ±25 mV
10.2.1.2 Detailed Design Procedure
Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore, the currentsensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, use a differential
amplifier with a reference pin. This procedure allows for the differentiation between positive and negative
currents by biasing the output stage such that it can respond to negative input voltages. There are a variety of
methods for supplying power (V+) and the reference voltage (VREF, or VBIAS) to the differential amplifier. For a
low-drift solution, use a monolithic reference that supplies both power and the reference voltage. Figure 10-2
shows the general circuit topology for a low-drift, low-side, bidirectional, current-sensing solution. This topology
is particularly useful when interfacing with an ADC; see Figure 10-1. Not only do VREF and VBIAS track over
temperature, but their matching is much better than alternate topologies.
REF20-Q1
VREF
+
VIN
Reference
EN
+
VCC
VBIAS
+
–
GND
REF1
VS
±ILOAD
REF2
VBUS
+
–
IN+
± VSHUNT
+
RSHUNT
OUT
VOUT
INGND
INA240-Q1
Figure 10-2. Low-Drift, Low-Side, Bidirectional, Current-Sensing Circuit Topology
The transfer function for the circuit given in Figure 10-2 is as shown in Equation 5:
VOUT
G ‡ r VSHUNT
VBIAS
G ‡ rILOAD ‡ RSHUNT
VBIAS
(5)
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10.2.1.2.1 Shunt Resistor
As illustrated in Figure 10-2, the value of VSHUNT is the ground potential for the system load. If the value of
VSHUNT is too large, issues may arise when interfacing with systems whose ground potential is actually 0 V. Also,
a value of VSHUNT that is too negative may violate the input common-mode voltage of the differential amplifier
in addition to potential interfacing issues. Therefore, limiting the voltage across the shunt resistor is important.
Equation 6 can be used to calculate the maximum value of RSHUNT.
R SHUNT(max)
VSHUNT(max)
I LOAD(max)
(6)
Given that the maximum shunt voltage is ±25 mV and the load current range is ±2.5 A, the maximum shunt
resistance is calculated as shown in Equation 7.
R SHUNT (max)
VSHUNT (max)
I LOAD (max)
25mV
10m:
2.5A
(7)
To minimize errors over temperature, select a low-drift shunt resistor. To minimize offset error, select a shunt
resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.
10.2.1.2.2 Differential Amplifier
The differential amplifier used for this design must have the following features:
1. Single-supply (3 V)
2. Reference voltage input
3. Low initial input offset voltage (VOS)
4. Low-drift
5. Fixed gain
6. Low-side sensing (input common-mode range below ground)
For this design, a current-shunt monitor (INA240-Q1) is used. The INA240-Q1 family topology is shown in
Figure 10-3. The INA240-Q1 specifications can be found in the INA240-Q1 product data sheet.
VS
REF1
REF2
IN+
+
OUT
INGND
Figure 10-3. INA240-Q1 Current-Shunt Monitor Topology
The INA240-Q1 is an excellent choice for this application because all the required features are included. In
general, instrumentation amplifiers (INAs) do not have the input common-mode swing to ground that is essential
for this application. In addition, INAs require external resistors to set their gain, which is not desirable for low-drift
applications. Difference amplifiers typically have larger input bias currents, which reduce solution accuracy at
small load currents. Difference amplifiers typically have a gain of 1 V/V. When the gain is adjustable, these
amplifiers use external resistors that are not conducive to low-drift applications.
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10.2.1.2.3 Voltage Reference
The voltage reference for this application must have the following features:
1. Dual output (3.0 V and 1.5 V)
2. Low drift
3. Low tracking errors between the two outputs
For this design, the REF2030-Q1 is used. The REF20xx-Q1 topology is as shown in the Section 9.2 section.
The REF2030-Q1 is an excellent choice for this application because of its dual output. The temperature drift of
8 ppm/°C and initial accuracy of 0.05% make the errors resulting from the voltage reference minimal in this
application. In addition, there is minimal mismatch between the two outputs and both outputs track very well
across temperature, as shown in Figure 10-4 and Figure 10-5.
60
40
50
Population (%)
Population (%)
30
20
40
30
20
10
0
80
60
40
20
0
±20
±40
±60
±80
0
±100
10
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/ƒC)
VREF and VBIAS Matching (ppm)
C016
C004
Figure 10-4. VREF – 2 × VBIAS Distribution
(At TA = 25°C)
Figure 10-5. Distribution of VREF – 2 × VBIAS Drift
Tracking Over Temperature
10.2.1.2.4 Error Calculations
Two types of errors will be discussed: initial accuracy and drift. Accuracy errors include:
•
•
•
•
•
•
Shunt resistor tolerance: αshunt_tol = 0.1% (maximum)
INA initial input offset voltage: VOS_INA = 5 μV (typical)
INA PSRR: VOS_INA_PSRR = 1 μV/V (typical)
INA CMRR: VOS_INA_CMRR = 132 dB (typical)
INA gain error: αINA_GE = 0.05% (typical)
Reference output accuracy: αREF_output = 0.05% (maximum)
It should be noted that these error sources can be greatly reduced at 25ºC by performing a two point system
calibration. Drift errors, on the other hand, can only be reduced by performing the calibration over temperature.
The drift errors include:
•
•
•
•
Shunt resistor drift: δshunt_drift = 15 ppm/ºC (maximum)
INA offset voltage drift: δINA_drift_Vos = 50 nV/ºC (typical)
INA gain error drift: δINA_drift_GE = 0.5 ppm/ºC (typical)
Reference output drift: δREF_drift_output = 3 ppm/ºC (typical)
Equation 8 can be used to convert specifications given in parts per million (ppm) to a percentage (%), and vice
versa.
% = (ppm/10,000)
(8)
Equation 9 can be used to convert specifications given in decibels (dB) to a linear representation.
(V / V) = (1 / 10(dB/20))
(9)
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For some error calculations a full-scale range (FSR) is required. The FSR for this design is determined by the
voltage across the shunt resistor, which is ±25 mV (or 50 mV).
For drift errors, the largest change in temperature (ΔT) is 100ºC, which is the difference between the maximum
specified temperature (125ºC) and room temperature (25ºC). This temperature change is used when calculating
drift errors for the shunt resistor and INA240-Q1. Because the REF20-Q1 uses the box method to determine
drift, the temperature range used for calculations is the entire operating range, or 150ºC.
Finally, errors due to CMRR and PSRR specifications require an adjustment depending on the difference
between the system’s requirements and how the devices were characterized. For example, the INA240-Q1 was
characterized using a common-mode voltage of 12 V. The common-mode voltage in this design is ~0V. This
discrepancy causes an input-referred offset voltage.
Below, Table 10-1 summarizes the initial accuracy calculations.
Table 10-1. Initial Accuracy Error Summary
ERROR SOURCE
DEVICE: RSHUNT (PPM)
DEVICE: IN240-Q1 (PPM)
DEVICE: REF2030-Q1 (PPM)
TOTAL (PPM, RSS)
OFFSET
100 FSR
500 FSR
510 FSR
CMRR
60 FSR
60 FSR
PSRR
40 FSR
40 FSR
GAIN ERROR
1000
TOTAL (PPM, RSS)
1000
500
1118
1087.5 FSR
1231 FSR
(0.123%)
500 FSR
Below, Table 10-2 summarizes the total temperature drift calculations.
Table 10-2. Temperature Drift Error Summary
ERROR SOURCE
DEVICE: RSHUNT (PPM)
OFFSET DRIFT
24
DEVICE: IN240-Q1 (PPM)
DEVICE: REF2030-Q1 (PPM)
TOTAL (PPM, RSS)
100 FSR
495
505 FSR
GAIN ERROR DRIFT
1500
50
TOTAL (PPM, RSS)
1500
111.8 FSR
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1501
495
1583.52 FSR
(0.194%)
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10.2.1.2.5 Application Curves
Performing a two-point calibration at 25°C removes the errors associated with offset voltage, gain error, and so
forth. Figure 10-6 to Figure 10-8 show the measured error at different conditions. For a more detailed description
on measurement procedure, calibration, and calculations, please refer to TIDU357.
3
800
Uncalibrated error (ppm)
Output Voltage (Vout)
-40°C
600
2.5
2
1.5
1
0.5
400
0°C
200
0
25°C
85°C
±200
±400
±600
0
125°C
±800
-3
-2
-1
0
1
2
Load current (mA)
3
±3
±2
±1
0
Load current (mA)
C00
Figure 10-6. Measured Transfer Function
1
2
3
C00
Figure 10-7. Uncalibrated Error vs Load Current
800
-40°C
Calibrated error (ppm)
600
400
0°C
200
0
25°C
85°C
±200
±400
±600
125°C
±800
±3
±2
±1
0
1
Load current (mA)
2
3
C00
Figure 10-8. Calibrated Error vs Load Current
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11 Power-Supply Recommendations
The REF20xx-Q1 family of references feature an extremely low-dropout voltage. These references can be
operated with a supply of only 20 mV above the output voltage. For loaded reference conditions, a typical
dropout voltage versus load is shown in Figure 11-1. A supply bypass capacitor ranging between 0.1 µF to 10 µF
is recommended.
400
Dropout Voltage (mV)
125°C
300
25°C
±40°C
200
100
0
±30
±20
±10
0
10
Load Current (mA)
20
30
C005
Figure 11-1. Dropout Voltage vs Load Current
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12 Layout
12.1 Layout Guidelines
Figure 12-1 shows an example of a PCB layout for a data acquisition system using the REF2030-Q1. Some key
considerations are:
• Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030-Q1.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise
pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Analog Inputs
Via to
Input Power
C
REF2
NC
C
REF1
VBIAS
C
VS
GND
C
OUT
EN
REF20xx-Q1
GND
IN+
INA240-Q1
IN-
VREF
REF
C
Microcontroller
A/D Input
C
VIN
DIG1
Via
to GND
Plane
AIN
Figure 12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•
•
INA240-Q1 Automotive, Wide Common-Mode Range, High- and Low-Side, Bidirectional, Zero-Drift, CurrentSense Amplifier With Enhanced PWM Rejection (SBOS808)
Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design (TIDU357)
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
e-Trim™ is a trademark of Texas Instruments, Inc.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
REF2025QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GACQ
REF2030QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GADQ
REF2033QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAEQ
REF2041QDDCRQ1
ACTIVE
SOT-23-THIN
DDC
5
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
GAFQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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