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REF5025-HT
SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
REF5025-HT Low-Noise, Very-Low-Drift, Precision Voltage Reference
1 Features
3 Description
•
•
•
•
The REF5025-HT is a low-noise, very low-drift, very
high precision voltage references. This reference is
capable of both sinking and sourcing, and is very
robust with regard to line and load changes.
1
•
•
•
•
Low Temperature Drift: 40 ppm/°C
Low Noise: 3 μVPP/V
High Output Current: ±7 mA
Low Temperature Drift:
5 ppm/°C (Maximum)
Available in Military (–55°C to +210°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Excellent temperature drift and high accuracy are
achieved using proprietary design techniques. These
features, combined with very low noise, make the
REF5025-HT suitable for use in high-precision data
acquisition systems.
The device is offered in HKJ and HKQ packages, as
well as Known-Good-Die (KGD) form, and is specified
from –55°C to +210°C.
2 Applications
•
•
•
•
•
•
•
•
•
(1)
Device Information(a)
16-Bit Data Acquisition Systems
ATE Equipment
Industrial Process Control
Medical Instrumentation
Optical Control Systems
Precision Instrumentation
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
PART NUMBER
REF5025-HT
PACKAGE
BODY SIZE (NOM)
CFP (HKJ)(8)
6.9 mm × 5.65 mm
CFP (HKQ) (8)
6.9 mm × 5.65 mm
XCEPT (KGD) (0)
2.04 mm × 1.676 mm
(a) For all available packages, see the orderable addendum at
the end of the data sheet.
Custom temperature ranges available
Simplified Schematic
5V
Input
Signal
0 V to 4 V
5V
R1
50 W
VDD
+IN
OPA365
ADS8326
C1
1.2 nF
-IN
REF
GND
REF5025
+5 V
VIN
CBYPASS
1 mF
GND
VOUT
C2
22 mF
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF5025-HT
SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 12
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
12
14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Applications ............................................... 15
8.3 System Example ..................................................... 19
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
10.3 Power Dissipation ................................................. 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (November 2013) to Revision F
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Ordering Information table, see POA at the end of the data sheet........................................................................... 1
Changes from Revision D (April 2012) to Revision E
•
2
Page
Added KGD2 package option ................................................................................................................................................ 1
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SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
5 Pin Configuration and Functions
HKJ Package
8-Pin CFP
Top View
DNC
VIN
TEMP
GND
1
8
2
7
3
6
4
5
HKQ Package
8-Pin CFP
Top View
DNC
NC
VOUT
TRIM/NR
DNC
NC
VOUT
TRIM/NR
DNC = Do not connect
NC = No internal connection
8
1
7
2
6
3
5
4
DNC
VIN
TEMP
GND
HKQ is a dead bug performed version of
HKJ
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
DNC
1, 8
—
Do not connect
GND
4
Power
System ground
NC
7
—
No internal connection
TEMP
3
O
Temperature monitoring pin provides a temperature-dependent voltage output
TRIM/NR
5
I
Output adjustment and noise reduction input. Connecting 1 μF to this pin creates a lowpass filter at the bandgap and reduce output noise
VIN
2
Power
VOUT
6
O
Power supply voltage. Range from VOUT + 0.2 V up to 18 V. TI recommends a bypass
capacitor with a value from 1 μF up to 10 μF
Very accurate, factory-trimmed voltage output. TI recommends a bypass capacitor with a
value from 1 μF up to 50 μF with ESR between 1 and 1.5 Ω
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REF5025-HT
SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
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Bare Die Information
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION
COMPOSITION
BOND PAD
THICKNESS
15 mils
Silicon with backgrind
GND
Al-Cu (0.5%)
598 nm
½
½
2040 mm
12
10
9
8
6
7
|
1676 µm
11
½
DIE THICKNESS
38 mm
2
1
0.0
3
4
5
½
|
38 mm
0.0
Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
NC
NC
4
X MIN
Y MIN
X MAX
Y MAX
1
35.45
46.55
111.45
122.55
2
496.75
56.55
572.75
132.55
VIN
3
607.45
56.55
683.45
132.55
NC
4
637.9
39.4
1013.9
115.4
TEMP
5
1660.1
47.2
1736.1
123.2
GND
6
1770.9
38.85
1847.05
115
GND
7
1877.1
59.6
2016.8
135.6
TRIM/NR
8
1904.65
1553.4
1980.65
1629.4
NC
9
1782.15
1553.4
1858.15
1629.4
VOUT
10
1080.2
1559.85
1219.9
1636
VOUT
11
880.25
1543.55
956.25
1619.55
NC
12
35.45
1553.45
111.45
1629.45
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SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Input voltage
MAX
UNIT
18
V
VIN
Output short-circuit
Operating temperature
–55
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
30
mA
210
°C
210
°C
210
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
3.25
18
V
IOUT
–7
7
mA
6.4 Thermal Information
REF5025-HT
THERMAL METRIC (1)
HJK, HKQ (CFP)
UNIT
8 PINS
RθJC
(1)
Junction-to-case thermal resistance
To ceramic side of case
5.7
To top of case lid (metal side of case)
13.7
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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REF5025-HT
SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
www.ti.com
6.5 Electrical Characteristics
at TA = 25°C, ILOAD = 0, CL = 1 μF, VIN = 3.25 V to 18 V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
TA = –55 to +125°C
MIN
TYP
TA = 210°C
MAX
MIN
TYP
MAX
UNIT
OUTPUT VOLTAGE (2.5 V)
VOUT
Output voltage
2.5
Initial accuracy (1)
VIN = 3.25 V
Output voltage
noise
f = 0.1 Hz to 10 Hz
0%
2.5
0.9%
V
0.14%
NOISE
7.5
μVPP
OUTPUT VOLTAGE TEMPERATURE DRIFT
dVOUT/dT
Output voltage
temperature drift (2)
Calculated from
–55°C to +210°C
40
ppm/°C
LINE REGULATION
dVOUT/dVIN
Line regulation
From VIN = 3.25 V to VIN = 18 V
1
2.2
63
215
ppm/V
–7 mA < ILOAD < 10 mA, VIN = 3.25 V
20
50
20
75
ppm/mA
Short-circuit current
VOUT = 0 V
25
Voltage output
At TA = 25°C
LOAD REGULATION
dVOUT/dILOAD
Load regulation
SHORT-CIRCUIT CURRENT
ISC
11
mA
TEMP PIN
Temperature sensitivity (3)
575
mV
2.64
mV/°C
200
μs
TURN-ON SETTLING TIME
Turn-on settling
time
To 0.1% with CL = 1 μF
POWER SUPPLY
VS
Supply voltage
3.25
Quiescent current
18
0.8
1.2
3.25
18
V
1.5
mA
TEMPERATURE RANGE
(1)
(2)
(3)
6
Specified range
–55°C to +210°C
Operating range
–55°C to +210°C
See Figure 5.
See Figure 4.
See Figure 10.
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SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
Estimated Life (Hours)
1000000
100000
Electromigration Fail Mode
10000
1000
110
130
150
170
190
210
230
Continous T J (°C)
(1)
See Absolute Maximum Ratings and Recommended Operating Conditions.
(2)
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. REF5025SKGD1 and REF5025SKGD2 Operating Life Derating Chart
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REF5025-HT
SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
www.ti.com
6.6 Typical Characteristics
7.50
8.00
6.50
7.00
5.50
6.00
5.00
4.50
M o re
Output Initial Accuracy (%)
Drift (ppm/°C)
0 .6
0 .5
0 .4
0 .3
0 .2
0
0 .1
-0 .1
-0 .2
-0 .3
-0 .4
-0 .5
-0 .6
54
46
50
42
38
30
34
26
22
14
18
10
6
2
Population (%)
P o p u la tio n (% )
Figure 3. Temperature Drift (–40°C to +125°C)
Figure 4. Temperature Drift (–55°C to +210°C)
Figure 5. Output Voltage and Initial Accuracy (210°C)
0.5
160
0.4
140
120
0.3
PSRR (dB)
Output Voltage Accuracy (%)
3.50
Drift (ppm/°C)
Figure 2. Temperature Drift (0°C to 85°C)
0.2
0.1
0
100
80
60
40
-0.1
20
0
-0.2
Temperature (°C)
1k
Frequency (Hz)
Figure 6. Output Voltage Accuracy vs Temperature
Figure 7. Power-Supply Rejection Ratio vs Frequency
-55
8
4.00
2.50
Drift (ppm/°C)
3.00
1.50
2.00
0.50
1.00
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
0
Population (%)
Population (%)
at TA = 25°C, ILOAD = 0, VS = 3.25 V (unless otherwise noted).
25
125
180
210
10
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100
10k
100k
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Typical Characteristics (continued)
at TA = 25°C, ILOAD = 0, VS = 3.25 V (unless otherwise noted).
0.8
2.514
+125°C
55°C
2.512
25°C
2.51
0.6
+25°C
2.508
Output Voltage (V)
Dropout Voltage (V)
0.7
0.5
-40°C
0.4
0.3
2.506
2.504
2.502
0.2
2.5
0.1
2.498
210°C
2.496
0
-15
-5
0
5
Load Current (mA)
-10
10
2.494
15
-10
-5
Figure 8. Dropout Voltage vs Load Current
10
1200
1
1100
0.9
1000
IQ (µA)
0.8
0.7
900
0.6
800
0.5
700
0.4
0.3
600
-75
-50
-25
0
25
50
75
100 125 150 175 200 225
-75
-50 -25
0
25
Temperature (°C)
50
75
100 125 150 175 200 225
Temperature (°C)
Figure 10. Temperature Pin Output Voltage vs Temperature
Figure 11. Quiescent Current vs Temperature
1400
70
1300
Line Regulation (ppm/V)
60
210°C
1200
1100
IQ (µA)
5
Figure 9. Output Voltage vs Load Current
1.1
Temp Pin Output Voltage (V)
0
L o ad C u rren t (m A)
1000
900
25°C
800
–55°C
700
50
40
30
20
10
0
-10
600
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
-75
-50
-25
0
25
50
75
100 125 150 175 200 225
V IN (V)
Temperature (°C)
Figure 12. Quiescent Current vs Input Voltage
Figure 13. Line Regulation vs Temperature
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REF5025-HT
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Typical Characteristics (continued)
at TA = 25°C, ILOAD = 0, VS = 3.25 V (unless otherwise noted).
25
Sourcing
20
1mV/div
Short-Circuit Current (mA)
30
15
Sinking
10
5
0
-75
-50
-25
0
25
50
75
100 125 150
175 200
Temperature (°C)
1s/div
Figure 14. Short-Circuit Current vs Temperature
Figure 15. Noise
VIN
5V/div
VIN
2V/div
VOUT
VOUT
1V/div
1V/div
40ms/div
400ms/div
CL = 1 μF
CL = 10 μF
Figure 16. Start-Up (REF5025)
Figure 17. Start-Up (REF5025)
ILOAD
+1mA
ILOAD
10mA/div
+10mA
+10mA
-1mA
-1mA
1mA/div
-10mA
VOUT
VOUT
5mV/div
2mV/div
20ms/div
IOUT = 1 mA
CL = 1 μF
20ms/div
IOUT = 10 mA
Figure 18. Load Transient
10
CL = 1 μF
Figure 19. Load Transient
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Typical Characteristics (continued)
at TA = 25°C, ILOAD = 0, VS = 3.25 V (unless otherwise noted).
ILOAD
+1mA
ILOAD
10mA/div
+10mA
-10mA
-10mA
-1mA
-1mA
1mA/div
VOUT
VOUT
2mV/div
5mV/div
100ms/div
CL = 10 μF
IOUT = 1 mA
100ms/div
CL = 10 μF
Figure 20. Load Transient
IOUT = 10 mA
Figure 21. Load Transient
500mV/div
VIN
VIN
500mV/div
5mV/div
VOUT
VOUT
5mV/div
20ms/div
100ms/div
CL = 1 μF
CL = 10 μF
Figure 22. Line Transient
Figure 23. Line Transient
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REF5025-HT
SBOS502F – SEPTEMBER 2009 – REVISED DECEMBER 2016
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7 Detailed Description
7.1 Overview
The REF5025-HT devices are low-noise, low-drift, very high precision voltage references. These references can
both sink and source, and are very robust with regard to line and load changes.
7.2 Functional Block Diagram
VIN
REF5025
R2
R1
aT
(10mA
at +25°C)
VOUT
R4
TEMP
aT
10kW
R3
TRIM/NR
1.2V
R5
60kW
1kW
GND
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7.3 Feature Description
7.3.1 Output Adjustment Using the TRIM/NR Pin
The REF5025-HT provides a very accurate, factory-trimmed voltage output. However, VOUT can be adjusted
using the trim and noise reduction pin (TRIM/NR, pin 5). Figure 24 shows a typical circuit that allows an output
adjustment of ±15 mV.
+VSUPPLY
REF5025
DNC
VIN
TEMP
DNC
NC
VOUT
GND TRIM/NR
10kW
470W
1kW
Copyright © 2016, Texas Instruments Incorporated
Figure 24. VOUT Adjustment Using the TRIM/NR Pin
The REF5025-HT allows access to the bandgap through the TRIM/NR pin. Placing a capacitor from the
TRIM/NR pin to GND (see Figure 26) in combination with the internal R3 and R4 resistors creates a low-pass
filter. A capacitance of 1 μF creates a low-pass filter with the corner frequency between 10 Hz and 20 Hz. Such a
filter decreases the overall noise measured on the VOUT pin by half. Higher capacitance results in a lower filter
cutoff frequency, further reducing output noise. Use of this capacitor increases start-up time.
12
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Feature Description (continued)
7.3.2 Low Temperature Drift
The REF5025-HT is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by Equation 1:
æ V
- VOUTMIN ö
6
Drift = ç OUTMAX
÷ ´ 10 (ppm)
è VOUT ´ Temp Range ø
(1)
7.3.3 Temperature Monitoring
The temperature output terminal (TEMP, pin 3) provides a temperature-dependent voltage output with
approximately 60-kΩ source impedance. As seen in Figure 10, the output voltage follows the nominal
relationship:
VTEMP
PIN
= 509 mV + 2.64 × T(°C)
(2)
This pin indicates general chip temperature, accurate to approximately ±15°C. Although it is not generally
suitable for accurate temperature measurements, it can be used to indicate temperature changes or for
temperature compensation of analog circuitry. A temperature change of 30°C corresponds to an approximate 79
mV change in voltage at the TEMP pin.
The TEMP pin has high output impedance (see Functional Block Diagram). Loading this pin with a lowimpedance circuit induces a measurement error; however, it does not have any effect on VOUT accuracy. To
avoid errors caused by low-impedance loading, buffer the TEMP pin output with a suitable low-temperature drift
operational amplifiers, such as the OPA333, OPA335, or OPA376, as shown in Figure 25.
+V
REF5025
DNC
VTEMP
2.6 mV/°C
OPA(1)
VIN
TEMP
GND
DNC
NC
VOUT
TRIM/NR
NOTE: (1) Low drift op amp, such as the OPA333, OPA335, or OPA376.
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Figure 25. Buffering the TEMP Pin Output
7.3.4 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise the REF5025-HT is specified in the Electrical Characteristics table. The
noise voltage increases with output voltage and operating temperature. Additional filtering can improve output
noise levels, although take care to ensure the output impedance does not degrade performance.
For additional information about how to minimize noise and maximize performance in mixed-signal applications
such as data converters, see Analog Applications Journal articles entitled How a Voltage Reference Affects ADC
Performance. Part 1 (SLYT331), How the Voltage Reference Affects ADC Performance, Part 2 (SLYT339), and
How the Voltage Reference Affects ADC Performance, Part 3 (SLYT355). This three-part series is available for
download from the TI website.
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Feature Description (continued)
+VSUPPLY
REF5025
DNC
VIN
TEMP
GND
DNC
NC
VOUT
TRIM/NR
C1
1 mF
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Noise Reduction Using the TRIM/NR Pin
7.4 Device Functional Modes
The REF5025-HT is powered on when the voltage on the VIN pin is greater than 3.25 V. The maximum input
voltage for the REF5025-HT is 18 V. Use a supply bypass capacitor with a value ranging from 1 μF to 10 μF. The
total capacitive load at the output must be between 1 μF to 50 μF to ensure the best output stability.
14
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The REF5025-HT device is a low-noise, precision bandgap voltage reference that is specifically designed for
excellent initial voltage accuracy and drift. See the Functional Block Diagram.
When designing circuits with a voltage reference, output noise is one of the main concerns. The main source of
voltage noise in the reference voltages originates from the bandgap and output amplifier, which contribute
significantly to the overall noise. During the design process, it is important to minimize these sources of voltage
noise.
8.2 Typical Applications
8.2.1 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF5025-HT and OPA735 can provide
a dual-supply reference from a 5-V supply. Figure 27 shows how the REF5025-HT provides a 2.5-V supply
reference voltage. The low-drift performance of the REF5025-HT complements the low offset voltage and zero
drift of the OPA735 to provide an accurate solution for split-supply applications. Take care to match the
temperature coefficients of R1 and R2.
+5 V
REF5025
DNC
VIN
DNC
NC
TEMP
GND
VOUT
TRIM/NR
+2.5 V
1m F
R1
10 kW
R2
10 kW
+5 V
OPA735
-2.5 V
-5 V
NOTE: Bypass capacitors not shown.
Copyright © 2016, Texas Instruments Incorporated
Figure 27. The REF5025-HT and OPA735 Create Positive and Negative Reference Voltages
8.2.1.1 Design Requirements
When using REF5025-HT in the design, it is important to select a proper capacitive load that do not create gain
peaking adding noise to the output voltage. At the same time, the capacitor must be selected to provide required
filtering performance for the system. Input bypass capacitor and noise reduction capacitors must be added for
optimum performances.
8.2.1.2 Detailed Design Procedure
Proper design procedure will require first to select output capacitor. If the ESR of the capacitor is not in 1-Ω
range additional resistor must be added in series with the load capacitor. Next, add a 1-µF capacitor to the NR
pin to reduce internal noise of the REF5025-HT. Measuring output noise will confirm if the design has met the
initial target.
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Typical Applications (continued)
8.2.1.3 Application Curves
Figure 28. Noise Measurements of Properly Design
REF5025 Data Acquisition System From Figure 35
Figure 29. FFT of Data Acquisition System Design With
REF5025 From Figure 35
8.2.2 Positive Reference Voltage
Variable
+5 V
NC
1
VIN
2
8 NC
7 NC
REF5025
CIN
10 µF
TEMP
3
6 VOUT
GND
4
5 TRIM
+2.5 V
COUT
1 µF - 50 µF
Copyright © 2016, Texas Instruments Incorporated
Figure 30. REF5025-HT With Load Capacitor
8.2.2.1 Detailed Design Procedure
8.2.2.1.1 Load Capacitance
To determine how much noise the reference voltage is contributing in a real application, this design uses the
circuit presented in Figure 30. For the same conditions as power supply, input decoupling, and load current,
measure the output noise for different output decoupling or load capacitors. The load capacitor type will change
the low-pass filter frequency that is created on the output. This filter is determined by an added capacitor value
and two parasitic components: the open-loop output impedance of the internal amplifier to the reference voltage,
and the ESR of the external capacitor.
Figure 31 shows a fast-Fourier-transform (FFT) plot of the output signal of the reference voltage circuit with a 10μF ceramic capacitor load. The output noise level peaks at around 9 kHz because of the response of the internal
amplifier of the circuit to the capacitive load (CL).
This peaking is the main contributor to the overall measured noise. This output noise, measured with an analog
meter over a frequency range of up to 80 kHz, is approximately 16.5 μVRMS. If the voltage-reference circuit was
connected to the input of an ADC, the measured noise across a 65-kHz frequency range would be 138 μVPP.
This noise level makes this solution adequate for 8- to 14-bit converters.
16
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Typical Applications (continued)
Figure 31. REF5025 FFT Plot of the Noise
With 10-µF Load Capacitor and 10-µΩ ESR
Every capacitor can be represented with a complicated equivalent model, which is voltage and frequency
dependent with a large number of passive components. For the purposes of this design, this model is limited to
the few components. The biggest impact on the creation of the low-pass filter and stability analysis is the
simplified model of equivalent series inductance and resistance. Considering good layout practice and inherently
low equivalent series inductance of today’s components, this model in the future analysis will be presented only
by equivalent capacitance and series resistance.
VCC
RO
ESR
CL
ƒP =
1
2p • (R + ESR) • CL
ƒZ =
1
2p • ESR • CL
Figure 32. Equivalent SCH of REF5025 With Load Capacitor for Stability Analysis
When evaluating the impact of ESR and CL on the performance the reference voltage, it is important to include
the effect of the open-loop output resistance (RO) of the output amplifier. The combination of RO, ESR, and CL
modifies the open-loop response curve by introducing one pole (fP) and one zero (fZ). The values RO, ESR, and
CL determine the corner frequency of the added pole fP; and the values of ESR and CL determine the corner
frequency of the added zero.
The introduction of the external ESR-CL on the output of the reference voltage modifies the output amplifier
open-loop gain curve. The added pole modifies the open-loop gain curve of the reference voltage output amplifier
by introducing a –20 dB/decade change at the frequency fP to the already –20 dB/decade slope of the open-loop
gain curve, making the slope equal to –40 dB/decade. The added zero at frequency fZ changes the open-loop
gain curve back to –20 dB/decade.
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Typical Applications (continued)
Table 1. Noise Measurement Results for Different Load Capacitors
NOISE
22 kHz
LP-5P
30 kHz
LP-3P
80 kHz
LP-3P
> 500 kHz
GND
0.8
1
1.8
4.9
1 µF
37.8
41.7
53.7
9017
2.2 µF (cer)
41.7
46.2
55.1
60.8
10 µF
33.4
33.4
35.2
38.5
10 µF (cer)
37.1
37.2
37.8
39.1
20 µF (cer)
33.1
33.1
33.2
34.5
47 µF
23.2
23.8
24.1
26.5
UNIT
µVRMS
Table 1 shows the measured noise values for different frequency bandwidths as well as different values and
types of external capacitors. These measurements show that low-ESR (approximately 100-mΩ) ceramic
capacitors tend to increase the noise, compared to normal-ESR (approximately 2-Ω) tantalum capacitors. This
tendency is caused by a stability issue with the output amplifier and gain peaking in the amplifier frequency
response.
8.2.2.1.2 Bandgap Noise Reduction
R2
R1
VOUT
10k
1.2V
TRIM
1k
Figure 33. REF5025-HT Internal Structure of Trim/NR Pin
The internal schematic of the REF5025-HT device shows that the trim pin allows direct access to the bandgap
output. Figure 33 shows the trim pin connection to the internal bandgap circuit through a resistor. Adding a
capacitor on the trim pin creates a lowpass filter that has a broadband attenuation of −21 dB.
For example, a small 1-μF capacitor adds a pole at 14.5 Hz and a zero at 160 Hz. If more filtering is needed, a
larger value capacitor can be added, which will lower the filter cutoff frequency and the noise contributed by the
bandgap.
18
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Table 2. Measured Noise (µVRMS) for Four Bandwidths
NOISE
22 kHz (LOW-PASS 30 kHz (LOW-PASS
5-POLE)
3-POLE)
80 kHz (LOWPASS 3-POLE)
> 500 kHz
GND
0.8
1
1.8
4.6
2.2 µF (ceramic)
42.5
47.2
61.2
68.3
2.2 µF + 1 µF
17.5
19.4
22.6
24.5
10 µF (ceramic)
34.4
35.6
37.7
44.5
10 µF + 1 µF
14.1
14.4
14.9
16.4
20 µF (ceramic)
34.8
34.9
35.1
35.2
20 µF + 1 µF
14.4
14.4
14.7
15.1
UNIT
µVRMS
Adding a 1-μF capacitor in this example filters the noise contribution of the bandgap and lowers the total noise by
a factor of 2.5 times.
8.3 System Example
8.3.1 Data Acquisition
Data acquisition systems often require stable voltage references to maintain accuracy. The REF5025-HT family
features low noise, very low drift, and high initial accuracy for high-performance data converters. Figure 34
shows the REF5040 as an example in a basic data acquisition system. The same principle can be applied when
designing with REF5025-HT.
+5 V
Input
Signal
0 V to 4 V
+5 V
R1
50 W
OPA365
VDD
+IN
ADS8326
C1
1.2 nF
-IN
REF
GND
REF5040
VIN
+5 V
VOUT
CBYPASS
1 mF
C2
22 mF
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Basic Data Acquisition System
During the design of the data acquisition system, equal consideration must be given to the buffering analog input
signal as well as the reference voltage. Having a properly designed input buffer with an associated RC filter is a
necessary requirement, but does not ensure the maximum performance.
REF5040
ESR
10 uF
47 uF
REFIN
CS
124 W
ADS8326
0-4 V
OPA365
CLK
SDO
1 nF
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Complete Data Acquisition System Using REF50xx
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System Example (continued)
Three measurements using different components of the output are shown for this data acquisition system.
Table 3 shows improvements on the FFT for a properly designed system.
Table 3. Data Acquisition Measurement Results for Different Conditions
OPA365
REF5040
TRIM
124 Ω, 1 nF
10 µF
0 µF
124 Ω, 1 nF
10 µF + 47 µF
1 µF
124 Ω, 100 µF
10 µF + 47 µF
1 µF
UNIT
Resolution
16
16
16
Bits
States
65536
65536
65536
VREF
4.096
4.096
4.096
V
LSB
62.5
62.5
62.5
µV
VIN
4.02
4.02
4.02
V
Data Std
1.07
0.53
0.41
LSB
Noise
67.0
33.4
25.8
µVRMS
Noise
442.3
220.5
170.2
µVPP
SNR
86.7
92.8
95.0
dB
FTT Points
32768
32768
32768
Noise Flor
–128.8
–134.9
–131.7
dB
Once the correct components for data acquisition system from Figure 35 are selected, measurement results can
be compared to the ADS8326 data sheet specifications.
Table 4. AC Performance for Data Acquisition System From Figure 35
20
REF5040
TRIM
ADS8326
DATA SHEET
ADS8326B
DATA SHEET
SYSTEM
LOW ESR
SYSTEM
10 µF + 47 µF
1µF
UNIT
SNR
91
91.5
90.6
92.2
dB
SINAD
87.5
88
85.7
89.5
dB
SFDR
94
95
88.3
98.4
dB
THD
–90
–91
–87.3
–92.9
dB
ENOB
14.28
14.35
13.94
14.58
Bits
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9 Power Supply Recommendations
The minimum recommended power supply voltage for REF5025-HT is 3.25 V. The maximum power supply
voltage for the REF5025-HT is 18 V. TI recommends adding a bypass capacitor of 1 μF to 10 μF at the input to
compensate for the layout and power supply source impedance.
Figure 36 shows the typical connections for the REF5025-HT. TI recommends a supply bypass capacitor with a
value ranging from 1 μF to 10 μF. A 1-μF to 50-μF output capacitor (CL) must be connected from VOUT to GND.
The ESR value of CL must be less than or equal to 1.5-Ω to ensure output stability. To minimize noise, TI
recommends the ESR value of the of CL is between 1-Ω and 1.5-Ω.
+VSUPPLY
REF5025
DNC
CBYPASS
1mF to 10mF
VIN
TEMP
DNC
NC
VOUT
GND TRIM/NR
VOUT
CL
1mF to 50mF
Copyright © 2016, Texas Instruments Incorporated
Figure 36. Basic Connections
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place the power-supply bypass capacitor as closely as possible to the VIN pin and ground pins. TI
recommends a bypass capacitor value of 1 μF to 10 μF. If necessary, additional decoupling capacitance can
be added to compensate for noisy or high-impedance power supplies.
Place a 1-µF noise filtering capacitor between the NR pin and ground.
The output must be decoupled with a 1-µF to 50-µF capacitor. In series with the load capacitor, add an ESR
of 1-Ω for the best noise performance.
A high-frequency, 1-µF capacitor can be added in parallel between the output and ground to filter noise and
help with switching loads as data converters.
10.2 Layout Example
ESR
Low ESR
Capacitor
Bypass
Capacitor
VIH
TMP
VOUT
GND
Trim/NR
Low ESR
Capacitor
VOUT
GND
Noise
Reduction
Capacitor
Figure 37. Recommended Layout for REF5025-HT
10.3 Power Dissipation
The REF50xx family is specified to deliver current loads of ±10-mA over the specified input voltage range. The
temperature of the device increases according to Equation 3:
TJ = TA + PD × RθJA
Where:
•
•
•
•
TJ = Junction temperature (°C)
TA = Ambient temperature (°C)
PD = Power dissipated (W)
RθJA = Junction-to-ambient thermal resistance (°C/W)
(3)
The REF50xx junction temperature must not exceed the absolute maximum rating of +150°C.
22
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• 0.05uV/degC (max), Single-Supply CMOS Zero-Drift Series Operational Amplifier (SBOS282)
• REF5020 PSpice Model (SLIM160)
• REF5020 TINA-TI Reference Design (SLIM159)
• REF5020 TINA-TI Spice Model (SLIM158)
• INA270 PSpice Model (SBOM485)
• INA270 TINA-TI Reference Design (SBOC246)
• INA270 TINA-TI Spice Model (SBOM306)
• How a Voltage Reference Affects ADC Performance (SLYT331)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF5025SHKJ
ACTIVE
CFP
HKJ
8
25
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
REF5025S
HKJ
Samples
REF5025SHKQ
ACTIVE
CFP
HKQ
8
25
RoHS & Green
AU
N / A for Pkg Type
-55 to 210
REF5025S
HKQ
Samples
REF5025SKGD1
ACTIVE
XCEPT
KGD
0
195
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
Samples
REF5025SKGD2
ACTIVE
XCEPT
KGD
0
10
RoHS & Green
Call TI
N / A for Pkg Type
-55 to 210
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
