REF5010, REF5020, REF5025, REF5030, REF5040, REF5045, REF5050
SBOS410J – JUNE 2007 – REVISED JULY 2022
REF50xx
Low-Noise, Very Low Drift, Precision Voltage Reference
1 Features
3 Description
•
The REF50xx is a family of low-noise, low-drift, very
high precision voltage references. These references
are capable of both sinking and sourcing current, and
have excellent line and load regulation.
•
•
•
•
•
Low temperature drift:
– High-grade: 3 ppm/°C (maximum)
– Standard-grade: 8 ppm/°C (maximum)
High accuracy:
– High-grade: 0.05% (maximum)
– Standard-grade: 0.1% (maximum)
Low noise: 3 μVPP/V
Excellent long-term stability:
– 50 ppm/1000 hr (typical) first 1000 hours
(VSSOP)
Excellent temperature drift (3 ppm/°C) and high
accuracy (0.05%) are achieved using proprietary
design techniques. These features, combined with
very low noise, make the REF50xx family ideal for use
in high-precision data acquisition systems.
Each reference voltage is available in both high grade
(REF50xxIDGK and REF50xxID) and standard grade
(REF50xxAIDGK and REF50xxAID). The reference
voltages are offered in 8-pin VSSOP and SOIC
packages, and are specified from –40°C to 125°C.
– 25 ppm/1000 hr (typical) second 2000 hours
(VSSOP)
High-output current: ±10 mA
Temperature range: –40°C to 125°C
2 Applications
•
•
•
•
•
•
Device Information(1)
PART NUMBER
Precision data acquisition systems
Semiconductor test equipment
Industrial process controls
Medical instrumentation
Pressure and temperature transmitters
Lab and field instrumentation
REF50xx
(1)
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
5V
5V
R1
124 Ÿ
Input Signal,
0 V to 4 V
VDD
IN
OPA365
ADS8326
C1
1 nF
IN
+5V
REF GND
REF5040
VIN
VOUT
CBYPASS
1 µF
C2
22 µF
GND
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF5010, REF5020, REF5025, REF5030, REF5040, REF5045, REF5050
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SBOS410J – JUNE 2007 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 7
8 Parameter Measurement Information.......................... 12
9 Detailed Description......................................................14
9.1 Overview................................................................... 14
9.2 Functional Block Diagram......................................... 14
9.3 Feature Description...................................................15
9.4 Device Functional Modes..........................................18
10 Applications and Implementation.............................. 19
10.1 Application Information........................................... 19
10.2 Typical Applications................................................ 19
11 Power Supply Recommendations..............................20
12 Layout...........................................................................21
12.1 Layout Guidelines................................................... 21
12.2 Layout Example...................................................... 21
12.3 Power Dissipation................................................... 21
13 Device and Documentation Support..........................22
13.1 Documentation Support.......................................... 22
13.2 Receiving Notification of Documentation Updates..22
13.3 Support Resources................................................. 22
13.4 Trademarks............................................................. 22
13.5 Glossary..................................................................22
14 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (February 2020) to Revision J (July 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Changes from Revision H (June 2016) to Revision I (February 2020)
Page
• Added REF5045 to table.................................................................................................................................... 5
• Changed Long-Term Stability parameters.......................................................................................................... 5
• Changed Long-Term Stability Graphs for VSSOP ............................................................................................. 7
• Added section on Long-Term Stability ............................................................................................................. 16
2
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SBOS410J – JUNE 2007 – REVISED JULY 2022
5 Device Comparison Table
MODEL
OUTPUT VOLTAGE
REF5020
2.048 V
REF5025
2.5 V
REF5030
3V
REF5040
4.096 V
REF5045
4.5 V
REF5050
5V
REF5010
10 V
6 Pin Configuration and Functions
DNC(1)
1
VIN
2
8
DNC(1)
7
NC(2)
6
VOUT
5
TRIM/NR
REF50xx
TEMP
3
GND
4
NOTES: (1) DNC = Do not connect.
(2) NC = No internal connection.
Figure 6-1. D, DGK Packages 8-Pin SOIC, VSSOP Top View
Table 6-1. Pin Functions
PIN
NAME
DESCRIPTION
NO.
DNC
1
Do not connect
VIN
2
Input supply voltage
TEMP
3
Temperature monitoring pin. Provides a temperature-dependent output voltage
GND
4
Ground
TRIM/NR
5
Output adjustment and noise reduction pin
VOUT
6
Reference voltage output
NC
7
No internal connection
DNC
8
Do not connect
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SBOS410J – JUNE 2007 – REVISED JULY 2022
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input voltage
–0.2
18
V
Output short circuit
–30
30
mA
Operating temperature
–55
125
°C
150
°C
150
°C
Junction temperature (TJ max)
Storage temperature, Tstg
(1)
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
UNIT
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
IOUT
(1)
NOM
MAX
UNIT
VOUT + 0.2 V(1)
18
V
–10
10
mA
Except for the REF5020, where VIN (minimum) = 2.7 V
7.4 Thermal Information
REF50xx
THERMAL
D (SOIC)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
115
160.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
63.4
53.9
°C/W
RθJB
Junction-to-board thermal resistance
57.1
82.3
°C/W
ψJT
Junction-to-top characterization parameter
15.4
5.1
°C/W
ψJB
Junction-to-board characterization parameter
56.2
80.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
METRIC(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS410J – JUNE 2007 – REVISED JULY 2022
7.5 Electrical Characteristics
At TA = 25°C, ILOAD = 0, CL = 1 μF, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT VOLTAGE
REF5020 (VOUT = 2.048 V)(1),
2.7 V < VIN < 18 V
2.048
REF5025
VOUT
Output voltage
2.5
REF5030
3.0
REF5040
4.096
REF5045
4.5
REF5050
5.0
REF5010
10.0
V
Initial accuracy: high grade
All voltage options(1)
–0.05%
0.05%
Initial accuracy: standard grade
All voltage options(1)
–0.1%
0.1%
Output voltage noise
f = 0.1 Hz to 10 Hz
NOISE
3
µVPP/V
OUTPUT VOLTAGE TEMPERATURE DRIFT
dVOUT/dT
Output voltage temperature drift
High grade
2.5
3
ppm/°C
3
8
ppm/°C
VIN = (VOUT + 0.2) to 18 V(4)
0.1
1
ppm/V
VIN = VOUT + 0.2 V,
TA = –40°C to 125°C(4)
0.2
1
ppm/V
–10 mA < ILOAD < 10 mA,
VIN = VOUT + 0.75 V(5)
20
30
ppm/mA
50
ppm/mA
Standard grade
LINE REGULATION
ΔVO(ΔVI)
Line regulation
LOAD REGULATION
ΔVO(ΔIL)
Load regulation
–10 mA < ILOAD < 10 mA,
VIN = VOUT + 0.75 V
TA = –40°C to 125°C(5)
SHORT-CIRCUIT CURRENT
ISC
Short circuit current
VOUT = 0
25
mA
THERMAL HYSTERESIS(2) (3)
High grade
VSSOP-8
Cycle 1
50
ppm
Standard grade
VSSOP-8
Cycle 1
70
ppm
High grade
SOIC-8
Cycle 1
70
ppm
Standard grade
SOIC-8
Cycle 1
90
ppm
High grade
VSSOP-8
Cycle 2
40
ppm
Standard grade
VSSOP-8
Cycle 2
40
ppm
High grade
SOIC-8
Cycle 2
50
ppm
Standard grade
SOIC-8
Cycle 2
50
ppm
VSSOP-8
0 to 1000 hours
50
ppm/1000 hr
VSSOP-8
1000 to 2000 hours
25
ppm/1000 hr
SOIC-8
0 to 1000 hours
100
ppm/1000 hr
SOIC-8
1000 to 2000 hours
50
ppm/1000 hr
LONG-TERM STABILITY(3)
TEMP PIN
Voltage output
At TA = 25°C
575
mV
Temperature sensitivity
TA = -40°C to 125°C
2.64
mV/°C
To 0.1% with CL = 1 μF
200
μs
TURN-ON SETTLING TIME
Turn-on settling time
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At TA = 25°C, ILOAD = 0, CL = 1 μF, and VIN = (VOUT + 0.2 V) to 18 V, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
Supply voltage
Quiescent current
See note (1)
VOUT +
0.2(1)
0.8
TA = –40°C to 125°C
18
V
1
mA
1.2
mA
TEMPERATURE RANGE
(1)
(2)
(3)
(4)
(5)
6
Specified range
–40
125
°C
Operating range
–55
125
°C
For VOUT ≤ 2.5 V, the minimum supply voltage is 2.7 V.
The thermal hysteresis procedure is explained in more detail in Section 9.3.3.
Data collected using devices soldered onto the test board.
Except for REF5020, where VIN = 2.7 V to 18 V
Except for REF5020, where VIN = 3 V
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7.6 Typical Characteristics
7.50
8.00
6.50
7.00
5.50
6.00
4.50
5.00
3.50
4.00
2.50
Drift (ppm/°C)
3.00
1.50
2.00
0.50
1.00
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
0
Population (%)
Population (%)
At TA = 25°C, ILOAD = 0, and VS = VOUT + 0.2 V, unless otherwise noted. For VOUT ≤ 2.5 V, the minimum supply
voltage is 2.7 V.
Drift (ppm/°C)
0°C to 85°C
–40°C to 125°C
Figure 7-1. Temperature Drift
Figure 7-2. Temperature Drift
0.015
0.01
0.005
0
-0.005
-0.01
-0.015
-0.02
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
Population (%)
Output Voltage Accuracy (%)
0.02
±50
±25
25
50
75
100
125
0.8
140
0.7
120
0.6
Dropout Voltage (V)
160
100
80
60
40
20
C001
Figure 7-4. Output Voltage Accuracy vs
Temperature
Figure 7-3. Output Voltage Initial Accuracy
PSRR (dB)
0
Temperature (ºC)
Output Initial Accuracy (%)
+125°C
+25°C
0.5
-40°C
0.4
0.3
0.2
0.1
0
0
10
100
1k
Frequency (Hz)
10k
100k
Figure 7-5. Power-Supply Rejection Ratio vs
Frequency
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-15
-10
-5
0
5
Load Current (mA)
10
15
Figure 7-6. Dropout Voltage vs Load Current
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SBOS410J – JUNE 2007 – REVISED JULY 2022
2.50125
0.9
TEMP Pin Output Voltage (V)
2.50100
Output Voltage (V)
2.50075
2.50050
2.50025
+25°C
2.50000
2.49975
2.49950
-40°C
2.49925
+125°C
2.49900
2.49875
-10
-5
0
Load Current (mA)
5
0.5
0.4
0
-25
25
50
Temperature (°C)
75
100
125
Figure 7-8. Temp Pin Output Voltage vs
Temperature
1050
1000
1000
950
950
900
+125?C
900
850
IQ (mA)
Quiescent Current (mA)
0.6
-50
850
800
+25?C
800
750
750
-40?C
700
700
650
650
600
600
-50
-25
0
25
50
Temperature (°C)
75
100
2
125
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
VIN (V)
Figure 7-9. Quiescent Current vs Temperature
Figure 7-10. Quiescent Current vs Input Voltage
0.5
35
0.4
Sourcing
30
Short-Circuit Current (mA)
Line Regulation (ppm/V)
0.7
0.3
10
Figure 7-7. REF5025 Output Voltage vs Load
Current
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
25
20
Sinking
15
10
5
-0.4
0
-0.5
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 7-11. Line Regulation vs Temperature
8
0.8
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-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 7-12. Short Circuit Current vs Temperature
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1mV/div
VIN
2V/div
VOUT
1V/div
40ms/div
1s/div
Figure 7-13. NOISE
REF5025, CL = 1 μF
Figure 7-14. Start-Up
+1mA
VIN
ILOAD
5V/div
-1mA
-1mA
1mA/div
VOUT
5mV/div
VOUT
1V/div
400ms/div
20ms/div
REF5025, CL = 10 μF
CL = 1 μF, IOUT = 1 mA
Figure 7-15. Start-Up
Figure 7-16. Load Transient
ILOAD
10mA/div
+1mA
+10mA
+10mA
ILOAD
-1mA
-1mA
1mA/div
-10mA
VOUT
VOUT
5mV/div
2mV/div
20ms/div
CL = 1 μF, IOUT = 10 mA
Figure 7-17. Load Transient
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100ms/div
CL = 10 μF, IOUT = 1 mA
Figure 7-18. Load Transient
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ILOAD
10mA/div
+10mA
-10mA
-10mA
VIN
500mV/div
VOUT
2mV/div
VOUT
5mV/div
100ms/div
20ms/div
CL = 10 μF, IOUT = 10 mA
CL = 1 μF
Figure 7-19. Load Transient
Figure 7-20. Line Transient
250
5mV/div
VIN
Output Voltage Stability (ppm)
500mV/div
VOUT
200
150
100
50
0
-50
-100
100ms/div
0
CL = 10 μF
100
200
300
400
500 600
Hours
700
800
900 1000
VSSOP-8
Figure 7-21. Line Transient
250
250
200
200
Output Voltage Stability (ppm)
Output Voltage Stability (ppm)
Figure 7-22. REF50xx Long-Term Stability (First
1000 Hours)
150
100
50
0
-50
-100
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
Hours
VSSOP-8
Figure 7-23. REF50xx Long-Term Stability (Second
1000 Hours)
10
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150
100
50
0
-50
-100
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Hours
VSSOP-8
Figure 7-24. REF50xx Long-Term Stability (First
2000 Hours)
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250
250
200
200
Output Voltage Stability (ppm)
Output Voltage Stability (ppm)
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150
100
50
0
-50
150
100
50
0
-50
-100
2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000
Hours
A.
-100
0
400
800 1200 1600 2000 2400 2800 3200 3600 4000
Hours
VSSOP-8
VSSOP-8
Figure 7-25. REF50xx Long-Term Stability (Second
2000 Hours)
Figure 7-26. REF50xx Long-Term Stability (4000
Hours)
300
250
Output Voltage Stability (ppm)
Output Voltage Stability (ppm)
250
200
150
100
50
0
-50
-100
-150
-200
-250
-300
0
100
200
300
400
500
600
700
800
150
100
50
0
-50
-100
-150
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
900 1000
Hours
200
Hours
C001
SOIC-8
C001
SOIC-8
Figure 7-27. REF50xx Long-Term Stability (First
1000 Hours)
Figure 7-28. REF50xx Long-Term Stability (Second
1000 Hours)
300
Output Voltage Stability (ppm)
250
200
150
100
50
0
-50
-100
-150
-200
-250
-300
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Hours
C001
SOIC-8
Figure 7-29. REF50xx Long-Term Stability (2000 Hours)
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8 Parameter Measurement Information
Solder Heat Shift: The materials used in the manufacture of the REF50xx have differing coefficients of thermal
expansion, resulting in stress on the device die when the part is heated. Mechanical and thermal stress on
the device can cause the output voltages to shift, degrading the initial accuracy and drift specifications of the
product. Reflow soldering is a common cause of this error.
To illustrate this effect, a total of 36 devices were soldered on printed-circuit-boards using lead-free solder
paste and the paste manufacturer suggested reflow profile. The reflow profile is as shown in Figure 8-1. The
printed-circuit-board is comprised of FR4 material. The board thickness is 0.8 mm and the area is 13 mm × 13
mm.
The reference voltage is measured before and after the reflow process across temperature; the typical shift of
accuracy and drift is displayed in Figure 8-2 through Figure 8-9. Although all tested units exhibit very low shifts,
higher shifts are also possible depending on the size, thickness, and material of the printed-circuit-board. An
important note is that the histograms display the typical shift for exposure to a single reflow profile. Exposure to
multiple reflows, as is common on printed circuit boards (PCBs) with surface-mount components on both sides,
causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, then solder the
device in the last pass to minimize device exposure to thermal stress.
300
Temperature (ƒC)
250
200
150
100
50
0
0
50
100
150
200
250
300
Time (seconds)
350
400
C01
100
100
80
80
Population (%)
Population (%)
Figure 8-1. Reflow Profile
60
40
20
0
40
20
-0.02
-0.01
0
0.01
Solder Heat Shift Distribution (%) - SOIC
0
0.02
C005
Figure 8-2. Solder Heat Shift Distribution (%), SOIC
Package
12
60
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-0.02
-0.01
0
0.01
Solder Heat Shift Distribution (%) - MSOP
0.02
C004
Figure 8-3. Solder Heat Shift Distribution (%),
VSSOP Package
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60
60
50
50
40
40
Population (%)
Population (%)
www.ti.com
30
20
10
0
0
1
2
3
4
5
6
7
0
8
40
Population (%)
40
20
10
3
4
5
6
7
8
C007
30
20
10
0
1
2
3
4
5
6
7
0
8
Drift Distribution Pre-Soldering (ppm/ƒC) - MSOP Package
60
60
50
50
Population (%)
70
30
10
10
-1
0
1
2
Drift Shift Distribution (ppm/ƒC) - SOIC Package
0
3
C008
Figure 8-8. Drift Shift Distribution, SOIC Package
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3
4
5
6
7
8
C003
30
20
-2
2
40
20
-3
1
Figure 8-7. Drift Distribution Post-Soldering,
VSSOP Package
70
40
0
Drift Distribution Post-Soldering (ppm/ƒC) - MSOP Package
C002
Figure 8-6. Drift Distribution Pre-Soldering, VSSOP
Package
0
2
Figure 8-5. Drift Post Soldering Distribution, SOIC
Package
50
30
1
Drift Post Soldering (ppm/ƒC) - SOIC package
50
0
0
C006
Figure 8-4. Drift Pre-Soldering Distribution, SOIC
Package
Population (%)
20
10
Drift Pre-Soldering (ppm/ƒC) - SOIC Package
Population (%)
30
-3
-2
-1
0
1
2
3
Drift Shift Distribution due to Soldering (ppm/ƒC) - MSOP Package
C001
Figure 8-9. Drift Shift Distribution, VSSOP Package
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9 Detailed Description
9.1 Overview
The REF50xx is family of low-noise, precision band-gap voltage references that are specifically designed for
excellent initial voltage accuracy and drift. See Section 9.2 for a simplified block diagram of the REF50xx.
9.2 Functional Block Diagram
VIN
REF50xx
R2
R1
aT
(10mA
at +25°C)
VOUT
R4
TEMP
aT
10kW
R3
TRIM/NR
R5
60kW
1.2V
1kW
GND
14
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9.3 Feature Description
9.3.1 Temperature Monitoring
The temperature output terminal (TEMP, pin 3) provides a temperature-dependent voltage output with
approximately 60-kΩ source impedance. As illustrated in Figure 7-8, the output voltage follows the nominal
relationship:
VTEMP PIN = 509 mV + 2.64 × T(°C)
(1)
This pin indicates general chip temperature, accurate to approximately ±15°C. Although not generally suitable for
accurate temperature measurements, this pin can be used to indicate temperature changes or for temperature
compensation of analog circuitry. A temperature change of 30°C corresponds to an approximate 79-mV change
in voltage at the TEMP pin.
The TEMP pin has high-output impedance (see Section 9.2). Loading this pin with a low-impedance circuit
induces a measurement error; however, this pin does not have any effect on VOUT accuracy.
To avoid errors caused by low-impedance loading, buffer the TEMP pin output with a suitable low-temperature
drift op amp, such as the OPA333, OPA335, or OPA376, as shown in Figure 9-1.
+V
REF50xx
DNC
VTEMP
2.6mV/°C
OPA(1)
VIN
TEMP
DNC
NC
VOUT
GND TRIM/NR
NOTE: (1) Low drift op amp, such as the OPA333, OPA335, or OPA376.
Figure 9-1. Buffering the TEMP Pin Output
9.3.2 Temperature Drift
The REF50xx is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described in Equation 2.
Drift =
( VV
– V OUTMIN
Tem
p Range
×
OUTMAX
OUT
) × 10 (ppm)
6
(2)
The REF50xx features a maximum drift coefficient of 3 ppm/°C for the high-grade version, and 8 ppm/°C for the
standard-grade.
9.3.3 Thermal Hysteresis
Thermal hysteresis for the REF50xx is defined as the change in output voltage after operating the device at
25°C, cycling the device through the specified temperature range, and returning to 25°C. Thermal hysteresis can
be expressed as Equation 3:
æ V
- VPOST
VHYST = ç PRE
ç
VNOM
è
ö
6
÷÷ × 10 (ppm)
ø
(3)
where
•
•
•
VHYST = thermal hysteresis (in units of ppm)
VNOM = the specified output voltage
VPRE = output voltage measured at 25°C pre-temperature cycling
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•
VPOST = output voltage measured after the device has been cycled from 25°C through the specified
temperature range of –40°C to 125°C and returned to 25°C
9.3.4 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise for each member of the REF50xx family is specified in Section 7.5 table.
The noise voltage increases with output voltage and operating temperature. Additional filtering can be used to
improve output noise levels, although take care to ensure the output impedance does not degrade performance.
For additional information about how to minimize noise and maximize performance in mixed-signal applications
such as data converters, refer to the How a Voltage Reference Affects ADC Performance Part 1, How a Voltage
Reference Affects ADC Performance Part 2, and How a Voltage Reference Affects ADC Performance Part 3
analog design journals.
+VSUPPLY
REF50xx
DNC
VIN
TEMP
DNC
NC
VOUT
GND TRIM/NR
C1
1mF
Figure 9-2. Noise Reduction Using the TRIM/NR Pin
9.3.5 Long-Term Stability
Due to aging and environmental effects, all semiconductor devices experience physical changes of the
semiconductor die and the packaging material over time. These changes and the associated package stress
on the die cause the output voltage in precision voltage references to deviate over time. The value of such
change is specified in the data sheet by a parameter called the long-term stability (also known as the long-term
drift (LTD)). Equation 4 shows how LTD is calculated. Note that the LTD value is positive if the output voltage
drifts higher over time and negative if the voltage drifts lower over time. Figure 7-22 through Figure 7-29 show
the drift of the output voltage for REF50xx over the first 4000 operating hours.
LTD(ppm) t
(VOUT
n
t 0
VOUT
VOUT
t 0
t n
)
u 106
(4)
where
•
•
•
LTD(ppm)|t=n = long-term stability (in units of ppm)
VOUT|t=0 = output voltage at time = 0 hr
VOUT|t=n = output voltage at time = n hr
9.3.6 Output Adjustment Using the TRIM/NR Pin
The REF50xx provides a very accurate, factory-trimmed voltage output. However, VOUT can be adjusted using
the trim and noise reduction pin (TRIM/NR, pin 5). Figure 9-3 shows a typical circuit that allows an output
adjustment of ±15 mV.
16
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+VSUPPLY
REF50xx
DNC
VIN
TEMP
DNC
NC
VOUT
GND TRIM/NR
10kW
470kW
1kW
Figure 9-3. VOUT Adjustment Using the TRIM/NR Pin
The REF50xx allows access to the band-gap through the TRIM/NR pin. Placing a capacitor from the TRIM/NR
pin to GND (Figure 9-2) in combination with the internal R3 and R4 resistors creates a low-pass filter. A
capacitance of 1 μF creates a low-pass filter with the corner frequency from 10 Hz to 20 Hz. Such a filter
decreases the overall noise measured on the VOUT pin by half. Higher capacitance results in a lower filter cutoff
frequency, further reducing output noise. Using this capacitor increases start-up time.
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9.4 Device Functional Modes
9.4.1 Basic Connections
Figure 9-4 shows the typical connections for the REF50xx. TI recommends a supply bypass capacitor ranging
from 1 μF to 10 μF. A 1-μF to 50-μF output capacitor (CL) must be connected from VOUT to GND. The equivalent
series resistance (ESR) value of CL must be less than or equal to 1.5 Ω to ensure output stability. To minimize
noise, the recommended ESR of CL is from 1 Ω and 1.5 Ω.
+VSUPPLY
REF50xx
DNC
VIN
CBYPASS
1mF to 10mF
TEMP
DNC
NC
VOUT
GND TRIM/NR
VOUT
CL
1mF to 50mF
Figure 9-4. Basic Connections
9.4.2 Supply Voltage
The REF50xx family of voltage references features extremely low dropout voltage. With the exception of the
REF5020, which has a minimum supply requirement of 2.7 V, these references can be operated with a supply of
200 mV more than the output voltage in an unloaded condition. For loaded conditions, a typical dropout voltage
versus load plot is provided in Figure 7-6.
9.4.3 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF50xx and OPA735 can be used
to provide a dual-supply reference from a 5-V supply. Figure 9-5 shows the REF5025 used to provide a 2.5-V
supply reference voltage. The low-drift performance of the REF50xx complements the low offset voltage and
zero drift of the OPA735 to provide an accurate solution for split-supply applications. Take care to match the
temperature coefficients of R1 and R2.
+5V
REF5025
DNC
VIN
DNC
NC
TEMP
VOUT
GND TRIM/NR
+2.5V
1mF
R1
10kW
R2
10kW
+5V
OPA735
-2.5V
-5V
NOTE: Bypass capacitors not shown.
Figure 9-5. The REF5025 and OPA735 Create Positive and Negative Reference Voltages
18
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SBOS410J – JUNE 2007 – REVISED JULY 2022
10 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
Data acquisition systems often require stable voltage references to maintain accuracy. The REF50xx family
features low noise, very low drift, and high initial accuracy for high-performance data converters. Figure 10-1
shows the REF5040 in a basic data acquisition system.
10.2 Typical Applications
10.2.1 16-Bit, 250-KSPS Data Acquisition System
REF5040
ESR
10µF
47µF
REFIN
CS
124Ÿ
CLK
ADS8326
0-4V
SDO
1nF
OPA365
Figure 10-1. Complete Data Acquisition System Using the REF50xx
10.2.1.1 Design Requirements
When using the REF50xx in the design, select a proper output capacitor that does not create gain peaking,
thereby increasing total system noise. At the same time, the capacitor must be selected to provide required
filtering performance for the system. In addition, input bypass capacitor and noise reduction capacitors must be
added for optimum performances. During the design of the data acquisition system, equal consideration must
be given to the buffering analog input signal as well as the reference voltage. Having a properly designed input
buffer with an associated RC filter is a necessary requirement for good performance of the data acquisition
system.
10.2.1.2 Detailed Design Procedure
The OPA365 is used to drive the 16-bit analog-to-digital converter (ADS8326). The RC filter at the output of the
OPA365 is used to reduce the charge kick-back created by the opening and closing of the sampling switch inside
the ADC. Design the RC filter such that the voltage at the sampling capacitor settles to 16-bit accuracy within the
acquisition time of the ADC. The bandwidth of the driving amplifier must at least be four times the bandwidth of
the RC filter.
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The REF5040 is used to drive the REF pin of the ADS8326. Proper selection of voltage reference output
capacitor is very important for this design. Very low equivalent series resistance (ESR) creates gain-peaking,
which degrades SNR of the total system. If the ESR of the capacitor is not enough, then an additional resistor
must be added in series with the output capacitor. A capacitance of 1 μF can be connected to the NR pin to
reduce band-gap noise of the REF50xx.
SNR measurements using different RC filters at the output of the OPA365, different values of output capacitor for
the REF50xx and different values of capacitors at the TRIM/NR pin are shown in Table 10-1.
Table 10-1. Data Acquisition Measurement Results for Different Conditions
TEST CONDITION 1
TEST CONDITION 2
OPA365 RC filter
124 Ω, 1 nF
124 Ω, 1 nF
REF5040 output capacitor
10 μF
10 μF + 47 μF
TRIM/NR pin capacitor
0 μF
1 μF
SNR
86.7 dB
92.8 dB
10.2.1.3 Application Curve
Figure 10-2. FFT Plot-Noise Floor of Data Acquisition System
11 Power Supply Recommendations
The REF50xx family of voltage references features extremely low dropout voltage. With the exception of the
REF5020, which has a minimum supply requirement of 2.7 V, these references can be operated with a supply of
200 mV more than the output voltage in an unloaded condition. For loaded conditions, a typical dropout voltage
versus load plot is provided in Figure 7-6. TI recommends a supply bypass capacitor ranging from 1 μF to 50 μF.
20
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SBOS410J – JUNE 2007 – REVISED JULY 2022
12 Layout
12.1 Layout Guidelines
•
•
•
•
Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The
recommended value of this bypass capacitor is from 1 μF to 10 μF. If necessary, additional decoupling
capacitance can be added to compensate for noisy or high-impedance power supplies.
Place a 1-μF noise filtering capacitor between the NR pin and ground.
The output must be decoupled with a 1-μF to 50-μF capacitor. A resistor in series with the output capacitor is
optional. For better noise performance, the recommended ESR on the output capacitor is from 1 Ω to 1.5 Ω.
A high-frequency, 1-μF capacitor can be added in parallel between the output and ground to filter noise and
help with switching loads as data converters.
12.2 Layout Example
DNC
VIN
C
TEMP
REF50xx
C
GND
DNC
NC
R
VOUT
TRIM/NR
C
C
Figure 12-1. Layout Example
12.3 Power Dissipation
The REF50xx family is specified to deliver current loads of ±10 mA over the specified input voltage range. The
temperature of the device increases according to Equation 5:
TJ = TA + PD × θJA
(5)
where
•
•
•
•
TJ = junction temperature (°C)
TA = ambient temperature (°C)
PD = power dissipated (W)
θJA = junction-to-ambient thermal resistance (°C/W)
The REF50xx junction temperature must not exceed the absolute maximum rating of 150°C.
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, 0.05 μV/°C (Maximum), Single-Supply CMOS Zero-Drift Series Operational Amplifier data
sheet
• REF5020 PSpice Model.
• REF5020 TINA-TI Reference Design
• REF5020 TINA-TI Spice Model
• INA270 PSpice Model
• INA270 TINA-TI Reference Design
• INA270 TINA-TI Spice Model
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF5010AID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5010
A
REF5010AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50G
Samples
REF5010AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50G
Samples
REF5010AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5010
A
REF5010ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
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-40 to 125
REF
5010
Samples
REF5010IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI
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-40 to 125
R50G
Samples
REF5010IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
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-40 to 125
R50G
Samples
REF5020AID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5020
A
REF5020AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5020
A
REF5020AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50A
Samples
REF5020AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
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-40 to 125
R50A
Samples
REF5020AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5020
A
REF5020AIDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5020
A
REF5020ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
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-40 to 125
REF
5020
Samples
REF5020IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
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-40 to 125
R50A
Samples
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Samples
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Samples
Samples
PACKAGE OPTION ADDENDUM
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Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF5020IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50A
Samples
REF5020IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
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-40 to 125
REF
5020
Samples
REF5020IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
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-40 to 125
REF
5020
Samples
REF5025AID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5025
A
REF5025AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5025
A
REF5025AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50B
Samples
REF5025AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50B
Samples
REF5025AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5025
A
REF5025AIDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5025
A
REF5025ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5025
Samples
REF5025IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
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Level-2-260C-1 YEAR
-40 to 125
REF
5025
Samples
REF5025IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50B
Samples
REF5025IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
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Level-2-260C-1 YEAR
-40 to 125
R50B
Samples
REF5025IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
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-40 to 125
REF
5025
Samples
REF5025IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5025
Samples
REF5030AID
ACTIVE
SOIC
D
8
75
RoHS & Green
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Level-2-260C-1 YEAR
-40 to 125
REF
5030
A
Addendum-Page 2
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Orderable Device
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(1)
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Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF5030AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5030
A
REF5030AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50C
Samples
REF5030AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50C
Samples
REF5030AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5030
A
REF5030ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5030
Samples
REF5030IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50C
Samples
REF5030IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50C
Samples
REF5030IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5030
Samples
REF5040AID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5040
A
REF5040AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5040
A
REF5040AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50D
Samples
REF5040AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50D
Samples
REF5040AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5040
A
REF5040ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5040
Samples
REF5040IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5040
Samples
REF5040IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50D
Samples
REF5040IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50D
Samples
Addendum-Page 3
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF5040IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5040
Samples
REF5040IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5040
Samples
REF5045AID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5045
A
REF5045AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5045
A
REF5045AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50E
Samples
REF5045AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50E
Samples
REF5045AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5045
A
REF5045ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5045
Samples
REF5045IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50E
Samples
REF5045IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50E
Samples
REF5045IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5045
Samples
REF5050AID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5050
A
REF5050AIDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5050
A
REF5050AIDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50F
Samples
REF5050AIDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
R50F
Samples
REF5050AIDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
REF
5050
A
Addendum-Page 4
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF5050ID
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5050
Samples
REF5050IDG4
ACTIVE
SOIC
D
8
75
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5050
Samples
REF5050IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50F
Samples
REF5050IDGKT
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
R50F
Samples
REF5050IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5050
Samples
REF5050IDRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
REF
5050
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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