REF70
SNAS781G – OCTOBER 2020 – REVISED SEPTEMBER 2023
REF70 2 ppm/°C Maximum Drift, 0.23 ppmp-p 1/f Noise, Precision Voltage Reference
1 Features
3 Description
•
The REF70 is a family of high precision series voltage
references that offers the industry’s lowest noise
(0.23 ppmp-p), very low temperature drift coefficient
(2 ppm/°C), and high accuracy (±0.025%). The
REF70 offers a high PSRR, low drop-out voltage
and excellent load and line regulation to help meet
strict transient requirements. This combination of
precision and features is designed for applications
such as test and measurement that demand a precise
reference to be paired with precision, high-resolution
data converters such as ADS8900B, ADS127L01 and
DAC11001A, to achieve optimal performance in the
signal chain. The REF70 is also designed for noisesensitive medical applications such as ultrasound and
X-ray to help enable low-noise measurements from
the analog front end.
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Low noise enables precision measurements:
– 1/f Noise (0.1 Hz to 10 Hz): 0.23 ppmp-p
– 10 Hz to 1 kHz: 0.35 ppmrms
Low temperature drift coefficient:
– 2 ppm/°C maximum (-40°C to 125°C)
High accuracy: ±0.025% maximum
Humidity resistant hermetic ceramic package
(LCCC)
Excellent long-term stability (1k hr): 35 ppm
Low dropout: 400 mV
Designed for a wide range of applications:
– Wide input voltage up to 18 V
– Output current: ±10 mA
– Voltage options: 1.25 V, 2.5 V, 3 V, 3.3 V,
4.096 V, 5 V
Ultra-flexible solution:
– Stable with 1-μF to 100-μF output low-ESR
capacitor
– High PSRR: 107 dB at 1 kHz
– Operating temperature range: −40°C to +125°C
2 Applications
Semiconductor test equipment
Precision data acquisition systems
Precision weight scales
Ultrasound scanner
X-ray systems
Industrial instrumentation
PLC analog I/O modules
Field transmitters
Power monitoring
The REF70 is specified for the wide temperature
range of −40°C to +125°C. The wide temperature
range enables operation across various industrial
applications.
Device Information
PART NAME
REF70
(1)
2.501
0.56
2.50075
0.48
2.5005
0.4
0.32
0.24
0.16
BODY SIZE (NOM)
LCCC (8)
5.00 mm × 5.00 mm
VSSOP (8)
3.00 mm x 3.00 mm
2.50025
2.5
2.49975
2.4995
0.08
0.4
0.3
0.2
0.1
2.49925
0
0
PACKAGE (1)
For all available packages, see the orderable addendum at
the end of the data sheet.
0.64
Output Voltage (V)
Population (%)
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The REF70 family is available in VSSOP and LCCC
package options. The LCCC (FKH) package is a
hermetically sealed ceramic package that allows for
low, long-term drift for applications that require a
stable reference over a long time period without
calibration.
Noise (ppmp-p)
0.1-Hz to 10-Hz Voltage Noise Distribution
2.499
-50
-25
0
25
50
Temperature (°C)
75
100
125
Output Voltage Vs Free-Air-Temperature
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
REF70
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SNAS781G – OCTOBER 2020 – REVISED SEPTEMBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 REF7012 Electrical Characteristics............................ 7
7.6 REF7025 Electrical Characteristics............................ 8
7.7 REF7030 Electrical Characteristics............................ 9
7.8 REF7033 Electrical Characteristics.......................... 10
7.9 REF7040 Electrical Characteristics...........................11
7.10 REF7050 Electrical Characteristics........................ 12
7.11 Typical Characteristics............................................ 14
8 Parameter Measurement Information.......................... 19
8.1 Solder Heat Shift.......................................................19
8.2 Long-Term Stability................................................... 20
8.3 Thermal Hysteresis................................................... 20
8.4 Noise Performance................................................... 21
8.5 Temperature Drift...................................................... 24
8.6 Power Dissipation..................................................... 24
9 Detailed Description......................................................25
9.1 Overview................................................................... 25
9.2 Functional Block Diagram......................................... 25
9.3 Feature Description...................................................25
9.4 Device Functional Modes..........................................25
10 Application and Implementation................................ 27
10.1 Application Information........................................... 27
10.2 Typical Applications................................................ 27
10.3 Power Supply Recommendation.............................32
10.4 Layout..................................................................... 32
11 Device and Documentation Support..........................34
11.1 Documentation Support.......................................... 34
11.2 Receiving Notification of Documentation Updates.. 34
11.3 Support Resources................................................. 34
11.4 Trademarks............................................................. 34
11.5 Electrostatic Discharge Caution.............................. 34
11.6 Glossary.................................................................. 34
12 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2023) to Revision G (September 2023)
Page
• Update table to highlight REF7025 and REF7040 release in VSSOP package................................................. 4
• Added performance parameters for VSSOP package........................................................................................8
• Added performance parameters for VSSOP package...................................................................................... 11
• Changed Figure 7-25 to longer duration (10000 hours)................................................................................... 14
• Added Figure 7-27 ........................................................................................................................................... 14
• Changed Figure 8-4 and Figure 8-4, to longer duration (10000 hours)............................................................ 20
• Changed Figure 8-10, to highlight performance at different supply voltages................................................... 21
• Changed minimum ESR value from 10 mΩ to 1 mΩ........................................................................................ 25
• Changed minimum ESR value from 10 mΩ to 1 mΩ........................................................................................ 28
Changes from Revision E (July 2022) to Revision F (March 2023)
Page
• Add line break to voltage options feature to improve readability........................................................................ 1
• Removed VSSOP package preview footnote.....................................................................................................1
• Added footnote to indicate VSSOP package preview material...........................................................................4
• Added performance parameters for VSSOP package........................................................................................7
• Added performance graphs for VSSOP package devices................................................................................14
• Added solder shift histogram for VSSOP package........................................................................................... 19
• Added long term stability details for VSSOP package......................................................................................20
• Added thermal hysteresis details for VSSOP package.....................................................................................20
• Added layout details for VSSOP package........................................................................................................ 33
Changes from Revision D (November 2021) to Revision E (July 2022)
Page
• Updated Long-term Stability feature text based on documentation feedback and updated number from 28
ppm to 35 ppm based on additional tests conducted......................................................................................... 1
2
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•
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•
SNAS781G – OCTOBER 2020 – REVISED SEPTEMBER 2023
Added footnote for Device Information table for VSSOP package..................................................................... 1
Updated Long-term stability numbers to reflect latest evaluation results........................................................... 8
Changed Figure 7-25 to longer duration (4000 hours)..................................................................................... 14
Changed Figure 8-4, to longer duration (4000 hours)...................................................................................... 20
Changes from Revision C (September 2021) to Revision D (November 2021)
Page
• Changed REF7012 status from Preproduction device to Released device........................................................4
• Changed REF7012 status to Released Device. Updated specifications to meet production release device..... 7
• Added REF7030 Electrical Characteristics table................................................................................................ 9
• Added REF7033 Electrical Characteritics table................................................................................................10
• Added REF7012 Thermal Hysteresis figure..................................................................................................... 14
• Added JEDEC standard details to follow for solder reflow profiles. Updated solder shift histogram plot......... 19
• Added Thermal Hysteresis plots for REF7012 device ..................................................................................... 20
Changes from Revision B (April 2021) to Revision C (September 2021)
Page
• Add 1.25 V variant to Features on page1...........................................................................................................1
• In the Device Comparison Table, added the 1.25V variant and added foot notes to indicate which devices are
released vs pre-production ................................................................................................................................ 4
• Changed Dropout voltage to min VIN = 2.75 V for VOUT < 2.5 V. .................................................................... 6
• Added Electrical Characteristics table for REF7012 (Product Preview)............................................................. 7
• Changed VINMIN from 3 V to VOUT + VDO ........................................................................................................... 8
• Added Electrical Characteristics table for REF7040 (Product Preview)............................................................11
• Added Electrical Characteristics table for REF7050 (Product Preview)........................................................... 12
• Added to the notes above the Typical Characteristics plots, Vref = 2.5 V to the default conditions................. 14
• Under Temperature Drift section of the Parameter Measurement Information, corrected the figure from Long
Term Drift plot to Temperature Drift...................................................................................................................24
Changes from Revision A (December 2020) to Revision B (April 2021)
Page
• Changed REF7025 to more general REF70 series in heading and device information. Added ADC companion
products.............................................................................................................................................................. 1
• Changed Figures 7-2 and 7-20, Long-Term Stability (First 1000 Hours), to longer duration (2000 hours).......14
• Corrected typical shift from 0.021% to 0.009%.................................................................................................19
• Changed Figure 8-3, Long-Term Stability LCCC -1000 hours), to longer duration (2000 hours)..................... 20
• Corrected Figure 8-5, Thermal Hysteresis Distribution Cycle 2 (-40°C to 125°C), data and title..................... 20
• Reordered figures and paragraphs for better flow............................................................................................ 23
• Changed VREF to VREF(25°C) in Equation 2........................................................................................................24
• Added missing supply bypass capacitor value (10-μF).................................................................................... 25
• Clarified piezoelectric contribution to noise and added links to resources....................................................... 28
• Added clarification on how to connect OUTF and OUTS in specific load current condition............................. 29
• Corrected part numbers and added links in Table 10-2, Reference Op Amp Options .....................................30
Changes from Revision * (October 2020) to Revision A (December 2020)
Page
• APL to RTM release........................................................................................................................................... 1
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5 Device Comparison Table
PRODUCT
VSSOP package
REF7012QFKHT (1)
REF7012QDGKR (1)
1.25 V
REF7025QFKHT (1)
REF7025QDGKR (1)
2.5 V
REF7030QFKHT
(1)
REF7033QFKHT (1)
REF7040QFKHT
(1)
REF7050QFKHT (1)
(1)
(2)
4
VOUT
LCC package
2
3.0 V
REF7033QDGKR 2
3.3 V
REF7030QDGKR
REF7040QDGKR
(1)
REF7050QDGKR 2
4.096 V
5.0 V
This orderable is released to market.
Samples available for the orderable upon request.
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6 Pin Configuration and Functions
GND
8
EN
1
7
OUTF
VIN
2
6
OUTS
GND
3
5
GND
4
GND
Figure 6-1. FKH Package
8-Pin LCCC
Top View
EN 1
8 GND
VIN 2
7 OUTF
GND 3
6 OUTS
GND 4
5 GND
Figure 6-2. DGK Package
8-Pin VSSOP
Top View
Table 6-1. Pin Functions
PIN
NAME
FKH
DGK
TYPE
DESCRIPTION
Device enable control. Low level input disables the reference output
and device enters shutdown mode. Device can be enabled by
driving voltage > 1.6V. If the pin is left floating, the internal pull up
will enable the device.
EN
1
1
Input
VIN
2
2
Power
Input supply voltage connection. Connect a minimum 0.1-μF
decoupling capacitor to ground for the best performance.
GND
3
3
Ground
Ground connection.
GND
4
4
Ground
Ground connection.
GND
5
5
Ground
Ground connection
OUTS
6
6
Input
OUTF
7
7
Output
Reference voltage output force connection. Connect a output
capacitor between 1-μF to 100-μF for the best performance.
GND
8
8
Ground
Ground connection.
Reference voltage output sense connection.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input voltage
VIN
-0.3
20
V
Enable voltage
EN
-0.3
VIN + 0.3
V
Output voltage
VOUT
-0.3
Output short circuit current
ISC
Operating temperature range
TA
Storage temperature range
Tstg
(1)
6
V
25
mA
-55
150
°C
-65
170
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those specified in the Electrical Characteristics Table is not implied.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
± 1000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
± 500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
18
V
VIN
V
10
mA
125
°C
VIN
Input voltage
EN
Enable voltage
0
IL
Output current
–10
TA
Operating temperature
–40
(1)
VOUT + VDO
NOM
(1)
25
VDO = Dropout voltage. For VOUT < 2.5 V minimum VIN = 2.75 V
7.4 Thermal Information
REF70xx
THERMAL METRIC(1)
DGK (MSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
95.8
201.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.0
85.7
°C/W
RθJB
Junction-to-board thermal resistance
58.3
122.9
°C/W
ΨJT
Junction-to-top characterization parameter
48.2
21.2
°C/W
ΨJB
Junction-to-board characterization parameter
58.1
121.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
28.5
N/A
°C/W
(1)
6
FKH (CERAMIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 REF7012 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = 3 V, OUTS connected to OUTF, unless
otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
–0.025
0.025
%
–0.05
0.05
%
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
Output voltage accuracy TA = 25°C; DGK package
Output voltage
temperature coefficient
–40°C ≤ TA ≤ 125°C
2
ppm/℃
Output voltage
temperature coefficient
–40°C ≤ TA ≤ 85°C; DGK package
2
ppm/℃
Output voltage
temperature coefficient
–40°C ≤ TA ≤ 125°C; DGK package
4.2
ppm/℃
LINE AND LOAD REGULATION
ΔVO / ΔVIN Line regulation
2.75 V ≤ VIN ≤ 18 V
4
2.75 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
30
IL = 0 mA to 10mA
ΔVO / ΔIL
Load regulation
ppm/V
5
IL = 0 mA to 10mA, –40°C ≤ TA ≤ 125°C
15
IL = 0 mA to –10mA
15
IL = 0 mA to –10mA, –40°C ≤ TA ≤ 125°C
ppm/mA
30
NOISE
enp-p
Low frequency noise
ƒ = 0.1 Hz to 10 Hz
0.25
ppmp-p
en
Output voltage noise
ƒ = 10 Hz to 1 kHz
0.35
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
Long-term stability
Output voltage
hysteresis (cycle 1)
Output voltage
hysteresis (cycle 1)
0 to 250h at 35°C –FKH package
15
0 to 1000h at 35°C – FKH package
35
0 to 250h at 35°C – DGK package
27
0 to 1000h at 35°C – DGK package
37
25°C, –40°C, 125°C, 25°C – FKH package
18
25°C, –40°C, 85°C, 25°C – FKH package
11
25°C, 0°C, 70°C, 25°C – FKH package
11
25°C, –40°C, 125°C, 25°C – DGK package
410
25°C, –40°C, 85°C, 25°C – DGK package
35
25°C, 0°C, 70°C, 25°C – DGK package
33
0.1% settling, COUT = 1µF
0.5
ppm
ppm
ppm
ppm
TURN ON TIME
tON
Turn-on time
ms
CAPACITIVE LOAD
CIN
Stable input capacitor
range
–40℃ ≤ TA ≤ 125℃
0.1
COUT
Stable output capacitor
range (1)
–40℃ ≤ TA ≤ 125℃
1
100
µF
2.75
18
V
6.5
mA
7.5
mA
10
uA
12
uA
µF
POWER SUPPLY
VIN
Input voltage
TA = 25°C
IQ
Quiescent current
–40°C ≤ TA ≤ 125°C
TA = 25°C
–40°C ≤ TA ≤ 125°C
VEN
Enable pin voltage
4
Active mode
5
Shutdown mode
Active mode (EN=1)
Shutdown mode (EN=0)
1.6
V
0.5
V
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7.5 REF7012 Electrical Characteristics (continued)
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = 3 V, OUTS connected to OUTF, unless
otherwise noted
PARAMETER
IEN
Enable pin current
ISC
Short circuit current
(1)
TEST CONDITION
MIN
VIN = VEN = 18V
TYP
MAX
3.2
4
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
5
VOUT = 0V
30
UNIT
uA
uA
mA
ESR for the capacitor can range from 1 mΩ to 400 mΩ
7.6 REF7025 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.025
%
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
Output voltage
temperature coefficient
–0.025
–40°C ≤ TA ≤ 125°C
2
ppm/℃
LINE AND LOAD REGULATION
ΔVO / ΔVIN Line regulation
VOUT + VDO ≤ VIN ≤ 18 V
4
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
30
IL = 0 mA to 10mA, VIN = VOUT + VDO
ΔVO / ΔIL
Load regulation
ppm/V
5
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
10
IL = 0 mA to –10mA, VIN = VOUT + VDO
ppm/mA
5
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
15
NOISE
enp-p
Low frequency noise
ƒ = 0.1 Hz to 10 Hz
0.23
ppmp-p
en
Output voltage noise
ƒ = 10 Hz to 1 kHz
0.35
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
Long-term stability
Output voltage
hysteresis (cycle 1)
0 to 250h at 35°C - FKH package
15
0 to 1000h at 35°C - FKH package
35
0 to 250h at 35°C – DGK package
35
ppm
75
ppm
0 to 1000h at 35°C – DGK package
25°C, –40°C, 125°C, 25°C – FKH package
180
25°C, –40°C, 85°C, 25°C – FKH package
100
25°C, 0°C, 70°C, 25°C – FKH package
Output voltage
hysteresis (cycle 1)
ppm
ppm
40
25°C, –40°C, 125°C, 25°C – DGK package
290
25°C, –40°C, 85°C, 25°C – DGK package
50
25°C, 0°C, 70°C, 25°C – DGK package
45
0.1% settling, COUT = 1µF
0.5
ppm
TURN ON TIME
tON
Turn-on time
ms
CAPACITIVE LOAD
CIN
Stable input capacitor
range
–40℃ ≤ TA ≤ 125℃
0.1
COUT
Stable output capacitor
range (1)
–40℃ ≤ TA ≤ 125℃
1
µF
100
µF
POWER SUPPLY
8
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7.6 REF7025 Electrical Characteristics (continued)
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
VIN
TEST CONDITION
Input voltage
TA = 25°C
IQ
Quiescent current
–40°C ≤ TA ≤ 125°C
TA = 25°C
–40°C ≤ TA ≤ 125°C
VEN
Enable pin voltage
IEN
Enable pin current
VDO
Dropout voltage
ISC
Short circuit current
(1)
MIN
TYP
VOUT +
VDO
4
Active mode
5
Shutdown mode
Active mode (EN=1)
MAX
UNIT
18
V
6
mA
6.5
mA
10
uA
12
uA
1.6
V
Shutdown mode (EN=0)
0.5
V
4
uA
5
uA
IL = 5mA, –40°C ≤ TA ≤ 125°C
250
mV
IL = 10mA, –40°C ≤ TA ≤ 125°C
400
mV
VIN = VEN = 18V
3.2
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
VOUT = 0V
25
mA
ESR for the capacitor can range from 1 mΩ to 400 mΩ
7.7 REF7030 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.025
%
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
Output voltage
temperature coefficient
–0.025
–40°C ≤ TA ≤ 125°C
2
ppm/℃
LINE AND LOAD REGULATION
ΔVO / ΔVIN Line regulation
3.2 V ≤ VIN ≤ 18 V
IL = 0 mA to 10mA, VIN = 3.5 V
ΔVO / ΔIL
Load regulation
4
3.2 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
30
5
IL = 0 mA to 10mA, VIN = 3.5 V, –40°C ≤ TA ≤
125°C
IL = 0 mA to –10mA, VIN = 3.5 V
ppm/V
10
ppm/mA
5
IL = 0 mA to –10mA, VIN = 3.5 V, –40°C ≤ TA ≤
125°C
15
NOISE
enp-p
Low frequency noise
ƒ = 0.1 Hz to 10 Hz
0.23
ppmp-p
en
Output voltage noise
ƒ = 10 Hz to 1 kHz
0.35
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
Output voltage
hysteresis (cycle 1)
0 to 250h at 35°C - FKH package
15
0 to 1000h at 35°C - FKH package
35
25°C, –40°C, 125°C, 25°C – FKH package
180
25°C, –40°C, 85°C, 25°C – FKH package
100
25°C, 0°C, 70°C, 25°C – FKH package
40
0.1% settling, COUT = 1µF
0.5
ppm
ppm
TURN ON TIME
tON
Turn-on time
ms
CAPACITIVE LOAD
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7.7 REF7030 Electrical Characteristics (continued)
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
CIN
Stable input capacitor
range
–40℃ ≤ TA ≤ 125℃
0.1
COUT
Stable output capacitor
range (1)
–40℃ ≤ TA ≤ 125℃
1
100
µF
VOUT +
VDO
18
V
4
6
mA
7
mA
5
10
uA
12
uA
µF
POWER SUPPLY
VIN
Input voltage
TA = 25°C
IQ
Quiescent current
–40°C ≤ TA ≤ 125°C
TA = 25°C
–40°C ≤ TA ≤ 125°C
VEN
Enable pin voltage
IEN
Enable pin current
VDO
Dropout voltage
ISC
Short circuit current
(1)
Active mode
Shutdown mode
Active mode (EN=1)
1.6
V
Shutdown mode (EN=0)
VIN = VEN = 18V
3.2
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
0.5
V
4
uA
5
uA
250
mV
400
mV
25
mA
ESR for the capacitor can range from 1 mΩ to 400 mΩ
7.8 REF7033 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.025
%
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
Output voltage
temperature coefficient
–0.025
–40°C ≤ TA ≤ 125°C
2
ppm/℃
LINE AND LOAD REGULATION
ΔVO / ΔVIN Line regulation
3.5 V ≤ VIN ≤ 18 V
IL = 0 mA to 10mA, VIN = 3.8 V
ΔVO / ΔIL
Load regulation
4
3.5 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
30
5
IL = 0 mA to 10mA, VIN = 3.8 V, –40°C ≤ TA ≤
125°C
IL = 0 mA to –10mA, VIN = 3.8 V
ppm/V
10
ppm/mA
5
IL = 0 mA to –10mA, VIN = 3.8 V, –40°C ≤ TA ≤
125°C
15
NOISE
enp-p
Low frequency noise
ƒ = 0.1 Hz to 10 Hz
0.23
ppmp-p
en
Output voltage noise
ƒ = 10 Hz to 1 kHz
0.35
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
10
0 to 250h at 35°C - FKH package
15
0 to 1000h at 35°C - FKH package
35
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7.8 REF7033 Electrical Characteristics (continued)
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
Output voltage
hysteresis (cycle 1)
TEST CONDITION
MIN
TYP
25°C, –40°C, 125°C, 25°C – FKH package
180
25°C, –40°C, 85°C, 25°C – FKH package
100
25°C, 0°C, 70°C, 25°C – FKH package
40
0.1% settling, COUT = 1µF
0.5
MAX
UNIT
ppm
TURN ON TIME
tON
Turn-on time
ms
CAPACITIVE LOAD
CIN
Stable input capacitor
range
–40℃ ≤ TA ≤ 125℃
0.1
COUT
Stable output capacitor
range (1)
–40℃ ≤ TA ≤ 125℃
1
100
µF
VOUT +
VDO
18
V
4
6
mA
7
mA
5
10
uA
12
uA
µF
POWER SUPPLY
VIN
Input voltage
TA = 25°C
IQ
Quiescent current
–40°C ≤ TA ≤ 125°C
TA = 25°C
–40°C ≤ TA ≤ 125°C
VEN
Enable pin voltage
IEN
Enable pin current
VDO
Dropout voltage
ISC
Short circuit current
(1)
Active mode
Shutdown mode
Active mode (EN=1)
1.6
V
Shutdown mode (EN=0)
VIN = VEN = 18V
3.2
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
0.5
V
4
uA
5
uA
250
mV
400
mV
25
mA
ESR for the capacitor can range from 1 mΩ to 400 mΩ
7.9 REF7040 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.025
%
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
Output voltage
temperature coefficient
–0.025
–40°C ≤ TA ≤ 125°C
2
ppm/℃
LINE AND LOAD REGULATION
ΔVO / ΔVIN Line regulation
VOUT + VDO ≤ VIN ≤ 18 V
IL = 0 mA to 10mA, VIN = VOUT + VDO
ΔVO / ΔIL
Load regulation
4
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
30
5
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
IL = 0 mA to –10mA, VIN = VOUT + VDO
ppm/V
10
ppm/mA
5
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
15
NOISE
enp-p
Low frequency noise
ƒ = 0.1 Hz to 10 Hz
0.23
ppmp-p
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7.9 REF7040 Electrical Characteristics (continued)
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
en
Output voltage noise
TEST CONDITION
MIN
ƒ = 10 Hz to 1 kHz
TYP
MAX
0.35
UNIT
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
Long-term stability
Output voltage
hysteresis (cycle 1)
0 to 250h at 35°C - FKH package
15
0 to 1000h at 35°C - FKH package
35
0 to 250h at 35°C – DGK package
35
0 to 1000h at 35°C – DGK package
75
25°C, –40°C, 125°C, 25°C – FKH package
180
25°C, –40°C, 85°C, 25°C – FKH package
100
25°C, 0°C, 70°C, 25°C – FKH package
Output voltage
hysteresis (cycle 1)
ppm
ppm
ppm
40
25°C, –40°C, 125°C, 25°C (cycle 1) – DGK
package
290
25°C, –40°C, 85°C, 25°C (cycle 1) – DGK
package
50
25°C, 0°C, 70°C, 25°C (cycle 1) – DGK package
45
0.1% settling, COUT = 1µF
0.5
ppm
TURN ON TIME
tON
Turn-on time
ms
CAPACITIVE LOAD
CIN
Stable input capacitor
range
–40℃ ≤ TA ≤ 125℃
0.1
COUT
Stable output capacitor
range (1)
–40℃ ≤ TA ≤ 125℃
1
100
µF
VOUT +
VDO
18
V
6
mA
6.5
mA
10
uA
12
uA
µF
POWER SUPPLY
VIN
Input voltage
TA = 25°C
IQ
Quiescent current
–40°C ≤ TA ≤ 125°C
TA = 25°C
–40°C ≤ TA ≤ 125°C
VEN
IEN
Enable pin voltage
Enable pin current
VDO
Dropout voltage
ISC
Short circuit current
(1)
4
Active mode
5
Shutdown mode
Active mode (EN=1)
1.6
V
Shutdown mode (EN=0)
VIN = VEN = 18V
3.2
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
0.5
V
4
uA
5
uA
250
mV
400
mV
25
mA
ESR for the capacitor can range from 1 mΩ to 400 mΩ
7.10 REF7050 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.025
%
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
Output voltage
temperature coefficient
12
–0.025
–40°C ≤ TA ≤ 125°C
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ppm/℃
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7.10 REF7050 Electrical Characteristics (continued)
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
LINE AND LOAD REGULATION
ΔVO / ΔVIN Line regulation
VOUT + VDO ≤ VIN ≤ 18 V
4
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
30
IL = 0 mA to 10mA, VIN = VOUT + VDO
ΔVO / ΔIL
Load regulation
ppm/V
5
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
10
IL = 0 mA to –10mA, VIN = VOUT + VDO
ppm/mA
5
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
15
NOISE
enp-p
Low frequency noise
ƒ = 0.1 Hz to 10 Hz
0.23
ppmp-p
en
Output voltage noise
ƒ = 10 Hz to 1 kHz
0.35
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
Output voltage
hysteresis (cycle 1)
0 to 250h at 35°C - FKH package
15
0 to 1000h at 35°C - FKH package
35
25°C, –40°C, 125°C, 25°C – FKH package
180
25°C, –40°C, 85°C, 25°C – FKH package
100
25°C, 0°C, 70°C, 25°C – FKH package
40
0.1% settling, COUT = 1µF
0.5
ppm
ppm
TURN ON TIME
tON
Turn-on time
ms
CAPACITIVE LOAD
CIN
Stable input capacitor
range
–40℃ ≤ TA ≤ 125℃
0.1
COUT
Stable output capacitor
range (1)
–40℃ ≤ TA ≤ 125℃
1
100
µF
VOUT +
VDO
18
V
6
mA
6.5
mA
10
uA
12
uA
µF
POWER SUPPLY
VIN
Input voltage
TA = 25°C
IQ
Quiescent current
–40°C ≤ TA ≤ 125°C
TA = 25°C
–40°C ≤ TA ≤ 125°C
VEN
IEN
Enable pin voltage
Enable pin current
VDO
Dropout voltage
ISC
Short circuit current
(1)
4
Active mode
5
Shutdown mode
Active mode (EN=1)
1.6
V
Shutdown mode (EN=0)
VIN = VEN = 18V
3.2
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
25
0.5
V
4
uA
5
uA
250
mV
400
mV
mA
ESR for the capacitor can range from 1 mΩ to 400 mΩ
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7.11 Typical Characteristics
2.501
1.251
2.50075
1.25075
2.5005
1.2505
Output Voltage (V)
Output Voltage (V)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
2.50025
2.5
2.49975
1.25025
1.25
1.24975
2.4995
1.2495
2.49925
1.24925
2.499
-50
-25
0
25
50
Temperature (°C)
75
100
1.249
-50
125
50%
40%
40%
Population (%)
50%
30%
20%
2
1.8
1.6
1.4
1.2
1
0.8
0
0.6
0
0.4
75
100
125
20%
10%
0.2
25
50
Temperature (C)
30%
10%
0
0
Figure 7-2. Output Voltage Vs Free-Air Temperature
(REF7012QDGKR)
Figure 7-1. Output Voltage Vs Free-Air Temperature
(REF7025QFKHR)
Population (%)
-25
0
Figure 7-3. Temperature Drift Distribution (REF7025QFKHR)
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Temperature Drift −40C to 85 C (ppm/C)
Temperature Drift -40°C to 125°C (ppm/°C)
Figure 7-4. Temperature Drift Distribution (REF7012QDGKR)
50%
Population (%)
40%
30%
20%
Figure 7-5. Temperature Drift Distribution (REF7012QDGKR)
0.02
0.016
0.012
0.008
0.004
0
-0.004
-0.008
-0.012
-0.016
0
-0.02
10%
Output Initial Accuracy (%)
Figure 7-6. Accuracy Distribution (REF7025QFKHR)
14
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7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
16
100%
14
Line Regulation (ppm/V)
Population (%)
80%
60%
40%
20%
12
10
8
6
4
2
0
-0.05 -0.04 -0.03 -0.02 -0.01
0
0
-50
0.01 0.02 0.03 0.04 0.05
-25
0
Output Initial Accuracy (%)
100
125
16
Load Regulation Sinking (ppm/mA)
16
Load Regulation Sourcing (ppm/mA)
75
Figure 7-8. Line Regulation vs Temperature
Figure 7-7. Accuracy Distribution (REF7012QDGKR)
14
12
10
8
6
4
2
0
-50
25
50
Temperature (qC)
-25
0
25
50
Temperature (°C)
75
100
125
Figure 7-9. Load Regulation (Sourcing) vs Temperature
14
12
10
8
6
4
2
0
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 7-10. Load Regulation (Sinking) vs Temperature
10mA
10 mA/div
VIN
-10mA
-10mA
5 V/div
VOUT
100 mV/div
10 mV/div
100µs/div
200µs/div
Figure 7-11. Line Regulation Response
Figure 7-12. Load Transient Response (CL = 1 μF)
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7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
2
10mA
10 mA/div
1PF
10PF
100PF
Output Impedance :)
1.75
-10mA
-10mA
10 mV/div
1.5
1.25
1
0.75
0.5
0.25
0
10 20
200µs/div
6
2.4
5
2
4
3
2
1
-25
0
25
50
Temperature (°C)
75
100
100000
1000000
1.6
1.2
0.8
0
-50
125
Figure 7-15. Quiescent Current vs Temperature
-25
0
25
50
Temperature (°C)
75
100
125
Figure 7-16. Shutdown Current vs Temperature
300
1.5
VEN_HIGH
VEN_LOW
0mA
5mA
10mA
250
Dropout Voltage (mV)
1.2
Voltage (V)
1000
10000
Frequency (Hz)
0.4
0
-50
0.9
0.6
0.3
200
150
100
50
0
0
4
8
12
Input Voltage (V)
16
Figure 7-17. Enable Threshold vs VIN
16
50 100
Figure 7-14. Output Impedance
Shutdown Current (µA)
Quiescent Current (mA)
Figure 7-13. Load Transient Response (CL = 10 μF)
20
0
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 7-18. Dropout Voltage vs Temperature
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7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
100
50
Vin =5.5V
Vin=12V
90
80
70
Noise (nV/vHz)
Population (%)
40
30
20
60
50
40
30
10
20
10
0
0
0.1
0.2
0.3
0
10
0.4
Noise (ppmp-p)
Figure 7-19. 0.1-Hz to 10-Hz Voltage Noise Distribution (300
units)
100k
30%
25%
80
Population (%)
Power Supply Rejection Ratio (dB)
10k
35%
1uF
10uF
100uF
60
40
20%
15%
10%
20
5%
0
10
0
100
1k
Frequency (Hz)
10k
100k
Figure 7-21. Power-Supply Rejection Ratio vs Frequency
0
75%
40
60%
20
20
30
40
50
60
70
80
90
100
Figure 7-22. REF7025QFKHR Thermal Hysteresis Distribution
(0°C to 70°C)
50
30
10
Thermal Hysteresis (ppm)
Population (%)
Population (%)
1k
Frequency (Hz)
Figure 7-20. Noise Performance 10 Hz to 100 kHz
120
100
100
45%
30%
15%
10
0
0
0
5
10
20
25
0
30
10
20
30
40
50
Thermal Hysteresis (ppm)
Thermal Hysteresis (ppm)
Figure 7-23. REF7012QFKHR Thermal Hysteresis Distribution
(0°C to 70°C)
Figure 7-24. REF7012QDGKR Thermal Hysteresis Distribution
(0°C to 70°C)
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7.11 Typical Characteristics (continued)
200
200
150
150
Output Voltage Stability (ppm)
Output voltage stability (ppm)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
100
50
0
-50
-100
-150
-200
0
2000
4000
6000
Time (hr)
8000
10000
Figure 7-25. Long-Term Stability LCCC package (First 10000
Hours)
100
50
0
-50
-100
-150
-200
0
200
400
600
Time (hr)
800
1000
Figure 7-26. Long-Term Stability VSSOP package REF7012
(First 1000 Hours)
Output Voltage Stability (ppm)
300
200
100
0
-100
-200
-300
0
2000
4000
6000
Time (hr)
8000
10000
Figure 7-27. Long-Term Stability VSSOP package REF7025 (First 10000 Hours)
18
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF70 have differing coefficients of thermal expansion, resulting
in stress on the device die when the part is heated during soldering process. Mechanical and thermal stress on
the device die can cause the output voltages to shift, degrading the initial accuracy specifications of the product.
Reflow soldering is a common cause of this error. In order to illustrate this effect, a total of 32 devices were
soldered on two printed circuit boards [16 devices on each printed circuit board (PCB)] using lead-free solder
paste and the paste manufacturer suggested reflow profile. The reflow profile is as shown in Figure 8-1. The
printed circuit board is comprised of FR4 material. The board thickness is 1.65 mm and the area is 114 mm ×
152 mm.
For recommended reflow profiles using 'Sn-Pb Eutectic Assembly' or 'Pb-Free Assembly' please refer JEDEC
J-STD-020 standard.
300
Temperature (ƒC)
250
200
150
100
50
0
0
50
100
150
200
250
300
Time (seconds)
350
400
C01
Figure 8-1. Reflow Profile
80%
80%
60%
60%
Population (%)
Population (%)
The reference output voltage is measured before and after the reflow process. Although all tested units exhibit
very low shifts, higher shifts are also possible depending on the size, thickness, and material of the printed circuit
board. An important note is that the Figure 8-2 and Figure 8-3 display the typical shift for exposure to a single
reflow profile. Exposure to multiple reflows, as is common on PCBs with surface-mount components on both
sides, causes additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device
must be soldered in the last pass to minimize its exposure to thermal stress.
40%
40%
20%
20%
0
0
0
0.01
0.02
0.03
0.04
-0.08
0.05
-0.06
-0.04
-0.02
0
Solder Shift (%)
Solder Shift (%)
Figure 8-2. Solder Shift (LCCC Package)
Figure 8-3. Solder Shift (VSSOP Package)
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8.2 Long-Term Stability
One of the key parameters of the REF70 references is long-term stability also known as long-term drift. The
long-term stability value was tested in a typical setup that reflects standard PCB board manufacturing practices.
The boards are made of standard FR4 material and the board does not have special cuts or grooves around the
devices to relieve the mechanical stress of the PCB. The devices and boards in this test do not undergo high
temperature burn in post-soldering prior to testing. These conditions reflect a real world use case scenario and
common manufacturing techniques.
During the long-term stability testing, precautions are taken to ensure that only the long-term stability drift is
being measured. The boards are maintained at 35°C in an oil bath. The oil bath ensures that the temperature
is constant across the device over time compared to an air oven. The measurements are captured every 30
minutes with a calibrated 8.5 digit multimeter.
Typical long-term stability characteristic is expressed as a deviation over time. Figure 8-4 shows the typical drift
value for the REF70 in LCCC (FKH) package is 35 ppm from 0 to 1000 hours. It is important to understand that
long-term stability is not ensured by design and that the value is typical. The REF70 will experience the highest
drift in the initial 1000 hr. Subsequent deviation is typically lower than previous 1000 hr.
200
Output voltage stability (ppm)
150
100
50
0
-50
-100
-150
-200
0
2000
4000
6000
Time (hr)
8000
10000
Figure 8-4. Long Term Stability LCCC -10000 hours (VOUT)
Figure 8-5 shows the typical drift value for the REF70 in VSSOP (DGK) package is 75 ppm from 0 to 1000
hours. It is important to understand that long-term stability is not ensured by design and that the value is typical.
The REF70 will experience the highest drift in the initial 1000 hr.
Output Voltage Stability (ppm)
300
200
100
0
-100
-200
-300
0
2000
4000
6000
Time (hr)
8000
10000
Figure 8-5. Long Term Stability VSSOP -10000 hours (VOUT)
8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF70 soldered to a PCB, similar to a real-world application. Thermal
hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling
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the device through the specified temperature range, and returning to 25°C. This can be seen in Figure 8-6 to
Figure 8-8. Hysteresis can be expressed by Equation 1:
VHYST
§ | VPRE VPOST | ·
6
¨
¸ u 10 ppm
V
NOM
©
¹
(1)
where
VHYST = thermal hysteresis (in units of ppm)
VNOM = the specified output voltage
VPRE = output voltage measured at 25°C pre-temperature cycling
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to +125°C and returns to 25°C.
50%
50%
40%
40%
Population (%)
Population (%)
•
•
•
•
30%
20%
30%
20%
10%
10%
0
350
0
120 130 140 150 160 170 180 190 200 210 220 230 240
Thermal Hysteresis (ppm)
Figure 8-6. REF7025QFKHR Thermal Hysteresis
Distribution (-40°C to 125°C)
390
430
470
510
550
Thermal Hysteresis (ppm)
Figure 8-7. REF7012QDGKR Thermal Hysteresis
Distribution (-40°C to 125°C)
50%
Population (%)
40%
30%
20%
10%
0
0
10
20
30
40
Thermal Hysteresis (ppm)
Figure 8-8. REF7012QFKHR Thermal Hysteresis Distribution (-40°C to 125°C)
8.4 Noise Performance
8.4.1 1/f Noise
1/f noise, also known as flicker noise, is a low frequency noise that affects the device output voltage which can
affect precision measurements in ADCs. This noise increases proportionally with output voltage and operating
temperature. It is measured by filtering the output from 0.1-Hz to 10-Hz. Since the 1/f noise is an extremely
low value, the frequency of interest needs to be amplified and band-pass filtered. This is done by using a
high-pass filter to block the DC voltage. The resulting noise is then amplified by a gain of 1000. The bandpass
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filter is created by a series of high-pass and low-pass filter that adds additional gain to make it more visible
on a oscilloscope as shown in Figure 8-9. 1/f noise must be tested in a Faraday cage enclosure to block
environmental noise.
VIN
VREFP
CIN
VIN EN
OUTF
REF70xx
Low Noise
Preamplifier
G = 1000
High-pass Filter
FC = 0.07 Hz
OUTS
CL
GND
2nd Order
High-pass Filter
FC = 0.1 Hz
G = 10
2nd Order
Low-pass Filter
FC = 10 Hz
G = 10
2nd Order
Low-pass Filter
FC = 10 Hz
G=1
Scope
Copyright © 2017, Texas Instruments Incorporated
Figure 8-9. 1/f Noise Test Setup
Typical 1/f noise (0.1-Hz to 10-Hz) distribution can be seen in Figure 8-10. The noise is measured at two
different supply voltages. The REF70 noise performance is not impacted by supply voltage.
50
Vin =5.5V
Vin=12V
Population (%)
40
30
20
10
0
0
0.1
0.2
0.3
0.4
Noise (ppmp-p)
Figure 8-10. 0.1-Hz to 10-Hz Voltage Noise Distribution
The 1/f noise is in such a low frequency range that it is not practical to filter out which makes it a key parameter
for ultra-low noise measurements. Noise sensitive designs must use the lowest 1/f noise for the highest precision
measurements. Figure 8-11 shows the effect of 1/f noise over 10s.
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Time 1s/div
Figure 8-11. 0.1-Hz to 10-Hz Voltage Noise
8.4.2 Broadband Noise
Broadband noise is a noise that appears at higher frequency compared to 1/f noise. The broadband noise is
usually flat and uniform over frequency as shown in Figure 8-13. The broadband noise is measured by high-pass
filtering the output of the REF70 and measuring the result on a spectrum analyzer as shown in Figure 8-12.
The DC component of the REF70 is removed by using a high-pass filter and then amplified. When measuring
broadband noise, it is not necessary to have high gain in order to achieve maximum bandwidth.
VIN
VREFP
CIN
VIN EN
REF70xx
OUTF
High-pass Filter
G = 11
OUTS
Post Amplifier
G = 11
Spectrum
Analyzer
CL
GND
Figure 8-12. Broadband Noise Test Setup
For noise sensitive designs, a low-pass filter can be used to reduce broadband noise output noise levels by
removing the high frequency components. When designing a low-pass filter special care must be taken to
ensure the output impedance of the filter does not degrade ac performance. This can occur in RC low-pass
filters where a large series resistance can impact the load transients due to output current fluctuations.
100
90
Noise (nV/vHz)
80
70
60
50
40
30
20
10
0
10
100
1k
Frequency (Hz)
10k
100k
Figure 8-13. Noise Performance 10 Hz to 100 kHz
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8.5 Temperature Drift
The REF70 is designed and tested for a minimal output voltage temperature drift, which is defined as the
change in output voltage over temperature. Every unit shipped is tested at multiple temperatures to ensure that
the product meets data sheet specifications. The temperature coefficient is calculated using the box method
in which a box is formed by the min/max limits for the nominal output voltage over the operating temperature
range. REF70 has a low maximum temperature coefficient of 2 ppm/°C from –40°C to +125°C. This method
corresponds more accurately to the method of test and provides a closer estimate of actual error than the other
methods. The box method specifies limits for the temperature error but does not specify the exact shape and
slope of the device under test. Due to temperature curvature correction to achieve low-temperature drift, the
temperature drift is expected to be non-linear. See SLYT183 for more information on the box method. The box
method equation is shown in Equation 2:
Drift
§
·
VREF(MAX) VREF(MIN)
¨
¸ u 106
¨ VREF(25qC) u Temperature Range ¸
©
¹
(2)
2.501
2.50075
Output Voltage (V)
2.5005
2.50025
2.5
2.49975
2.4995
2.49925
2.499
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 8-14. Output Voltage Vs Free-Air Temperature
8.6 Power Dissipation
The REF70 voltage references are capable of source and sink up to 10 mA of load current across the rated
input voltage range. However, when used in applications subject to high ambient temperatures, the input voltage
and load current must be carefully monitored to ensure that the device does not exceeded its maximum power
dissipation rating. The maximum power dissipation of the device can be calculated with Equation 3:
TJ
TA
PD u RTJA
(3)
where
•
•
•
•
PD is the device power dissipation
TJ is the device junction temperature
TA is the ambient temperature
RθJA is the package (junction-to-air) thermal resistance
Because of this relationship, acceptable load current in high temperature conditions may be less than the
maximum current-sourcing capability of the device. In no case should the device be operated outside of its
maximum power rating because doing so can result in premature failure or permanent damage to the device.
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9 Detailed Description
9.1 Overview
The REF70 is family of ultra low-noise, precision bandgap voltage references that are specifically designed for
excellent initial voltage accuracy and drift. The Section 9.2 is a simplified block diagram of the REF70 showing
basic band-gap topology.
9.2 Functional Block Diagram
VIN
Digital
Core
Bandgap
Core
VIN
+
Reference
Buffer
Å
OUTF
REN
OUTS
Enable
Controller
EN
GND
9.3 Feature Description
9.3.1 EN Pin
The EN pin of the REF70 has an internal 16 MΩ pull-up resistor (REN) to VIN. This allows the EN pin of the
REF70 to be left floating. When the EN pin of the REF70 is pulled high, the device is in active mode. The device
must be in active mode for normal operation. The REF70 can be placed in shutdown mode by pulling the EN pin
low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of
the device reduces to 12 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply voltage.
See the Section 7.6 for logic high and logic low voltage levels.
9.4 Device Functional Modes
9.4.1 Basic Connections
Figure 9-1 shows the typical connections for the REF70. TI recommends a supply bypass capacitor (CIN)
ranging from 0.1-μF to 10-μF. A 1-μF to 100-μF output capacitor (CL) must be connected from OUTF to GND.
The equivalent series resistance (ESR) value of CL must be 1 mΩ to 400 mΩ to ensure output stability.
AVDD
VOUT
OUTF
VIN
EN
CIN
REF7025
GND
OUTS
CL
Copyright © 2020, Texas Instruments Incorporated
Figure 9-1. Basic Connections
9.4.2 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF70 and OPA211 can be used to
provide a dual-supply reference from a 5-V supply. Figure 9-2 shows the REF70 used to provide a 2.5-V supply
reference voltage and -2.5V negative reference voltage. The low noise performance of the REF70 complements
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the low noise of the OPA211 to provide an accurate solution for split-supply applications. Take care to match the
temperature coefficients of R1 and R2.
+5V
VIN EN
REF7025
OUTF
+2.5V
OUTS
GND
R1
10 k
R2
10 k
+5V
-2.5V
OPA211
-5V
Copyright © 2020, Texas Instruments Incorporated
Figure 9-2. The REF70 and OPA211 Create Positive and Negative Reference Voltages
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
This device is a natural fit for many precision applications and it can be connected to system components
in various ways and thus there are many situations that this data sheet can not characterize in detail. Basic
applications include positive/negative voltage reference and data acquisition systems. The table below shows
the typical applications of REF70 and its companion data converters.
APPLICATION
DATA CONVERTER
Precision Data Acquisition
ADS124S08, ADS8900B, ADS1278, ADS1262, DAC80501,
DAC8562
Industrial Instrumentation
ADS127L01, ADS8699, ADS1256, ADS1251, DAC9881, DAC8811,
DAC1220, DAC80508
Semiconductor Test
ADS8598H, ADS131M08, ADS8686S, ADS8881, DAC11001A,
DAC91001A, DAC7744
Power Monitoring, PLC Analog I/O
ADS131E04, ADS131A02,
Field Transmitters
ADS1247, ADS1220
10.2 Typical Applications
10.2.1 Typical Application: Basic Voltage Reference Connection
The circuit shown in Figure 10-1 shows the basic configuration for the REF70 references. Connect bypass
capacitors according to the guidelines in Section 10.2.1.2.1.
AVDD
VIN EN
REF7025
OUTF
OUTS
GND
AVDD
OPA2320
REFN0 REFP0
AVDD
AIN0
AVDD
AIN
ADS124S08
AVDD
AVSS
AIN1
OPA2320
Copyright © 2020, Texas Instruments Incorporated
Figure 10-1. Basic Reference Connection
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10.2.1.1 Design Requirements
A detailed design procedure is based on a design example. For this design example, use the parameters listed
in Table 10-1 as the input parameters.
Table 10-1. Design Example Parameters
DESIGN PARAMETER
VALUE
Input voltage VIN
5.5 V
Output voltage VOUT
2.5 V
REF7025 input capacitor
10-µF
REF7025 output capacitor
10-µF
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Input and Output Capacitors
A 1 μF to 10 μF bypass capacitor should be connected to the input to improve transient response in applications
where the supply voltage may fluctuate. Connect an additional 0.1 μF capacitor in parallel to reduce high
frequency supply noise.
A low ESR capacitor of 1 μF to 100 μF must be connected to the output to improve stability and help filter
out high frequency noise. Best performance and stability is attained with low-ESR output capacitors with an
ESR from 1 mΩ to 400 mΩ. For very low noise applications, special care must be taken with X7R and
other MLCC capacitors due to their piezoelectric effect. Mechanical vibration can transduce to voltage via the
piezoelectric effect which appears as noise in the μV range, potentially dominating the noise of the REF70. More
information on how the piezoelectric effect can be explored in systems can be found in Stress-induced outbursts:
Microphonics in ceramic capacitors (Part 1) and Stress-induced outbursts: Microphonics in ceramic capacitors
(Part 2). It is recommended that to use film capacitors for noise sensitive applications.
The transient startup response of the REF70 is shown in Figure 10-2. The startup response of the REF70 family
is dependent on the output capacitor. While larger capacitors will decrease the output noise, they will increase
the startup response.
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10.2.1.2.1.1 Application Curve
Figure 10-2. REF7025 Startup (C = 10 μF)
10.2.1.2.2 Force and Sense Connection
Current flowing through a PCB trace produces an IR voltage drop, and with longer traces, this drop can reach
several millivolts or more, introducing a considerable error into the output voltage of the reference. A 3000-mil
long, 15-mil wide trace of 1-ounce copper has a resistance of approximately 100 mΩ at room temperature; at a
load current of 10 mA, this can introduce a full millivolt of error. In an ideal board layout, the reference must be
mounted as close as possible to the load to minimize the length of the output traces, and, therefore, the error
introduced by voltage drop. However, in applications where this is not possible or convenient, force and sense
connections (sometimes referred to as Kelvin sensing connections) are provided as a means of minimizing the
IR drop and improving accuracy.
Kelvin connections work by providing a set of high impedance voltage-sensing lines to the output and ground
nodes. Because very little current flows through these connections, the IR drop across their traces is negligible,
and the output and ground. The REF70 has kelvin connection capabilities due to its output force (OUTF) and
input sense (OUTS) connection as shown in Basic Reference Connection. The output force voltage will vary
upwards from the internal VREF voltage to ensure that at VOUT, which is where the OUTF and OUTS connect at
the point-of-load, the voltage will be precisely VREF. The sense connection on the REF70 requires 4 mA due to
its architecture.
It is always advantageous to use Kelvin connections whenever possible. However, in applications where the IR
drop is negligible or an extra set of traces cannot be routed to the load, the force and sense pins for VOUT can
simply be tied together close to the pins, and the device can be used in the same fashion as a normal 3-terminal
reference.
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10.2.2 Typical Application: DAC Force and Sense Reference Drive Circuit
Certain DACs require external voltage references to operate properly. There are DACs that only require a
positive voltage for operating in which the basic connection will work. For other DACs there can be a need a
positive and negative reference voltage due to their bipolar output.
The circuit shown in Figure 10-3 shows a DAC force and sense reference drive circuit for the DACx1001 using
the REF70. This circuit takes advantage of the DACx1001 RCM circuit to remove the need of additional external
resistors to make a negative reference due to the integrated precision resistors. This circuit requires additional
buffers due to undesired series resistance on the reference input of the DAC.
VIN
VREFP
CIN
VIN EN
OUTF
REF7050
REFPF
OUTS
GND
CL
C1
REFPS
ROFS
RCM
DACx1001
RFB
REFNS
C2
REFNF
VREFN
Copyright © 2020, Texas Instruments Incorporated
Figure 10-3. Basic Force and Sense Reference Drive Circuit Connections with DACx1001
10.2.2.1 Design Requirements
For this design example, use the reference op amp recommendation listed in Table 10-2 for the buffer circuit.
Table 10-2. Reference Op Amp Options
SELECTION PARAMETERS
Low voltage and current noise
OP AMPS
OPA211, OPA827, OPA828
Low offset and drift
OPA189
The REF70 turn-on time is dependent on the output capacitor. In certain applications that require a fast turn-on
can require a smaller output capacitor as shown in Figure 10-4
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2
1PF
10PF
Turn-on Time (ms)
1.6
1.2
0.8
0.4
0
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 10-4. REF70 Turn-on Time
For DAC designs that do not have the RCM feature, use Figure 10-5 as it in generates the negative reference
circuit to create the VREFN. More details on this type of design can be found in SBAA322.
VIN
VCC
CIN
VIN EN
REF7050
OUTF
VREFH-F
OUTS
GND
C1
CL
VSS
VREFH-S
DAC8871
R1
10 k
R2
10 k
VREFL-S
VCC
VCC
C2
VREFL-F
VSS
VSS
Copyright © 2020, Texas Instruments Incorporated
Figure 10-5. Basic Force and Sense Reference Drive Circuit Connections
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10.3 Power Supply Recommendation
The REF70 family of references features a low-dropout voltage. These references can be operated with a supply
of only 50 mV above the output voltage for 0-mA output current conditions. The dropout voltage will vary with
the output current so refer to the dropout voltage to see typical dropout voltage requirements. TI recommends a
supply bypass capacitor ranging between 0.1 µF to 10 µF.
During start-up the REF70 can experience moments of high input current due to the output capacitors. The input
current can momentarily rise to ISC.
300
Dropout Voltage (mV)
250
0mA
5mA
10mA
200
150
100
50
0
-50
-25
0
25
50
Temperature (°C)
75
100
125
Figure 10-6. Dropout Voltage vs Temperature
10.4 Layout
10.4.1 Layout Guidelines
Figure 10-7 and Figure 10-8 illustrate an example of a PCB layout for a data acquisition system using the
REF70. Some key considerations are:
• Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN of the REF70.
• Connect low-ESR, 1-uF to 100-uF capacitor at OUTF of the REF70.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
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10.4.2 Layout Example
Analog GND
GND
Enable Control
8
Input Voltage
CIN
EN
1
7
OUTF
VIN
2
6
OUTS
GND
3
5
GND
VREF
CL
4
GND
Copyright © 2020, Texas Instruments Incorporated
Figure 10-7. Layout Example FKH Package
Enable Control
EN 1
8 GND
Input Voltage
VIN 2
7 OUTF
GND 3
6 OUTS
GND 4
5 GND
CIN
Analog GND
VREF
CL
Analog GND
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Figure 10-8. Layout Example DGK Package
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Voltage Reference Design Tips For Data Converters
Texas Instruments, Voltage Reference Selection Basics
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
REF7012QDGKR
ACTIVE
VSSOP
DGK
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2L1S
Samples
REF7012QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
-40 to 125
REF12FKH
Samples
REF7025QDGKR
ACTIVE
VSSOP
DGK
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2TAS
Samples
REF7025QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
-40 to 125
REF25FKH
Samples
REF7030QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
-40 to 125
REF30FKH
Samples
REF7033QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
-40 to 125
REF33FKH
Samples
REF7040QDGKR
ACTIVE
VSSOP
DGK
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2TDS
Samples
REF7040QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
-40 to 125
REF40FKH
Samples
REF7050QDGKR
ACTIVE
VSSOP
DGK
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2TES
Samples
REF7050QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
N / A for Pkg Type
-40 to 125
REF50FKH
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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