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RF430CL331H
SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
RF430CL331H NFC Type 4B Dynamic Dual Interface Transponder
1 Device Overview
1.1
Features
1
• Pass-Through Operation Sends Data Updates and
Requests to Host Controller
• I2C Interface Allows Writing and Reading of
Internal SRAM
• Prefetching, Caching, and Auto ACK Features
Increase Data Throughput
1.2
•
•
Applications
Wireless Firmware Updates
Wi-Fi® and Bluetooth® Pairing
1.3
• Enables Data Streaming
• All RF Communication up to Layer 4 Handled
Automatically
• Supports up to Maximum NDEF Message Size
• Compliant With ISO/IEC 14443B
• Supports up to 848 kbps
•
•
Service Interface
Wireless Sensor Interfaces
Description
The TI Dynamic NFC/RFID Interface Transponder RF430CL331H is an NFC Tag Type 4 device that
combines a contactless NFC/RFID interface and a wired I2C interface to connect the device to a host. The
NDEF message can be written and read from the integrated I2C serial communication interface and can
also be accessed and updated over a contactless interface using the integrated ISO/IEC 14443 Type B
compliant RF interface that supports up to 848 kbps.
The device requests responses to NFC Type 4 commands on demand from the host controller and stores
only a portion of the NDEF message in its buffer at any one time. This allows NDEF message size to be
limited only by the memory capacity of the host controller and specification limitations.
Support of read caching, prefetching, and write automatic acknowledgment features allows for greater
data throughput.
This device enables NFC connection handover for an alternative carrier like Bluetooth®, Bluetooth® low
energy (BLE), or Wi-Fi as an easy and intuitive pairing process or authentication process with only a tap.
As a general NFC interface, the RF430CL331H enables end equipment to communicate with the fastgrowing infrastructure of NFC-enabled smart phones, tablets, and notebooks.
Device Information
PART NUMBER
(1)
(2)
PACKAGE
BODY SIZE
RF430CL331HIPW
TSSOP (14)
5 mm × 4.4 mm
RF430CL331HRGT
VQFN (16)
3 mm × 3 mm
(1)
(2)
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 8, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 8.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RF430CL331H
SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
1.4
www.ti.com
Typical Application
Figure 1-1 shows a typical application.
2
IC
Microcontroller
I2C Bus
Flow Control
RF430
NFC/RFID
Tag
NFC/RFID
Reader
INTO
Figure 1-1. Typical Application
2
Device Overview
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SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
Table of Contents
1
Device Overview ......................................... 1
5.2
Functional Block Diagram ........................... 12
1.1
Features .............................................. 1
5.3
Terms and Acronyms
1.2
Applications ........................................... 1
5.4
Serial Communication Interface ..................... 12
1.3
Description ............................................ 1
5.5
Communication Protocol ............................ 13
...................................
Revision History .........................................
Terminal Configuration and Functions ..............
3.1
Pin Diagrams .........................................
3.2
Pin Attributes .........................................
3.3
Signal Descriptions ...................................
3.4
Pin Multiplexing .......................................
3.5
Connections for Unused Pins ........................
Specifications ............................................
4.1
Absolute Maximum Ratings ..........................
4.2
ESD Ratings ..........................................
4.3
Recommended Operating Conditions ................
1.4
2
3
4
4.4
2
3
4
4
5
6
6
6
6
7
7
7
7
7
Recommended Operating Conditions, Resonant
Circuit ................................................. 7
...................................... 8
4.6
Electrical Characteristics, Digital Inputs .............. 8
4.7
Electrical Characteristics, Digital Outputs ............ 8
4.8
Thermal Characteristics .............................. 9
4.9
Timing and Switching Characteristics ............... 10
Detailed Description ................................... 12
5.1
Overview ............................................ 12
4.5
5
Typical Application
Supply Currents
8
...............................
.........................................
.........................
5.8
NDEF Structure .....................................
5.9
Typical Operation....................................
5.10 RF Command Response Timing Limits .............
5.11 Registers ............................................
5.12 Identification .........................................
Applications, Implementation, and Layout........
6.1
Application Diagram .................................
6.2
References ..........................................
Device and Documentation Support ...............
7.1
Device Support ......................................
7.2
Documentation Support .............................
7.3
Community Resources ..............................
7.4
Trademarks..........................................
7.5
Electrostatic Discharge Caution .....................
7.6
Export Control Notice ...............................
7.7
Glossary .............................................
5.6
I2C Protocol
5.7
NFC Type 4B Tag Platform
12
13
16
19
21
33
35
48
49
49
49
50
50
51
51
51
52
52
52
Mechanical, Packaging, and Orderable
Information .............................................. 52
2 Revision History
Changes from September 29, 2015 to November 30, 2015
•
•
Page
Deleted "Suggested to be set to 0x3B" from Step 7(a) ........................................................................ 34
Deleted "The recommended setting is maximum possible value, which is 0x3B" in the paragraph that starts
"When the internal state machine determines..."................................................................................ 46
Revision History
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RF430CL331H
SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
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3 Terminal Configuration and Functions
3.1
Pin Diagrams
Figure 3-1 shows the pinout for the 14-pin PW package.
VCC
1
14
VSS
ANT1
2
13
VCORE
ANT2
3
12
SDA
RST
4
11
SCL
E0
5
10
I2C_SIGNAL
E1
6
9
I2C_READY
E2
7
8
INTO
Figure 3-1. 14-Pin PW Package (Top View)
VSS
NC
VCC
NC
Figure 3-2 shows the pinout for the 16-pin RGT package.
ANT1
16 15 14 13
12
1
ANT2
2
RST
3
E0
4
SCL
9
I2C_SIGNAL
5
6
7
8
I2C_READY
10
INTO
SDA
E2
11
E1
Exposed
Thermal
Pad
VCORE
Figure 3-2. 16-Pin RGT Package (Top View)
4
Terminal Configuration and Functions
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3.2
SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
Pin Attributes
Table 3-1. Pin Attributes
PIN NUMBER
(1)
(2)
(3)
SIGNAL NAME
SIGNAL TYPE
(1)
BUFFER TYPE
(2)
POWER SOURCE
RESET STATE
PW
RGT
1
15
VCC
PWR
Power
VCC
N/A
2
1
ANT1
RF
Analog
–
N/A
3
2
ANT2
RF
Analog
–
N/A
4
3
RST
I
LVCMOS
VCC
PU
5
4
E0
I
LVCMOS
VCC
OFF
6
5
E1
I
LVCMOS
VCC
OFF
7
6
E2
I
LVCMOS
VCC
OFF
8
7
INTO
O
LVCMOS
VCC
OFF
9
8
I2C_READY
O
LVCMOS
VCC
DRIVE1
10
9
I2C_SIGNAL
O
LVCMOS
VCC
DRIVE1
11
10
SCL
I/O
LVCMOS
VCC
OFF
12
11
SDA
I/O
LVCMOS
VCC
OFF
13
12
VCORE
PWR
Power
VCC
N/A
14
13
VSS
PWR
Power
VCC
N/A
–
14
NC
–
–
–
–
–
16
NC
–
–
–
–
(3)
Signal Types: I = Input, O = Output, I/O = Input or Output, PWR = Power, RF = Radio frequency
Buffer Types: See Table 3-3 for details.
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
Terminal Configuration and Functions
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SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
3.3
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Signal Descriptions
Table 3-2 describes the signals.
Table 3-2. Signal Descriptions
FUNCTION
SIGNAL NAME
PIN NUMBER
I/O
(1)
DESCRIPTION
PW
RGT
VCC
1
15
PWR
3.3-V power supply
VCORE
13
12
PWR
Regulated core supply voltage
VSS
14
13
PWR
Ground supply
ANT1
2
1
RF
Antenna input 1
ANT2
3
2
RF
Antenna input 2
E0
5
4
I
I2C address select 0
E1
6
5
I
I2C address select 1
E2
7
6
I
I2C address select 2
Serial
I2C_READY
communication
9
8
O
High indicates that I2C communication can be started. Low indicates
that I2C communication must not be started.
I2C_SIGNAL
10
9
O
Low indicates that a wait time extension command is automatically
being sent. I2C communication does not have to be stopped.
SCL
11
10
I/O
I2C clock
SDA
12
11
I/O
I2C data
INTO
8
7
O
Interrupt output
RST
4
3
I
Reset input (active low)
NC
–
14
16
–
Leave open, no connection
Power
RF
System
No connect
(1)
(2)
(2)
I = Input, O = Output, PWR = Power, RF = RF antenna
With integrated pullup
3.4
Pin Multiplexing
None of the pins on this device are multiplexed.
Table 3-3. Buffer Type
BUFFER TYPE
(STANDARD)
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
LVCMOS
3.3 V
Y
N/A
Analog, RF
3.3 V
N
N/A
N/A
N/A
Power
3.3 V
Y with SVS on
N/A
N/A
N/A
3.5
OTHER
CHARACTERISTICS
See Section 4.6, See Section 4.7,
Electrical
Electrical
Characteristics, Characteristics,
Digital Inputs
Digital Outputs
See analog modules in
Section 4, Specifications,
for details
Connections for Unused Pins
Leave no connect (NC) pins unconnected.
Leave unused outputs unconnected.
Drive or pull unused inputs high or low.
6
Terminal Configuration and Functions
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4 Specifications
4.1
Absolute Maximum Ratings
(1) (2)
MIN
MAX
Voltage applied at VCC referenced to VSS (VAMR)
–0.3
4.1
V
Voltage applied at VANT referenced to VSS (VAMR)
–0.3
4.1
V
Voltage applied to any pin (references to VSS)
–0.3
VCC + 0.3
Diode current at any device pin
Storage temperature, Tstg
(1)
(2)
(3)
(3)
–40
V
±2
mA
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are referenced to VSS.
For soldering during board manufacturing, it is required to follow the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
4.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
UNIT
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3
Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
NOM
MAX
During program execution no RF field present
3.0
3.3
3.6
During program execution with RF field present
2.0
3.3
3.6
VCC
Supply voltage
VSS
Supply voltage (GND reference)
TA
Operating free-air temperature
C1
Decoupling capacitor on VCC
(1)
0.1
C2
Decoupling capacitor on VCC
(1)
1
CVCORE
Capacitor on VCORE
(1)
UNIT
V
0
V
–40
(1)
0.1
85
°C
µF
µF
0.47
1
NOM
MAX
µF
Low ESR (equivalent series resistance) capacitor
4.4
Recommended Operating Conditions, Resonant Circuit
MIN
fc
Carrier frequency
13.56
UNIT
MHz
VANT_peak Antenna input voltage
V
15.5
kΩ
Z
Impedance of LC circuit
LRES
Coil inductance (1)
2.66
µH
CRES
Total resonance capacitance (1), CRES = CIN + CTune
51.8
pF
CTune
External resonance capacitance
QT
Tank quality factor
(1)
(2)
6.5
3.6
CRES – CIN
(2)
pF
30
The coil inductance of the antenna LRES with the external capacitance CTune plus the device internal capacitance CIN is a resonant
circuit. The resonant frequency of this LC circuit must be close to the carrier frequency fc:
fRES = 1 / [2π(LRESCRES)1/2] = 1 / [2π(LRES(CIN+CTune))1/2] ≈ fc
For CIN refer to Section 4.9.3.
Specifications
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4.5
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Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
ICC(I2C)
I2C, 400 kHz, Writing into NDEF memory
3.3 V
250
µA
ICC(RF enabled)
RF enabled, no RF field present
3.3 V
40
µA
ICC(Inactive)
Standby enable = 0, RF disabled, no serial
communication
3.3 V
15
µA
ICC(Standby)
Standby enable = 1, RF disabled, no serial
communication
3.3 V
10
ΔICC(StrongRF)
Additional current consumption with strong RF field
present
ICC(RF,lowVCC)
Current drawn from VCC < 3.0 V with RF field present
(passive operation)
4.6
45
µA
3.0 V to 3.6 V
160
µA
2.0 V to 3.0 V
0
µA
Electrical Characteristics, Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
0.3 ×
VCC
V
VIL
Low-level input voltage
VIH
High-level input voltage
0.7 ×
VCC
V
VHYS
Input hysteresis
0.1 ×
VCC
V
IL
High-impedance leakage current
RPU(RST)
Integrated RST pullup resistor
4.7
3.3 V
–50
50
nA
35
50
kΩ
MIN
MAX
20
Electrical Characteristics, Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOL
Output low voltage
TEST CONDITIONS
IOL = 3 mA
VCC
3V
0.4
3.3 V
0.4
3.6 V
VOH
8
Output high voltage
IOH = –3 mA
Specifications
UNIT
V
0.4
3V
2.6
3.3 V
2.9
3.6 V
3.2
V
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4.8
SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
VALUE
UNIT
116.0
°C/W
45.1
°C/W
57.6
°C/W
57.0
°C/W
RθJA
Junction-to-ambient thermal resistance, still air
RθJC(TOP)
Junction-to-case (top) thermal resistance (2)
RθJB
Junction-to-board thermal resistance (3)
ΨJB
Junction-to-board thermal characterization parameter
ΨJT
Junction-to-top thermal characterization parameter
4.6
°C/W
RθJA
Junction-to-ambient thermal resistance, still air (1)
48.8
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance (2)
60.8
°C/W
RθJC(BOT)
Junction-to-case (bottom) thermal resistance
RθJB
Junction-to-board thermal resistance (3)
ΨJB
ΨJT
(1)
(2)
(3)
(4)
TSSOP-14 (PW)
(4)
7.1
°C/W
21.9
°C/W
Junction-to-board thermal characterization parameter
21.9
°C/W
Junction-to-top thermal characterization parameter
1.5
°C/W
VQFN-16 (RGT)
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Specifications
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4.9
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Timing and Switching Characteristics
4.9.1
Reset Timing
Table 4-1. I2C Power-up Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tReady
(1)
MIN
2
Time after power up or reset until device is ready to communicate using I C
(1)
MAX
20
UNIT
ms
The device is ready to communicate after tReady(MAX) at the latest.
4.9.2
Serial Communication Protocol Timing
Table 4-2. I2C Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1)
PARAMETER
TEST CONDITIONS
MIN
MAX
3.3 V
0
400
Write
3.3 V
0
120
Read
3.3 V
0
100
SCL clock frequency (with Master supporting clock stretching
according to I2C standard, or when the device is not being
addressed)
fSCL
SCL clock frequency (device being addressed by Master not
supporting clock stretching)
VCC
UNIT
kHz
fSCL ≤ 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
3.3 V
0
tSU,DAT
Data setup time
3.3 V
250
ns
tSU,STO
Setup time for STOP
3.3 V
4
µs
tSP
Pulse duration of spikes suppressed by input filter
3.3 V
6.25
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
tSU,STA
3.3 V
4
3.3 V
µs
0.6
4.7
µs
0.6
ns
75
ns
tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 4-1. I2C Mode Timing
10
Specifications
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4.9.3
SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015
RF143B NFC/RFID Analog Front End
Table 4-3. Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDDH
Antenna rectified voltage
Peak voltage limited by antenna limiter
IDDH
Antenna load current
RMS, without limiter current
CIN
Input capacitance
ANT1 to ANT2, 2 V RMS
MIN
TYP
MAX
3.0
3.3
3.6
V
100
µA
38.5
pF
TYP
MAX
UNIT
106
848
kbps
31.5
35
UNIT
Table 4-4. ISO/IEC 14443B ASK Demodulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
DR10
Input signal data rate 10% downlink modulation, 7% to 30% ASK, ISO1443B
m10
Modulation depth 10%, tested as defined in ISO/IEC 10373-6
7%
30%
Table 4-5. ISO/IEC 14443B-Compliant Load Modulator
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
1
MHz
fPICC
Uplink subcarrier modulation frequency
0.2
VA_MOD
Modulated antenna voltage, VA_unmod = 2.3 V
0.5
V
0.5
mV
VSUB14
Uplink modulation subcarrier level, ISO/IEC 14443B: H = 1.5 to 7.5 A/m
22/H
Table 4-6. Power Supply
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLIM
Limiter clamping voltage
ILIM,MAX
Maximum limiter current
TEST CONDITIONS
ILIM ≤ 70 mA RMS, f = 13.56 MHz
MIN
3.0
TYP
MAX
Vpk
70
mA
Specifications
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UNIT
3.6
11
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5 Detailed Description
5.1
Overview
Figure 5-1 shows the functional block diagram.
5.2
Functional Block Diagram
RST
VCC
Buffer
Memory
(SRAM)
VSS
VCORE
SCL
SDA
Processing
Unit
(MSP430based)
I2C
Interface
I2C_READY
NFC Type 4B
Tag Platform
ISO/IEC 14443
RF Interface
ANT1
ANT2
I2C_SIGNAL
E0
E1
E2
INTO
Figure 5-1. Functional Block Diagram
5.3
Terms and Acronyms
Table 5-1 describes the terms and acronyms used in this document.
Table 5-1. Term Definitions
NAME
DESCRIPTION
PCD
Proximity coupling device, such as NFC enabled handset, NFC/RFID reader/writer devices
PICC
Proximity integrated circuit card, dynamic tag, RF430CL331H IC
NFC Type 4 command
See the NFC Forum Type 4 Tag Operation Specification (http://nfc-forum.org/) for details
PICC Buffer
This is a memory range (0 through 2999) that is accessible through the I2C bus, where buffer data is stored.
Host Controller
This is a MCU or processor connected to the PICC through the I2C bus. It responds to all the of Type 4 data
requests that come from the PICC.
SW
Type 4 command acknowledgments, referred also as SW1 and SW2 (status word). Refer to NFC/RFID and
ISO14443-B specifications for details.
SWTX or S(WTX)
Frame wait time extension. When the RF430CL331H cannot respond to a command that PCD sends, it must
send a S(WTX) request indicating that it needs more time. The PCD then responds and the RF430CL331H has
the negotiated time that it requested.
5.4
Serial Communication Interface
The serial interface of this device is I2C. The serial interface allows a connected MCU to configure the
device and write to and read from the available registers and the RAM buffer on the RF430CL331H.
12
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5.5
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Communication Protocol
The tag is programmed and controlled by writing data into and reading data from the address map shown
in Table 5-2 through the I2C serial interface.
Table 5-2. User Address Map
RANGE
Registers
ADDRESS
SIZE
0xFFFE
2B
Control register
0xFFFC
2B
Status register
0xFFFA
2B
Interrupt Enable
0xFFF8
2B
Interrupt Flags
0xFFF6
2B
CRC Result (16-bit CCITT)
0xFFF4
2B
CRC Length
0xFFF2
2B
CRC Start Address
0xFFF0
2B
Communication Watchdog Control register
0xFFEE
2B
Version
0xFFEC
2B
NDEF File ID register
0xFFEA
2B
Host Response register
0xFFE8
2B
NDEF Block Length register
0xFFE6
2B
NDEF File Offset register
0xFFE4
2B
Buffer Start register
0xFFE2
2B
Reserved
0xFFE0
2B
Reserved
0xFFDE
2B
SWTX register
0xFFDC
2B
Reserved
0xFFDA
2B
Custom SW1 and SW2 Response
0x4000 to 0xFFDF
Reserved
Buffer
DESCRIPTION
Reserved
0x0BB8 to 0x3FFF
13KB
0x0000 to 0x0BB7
3000 B
Reserved (for example, for future extension of NDEF Memory size)
Buffer Memory
NOTE
Crossing range boundaries causes writes to be ignored and reads to return undefined data.
5.6
I2C Protocol
A command is always initiated by the master by addressing the device using the specified I2C device
address. The device address is a 7-bit I2C address. The upper 4 bits are hard-coded, and the lower 3 bits
are programmable by the input pins E0, E1, and E2 (see Table 5-3).
Table 5-3. I2C Device Address
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
0
0
1
1
E2
E1
MSB
BIT 0
E0
LSB
To write data, the device is addressed using the specified I2C device address with R/W = 0, followed by
the upper 8 bits of the first address to be written and the lower 8 bits of that address. Next (without a
repeated START), the data to be written starting at the specified address is received. With each data byte
received, the address is automatically incremented by 1. The write access is terminated by the STOP
condition on the I2C bus.
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Device Address
WRITE
START
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Address Bits 15-8
Address Bits 7-0
LSB
ACK
LSB
ACK
MSB
MSB
LSB
R/W
ACK
MSB
SDA
Data @ Addr + 0
Data @ Addr + 1
STOP
Driven by:
Master
Slave (NFC Tag)
Data @ Addr + n
LSB
ACK
MSB
LSB
ACK
LSB
ACK
MSB
MSB
SDA
Driven by:
Master
Slave (NFC Tag)
Figure 5-2. I2C Write Access
NOTE
The minimum I2C write transaction is 2 address bytes and 2 data bytes. Writes with only one
1 byte cause the data to be ignored. Avoid a transaction less than 1 data byte, as it results in
an error.
Address Bits 7-0
Device Address
READ
Address Bits 15-8
START
Device Address
WRITE
START
To read data, the device is addressed using the specified I2C device address with R/W = 0, followed by
the upper 8 bits of the first address to be read and then the lower 8 bits of that address. Next, a repeated
START condition is expected with the I2C device address and R/W = 1. The device then transmit data
starting at the specified address until a not acknowledge (NACK) and a STOP condition are received.
LSB
R/W
ACK
MSB
LSB
ACK
LSB
ACK
MSB
LSB
R/W
ACK
MSB
MSB
SDA
Data @ Addr + 0
Data @ Addr + 1
Data @ Addr + n
STOP
Driven by:
Master
Slave (NFC Tag)
Driven by:
Master
Slave (NFC Tag)
LSB
NO ACK
MSB
LSB
ACK
LSB
ACK
MSB
MSB
SDA
Figure 5-3. I2C Read Access
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I2C Examples
5.6.1
Figure 5-4 and Figure 5-5 show examples of I2C accesses to the Control and Status registers,
respectively. Comments are provided on the tags in the figures.
5.6.1.1
I2C Write
B
C
E
A
D
Figure 5-4. I2C Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x16 (RF
Enable = 1)
A. I2C_READY signal, by being high indicates that I2C communication can be started.
B. The device address (18h because E0 = E1 = E2 = 0) is being transmitted out.
C. Register address is 0xFFFEh (which is the Control register).
D. I2C_READY line is now low, new I2C communication should not be started.
E. The data to write is transmitted (0016h).
5.6.1.2
I2C Read
B
C
D
G
E
A
F
H
Figure 5-5. I2C Access Example: Read of the Status Register at Address 0xFFFC, Responds With 0x00,
0x01 (Device_Ready = 1)
A. I2C_READY signal, by being high indicates that I2C communication can be started.
B. Packet has started: the device address (18h because E0 = E1 = E2 = 0) is being sent out.
C. Address FFFCh next is transmitted, which is the address of the status register.
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D. An I2C restart was done and device address sent with a read selection.
E. Clock stretching is being used by the RF430CL331H when it needs more time to respond due to
unfinished internal processing.
F. I2C_READY line is now low, new I2C communication should not be started.
G. RF430CL331H drives the SDA line and returns the value of the status register, which is 0001h.
H. I2C_READY signal has returned to high, indicating communication can be started. This occurs after a
short period of time after a STOP condition (in square red). This brief time is necessary for the
RF430CL331H to finish internal processing.
5.6.2
BIP-8 Communication Mode With I2C
The BIP-8 communication mode is enabled by setting the BIP-8 bit in the General Control register. All
communication after setting this bit uses the following conventions with exactly 2 address bytes (16-bit
address) and 2 data bytes (16-bit data) (see Table 5-4 and Table 5-5).
Table 5-4. Write Access
Master
Slave
Address Bits
15 to 8
Address Bits
7 to 0
Data at Addr + 0
Data at Addr + 1
BIP-8
N/A
N/A
N/A
N/A
N/A
The Bit-Interleaved Parity (BIP-8) is calculated using 16-bit address and 16-bit data. If the received BIP-8
does not match with received data, no write is performed. The BIP-8 calculation does not include the I2C
device address.
Table 5-5. Read Access
Master
Slave
Address Bits
15 to 8
Address Bits
7 to 0
N/A
N/A
N/A
N/A
N/A
Data at Addr + 0
Data at Addr + 1
BIP-8
For read access, the Bit-Interleaved Parity (BIP-8) is calculated using the received 16-bit address and the
2 transmitted data bytes, and it is transmitted back to the master. The BIP-8 does not include the device
address.
5.7
NFC Type 4B Tag Platform
This device is an NFC Forum Type 4B Tag Platform and ISO/IEC 14443B-compliant transponder that
operates according to the NFC Forum Tag Type-4 specification and supports NDEF (NFC Data Exchange
Format) data structure. Through the RF interface, the user can read and update the contents in the NDEF
memory. The NDEF message in its entirety would only be present on the memory of the host controller.
The RF430CL331H only has a portion of the NDEF message at any one time.
NOTE
This device does not have nonvolatile memory; therefore, the information stored in the NDEF
memory is lost when power is removed.
This device does not support the peer-to-peer mode or the reader/writer mode. All RF communication
between an NFC forum device and this device is in the passive tag mode. The device responds by load
modulation and is not considered an intentional radiator.
This device is intended to be used in applications where the primary reader/writer is, for example, an NFCenabled handset. In this case, the host application can be considered the destination device, and the cell
phone or other type of mobile device is treated as the end-point device.
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This device supports ISO/IEC 14443-3, ISO/IEC 14443-4, and NFC Forum commands as described in the
following sections.
The device supports data rates of 106, 212, 424, and 848 kbps.
Even though all data rates up to 848 kbps are supported, the device by default reports only the capability
to support 106 kbps to the PCD. To change this behavior, use the sequence described in Section 5.7.3.
The device always answers ATTRIB commands from the PCD that request higher data rates. The NFC
Forum specifies for NFC-B a maximum data rate of 106 kbps. It is assumed that an NFC-compliant PCD
would not request higher data rates, thus, no interoperability issues are expected.
The NFC Forum Type 4B Tag Platform and ISO/IEC 14443B command and response structure is detailed
in ISO/IEC 14443-3, ISO/IEC 14443-4, and NFC Forum-TS-Digital Protocol. The applicable ISO/IEC 78164 commands are detailed in NFC Forum-TS-Type-4-Tag_2.0.
5.7.1
ISO/IEC 14443-3 Commands
These commands use the character, frame format, and timing that are described in ISO/IEC 14443-3,
clause 7.1. The following commands are used to manage communication:
REQB and WUPB
The REQB and WUPB commands sent by the PCD are used to probe the field for PICCs of Type B. In
addition, WUPB is used to wake up PICCs that are in the HALT state. The number of slots N is
included in the command as a parameter to optimize the anticollision algorithm for a given application.
Slot-MARKER
After a REQB or WUPB command, the PCD may send up to (N – 1) Slot-MARKER commands to
define the start of each timeslot. Slot-MARKER commands can be sent after the end of an ATQB
message received by the PCD to mark the start of the next slot or earlier if no ATQB is received (no
need to wait until the end of a slot, if this slot is known to be empty).
ATTRIB
The ATTRIB command sent by the PCD includes information required to select a single PICC. A PICC
receiving an ATTRIB command with its identifier becomes selected and assigned to a dedicated
channel. After being selected, this PICC only responds to commands defined in ISO/IEC 14443-4 that
include its unique CID.
HLTB
The HLTB command is used to set a PICC in HALT state and stop responding to a REQB.
After answering to this command, the PICC ignores any commands except the WUPB.
5.7.2
NFC Tag Type 4 Commands
Select
Selection of applications or files
Read Binary
Read data from file
Update Binary
Update (erase and write) data to file
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5.7.3
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Data Rate Settings
The device supports data rates of 106, 212, 424, and 848 kbps.
The device always answers ATTRIB commands from the PCD that request higher data rates. The NFC
Forum specifies for NFC-B a maximum data rate of 106 kbps. It is assumed that an NFC-compliant PCD
would not request higher data rates, thus, no interoperability issues are expected.
Even though all data rates up to 848 kbps are supported, the device by default reports only the capability
to support 106 kbps to the PCD.
To change this behavior, follow these steps using the I2C serial interface:
1. If you do not want to support all data rates up to 848 kbps, change the Data Rate Capability byte
according to Table 5-7. Table 5-6 summarizes how to write the data rate, and the Data Rate Capability
byte is set by the DATA 0 value in Step 3. Write Access.
2. Do the steps of the selected sequence. It is important to execute this sequence (in Table 5-6) before
setting the Control register.
NOTE
The General Control register (see Section 5.11.1) is set to 0 after the sequence is completed
in Table 5-6.
Table 5-6. Data Rate Setting Sequence
(1)
ACCESS TYPE
ADDRESS BITS
15 TO 8
ADDRESS BITS
7 TO 0
DATA 0
DATA 1
1. Write Access
0xFF
0xE0
0x4E
0x00
2. Write Access
0xFF
0xFE
0x80
0x00
3. Write Access
0x2A
0xBA
4. Write Access
0x27
0xB8
0x00
0x00
5. Write Access
0xFF
0xE0
0x00
0x00
0xF7
(1)
0x00
Data Rate Capability according to Table 5-7. 0xF7: all data rates up to 848 kbps are supported.
Table 5-7. Data Rate Capability
DATA RATA CAPABILITY BYTE
18
DESCRIPTION
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
PICC supports only 106 kbps in both directions (default).
1
x
x
x
0
x
x
x
Same data rate from PCD to PICC and from PICC to PCD compulsory
x
x
x
1
0
x
x
x
PICC to PCD, data rate supported is 212 kbps
x
x
1
x
0
x
x
x
PICC to PCD, data rate supported is 424 kbps
x
1
x
x
0
x
x
x
PICC to PCD, data rate supported is 848 kbps
x
x
x
x
0
x
x
1
PCD to PICC, data rate supported is 212 kbps
x
x
x
x
0
x
1
x
PCD to PICC, data rate supported is 424 kbps
x
x
x
x
0
1
x
x
PCD to PICC, data rate supported is 848 kbps
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5.8
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NDEF Structure
The NDEF message in its entirety is not stored at any time on the PICC. The host controller writes to the
buffer memory as the NFC Type 4 requests come in.
Table 5-8 shows the mandatory structure. This NDEF message would be present on the memory of the
host controller. For more information, refer to the NFC Forum Type 4 Tag Operation Specification (see
Section 6.2).
Table 5-8. NDEF Application Data
2B - CCLen
1B - Mapping version
2B - MLe = 000F9h
(1)
(2)
2B - MLc = 000F6h
NDEF Application
Selectable by Name =
D2760000850101h
Capability Container
Selectable by
File ID = E103h
1B - Tag = 04h
1B - Len = 06h
2B - File Identifier
NDEF File Ctrl TLV
6B - Val
2B - Maximum file size
The NDEF file
control TLV is
mandatory
1B - Read access
1B - Write access
NDEF File
Selectable by
File ID = xxyyh
(1)
(2)
2B - Len
xB - Binary NDEF file content
Mandatory NDEF
file
yB - Unused if Len < Maximum file size in File Ctrl TLV
RF430CL331H only supports mapping version up to 2.0.
RF430CL331H specific
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Table 5-9. NDEF Application Data (Includes Proprietary Sections)
2B - CCLen
1B - Mapping version
2B -MLe = 000F9h
(2)
2B -MLc = 000F6h
(2)
(1)
1B - Tag = 04h
1B - Len = 06h
2B - File Identifier
NDEF File Ctrl TLV
6B - Val
2B - Maximum file size
The NDEF file
control TLV is
mandatory
1B - Read access
1B - Write access
Capability Container
Selectable by
File ID = E103h
1B - Tag = 05h
1B - Len = 06h
2B - File Identifier
Proprietary File Ctrl
TLV (1)
6B - Val
2B - Maximum file size
1B - Read access
1B - Write access
NDEF Application
Selectable by Name =
D2_7600_0085_0101h
⋮
1B - Tag = 05h
Zero or more
proprietary file
control TLVs
1B - Len = 06h
2B - File Identifier
Proprietary File Ctrl
TLV (N)
6B - Val
2B - Maximum file size
1B - Read access
1B - Write access
NDEF File
Selectable by
File ID = xxyyh
Proprietary File (1)
Selectable by
File ID = xxyyh
2B - Len
Mandatory NDEF
file
xB - Binary NDEF file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
2B - Len
Optional
proprietary file
xB - Binary proprietary file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
⋮
Proprietary File (N)
Selectable by
File ID = xxyyh
(1)
(2)
20
2B - Len
Optional
proprietary file
xB - Binary proprietary file content
yB - Unused if Len < Maximum file size in File Ctrl TLV
RF430CL331H only supports mapping version up to 2.0.
RF430CL331H specific
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Typical Operation
Figure 5-6 shows typical operation of this device. Generally, on power up or reset, the host controller
initializes this device and then enables the RF. When a PCD approaches the dynamic tag, it starts by
performing the ISO14443-B anticollision sequence. This portion is handled automatically by the
RF430CL331H.
Eventually the sequence reaches the NFC Type 4 level. When the PCD issues a file select, Read Binary
or Update Binary commands, the RF430CL331H interrupts the host controller by asserting the INT0 pin to
request the necessary information or act on the information. Each type of interrupt request is detailed in
the following sections.
PCD/Mobile
PICC/Dynamic Tag
Host Controller
Enables RF field
ISO/IEC 14443B Layer 3
RF
Handled
automatically
RF
NDEF tag application
select
RF
Handled
automatically
RF
Yes
Select file?
Sets up registers for
host controller
RF
Interrupt, Then I2C
Responds based
on existence of
file
No
Deselect
command sent
RF
Turn off RF field
Sets up Layer 4
response
I2C
RF
No
Yes
Read or write
needed?
RF
Sets up the Layer 4
read or write request
by configuring
registers or the buffer
Interrupt, Then I2C
Services the
Layer 4 read or
write request
Formats response
into Type 4 format
Figure 5-6. High-Level Flow
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NDEF or Capability Container Select Procedure
This select procedure does not change between selection of the capability container or an NDEF file.
These two types of selects can be differentiated by the file identifier that the RF430CL331H reports in the
NDEF File Identifier register (see Section 5.11.7).
For the general flow, see Figure 5-7.
Reader (PCD)
Dynamic NFC Tag
(PICC)
PCD sends the Select File
request with a file identifier
RF
Configures the
registers to
describe the
request and then
asserts the
interrupt
INTO
Interrupt
Reads the file ID
from the registers
Does the file
exist?
RF
Examines the
response and
converts it to a
Type 4 protocol
format and sends
it to the PCD
I2C
Sets the Host
Response register
accordingly
Yes/No
Decides whether to
proceed with reading or
writing
Host Controller
Figure 5-7. Select System Flow
The procedure:
1. PCD procedure:
(a) Issues a Capability Container or a NDEF File Select command.
2. RF430CL331H procedure:
(a) Receives the RF packet.
(b) Sets the NDEF File Identifier register (see Section 5.11.7) using the file identifier that was included
in the packet from the PCD.
(c) Sets up the Status register (see Section 5.11.2) and the interrupt registers (see Section 5.11.3) to
describe the file select request.
(d) Ensure that General Type 4 request interrupt is enabled to generate the required interrupt on the
INTO pin.
3. Host controller procedure:
(a) Interrupt is received.
(b) Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
(c) The source of the interrupt is the General Type 4 request.
(d) When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read
and the Type 4 Command field examined to determine what Type 4 command has been received.
(e) The result is a File Select command.
(f) The NDEF File Identifier register (see Section 5.11.7) should be read.
(g) The host controller should, search its available files and determine if the file exists.
(h) The interrupt must be cleared by writing to the Interrupt Flag register (see Section 5.11.3). This
step must be done before setting the Interrupt Serviced field in the Host Response register (see
Section 5.11.8).
(i) If a specific Status Word (SW) response is necessary (generally for communicating specific error
conditions) to the Select command:
(i) Set the Custom Status Word Response register (see Section 5.11.13) with the desired status
word.
(ii) Set the Use Custom SW Response bit in the Host Response register (see Section 5.11.8).
(j) To complete servicing the Select command interrupt, set the Interrupt Serviced field in the Host
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Response register (see Section 5.11.8).
Servicing of the Select command is complete.
4. RF430CL331H procedure:
(a) If the custom Status Words (SW) feature was not used:
(i) If the host controller indicated that the file existed, the response to the PCD is SW1 = 90h and
SW2 = 00h.
(ii) If the host controller indicated that the file did not exist, the response to the PCD is SW1 = 6Ah
and SW2 = 82h.
(b) If the custom response feature was used, the response to the PCD is what was set in the Custom
Status Word Response register (see Section 5.11.13).
5.9.2
NDEF or Capability Container Read Binary Procedure
This read procedure does not change between when the PCD reads the Capability Container or an NDEF
file. These two types of reads can be differentiated by the file identifier that the RF430CL331H reports in
the NDEF File Identifier register (see Section 5.11.7).
For the general flow, see Figure 5-8.
Reader (PCD)
ReadBinary command is
sent
RF430CL331H (PICC)
RF
If necessary
PCD processes the data
and possibly repeats the
cycle
Is the data
already
available?
Host Controller
No/Interrupt
INTO
Responds with the
data over the
serial bus
Yes
RF
Sends the data
using ISO14443-B
protocol
I2C
Figure 5-8. Read System Flow
The procedure:
1. PCD procedure:
(a) Issues a Capability Container or a NDEF Read Binary command.
2. RF430CL331H procedure:
(a) Receives the RF packet.
(b) Checks its buffer and determines if all of the requested data in the Read Binary command exists
already in the buffer.
(c) If all the data is available in the buffer then (in the case that extra data was written in a previous
read request):
(i) No interrupt is issued to the host controller.
(ii) The data is supplied in the response packet to the PCD automatically.
(iii) The status word response SW1 = 90h and SW2 = 00h is appended to the packet.
(iv) The flow returns to wait for the next Type 4 request.
(d) If no data or only partial data is available, then an interrupt is issued to the host controller.
3. Host controller procedure:
(a) An interrupt is received.
(b) Checks the source of the interrupt by reading the interrupt registers (see Section 5.11.3).
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(c) The source of the interrupt is the General Type 4 request.
(d) When there is a General Type 4 request, the Status register (see Section 5.11.2) must be read
and the Type 4 Command field examined to determine what Type 4 command has been received.
(e) The result is a Read Binary command.
(f) The NDEF File Identifier register (see Section 5.11.7) may be read, but it is not necessary as it is
always the file that the last Select command selected.
(g) Read the Buffer Start register (see Section 5.11.11) to determine where in the buffer of the
RF430CL331H to begin storing the data.
(h) Read the NDEF File Offset register (see Section 5.11.10) to determine at which index in the NDEF
or CC file to begin supplying the data to the RF430CL331H.
(i) Read the NDEF Block Length register (see Section 5.11.9) to determine what block length the
PCD is requesting.
(j) Check if the request is valid:
(i) If it is valid, write the data into the buffer of the RF430CL331H starting at Buffer Start index for
NDEF Block Length bytes.
(ii) If it is not valid, assert the Custom Status Word option in the Host Response register (see
Section 5.11.8) and write the custom word in the Custom Status Word Response register (see
Section 5.11.13). Only the status word response supplied will be sent out.
(k) If caching is desirable, extra sequential data can be written to the RF430CL331H buffer, up to the
maximum RF430CL331H buffer length (length is 3000 bytes, highest index is 2999).
NOTE
To improve the Read Binary performance of the RF430CL331H , a caching feature may
be used. After writing the requested Read Binary request data into the RF430CL331H
buffer, extra sequential data may be written. If on the next Read Binary request, all of the
requested data is in the buffer, the RF430CL331H automatically responds and services
that request without any intervention of the host controller; that is, no interrupt is issued.
(l) Update the NDEF Block Length register (see Section 5.11.9) with the number of bytes written into
the buffer.
(m) The interrupt must be cleared by writing to the Interrupt Flag register. This step must be done
before setting the Interrupt Serviced field in the Host Response register.
(n) To complete servicing the Read Binary command interrupt, set the Interrupt Serviced field in the
Host Response register.
4. RF430CL331H procedure:
(a) Only the requested data (even if extra was supplied) is included in the response packet to the
PCD. The status words are appended to the response packet per NFC Type 4 specification.
(b) If the command was valid, the status words are SW1 = 90h and SW2 = 00h.
(c) If the custom response feature was used, the response to the PCD is only what was set in the
Custom Status Word Response register.
5.9.2.1
NDEF Read Command Internal Buffer Handling
Entire Buffer Space (not to scale)
1. PCD ± ReadBinary Request
N (
