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RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
RM44Lx20 16- and 32-Bit RISC Flash Microcontroller
1 Device Overview
1.1
Features
1
• High-Performance Microcontroller (MCU) for
Safety-Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
– Built-In Self-Test (BIST) for CPU and On-chip
RAMs
– Error Signaling Module With Error Pin
– Voltage and Clock Monitoring
• ARM® Cortex®-R4F 32-Bit RISC CPU
– 1.66 DMIPS/MHz With 8-Stage Pipeline
– FPU With Single and Double Precision
– 12-Region Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Conditions
– Up to 180-MHz System Clock
– Core Supply Voltage (VCC): 1.14 to 1.32 V
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
• Integrated Memory
– Up to 1MB of Flash With ECC
– 128KB of RAM With ECC
– 64KB of Flash for Emulated EEPROM With
ECC
• Common Platform Architecture
– Consistent Memory Map Across Family
– Real-Time Interrupt Timer (RTI) OS Timer
– 128-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Peripheral Requests
– Parity for Control Packet RAM
– DMA Accesses Protected by Dedicated MPU
• Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight™ Components
• Advanced JTAG Security Module (AJSM)
• Up to 64 General-Purpose I/O (GIO) Pins
– Up to 16 GIO Pins With Interrupt Generation
Capability
• Enhanced Timing Peripherals
– 7 Enhanced Pulse Width Modulator (ePWM)
Modules
– 6 Enhanced Capture (eCAP) Modules
– 2 Enhanced Quadrature Encoder Pulse (eQEP)
Modules
• Two Next Generation High-End Timer (N2HET)
Modules
– N2HET1: 32 Programmable Channels
– N2HET2: 18 Programmable Channels
– 160-Word Instruction RAM With Parity
Protection Each
– Each N2HET Includes Hardware Angle
Generator
– Dedicated High-End Timer Transfer Unit (HTU)
for Each N2HET
• Two 12-Bit Multibuffered ADC Modules
– ADC1: 24 Channels
– ADC2: 16 Channels
– 16 Shared Channels
– 64 Result Buffers With Parity Protection Each
• Multiple Communication Interfaces
– Up to Three CAN Controllers (DCANs)
– 64 Mailboxes With Parity Protection Each
– Compliant to CAN Protocol Version 2.0A and
2.0B
– Inter-Integrated Circuit (I2C)
– 3 Multibuffered Serial Peripheral Interfaces
(MibSPIs)
– 128 Words With Parity Protection Each
– 8 Transfer Groups
– One Standard Serial Peripheral Interface (SPI)
Module
– Two UART (SCI) Interfaces, One With Local
Interconnect Network (LIN 2.1) Interface
Support
• Packages
– 144-Pin Quad Flatpack (PGE) [Green]
– 100-Pin Quad Flatpack (PZ) [Green]
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
1.2
•
2
www.ti.com
Applications
Industrial Safety Applications
– Industrial Automation
– Safe Programmable Logic Controllers (PLCs)
– Power Generation and Distribution
– Turbines and Windmills
– Elevators and Escalators
Device Overview
•
Medical Applications
– Ventilators
– Defibrillators
– Infusion and Insulin Pumps
– Radiation Therapy
– Robotic Surgery
Copyright © 2014–2016, Texas Instruments Incorporated
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1.3
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Description
The RM44Lx20 device is part of the Hercules RM series of high-performance industrial-grade ARM®
Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to assist in the
development of IEC 61508 functional safety applications. Start evaluating today with the Hercules RM
LaunchPad Development Kit. The RM44Lx20 device has on-chip diagnostic features including: dual CPUs
in lockstep; CPU and memory Built-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parity
on peripheral memories; and loopback capability on most peripheral I/Os.
The RM44Lx20 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66
DMIPS/MHz, and has configurations which can run up to 180 MHz providing up to 298 DMIPS. The
RM44Lx20 device supports the little-endian [LE] format.
The RM44Lx20 device has up to 1MB of integrated flash and 128KB of RAM configurations with single-bit
error correction and double-bit error detection. The flash memory on this device is nonvolatile, electrically
erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The flash operates
on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase operations. The
SRAM supports single-cycle read and write accesses in byte, halfword, word, and doubleword modes
throughout the supported frequency range.
The RM44Lx20 device features peripherals for real-time control-based applications, including two NextGeneration High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven
Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two
Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters
(ADCs) supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,
capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for
applications requiring multiple sensor information and drive actuators with complex and accurate time
pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A
Memory Protection Unit (MPU) is built into the HTU.
The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or
intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation.
With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for
digital motor control applications.
The eCAP module is essential in systems where the accurately timed capture of external events is
important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when
not needed for capture applications.
The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position,
direction, and speed information from a rotating machine as used in high-performance motion and
position-control systems.
The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer
RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three
separate groups. Each group can be converted once when triggered or configured for continuous
conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster
conversion time is desired.
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Device Overview
3
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
www.ti.com
The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can
be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial
interaction for high-speed communications between similar shift-register type devices. The LIN supports
the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard
Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh
environments (for example, automotive and industrial fields) that require reliable serial communication or
multiplexed wiring.
The I2C module is a multimaster communication module providing an interface between the
microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds
of 100 and 400 kbps.
A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible
clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the
available clock sources and the device clock domains.
The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous
external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of
the device operating frequency.
The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests,
and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous
transfers.
The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external
error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored
externally as an indicator of a fault condition in the microcontroller.
With integrated functional safety features and a wide choice of communication and control peripherals, the
RM44Lx20 device is an ideal solution for high-performance, real-time control applications with safetycritical requirements.
Device Information (1)
PACKAGE
BODY SIZE
RM44L920PGE
PART NUMBER
LQFP (144)
20.0 mm × 20.0 mm
RM44L920PZ
LQFP (100)
14.0 mm × 14.0 mm
RM44L520PGE
LQFP (144)
20.0 mm × 20.0 mm
RM44L520PZ
LQFP (100)
14.0 mm × 14.0 mm
(1)
4
For more information, see Section 10, Mechanical Packaging and Orderable Information.
Device Overview
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1.4
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
NOTE: The block diagram reflects the 144PGE package. Some functions are multiplexed or not available
in other packages. For details, see the respective terminal functions table in Section 4.2, Terminal
Functions.
128KB RAM
with ECC
32K
32K
32K
32K
1MB(A)
Flash
with ECC
DMA
Dual Cortex-R4F
CPUs in Lockstep
HTU1
HTU2
Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
CRC
Peripheral Central Resource Bridge
Switched Central Resource
eQEPxA
eQEPxB
eQEPxS
eQEPxI
eQEP
1,2
64KB Flash
for EEPROM
Emulation
with ECC
eCAP
1..6
ESM
nERROR
PMM
DCAN1
eCAP[6:1]
nTZ[3:1]
SYNCO
SYNCI
ePWMxA
ePWMxB
ePWM
1..7
DCAN2
DCAN3
RTI
Color Legend for Power Domains
always on
nPORRST
nRST
ECLK
IOMM
VIM
Core/RAM
SYS
MibSPI1
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
DCC1
SPI2
DCC2
MibSPI3
RAM
Core
#1
#1
#3
#5
SPI4
A
B.
I2C_SCL
I2C
I2C_SDA
GIOB[7:0]
GIO
GIOA[7:0]
N2HET2_PIN_nDIS
N2HET2[15:0]
N2HET2[18,16]
N2HET1[31:0]
N2HET1_PIN_nDIS
AD1IN[23:16] \
AD2IN[7:0]
AD2EVT
VCCAD
VSSAD
ADREFHI
ADREFLO
MibADC2 N2HET1 N2HET2
AD1IN[15:8] \
AD2IN[15:8]
AD1EVT
AD1IN[7:0]
MibADC1
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MibSPI5
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
SPI2_nCS[1:0]
SPI2_nENA
MIBSPI3_CLK
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
SPI4_CLK
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
LIN
LIN_RX
LIN_TX
SCI
SCI_RX
SCI_TX
The RM44L520 device only supports 768KB Flash with ECC.
Denotes superset device, Not all peripherals are supported on all devices or all packages, see the Device Comparison table.
Figure 1-1. Functional Block Diagram(B)
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Device Overview
5
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
Device Overview ......................................... 1
6.15
DMA Controller ...................................... 76
1.1
Features .............................................. 1
6.16
Real-Time Interrupt Module ......................... 78
1.2
Applications ........................................... 2
6.17
Error Signaling Module .............................. 80
1.3
Description ............................................ 3
6.18
Reset/Abort/Error Sources .......................... 84
1.4
Functional Block Diagram ............................ 5
6.19
Digital Windowed Watchdog ........................ 87
2
3
Revision History ......................................... 7
Device Comparison ..................................... 8
6.20
Debug Subsystem ................................... 88
4
Terminal Configuration and Functions .............. 9
7.1
I/O Timings
Pin Diagrams ......................................... 9
7.2
Enhanced PWM Modules (ePWM) .................. 96
11
7.3
Enhanced Capture Modules (eCAP) ............... 102
29
7.4
7.5
Enhanced Quadrature Encoder (eQEP) ........... 105
12-Bit Multibuffered Analog-to-Digital Converter
(MibADC)........................................... 108
7.6
General-Purpose Input/Output ..................... 121
7.7
Enhanced High-End Timer (N2HET)
7.8
Controller Area Network (DCAN) .................. 126
1
Related Products ..................................... 8
3.1
4.1
.................................
4.3
Pin Multiplexing......................................
4.4
Buffer Type ..........................................
Specifications ..........................................
5.1
Absolute Maximum Ratings .........................
5.2
ESD Ratings ........................................
5.3
Power-On Hours (POH) .............................
5.4
Recommended Operating Conditions ...............
4.2
5
Signal Descriptions
5.5
36
36
36
37
5.7
Thermal Resistance Characteristics ................ 40
5.8
Timing and Switching Characteristics ............... 41
System Information and Electrical
Specifications ........................................... 43
Peripheral Information and Electrical
Specifications ........................................... 93
.........................................
..............
93
122
7.9
Local Interconnect Network Interface (LIN) ........ 127
7.10
Serial Communication Interface (SCI) ............. 128
7.11
7.12
Inter-Integrated Circuit (I2C) Module .............. 129
Multibuffered / Standard Serial Peripheral
Interface ............................................ 132
8
Applications, Implementation, and Layout ...... 144
9
Device and Documentation Support .............. 145
8.1
TI Designs or Reference Designs
.................
144
9.1
9.2
Getting Started and Next Steps ................... 145
Device and Development-Support Tool
Nomenclature ...................................... 145
Power Sequencing and Power-On Reset ........... 44
9.3
Tools and Software
6.4
Warm Reset (nRST)................................. 46
9.4
Documentation Support ............................ 149
6.5
.................
Clocks ...............................................
Clock Monitoring ....................................
Glitch Filters .........................................
Device Memory Map ................................
Flash Memory .......................................
Tightly Coupled RAM Interface Module .............
47
9.5
Related Links
51
9.6
Community Resources............................. 149
58
9.7
Trademarks ........................................ 150
60
9.8
Electrostatic Discharge Caution
61
9.9
Glossary............................................ 150
66
9.10
Device Identification................................ 151
69
9.11
Module Certifications............................... 152
6.1
Device Power Domains ............................. 43
6.2
Voltage Monitor Characteristics ..................... 43
6.3
ARM Cortex-R4F CPU Information
6.6
6.7
6.8
6.9
6.10
6.11
6.12
Parity Protection for Accesses to Peripheral RAMs
69
6.13
On-Chip SRAM Initialization and Testing
...........
Vectored Interrupt Manager .........................
71
6.14
6
35
36
Input/Output Electrical Characteristics Over
Recommended Operating Conditions ............... 38
Power Consumption Over Recommended
Operating Conditions ................................ 39
5.6
6
7
Table of Contents
73
................................
......................................
...................
147
149
150
10 Mechanical Packaging and Orderable
Information ............................................. 157
10.1
Packaging Information ............................. 157
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SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the SPNS229B device-specific
data manual to make it an SPNS229C revision.
Scope: Applicable updates to the RM44Lx20 device family, specifically relating to the RM44L920 and
RM44L520 devices (Silicon Revision A), which are now in the production data (PD) stage of development
have been incorporated.
Changes from October 31, 2015 to November 1, 2016 (from B Revision (October 2015) to C Revision)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Page
GLOBAL: PZ package is now fully qualified ...................................................................................... 1
Section 1.1 (Features): Updated/Changed the GIO pin count in GIO bullet .................................................. 1
Section 1.1: Updated/Changed the SPI features bullet .......................................................................... 1
Section 3.1 (Related Products): Added new section. ............................................................................ 8
Section 4.2 (Signal Descriptions): Updated/Changed reference to Technical Reference Manual ....................... 11
Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Added a description for pins 14 and 55
(N2HET1_PIN_nDIS and N2HET2_PIN_nDIS, respectively). ................................................................. 13
Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Added Pin 10, GIOA[5] / INT[5] / EXTCLKIN
/EPWM1A/N2HET1_PIN_nDIS.................................................................................................... 22
Table 6-20 (Device Memory Map): Updated/Changed the ACTUAL SIZE column value for "Flash Data Space
ECC" under Flash Module Bus2 Interface from "160KB" to "128KB". ....................................................... 62
Section 6.19 (Digital Windowed Watchdog): Added Figure 6-13, Digital Windowed Watchdog Example............... 87
Table 7-11 (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in MODULE INSTANCE
column............................................................................................................................... 103
Table 7-15 (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in MODULE INSTANCE
column............................................................................................................................... 106
Table 7-20 (MibADC1 Trigger Event Hookup): Added lead-in paragraph referencing the table ........................ 108
Table 7-21 (MibADC2 Event Trigger Hookup): Added lead-in paragraph referencing the table ........................ 110
Figure 7-11 (ePWM1SOC1A Switch Implementation): Added missing ePWM1 SOC1A detailed switch
connection example and lead-in reference sentence ......................................................................... 114
Section 9.1 (Getting Started and Next Steps): Added new section ......................................................... 145
Section 9.2 (Device and Development-Support Tool Nomenclature): Moved subsection after "Getting Started
and Next Steps" subsection (new) .............................................................................................. 145
Section 9.10.1 Added the address of the Device ID register. ................................................................ 151
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Revision History
7
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
www.ti.com
3 Device Comparison
Table 3-1 lists the features of the RM44Lx20 devices.
Table 3-1. RM44Lx20 Device Comparison (1)
FEATURES
Generic Part
Number
Package
CPU
DEVICES
RM46L852ZWT
RM46L852PGE
RM44L920PGE
RM44L920PZ
RM44L520PGE
RM44L520PZ
337 BGA
144 QFP
144 QFP
100 QFP
144 QFP
100 QFP
RM42L432PZ
100 QFP
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4F
ARM Cortex-R4
Frequency (MHz)
220
220
180
120
180
120
100
Flash (KB)
1280
1280
1024
1024
768
768
384
RAM (KB)
192
192
128
128
128
128
32
Data Flash
[EEPROM] (KB)
64
64
64
64
64
64
16
2+0 or 1+1
2+0 or 1+1
–
–
–
–
–
10/100
10/100
–
–
–
–
–
FlexRay
–
–
–
–
–
–
–
CAN
3
3
3
2
3
2
2
2 x (24ch)
2 x (24ch)
2 x (24ch)
2 x (16ch)
2 x (24ch)
2 x (16ch)
1 x (16ch)
2 (44)
2 (40)
2 (40)
2 (21)
2 (40)
2 (21)
1 (19)
ePWM Channels
14
14
14
8
14
8
–
eCAP Channels
6
6
6
4
6
4
–
eQEP Channels
2
2
2
1
2
1
2
3 (6 + 6 + 4)
3 (5 + 6 + 1)
3 (5 + 6 + 1)
2 (4 + 2)
3 (5 + 6 + 1)
2 (4 + 2)
1 (4)
USB OHCI +
Device
EMAC
MibADC
12-bit (Ch)
N2HET (Ch)
MibSPI (CS)
SPI (CS)
2 (2 + 1)
1 (1)
1 (1)
1 (1)
1 (1)
1 (1)
2 (4 + 4)
SCI (LIN)
2 (1 with LIN)
2 (1 with LIN)
2 (1 with LIN)
1(with LIN)
2 (1 with LIN)
1(with LIN)
1(with LIN)
I2C
GPIO (INT)
EMIF
1
1
1
–
1
–
–
101 (with 16 interrupt
capable)
64 (with 10 interrupt
capable)
64 (with 16 interrupt
capable)
45 (with 9 interrupt
capable)
64 (with 16 interrupt
capable)
45 (with 9 interrupt
capable)
45 (with 8 interrupt
capable)
16-bit data
–
–
–
–
–
–
ETM [Trace] (Data)
–
–
–
–
–
–
–
RTP/DMM (Data)
–
–
–
–
–
–
–
Operating
Temperature
-40ºC to 105ºC
-40ºC to 105ºC
-40ºC to 105ºC
-40ºC to 105ºC
-40ºC to 105ºC
-40ºC to 105ºC
-40ºC to 105ºC
Core Supply (V)
1.14 V – 1.32 V
1.14 V – 1.32 V
1.14 V – 1.32 V
1.14 V – 1.32 V
1.14 V – 1.32 V
1.14 V – 1.32 V
1.14 V – 1.32 V
3.0 V – 3.6 V
3.0 V – 3.6 V
3.0 V – 3.6 V
3.0 V – 3.6 V
3.0 V – 3.6 V
3.0 V – 3.6 V
3.0 V – 3.6 V
I/O Supply (V)
(1)
3.1
Bolding denotes a superset device. For additional device variants, see www.ti.com/rm
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for RM 16-Bit and 32-Bit MCUs
An expansive portfolio of software and pin-compatible high-performance ARM® Cortex®-R-based MCU
products from 80 MHz up to 300 MHz with on-chip features that prove a high level of diagnostic coverage,
as well as provide scalability to address a wide range of applications.
Companion Products for RM44L920/RM44L520
Review products that are frequently purchased or used with this product.
8
Device Comparison
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SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
4 Terminal Configuration and Functions
4.1
Pin Diagrams
PGE QFP Package Pinout (144-Pin)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TMS
N2HET1[28]
N2HET1[08]
MIBSPI1NCS[0]
VCCIO
VSS
VSS
VCC
MIBSPI5CLK
MIBSPI5SIMO[0]
MIBSPI5SOMI[0]
MIBSPI5NENA
MIBSPI1NENA
MIBSPI1CLK
MIBSPI1SOMI
MIBSPI1SIMO
N2HET1[26]
N2HET1[24]
CAN1RX
CAN1TX
VSS
VCC
AD1EVT
AD1IN[15] / AD2IN[15]
AD1IN[23] / AD2IN[07]
AD1IN[08] / AD2IN[08]
AD1IN[14] / AD2IN[14]
AD1IN[22] / AD2IN[06]
AD1IN[06]
AD1IN[13] / AD2IN[13]
AD1IN[05]
AD1IN[12] / AD2IN[12]
AD1IN[04]
AD1IN[11] / AD2IN[11]
AD1IN[03]
AD1IN[02]
4.1.1
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
AD1IN[10] / AD2IN[10]
AD1IN[01]
AD1IN[09] / AD2IN[09]
VCCAD
VSSAD
ADREFLO
ADREFHI
AD1IN[21] / AD2IN[05]
AD1IN[20] / AD2IN[04]
AD1IN[19] / AD2IN[03]
AD1IN[18] / AD2IN[02]
AD1IN[07]
AD1IN[0]
AD1IN[17] / AD2IN[01]
AD1IN[16] / AD2IN[0]
VCC
VSS
MIBSPI3NCS[0]
MIBSPI3NENA
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
VSS
VCC
VCC
VSS
nPORRST
VCC
VSS
VSS
VCCIO
N2HET1[15]
MIBSPI1NCS[2]
N2HET1[13]
N2HET1[06]
MIBSPI3NCS[1]
GIOB[3]
GIOA[0]
MIBSPI3NCS[3]
MIBSPI3NCS[2]
GIOA[1]
N2HET1[11]
FLTP1
FLTP2
GIOA[2]
VCCIO
VSS
CAN3RX
CAN3TX
GIOA[5]
N2HET1[22]
GIOA[6]
VCC
OSCIN
Kelvin_GND
OSCOUT
VSS
GIOA[7]
N2HET1[01]
N2HET1[03]
N2HET1[0]
VCCIO
VSS
VSS
VCC
N2HET1[02]
N2HET1[05]
MIBSPI5NCS[0]
N2HET1[07]
TEST
N2HET1[09]
N2HET1[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
nTRST
TDI
TDO
TCK
RTCK
VCC
VSS
nRST
nERROR
N2HET1[10]
ECLK
VCCIO
VSS
VSS
VCC
N2HET1[12]
N2HET1[14]
GIOB[0]
N2HET1[30]
CAN2TX
CAN2RX
MIBSPI1NCS[1]
LINRX
LINTX
GIOB[1]
VCCP
VSS
VCCIO
VCC
VSS
N2HET1[16]
N2HET1[18]
N2HET1[20]
GIOB[2]
VCC
VSS
A.
Pins can have multiplexed functions. Only the default function is shown in Figure 4-1.
Figure 4-1. PGE QFP Package Pinout (144-Pin)
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9
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
51
52
54
53
55
56
57
58
59
62
61
60
63
64
65
66
67
68
69
70
71
72
75
74
50
76
49
77
48
47
78
79
46
80
45
81
44
82
43
42
83
84
41
85
40
86
39
87
38
88
37
89
36
90
35
91
34
92
33
93
32
94
31
95
30
96
29
97
28
98
27
99
26
AD1IN[10]
AD1IN[1]
AD1IN[9]
VSSAD/ADREFLO
VCCAD/ADREFHI
AD1IN[21]
AD1IN[20]
AD1IN[7]
AD1IN[0]
AD1IN[17]
AD1IN[16]
MIBSPI1nCS[3]
MIBSPI3nCS[0]
MIBSPI3nENA
MIBSPI3CLK
MIBSPI3SIMO
MIBSPI3SOMI
VSS
VCC
nPORRST
VCC
VSS
VCCIO
MIBSPI1nCS[2]
N2HET1[6]
25
24
22
23
21
19
20
18
16
17
15
14
13
12
11
10
9
8
6
7
5
4
3
GIOA[0]/IN T[0]
GIOA[1]/IN T[1]
FLTP1
FLTP2
GIOA[2]/INT[2]
VCCIO
VSS
GIOA[3]/INT[3]
GIOA[4]/INT[4]
GIOA[5]/INT[5]
N2HET1[22]
GIOA[6]/INT[6]
VC C
OSCIN
KELVIN_GN D
OSCOUT
VSS
GIOA[7]/IN T[7]
N2HET1[0]
VSS
VC C
N2HET1[2]
SPI2nCS[0]
TEST
N2HET1[4]
2
100
1
nTRST
TDI
TDO
TCK
RTCK
nRST
nERROR
N2HET1[10]
ECLK
VCCIO
VSS
VSS
VCC
N2HET1[12]
N2HET1[14]
CAN2TX
CAN2RX
MIBSPI1nCS[1]
LINRX
LINTX
VCCP
N2HET1[16]
N2HET1[18]
VCC
VSS
VSS
SPI2CLK
SPI2SIMO
SPI2SOMI
MIBSPI1nENA
MIBSPI1C LK
MIBSPI1SOMI
MIBSPI1SIMO
N2HET1[24]
CAN1RX
CAN1T X
VCC
VCCIO
VSS
ADEVT
AD1IN[8]
AD1IN[6]
AD1IN[5]
AD1IN[4]
AD1IN[11]
AD1IN[3]
AD1IN[2]
PZ QFP Package Pinout (100-Pin)
TMS
N2HET1[8]
73 MIBSPI1nCS
4.1.2
www.ti.com
Figure 4-2. PZ QFP Package Pinout (100-Pin)
10
Terminal Configuration and Functions
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4.2
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Signal Descriptions
The signal descriptions section shows pin information in module function order per package.
Section 4.2.1 and Section 4.2.2 identify the external signal names, the associated pin or ball numbers
along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground),
whether the pin or ball has any internal pullup/pulldown, whether the pin or ball can be configured as a
GIO, and a functional pin or ball description. The first signal name listed is the primary function for that
terminal (pin or ball). The signal name in Bold is the function being described. For information on how to
select between different multiplexed functions, see Section 4.3, Pin Multiplexing or see the I/O Multiplexing
and Control Module (IOMM) chapter of the RM44Lx 16/32-Bit RISC Flash Microcontroller Technical
Reference Manual (SPNU608).
NOTE
All I/O signals except nRST are configured as inputs while nPORRST is low and immediately
after nPORRST goes high.
All output-only signals are configured as high impedance while nPORRST is low, and are
configured as outputs immediately after nPORRST goes high.
While nPORRST is low, the input buffers are disabled, and the output buffers are high
impedance.
In the Terminal Functions tables of Section 4.2.1 and Section 4.2.2, the RESET PULL
STATE is the state of the pullup or pulldown while nPORRST is low and immediately after
nPORRST goes high. The default pull direction may change when software configures the
pin for an alternate function. The PULL TYPE is the type of pull asserted when the signal
name in bold is enabled for the given terminal.
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11
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4.2.1
www.ti.com
PGE Package Terminal Functions
4.2.1.1
Multibuffered Analog-to-Digital Converters (MibADCs)
Table 4-1. PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
–
None
Description
ADREFHI (1)
66
Power
ADREFLO (1)
67
Power
ADC low reference supply
VCCAD (1)
69
Power
Operating supply for ADC
(1)
VSSAD
ADC high reference
supply
68
Ground
AD1EVT
86
I/O
Pulldown
Programmable,
20 µA
ADC1 event trigger input,
or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS
55
I/O
Pullup
Programmable,
20 µA
ADC2 event trigger input,
or GIO
AD1IN[0]
60
Input
–
None
ADC1 analog input
AD1IN[01]
71
AD1IN[02]
73
AD1IN[03]
74
AD1IN[04]
76
AD1IN[05]
78
AD1IN[06]
80
AD1IN[07]
61
AD1IN[08] / AD2IN[08]
83
Input
–
None
AD1IN[09] / AD2IN[09]
70
ADC1/ADC2 shared
analog inputs
AD1IN[10] / AD2IN[10]
72
AD1IN[11] / AD2IN[11]
75
AD1IN[12] / AD2IN[12]
77
AD1IN[13] / AD2IN[13]
79
AD1IN[14] / AD2IN[14]
82
AD1IN[15] / AD2IN[15]
85
AD1IN[16] / AD2IN[0]
58
AD1IN[17] / AD2IN[01]
59
AD1IN[18] / AD2IN[02]
62
AD1IN[19] / AD2IN[03]
63
AD1IN[20] / AD2IN[04]
64
AD1IN[21] / AD2IN[05]
65
AD1IN[22] / AD2IN[06]
81
AD1IN[23] / AD2IN[07]
84
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
51
Output
Pullup
–
AWM1 external analog
mux enable
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
52
Output
Pullup
–
AWM1 external analog
mux select line0
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
53
Output
Pullup
–
AWM1 external analog
mux select line0
(1)
12
The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
Terminal Configuration and Functions
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4.2.1.2
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Enhanced High-End Timer (N2HET) Modules
Table 4-2. PGE Enhanced High-End Timer (N2HET) Modules
TERMINAL
144
PGE
SIGNAL NAME
N2HET1[0]/SPI4CLK/EPWM2B
25
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A
23
N2HET1[02]/SPI4SIMO[0]/EPWM3A
30
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B
24
N2HET1[04]/EPWM4B
36
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
31
N2HET1[06]/SCIRX/EPWM5A
38
N2HET1[07]/N2HET2[14]/EPWM7B
33
N2HET1[08]/MIBSPI1SIMO[1]/
106
N2HET1[09]/N2HET2[16]/EPWM7A
35
N2HET1[10]/nTZ3
118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
N2HET1[12]
SIGNAL
TYPE
RESET
PULL
STATE
DESCRIPTION
PULL TYPE
Pulldown
6
124
N2HET1[13]/SCITX/EPWM5B
39
N2HET1[14]
125
N2HET1 timer input
capture
or
output
compare, or GIO.
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
41
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO
139
MIBSPI1NCS[1]/N2HET1[17]/EQEP1S
130
Pullup
N2HET1[18]/EPWM6A
140
Pulldown
MIBSPI1NCS[2]/N2HET1[19]
40
Pullup
N2HET1[20]/EPWM6B
141
N2HET1[22]
15
MIBSPI1NENA/N2HET1[23]/ECAP4
96
Pullup
N2HET1[24]/MIBSPI1NCS[5]
91
Pulldown
MIBSPI3NCS[1]/N2HET1[25]
37
Pullup
N2HET1[26]
92
Pulldown
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2
N2HET1[28]
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1
Programmable,
20 µA
I/O
Each terminal has a
suppression filter with a
programmable duration.
Pulldown
4
Pullup
107
Pulldown
3
Pullup
N2HET1[30]/EQEP2S
127
Pulldown
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
54
Pullup
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS
14
Pulldown
GIOA[2]/N2HET2[0]/EQEP2I
9
GIOA[6]/N2HET2[4]/EPWM1B
16
GIOA[7]/N2HET2[6]EPWM2A
22
N2HET1[01]/SPI4NENA//N2HET2[8]
23
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B
24
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EQEP3B
31
N2HET1[07]/N2HET2[14]/EPWM7B
33
N2HET1[09]/N2HET2[16]
35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
6
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1l/N2HET2_PIN_nDIS
55
Pulldown
I/O
Pullup
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Disable selected PWM
outputs
N2HET2 timer input
capture
or
output
compare, or GIO
Programmable,
20 µA
Each terminal has a
suppression filter with a
programmable duration.
Disable selected PWM
outputs
Terminal Configuration and Functions
13
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
4.2.1.3
www.ti.com
Enhanced Capture Modules (eCAP)
Table 4-3. PGE Enhanced Capture Modules (eCAP) (1)
TERMINAL
144
PGE
SIGNAL NAME
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
41
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
51
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
52
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
DESCRIPTION
Enhanced Capture Module 1
I/O
Pulldown
Enhanced Capture Module 2
I/O
I/O
Fixed, 20 µA
Enhanced Capture Module 4
I/O
MIBSPI1NENA/N2HET1[23]/ECAP4
96
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5
97
Enhanced Capture Module 5
I/O
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
105
Enhanced Capture Module 6
I/O
(1)
Pullup
Enhanced Capture Module 3
I/O
These signals, when used as inputs, are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
4.2.1.4
Enhanced Quadrature Encoder Pulse Modules (eQEP)
Table 4-4. PGE Enhanced Quadrature Encoder Pulse Modules (eQEP) (1)
TERMINAL
144
PGE
SIGNAL NAME
SIGNAL
TYPE
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
53
Input
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
54
Input
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS
55
I/O
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S
130
I/O
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A
23
Input
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B
24
Input
GIOA[2]/N2HET2[0]/EQEP2I
9
I/O
127
I/O
N2HET1[30]/EQEP2S
(1)
14
RESET
PULL
STATE
PULL TYPE
DESCRIPTION
Enhanced QEP1 Input A
Enhanced QEP1 Input B
Pullup
Enhanced QEP1 Index
Fixed, 20 µA
Pulldown
Enhanced QEP1 Strobe
Enhanced QEP2 Input A
Enhanced QEP2 Input B
Enhanced QEP2 Index
Enhanced QEP2 Strobe
These signals are double-synchronized and then optionally filtered with a 6-cycle VCLK4-based counter.
Terminal Configuration and Functions
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4.2.1.5
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Enhanced Pulse-Width Modulator Modules (ePWM)
Table 4-5. PGE Enhanced Pulse-Width Modulator Modules (ePWM)
TERMINAL
144
PGE
SIGNAL NAME
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS
14
GIOA[6]/N2HET2[4]/EPWM1B
16
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
6
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
DESCRIPTION
Enhanced PWM1 Output A
Output
Pulldown
–
Enhanced PWM1 Output B
External ePWM Sync Pulse
Output
Input
Pullup
139
GIOA[7]/N2HET2[6]/EPWM2A
22
N2HET1[0]/SPI4CLK/EPWM2B
25
N2HET1[02]/SPI4SIMO[0]/EPWM3A
30
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
31
MIBSPI5NCS[0]/EPWM4A
32
N2HET1[04]/EPWM4B
36
Enhanced PWM4 Output B
N2HET1[06]/SCIRX/EPWM5A
38
Enhanced PWM5 Output A
N2HET1[13]/SCITX/EPWM5B
39
N2HET1[18]/EPWM6A
140
N2HET1[20]/EPWM6B
141
Enhanced PWM6 Output B
N2HET1[09]/N2HET2[16]/EPWM7A
35
Enhanced PWM7 Output A
N2HET1[07]/N2HET2[14]/EPWM7B
33
Enhanced PWM7 Output B
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1
3
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2
4
Enhanced PWM2 Output A
Output
Pulldown
–
Output
Pullup
–
118
Enhanced PWM2 Output B
Enhanced PWM3 Output A
Enhanced PWM3 Output B
Enhanced PWM4 Output A
Enhanced PWM5 Output B
Output
Pulldown
–
Pullup
Input
N2HET1[10]/nTZ3
Fixed, 20 µA
External ePWM Sync Pulse
Output
N2HET1[16]/EPWM1SYNCI/EPWM1SYNCO
Fixed, 20 µA
Pulldown
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Enhanced PWM6 Output A
Trip Zone Inputs 1, 2 and 3.
These signals are either
connected asynchronously to
the ePWMx trip zone inputs,
or double-synchronized with
VCLK4, or doublesynchronized and then filtered
with a 6-cycle VCLK4-based
counter before connecting to
the ePWMx trip zone inputs.
Terminal Configuration and Functions
15
RM44L920, RM44L520
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
4.2.1.6
www.ti.com
General-Purpose Input/Output (GIO)
Table 4-6. PGE General-Purpose Input/Output (GIO)
Terminal
Signal Name
144 PGE
GIOA[0]
2
GIOA[1]
5
GIOA[2]/N2HET2[0]/EQEPII
9
GIOA[5]/EXTCLKIN1/EPWM1A/N2HET1_PIN_nDIS
14
GIOA[6]/N2HET2[4]/EPWM1B
16
GIOA[7]/N2HET2[6]/EPWM2A
22
GIOB[0]
126
GIOB[1]
133
Signal Reset Pull
Type
State
I/O
142
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nDIS
55 (1)
Pullup
1
Pulldown
GIOB[3]
Description
Programmable,
20 µA
General-purpose I/O.
All GIO terminals are
capable of generating
interrupts to the CPU
on rising / falling /
both edges.
Pulldown
GIOB[2]
(1)
Pull Type
GIOB[2] cannot output a level on to pin 55. Only the input functionality is supported so that the application can generate an interrupt
whenever the N2HET2_PIN_nDIS is asserted (driven low). Also, a pullup is enabled on the input. This is not programmable using the
GIO module control registers.
4.2.1.7
Controller Area Network Controllers (DCAN)
Table 4-7. PGE Controller Area Network Controllers (DCAN)
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
I/O
Pullup
Programmable,
20 µA
Description
CAN1RX
90
CAN1TX
89
CAN2RX
129
CAN2 receive, or GIO
CAN2TX
128
CAN2 transmit, or GIO
CAN3RX
12
CAN3 receive, or GIO
CAN3TX
13
CAN3 transmit, or GIO
4.2.1.8
CAN1 receive, or GIO
CAN1 transmit, or GIO
Local Interconnect Network Interface Module (LIN)
Table 4-8. PGE Local Interconnect Network Interface Module (LIN)
Terminal
Signal Name
144
PGE
LINRX
131
LINTX
132
16
Terminal Configuration and Functions
Signal
Type
Reset Pull
State
Pull Type
I/O
Pullup
Programmable,
20 µA
Description
LIN receive, or GIO
LIN transmit, or GIO
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4.2.1.9
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Standard Serial Communication Interface (SCI)
Table 4-9. PGE Standard Serial Communication Interface (SCI)
Terminal
Signal Name
144
PGE
N2HET1[06]/SCIRX/EPWM5A
38
N2HET1[13]/SCITX/EPWM5B
39
Signal
Type
Reset Pull
State
Pull Type
I/O
Pulldown
Programmable,
20 µA
Description
SCI receive, or GIO
SCI transmit, or GIO
4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
Table 4-10. PGE Inter-Integrated Circuit Interface Module (I2C)
Terminal
Signal Name
144
PGE
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2
4
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1
3
Signal
Type
Reset Pull
State
Pull Type
I/O
Pullup
Programmable,
20 µA
Description
I2C serial data, or GIO
I2C serial clock, or GIO
4.2.1.11 Standard Serial Peripheral Interface (SPI)
Table 4-11. PGE Standard Serial Peripheral Interface (SPI)
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
I/O
Pulldown
Programmable,
20 µA
Description
N2HET1[0]/SPI4CLK/EPWM2B
25
N2HET1[03]/SPI4NCS[0]/N2HET2[10]/EQEP2B
24
N2HET1[01]/SPI4NENA/N2HET2[8]/EQEP2A
23
SPI4 enable, or GIO
N2HET1[02]/SPI4SIMO[0]/EPWM3A
30
SPI4 slave-input masteroutput, or GIO
N2HET1[05]/SPI4SOMI[0]/N2HET2[12]/EPWM3B
31
SPI4 slave-output masterinput, or GIO
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SPI4 clock, or GIO
SPI4 chip select, or GIO
Terminal Configuration and Functions
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4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
Table 4-12. PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
Description
I/O
Pullup
Programmable,
20 µA
MibSPI1 clock, or GIO
Pulldown
Programmable,
20 µA
MibSPI1 chip select, or
GIO
Pullup
Programmable,
20 µA
MibSPI1 enable, or GIO
MIBSPI1CLK
95
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
105
MIBSPI1NCS[1]/N2HET1[17]//EQEP1S
130
MIBSPI1NCS[2]/N2HET1[19]/
40
N2HET1[15]/MIBSPI1NCS[4]/ECAP1
41
N2HET1[24]/MIBSPI1NCS[5]
91
MIBSPI1NENA/N2HET1[23]/ECAP4
96
MIBSPI1SIMO[0]
93
N2HET1[08]/MIBSPI1SIMO[1]
106
Pulldown
Programmable,
20 µA
MibSPI1 slave-in masterout, or GIO
MIBSPI1SOMI[0]
94
Pullup
MIBSPI1NCS[0]/MIBSPI1SOMI[1]/ECAP6
105
Programmable,
20 µA
MibSPI1 slave-out masterin, or GIO
MIBSPI3CLK/AWM1_EXT_SEL[1]/EQEP1A
53
Pullup
55
Programmable,
20 µA
MibSPI3 clock, or GIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/EQEP1I/N2HET2_PIN_nD
IS
MIBSPI3NCS[1]/N2HET1[25]
37
MIBSPI3NCS[2]/I2CSDA/N2HET1[27]/nTZ2
4
MIBSPI3NCS[3]/I2CSCL/N2HET1[29]/nTZ1
3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18]/EPWM1SYNCO
6
Pulldown
Programmable,
20 µA
MibSPI3 chip select, or
GIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
54
Pullup
Programmable,
20 µA
MibSPI3 chip select, or
GIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31]/EQEP1B
54
MibSPI3 enable, or GIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/ECAP3
52
MibSPI3 slave-in masterout, or GIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/ECAP2
51
MibSPI3 slave-out masterin, or GIO
MIBSPI5CLK
100
MIBSPI5NCS[0]/EPWM4A
32
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5
97
MibSPI5 enable, or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]
99
MibSPI5 slave-in masterout, or GIO
MIBSPI5SOMI[0]
98
MibSPI5 slave-out masterin, or GIO
MIBSPI5NENA/MIBSPI5SOMI[1]/ECAP5
97
MibSPI5 SOMI[0], or GIO
MIBSPI5SIMO[0]/MIBSPI5SOMI[2]
99
MibSPI5 SOMI[0], or GIO
18
Terminal Configuration and Functions
I/O
I/O
Pullup
Programmable,
20 µA
MibSPI1 chip select, or
GIO
MibSPI1 slave-in masterout, or GIO
MibSPI3 chip select, or
GIO
MibSPI5 clock, or GIO
MibSPI5 chip select, or
GIO
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SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
4.2.1.13 System Module Interface
Table 4-13. PGE System Module Interface
TERMINAL
144
PGE
SIGNAL NAME
nPORRST
46
SIGNAL
TYPE
Input
RESET
PULL
STATE
PULL TYPE
DESCRIPTION
100 µA
Power-on reset, cold reset
External power supply monitor
circuitry must drive nPORRST
low when any of the supplies
to the microcontroller fall out
of the specified range. This
terminal has a glitch filter.
See Section 6.8.
Pulldown
nRST
116
I/O
Pullup
100 µA
System reset, warm reset,
bidirectional.
The internal circuitry indicates
any reset condition by driving
nRST low.
The external circuitry can
assert a system reset by
driving nRST low. To ensure
that an external reset is not
arbitrarily generated, TI
recommends that an external
pullup resistor is connected to
this terminal.
This terminal has a glitch
filter. See Section 6.8.
nERROR
117
I/O
Pulldown
20 µA
ESM Error Signal
Indicates error of high
severity. See Section 6.8.
4.2.1.14 Clock Inputs and Outputs
Table 4-14. PGE Clock Inputs and Outputs
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
Input
–
None
OSCIN
18
KELVIN_GND
19
Input
OSCOUT
20
Output
ECLK
119
I/O
Pulldown
Programmable,
20 µA
GIOA[5]/EXTCLKIN1/EPWM1A /N2HET1_PIN_nDIS
14
Input
Pulldown
20 µA
Description
From external
crystal/resonator, or
external clock input
Kelvin ground for oscillator
To external
crystal/resonator
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External prescaled clock
output, or GIO.
External clock input #1
Terminal Configuration and Functions
19
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4.2.1.15 Test and Debug Modules Interface
Table 4-15. PGE Test and Debug Modules Interface
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
Description
Input
Pulldown
Fixed, 100 µA
Test enable. This terminal
must be connected to
ground directly or via a
pulldown resistor.
TEST
34
nTRST
109
Input
RTCK
113
Output
-
None
TCK
112
Input
Pulldown
Fixed, 100 µA
TDI
110
Input
Pullup
TDO
111
Output
Pulldown
TMS
108
Input
Pullup
JTAG test hardware reset
JTAG return test clock
JTAG test clock
JTAG test data in
JTAG test data out
JTAG test select
4.2.1.16 Flash Supply and Test Pads
Table 4-16. PGE Flash Supply and Test Pads
Terminal
Signal Name
144
PGE
Signal
Type
Reset Pull
State
Pull Type
Description
VCCP
134
3.3-V
Power
–
None
Flash pump supply
FLTP1
7
–
–
None
FLTP2
8
Flash test pads. These
terminals are reserved for
TI use only. For proper
operation these terminals
must connect only to a
test pad or not be
connected at all [no
connect (NC)].
4.2.1.17 Supply for Core Logic: 1.2V nominal
Table 4-17. PGE Supply for Core Logic: 1.2V nominal
Terminal
Signal Name
144
PGE
VCC
17
VCC
29
VCC
45
VCC
48
VCC
49
VCC
57
VCC
87
VCC
101
VCC
114
VCC
123
VCC
137
VCC
143
20
Terminal Configuration and Functions
Signal
Type
Reset Pull
State
Pull Type
1.2-V
Power
–
None
Description
Core supply
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4.2.1.18 Supply for I/O Cells: 3.3V nominal
Table 4-18. PGE Supply for I/O Cells: 3.3V nominal
Terminal
Signal Name
144
PGE
VCCIO
10
VCCIO
26
VCCIO
42
VCCIO
104
VCCIO
120
VCCIO
136
Signal
Type
Reset Pull
State
Pull Type
3.3-V
Power
–
None
Description
Operating supply for I/Os
4.2.1.19 Ground Reference for All Supplies Except VCCAD
Table 4-19. PGE Ground Reference for All Supplies Except VCCAD
Terminal
Signal Name
144
PGE
VSS
11
VSS
21
VSS
27
VSS
28
VSS
43
VSS
44
VSS
47
VSS
50
VSS
56
VSS
88
VSS
102
VSS
103
VSS
115
VSS
121
VSS
122
VSS
135
VSS
138
VSS
144
Signal
Type
Reset Pull
State
Pull Type
Ground
–
None
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Description
Ground reference
Terminal Configuration and Functions
21
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SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
4.2.2
www.ti.com
PZ Package Terminal Functions
4.2.2.1
High-End Timer (N2HET) Modules
Table 4-20. PZ Enhanced High-End Timer (N2HET) Modules
TERMINAL
SIGNAL NAME
100 PZ
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
I/O
Pulldown
Programmable,
20 µA
N2HET1[0]/ SPI4CLK / EPWM2B
19
N2HET1[2] / SPI4SIMO / EPWM3A
22
N2HET1[4] / EPWM4B
25
N2HET1[6] / SCIRX / EPWM5A
26
N2HET1[8] / MIBSPI1SIMO[1]
74
N2HET1[10] / nTZ3
83
N2HET1[12]
89
N2HET1[14]
90
N2HET1[16] / EPWM1SYNCI /
EPWM1SYNCO
97
MIBSPI1nCS[1] / N2HET1[17] / EQEP1S
93
Pullup
N2HET1[18] / EPWM6A
98
Pulldown
MIBSPI1nCS[2] / N2HET1[19]
27
Pullup
MIBSPI1nCS[3] / N2HET1[21]
39
N2HET1[22]
11
MIBSPI1nENA / N2HET1[23] / ECAP4
68
Pullup
N2HET1[24] / MIBSPI1nCS[5]
64
Pulldown
MIBSPI3nENA / MIBSPI3nCS[5] /
N2HET1[31] / EQEP1B
37
Pullup
GIOA[5] / INT[5] / EXTCLKIN
/EPWM1A/N2HET1_PIN_nDIS
10
Pulldown
GIOA[2] / INT[2] / N2HET2[0] / EQEP2I
5
Pulldown
GIOA[3] / INT[3] / N2HET2[2]
8
GIOA[6] / INT[6] / N2HET2[4] / EPWM1B
12
GIOA[7] / INT[7] / N2HET2[6] / EPWM2A
18
DESCRIPTION
N2HET2 timer input
compare, or GIO.
capture
or
output
Each terminal has a suppression filter with a
programmable duration.
Timer input capture or output compare. The N2HET
applicable terminals can be programmed as
general-purpose input/output (GIO).
Pulldown
Disable selected PWM outputs
N2HET2 timer input
compare, or GIO.
capture
or
output
Each terminal has a suppression filter with a
programmable duration.
Timer input capture or output compare. The N2HET
applicable terminals can be programmed as
general-purpose input/output (GIO).
4.2.2.2
Enhanced Capture Modules (eCAP)
Table 4-21. PZ Enhanced Capture Modules (eCAP)
Terminal
Signal
Type
Reset Pull
State
Pull Type
I/O
Pullup
Fixed, 20 µA
Description
Signal Name
100
PZ
MIBSPI3SOMI[0] /
AWM1_EXT_ENA / ECAP2
34
MIBSPI3SIMO[0] /
AWM1_EXT_SEL[0] / ECAP3
35
Enhanced Capture Module 3 I/O
MIBSPI1NENA / N2HET1[23] /
ECAP4
68
Enhanced Capture Module 4 I/O
MIBSPI1NCS[0] /
MIBSPI1SOMI[1] / ECAP6
73
Enhanced Capture Module 6 I/O
22
Terminal Configuration and Functions
Enhanced Capture Module 2 I/O
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4.2.2.3
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Enhanced Quadrature Encoder Pulse Modules (eQEP)
Table 4-22. PZ Enhanced Quadrature Encoder Pulse Modules (eQEP)
SIGNAL NAME
TERMINAL
100 PZ
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
MIBSPI3CLK / AWM1_EXT_SEL[1] /
EQEP1A
36
I/O
Pullup
Fixed, 20 µA
MIBSPI3nENA / MIBSPI3nCS[5] /
N2HET1[31] / EQEP1B
37
Enhanced QEP1 Input B
MIBSPI3nCS[0] / AD2EVT / GIOB[2]
/ EQEP1I/N2HET2_PIN_nDIS
38
Enhanced QEP1 Index
MIBSPI1nCS[1] / N2HET1[17] /
EQEP1S
93
Enhanced QEP1 Strobe
GIOA[2] / INT[2] / N2HET2[0] /
EQEP2I
5
4.2.2.4
Pulldown
DESCRIPTION
Enhanced QEP1 Input A
Enhanced QEP2 Index
Enhanced Pulse-Width Modulator Modules (ePWM)
Table 4-23. PZ Enhanced Pulse-Width Modulator Modules (ePWM)
TERMINAL
100 PZ
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
GIOA[5] / INT[5] / EXTCLKIN /
EPWM1A/N2HET1_PIN_nDIS
10
Output
Pulldown
–
GIOA[6] / INT[6] / N2HET2[4] /
EPWM1B
12
N2HET1[16] / EPWM1SYNCI /
EPWM1SYNCO
97
Input
Pulldown
Fixed, 20 µA
N2HET1[16] / EPWM1SYNCI /
EPWM1SYNCO
97
Output
Pulldown
–
GIOA[7] / INT[7] / N2HET2[6] /
EPWM2A
18
Enhanced PWM2 Output A
N2HET1[0] / SPI4CLK / EPWM2B
19
Enhanced PWM2 Output B
N2HET1[2] / SPI4SIMO / EPWM3A
22
Enhanced PWM3 Output A
N2HET1[4] / EPWM4B
25
Enhanced PWM4 Output B
N2HET1[6] / SCIRX / EPWM5A
26
Enhanced PWM5 Output A
N2HET1[18] / EPWM6A
98
N2HET1[10] / nTZ3
83
SIGNAL NAME
Pulldown
DESCRIPTION
Enhanced PWM1 Output A
Enhanced PWM1 Output B
External ePWM Sync Pulse Input
External ePWM Sync Pulse Output
Enhanced PWM6 Output A
Input
Pulldown
Trip Zone 1 input 3
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4.2.2.5
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General-Purpose Input/Output (GIO)
Table 4-24. PZ General-Purpose Input/Output (GIO)
Terminal
Signal Name
100
PZ
Signal
Type
Reset Pull
State
I/O
Pulldown
Pull Type
Description
GIOA
GIOA[0] / INT[0]
1
GIOA[1] / INT[1]
2
GIOA[2] / INT[2] / N2HET2[0] /
EQEP2I
5
GIOA[3] / INT[3] / N2HET2[2]
8
GIOA[4]/ INT[4]
9
GIOA[5] / INT[5] / EXTCLKIN /
EPWM1A/ N2HET1_PIN_nDIS
10
GIOA[6] / INT[6] / N2HET2[4] /
EPWM1B
12
GIOA[7] / INT[7] / N2HET2[6] /
EPWM2A
18
MIBSPI3nCS[0] / AD2EVT /
GIOB[2] /
EQEP1I/N2HET2_PIN_nDIS
38
Programmable,
20 µA
General-purpose input/output
All GPIO terminals are capable of generating
interrupts to the CPU on rising/falling/both edges.
GIOB
4.2.2.6
I/O
General-purpose input/output
Controller Area Network Interface Modules (DCAN1, DCAN2)
Table 4-25. PZ Controller Area Network Interface Modules (DCAN1, DCAN2)
Terminal
Signal Name
100
PZ
CAN1RX
63
CAN1TX
62
CAN2RX
92
CAN2TX
91
Signal
Type
Reset Pull
State
I/O
Pullup
Pull Type
Description
DCAN1
Programmable,
20 µA
CAN1 Receive, or general-purpose I/O (GPIO)
CAN1 Transmit, or GPIO
DCAN2
24
Terminal Configuration and Functions
I/O
Pullup
Programmable,
20 µA
CAN2 Receive, or GPIO
CAN2 Transmit, or GPIO
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4.2.2.7
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Standard Serial Peripheral Interfaces (SPI2 and SPI4)
Table 4-26. PZ Standard Serial Peripheral Interfaces (SPI2 and SPI4)
Terminal
Signal Name
Signal Type
Reset Pull
State
I/O
Pullup
100 PZ
Pull Type
Description
SPI2
SPI2CLK
71
SPI2nCS[0]
23
Programmable, 20 µA
SPI2 Serial Clock, or GPIO
SPI2 Chip Select, or GPIO
SPI2SIMO
70
SPI2 Slave-In-Master-Out, or GPIO
SPI2SOMI
69
SPI2 Slave-Out-Master-In, or GPIO
The drive strengths for the SPI2CLK, SPI2SIMO and SPI2SOMI signals are selected individually by configuring the respective SRS bits of the SPIPC9 register
fo SPI2.
SRS = 0 for 8mA drive (fast). This is the default mode as the SRS bits in the SPIPC9 register default to 0.
SRS = 1 for 2mA drive (slow)
SPI4
N2HET1[0] / SPI4CLK / EPWM2B
19
N2HET1[2] / SPI4SIMO / EPWM3A
22
4.2.2.8
I/O
Pulldown
Programmable, 20 µA
SPI2 Serial Clock, or GPIO
SPI2 Slave-In-Master-Out, or GPIO
Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
Table 4-27. PZ Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
Terminal
Signal
Type
Reset Pull
State
I/O
Pullup
Pull Type
Description
Signal Name
100 PZ
MIBSPI1CLK
67
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/
ECAP6
73
MIBSPI1nCS[1]/N2HET1[17]/
EQEP1S
93
MIBSPI1nCS[2]/N2HET1[19]
27
MIBSPI1nCS[3]/N2HET1[21]
39
MIBSPI1nENA/N2HET1[23]/
ECAP4
68
MibSPI1 Enable, or GPIO
MIBSPI1SIMO[0]
65
MibSPI1 Slave-In-Master-Out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1]
74
MIBSPI1SOMI[0]
66
MIBSPI1nCS[0]/MIBSPI1SOMI[1]/
ECAP6
73
MIBSPI3CLK/AWM1_EXT_SEL[1]/
EQEP1A
36
MIBSPI3nCS[0]/AD2EVT/GIOB[2]/
EQEP1I/N2HET2_PIN_nDIS
38
MIBSPI3nENA/MIBSPI3nCS[5]/
N2HET1[31]/EQEP1B
37
MIBSPI3nENA/MIBSPI3nCS[5]/
N2HET1[31]/EQEP1B
37
MibSPI3 Enable, or GPIO
MIBSPI3SIMO[0]/AWM1_EXT_SEL[0]/
ECAP3
35
MibSPI3 Slave-In-Master-Out, or GPIO
MIBSPI3SOMI[0]/AWM1_EXT_ENA/
ECAP2
34
MibSPI3 Slave-Out-Master-In, or GPIO
MibSPI1
Programmable, 20 µA MibSPI1 Serial Clock, or GPIO
MibSPI1 Chip Select, or GPIO
MibSPI1 Slave-Out-Master-In, or GPIO
MibSPI3
I/O
Pullup
Programmable, 20 µA MibSPI3 Serial Clock, or GPIO
MibSPI3 Chip Select, or GPIO
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4.2.2.9
www.ti.com
Local Interconnect Network Controller (LIN)
Table 4-28. PZ Local Interconnect Network Controller (LIN)
TERMINAL
100 PZ
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
LINRX
94
I/O
Pullup
Programmable, 20 µA
LINTX
95
SIGNAL NAME
DESCRIPTION
LIN Receive, or GPIO
LIN Transmit, or GPIO
4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
Table 4-29. PZ Multibuffered Analog-to-Digital Converter (MibADC)
Terminal
Signal Name
100
PZ
Signal
Type
Reset Pull
State
Pull Type
Description
MibADC1
AD1EVT
58
I/O
Pulldown
Programmable,
20 µA
ADC1 Event Trigger or GPIO
AD1IN[0]
42
Input
–
–
Analog Inputs
AD1IN[1]
49
AD1IN[2]
51
AD1IN[3]
52
AD1IN[4]
54
AD1IN[5]
55
AD1IN[6]
56
AD1IN[7]
43
AD1IN[8]/AD2IN[8]
57
AD1IN[9]/AD2IN[9]
48
AD1IN[10]/AD2IN[10]
50
AD1IN[11]/AD2IN[11]
53
AD1IN[16]/AD2IN[0]
40
AD1IN[17]/AD2IN[1]
41
AD1IN[20]/AD2IN[4]
44
AD1IN[21]/AD2IN[5]
45
ADREFHI/VCCAD
46
Input/
Power
–
–
ADC High Reference Level/ADC Operating
Supply
ADREFLO/VSSAD
47
Input/
Ground
–
–
ADC Low Reference Level/ADC Supply Ground
MIBSPI3SOMI[0]/AWM1_EXT_
ENA/
ECAP2
34
AWM external analog mux enable
MIBSPI3SIMO[0]/AWM1_EXT_
SEL[0]/
ECAP3
35
AWM external analog mux select line 0
MIBSPI3CLK/AWM1_EXT_SEL
[1]/
EQEP1A
36
AWM external analog mux select line1
MIBSPI3nCS[0]/AD2EVT/GIOB[
2]/
EQEP1I/N2HET2_PIN_nDIS
38
MibADC2
26
Terminal Configuration and Functions
I/O
ADC2 Event Trigger or GPIO
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4.2.2.11 System Module Interface
Table 4-30. PZ System Module Interface
TERMINAL
SIGNAL NAME
nPORRST
100 PZ
SIGNAL
TYPE
31
Input
RESET
PULL
STATE
Pullup
PULL TYPE
DESCRIPTION
100 µA
Power-on reset, cold reset External power supply
monitor circuitry must drive nPORRST low when any of
the supplies to the microcontroller fall out of the
specified range. This terminal has a glitch filter. See
Section 6.8.
nRST
81
I/O
Pullup
100 µA
The external circuitry can assert a system reset by
driving nRST low. To ensure that an external reset is not
arbitrarily generated, TI recommends that an external
pullup resistor is connected to this terminal. This
terminal has a glitch filter. See Section 6.8.
nERROR
82
I/O
Pulldown
20 µA
ESM Error Signal. Indicates error of high severity. See
Section 6.8.
4.2.2.12 Clock Inputs and Outputs
Table 4-31. PZ Clock Inputs and Outputs
TERMINAL
100 PZ
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
OSCIN
14
Input
–
–
From external crystal/resonator, or external clock input
KELVIN_GND
15
Input
–
–
Dedicated ground for oscillator
OSCOUT
16
Output
–
–
To external crystal/resonator
ECLK
84
I/O
Pulldown
Programmable, 20 µA
GIOA[5]/INT[5]/EXTCLKIN/EPWM1A
/N2HET1_PIN_nDIS
10
Input
Pulldown
20 µA
SIGNAL NAME
DESCRIPTION
External prescaled clock output, or GIO.
External Clock In
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4.2.2.13 Test and Debug Modules Interface
Table 4-32. PZ Test and Debug Modules Interface
TERMINAL
SIGNAL NAME
100 PZ
SIGNAL
TYPE
RESET
PULL
STATE
PULL TYPE
DESCRIPTION
nTRST
76
Input
Pulldown
Fixed, 100 µA
RTCK
80
Output
–
–
JTAG test hardware reset
TCK
79
Input
Pulldown
Fixed, 100 µA
JTAG test clock
TDI
77
I/O
Pullup
Fixed, 100 µA
JTAG test data in
TDO
78
I/O
Pulldown
Fixed, 100 µA
JTAG test data out
TMS
75
I/O
Pullup
Fixed, 100 µA
JTAG test select
TEST
24
I/O
Pulldown
Fixed, 100 µA
Test enable. This terminal must be connected to ground
directly or via a pulldown resistor.
JTAG return test clock
4.2.2.14 Flash Supply and Test Pads
Table 4-33. PZ Flash Supply and Test Pads
Terminal
Signal
Type
Reset Pull
State
Pull Type
96
3.3-V
Power
–
–
Flash external pump voltage (3.3 V). This
terminal is required for both Flash read and Flash
program and erase operations.
FLTP1
3
Input
–
–
FLTP2
4
Input
–
–
Flash Test Pins. For proper operation this
terminal must connect only to a test pad or not be
connected at all [no connect (NC)].
The test pad must not be exposed in the final
product where it might be subjected to an ESD
event.
Signal Name
100
PZ
VCCP
Description
4.2.2.15 Supply for Core Logic: 1.2-V Nominal
Table 4-34. PZ Supply for Core Logic: 1.2-V Nominal
Terminal
Signal Name
100
PZ
VCC
13
VCC
21
VCC
30
VCC
32
VCC
61
VCC
88
VCC
99
Signal
Type
Reset Pull
State
Pull Type
1.2-V
Power
–
–
Description
Digital logic and RAM supply
4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
Table 4-35. PZ Supply for I/O Cells: 3.3-V Nominal
Terminal
Signal Name
100
PZ
VCCIO
6
VCCIO
28
VCCIO
60
VCCIO
85
28
Signal
Type
Reset Pull
State
Pull Type
3.3-V
Power
–
–
Terminal Configuration and Functions
Description
I/O Supply
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4.2.2.17 Ground Reference for All Supplies Except VCCAD
Table 4-36. PZ Ground Reference for All Supplies Except VCCAD
Terminal
Signal Name
100
PZ
VSS
7
VSS
17
VSS
20
VSS
29
VSS
33
VSS
59
VSS
72
VSS
86
VSS
87
VSS
100
4.3
Signal
Type
Reset Pull
State
Pull Type
Ground
–
–
Description
Device Ground Reference. This is a single
ground reference for all supplies except for the
ADC Supply.
Pin Multiplexing
This microcontroller has several interfaces and uses extensive multiplexing to bring out the functions as
required by the target application. The multiplexing is mostly on the output signals. A few inputs are also
multiplexed to allow the same input signal to be driven in from a selected terminal.
4.3.1
Output Multiplexing
Table 4-37 and Table 4-38 show the pin multiplexing control x register (PINMMRx) and the associated bit
fields that control each pin mux function.
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Table 4-37. Multiplexing for Outputs on 144-Pin PGE Package(1)
144-PIN
PGE
30
DEFAULT
FUNCTION
CTRL1
OPTION 2
CTRL2
OPTION 3
CTRL3
OPTION 4
CTRL4
86
AD1EVT
10[0]
2
GIOA[0]
0[8]
5
GIOA[1]
1[0]
9
GIOA[2]
2[0]
14
GIOA[5]
2[24]
EXTCLKIN1
2[25]
EPWM1A
2[26]
16
GIOA[6]
3[16]
N2HET2[4]
3[17]
EPWM1B
3[18]
22
GIOA[7]
4[0]
N2HET2[6]
4[1]
EPWM2A
4[2]
126
GIOB[0]
18[24]
133
GIOB[1]
21[8]
1
GIOB[3]
0[0]
105
MIBSPI1NCS[0]
13[24]
MIBSPI1SOMI[1]
130
MIBSPI1NCS[1]
20[16]
N2HET1[17]
40
MIBSPI1NCS[2]
8[8]
N2HET1[19]
8[9]
96
MIBSPI1NENA
12[16]
N2HET1[23]
12[17]
53
MIBSPI3CLK
33[24]
AWM1_EXT_SEL[1]
33[25]
EQEP1A
33[26]
55
MIBSPI3NCS[0]
9[16]
AD2EVT
9[17]
GIOB[2]
9[18]
EQEP1I
9[19]
37
MIBSPI3NCS[1]
7[8]
N2HET1[25]
7[9]
4
MIBSPI3NCS[2]
0[24]
I2C_SDA
0[25]
N2HET1[27]
0[26]
nTZ2
0[27]
N2HET2[0]
2[3]
OPTION 5
CTRL5
OPTION 6
CTRL6
EQEP2I
2[4]
13[25]
ECAP6
13[28]
20[17]
EQEP1S
20[20]
ECAP4
12[20]
ECAP5
12[29]
4[19]
N2HET2[8]
4[20]
EQEP2A
4[21]
4[27]
N2HET2[10]
4[28]
EQEP2B
4[29]
EPWM7B
6[4]
3
MIBSPI3NCS[3]
0[16]
I2C_SCL
0[17]
N2HET1[29]
0[18]
nTZ1
0[19]
54
MIBSPI3NENA
9[8]
MIBSPI3NCS[5]
9[9]
N2HET1[31]
9[10]
EQEP1B
9[11]
52
MIBSPI3SIMO
33[16]
AWM1_EXT_SEL[0]
33[17]
ECAP3
33[18]
AWM1_EXT_ENA
33[9]
ECAP2
33[10]
EPWM4A
27[2]
51
MIBSPI3SOMI
33[8]
100
MIBSPI5CLK
13[16]
32
MIBSPI5NCS[0]
27[0]
97
MIBSPI5NENA
12[24]
MIBSPI5SOMI[1]
12[28]
99
MIBSPI5SIMO[0]
13[8]
MIBSPI5SOMI[2]
13[12]
98
MIBSPI5SOMI[0]
13[0]
25
N2HET1[0]
5[0]
SPI4CLK
5[1]
23
N2HET1[01]
4[16]
SPI4NENA
4[17]
30
N2HET1[02]
5[8]
SPI4SIMO
5[9]
24
N2HET1[03]
4[24]
SPI4NCS[0]
4[25]
36
N2HET1[04]
33[0]
EPWM4B
33[1]
31
N2HET1[05]
5[16]
SPI4SOMI
5[17]
N2HET2[12]
5[18]
38
N2HET1[06]
7[16]
SCIRX
7[17]
EPWM5A
7[18]
33
N2HET1[07]
6[0]
EPWM2B
5[2]
EPWM3A
5[10]
EPWM3B
5[19]
N2HET2[14]
6[3]
Terminal Configuration and Functions
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Table 4-37. Multiplexing for Outputs on 144-Pin PGE Package(1) (continued)
144-PIN
PGE
DEFAULT
FUNCTION
CTRL1
OPTION 2
CTRL2
106
N2HET1[08]
14[0]
MIBSPI1SIMO[1]
14[1]
35
N2HET1[09]
6[16]
N2HET2[16]
6[17]
118
N2HET1[10]
17[0]
6
N2HET1[11]
1[8]
124
N2HET1[12]
17[16]
39
N2HET1[13]
8[0]
125
N2HET1[14]
18[8]
41
N2HET1[15]
139
N2HET1[16]
140
OPTION 3
CTRL3
MIBSPI3NCS[4]
1[9]
N2HET2[18]
1[10]
SCITX
8[1]
EPWM5B
8[2]
8[16]
MIBSPI1NCS[4]
8[17]
ECAP1
8[18]
34[0]
EPWM1SYNCI
34[1]
EPWM1SYNCO
34[2]
N2HET1[18]
34[8]
EPWM6A
34[9]
141
N2HET1[20]
34[16]
EPWM6B
34[17]
15
N2HET1[22]
3[8]
91
N2HET1[24]
11[24]
MIBSPI1NCS[5]
11[25]
92
N2HET1[26]
12[0]
107
N2HET1[28]
14[8]
127
N2HET1[30]
19[8]
OPTION 4
CTRL4
OPTION 5
CTRL5
EPWM7A
6[20]
nTZ3
17[4]
OPTION 6
EPWM1SYNCO
EQEP2S
CTRL6
1[13]
19[11]
(1) The CTRLx columns contain a value of type x[y], which indicates the pin multiplexing control x register (PINMMRx) and the associated bit field [y].
Terminal Configuration and Functions
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Table 4-38. Multiplexing for Outputs on 100-Pin PZ Package (1)
100-PIN
PZ
(1)
32
DEFAULT
FUNCTION
CTRL1
OPTION 2
CTRL2
OPTION 3
CTRL3
2
GIOA[1]/INT[1]
1[0]
5
GIOA[2]/INT[2]
2[0]
10
GIOA[5]/INT[5]
2[24]
EXTCLKIN1
2[25]
EPWM1A
2[26]
12
GIOA[6]/INT[6]
3[16]
N2HET2[4]
3[17]
EPWM1B
3[18]
18
GIOA[7]/INT[7]
4[0]
N2HET2[6]
4[1]
EPWM2A
4[2]
73
MIBSPI1NCS[0]
13[24]
MIBSPI1SOMI[1]
93
MIBSPI1NCS[1]
20[16]
27
MIBSPI1NCS[2]
68
36
OPTION 4
N2HET2[0]
CTRL4
2[3]
OPTION 5
CTRL5
EQEP2I
2[4]
13[25]
ECAP6
13[28]
N2HET1[17]
20[17]
EQEP1S
20[20]
8[8]
N2HET1[19]
8[9]
MIBSPI1NENA
12[16]
N2HET1[23]
12[17]
ECAP4
12[20]
MIBSPI3CLK
33[24]
AWM1_EXT_SEL[1]
33[25]
EQEP1A
33[26]
38
MIBSPI3NCS[0]
9[16]
AD2EVT
9[17]
GIOB[2]
9[18]
EQEP1I
9[19]
37
MIBSPI3NENA
9[8]
MIBSPI3NCS[5]
9[9]
N2HET1[31]
9[10]
EQEP1B
9[11]
35
MIBSPI3SIMO[0]
33[16]
AWM1_EXT_SEL[0]
33[17]
ECAP3
33[18]
34
MIBSPI3SOMI[0]
33[8]
AWM1_EXT_ENA
33[9]
ECAP2
33[10]
19
N2HET1[0]
5[0]
SPI4CLK
5[1]
EPWM2B
5[2]
22
N2HET1[02]
5[8]
SPI4SIMO
5[9]
EPWM3A
5[10]
25
N2HET1[04]
33[0]
EPWM4B
33[1]
26
N2HET1[06]
7[16]
SCIRX
7[17]
EPWM5A
7[18]
74
N2HET1[08]
14[0]
MIBSPI1SIMO[1]
14[1]
83
N2HET1[10]
17[0]
nTZ3
17[4]
97
N2HET1[16]
34[0]
EPWM1SYNCI
34[1]
EPWM1SYNCO
34[2]
98
N2HET1[18]
34[8]
EPWM6A
34[9]
64
N2HET1[24]
11[24]
MIBSPI1NCS[5]
11[25]
OPTION 6
CTRL6
The CTRLx columns contain a value of type x[y], which indicates the pin multiplexing control x register (PINMMRx) and the associated bit field [y].
Terminal Configuration and Functions
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4.3.2
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Multiplexing of Inputs
Some signals are connected to more than one terminal, the inputs for these signals can come from any of
the terminals. A multiplexor is implemented to let the application choose the terminal that will be used,
providing the input signal is from among the available options.
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Table 4-39. Input Multiplexing and Control for All Packages [144-Pin PGE, and 100-Pin PZ](1)
SIGNAL
NAME
DEDICATED INPUTS
MULTIPLEXED INPUTS
INPUT MULTIPLEXOR
CONTROL
144 PGE
100 PZ
144 PGE
100 PZ
142
–
55
38
PINMUX29[16]
PINMUX29[16]
BIT1 = 0(3)
BIT1 = 1(3)
N2HET1[17]
–
–
130
93
PINMUX20[17]
PINMUX24[16]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[19]
–
–
40
27
PINMUX8[9]
PINMUX24[24]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[21]
–
–
–
–
PINMUX9[25]
PINMUX25[0]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[23]
–
–
96
68
PINMUX12[17]
PINMUX25[8]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[25]
–
–
37
–
PINMUX7[9]
PINMUX25[16]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[27]
–
–
4
–
PINMUX0[26]
PINMUX25[24]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[29]
–
–
3
–
PINMUX0[18]
PINMUX26[0]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
N2HET1[31]
–
–
54
37
PINMUX9[10]
PINMUX26[8]
not(BIT1) or (BIT1 and BIT2) = 1
BIT1 and not(BIT2) = 1
GIOB[2]
BIT1
INPUT PATH SELECTED
BIT2
DEDICATED, IF
MUXED, IF
(1) The default inputs to the modules are from the dedicated input terminals. The application must configure the PINMUX registers as shown in order to select the multiplexed input path, if
required.
(2) The SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4nENA and SPI4nCS[0] signals do not have a dedicated signal pad on this device. Therefore, the input multiplexors on these inputs are not
required. The control registers are still available to maintain compatibility to the emulation device.
(3) When the muxed input is selected for GIOB[2], the PINMUX9[16] and PINMUX9[17] must be cleared. These bits affect the control over the PULDIS (pull disable) and PSEL (pull select).
When the multiplexed input path is selected for GIOB[2], the PULDIS is tied to 0 (pull is enabled, cannot be disabled) and the PULSEL is tied to 1 (pull up selected, not programmable).
34
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4.4
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Buffer Type
Table 4-40. Output Buffer Drive Strengths
Low-level Output Current, IOL for VI = VOLmax
or
High-level Output Current, IOH for VI = VOHmin
Signals
MIBSPI5CLK, MIBSPI5SOMI[0], MIBSPI5SOMI[1], MIBSPI5SOMI[2], MIBSPI5SOMI[3],
MIBSPI5SIMO[0], MIBSPI5SIMO[1], MIBSPI5SIMO[2], MIBSPI5SIMO[3],
TMS, TDI, TDO, RTCK,
SPI4CLK, SPI4SIMO, SPI4SOMI, SPI4NCS[0], SPI4NENA, nERROR,
N2HET2[1], N2HET2[3],
N2HET2[13], N2HET2[15]
8mA
N2HET2[5],
N2HET2[7],
N2HET2[9],
N2HET2[11],
ECAP1, ECAP4, ECAP5, ECAP6
EQEP1I, EQEP1S, EQEP2I, EQEP2S
EPWM1A, EPWM1B, EPWM1SYNCO, EPW2A, EPWM2B, EPWM3A, EPWM3B,
EPWM4A, EPWM4B, EPWM5A, EPWM5B, EPWM6A, EPWM6B, EPWM7A, EPWM7B
TEST,
MIBSPI3SOMI,
MIBSPI1CLK,
4mA
MIBSPI3SIMO,
MIBSPI3CLK,
MIBSPI1SIMO,
MIBSPI1SOMI,
ECAP2, ECAP3
nRST
AD1EVT,
CAN1RX, CAN1TX, CAN2RX, CAN2TX, CAN3RX, CAN3TX,
GIOA[0-7], GIOB[0-7],
2mA zero-dominant
LINRX, LINTX,
MIBSPI1NCS[0],
MIBSPI1NCS[1-3],
MIBSPI1NENA,
MIBSPI3NENA, MIBSPI5NCS[0-3], MIBSPI5NENA,
MIBSPI3NCS[0-3],
N2HET1[0-31], N2HET2[0], N2HET2[2], N2HET2[4], N2HET2[6],
N2HET2[10], N2HET2[12], N2HET2[14], N2HET2[16], N2HET2[18],
N2HET2[8],
ECLK,
selectable 8mA / 2mA
SPI2CLK, SPI2SIMO, SPI2SOMI
The default output buffer drive strength is 8mA for these signals.
Table 4-41. Selectable 8mA/2mA Control
(1)
SIGNAL
CONTROL BIT
ADDRESS
8mA (DEFAULT)
2mA
ECLK
SYSPC10[0]
0xFFFF FF78
0
1
SPI2CLK
SPI2PC9[9]
0xFFF7 F668
0
1
SPI2SIMO
SPI2PC9[10]
0xFFF7 F668
0
1
SPI2SOMI
SPI2PC9[11] (1)
0xFFF7 F668
0
1
Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these two bits
differ, SPI2PC9[11] determines the drive strength.
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5 Specifications
Absolute Maximum Ratings (1)
5.1
Over Operating Free-Air Temperature Range
MIN
MAX
VCC (2)
–0.3
1.43
VCCIO, VCCP (2)
–0.3
4.6
VCCAD (2)
–0.3
6.25
All input pins, with exception of ADC pins
–0.3
4.6
ADC input pins
–0.3
6.25
All output pins
–0.3
4.6
IIK (VI < 0 or VI > VCCIO)
All pins, except AD1IN[23:0] or AD2IN[15:0]
–20
20
IIK (VI < 0 or VI > VCCAD)
AD1IN[23:0] or AD2IN[15:0]
–10
10
Total
–40
40
IOK (VO < 0 or VO > VCCIO)
All pins, except AWM1_EXT_x
–20
20
Total
–40
40
Operating free-air
temperature (TA)
–40
105
°C
Operating junction
temperature (TJ)
–40
130
°C
Storage temperature (Tstg)
–65
150
°C
Supply voltage range:
Input voltage
Output voltage
Input clamp current
Output clamp current
(1)
(2)
(1)
(2)
36
V
V
mA
mA
ESD Ratings
V(ESD)
5.3
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to their associated
grounds.
5.2
(1)
(2)
UNIT
Electrostatic discharge (ESD)
performance:
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001 (1)
Charged Device Model (CDM), per JESD22-C101 (2)
All pins
VALUE
UNIT
±2
kV
±250
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Power-On Hours (POH) (1) (2)
NOMINAL CVDD VOLTAGE (V)
JUNCTION
TEMPERATURE (Tj)
LIFETIME POH
1.2
105ºC
100K
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to
equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application
Report (SPNA207).
Specifications
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Recommended Operating Conditions (1)
5.4
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
NOM
MAX UNIT
VCC
Digital logic supply voltage (Core)
1.14
1.2
1.32
V
VCCIO
Digital logic supply voltage (I/O)
3
3.3
3.6
V
VCCAD
MibADC supply voltage
3
5.25
V
VCCP
Flash pump supply voltage
3
3.6
V
VSS
Digital logic supply ground
VSSAD
MibADC supply ground
VADREFHI
3.3
0
V
–0.1
0.1
V
Analog-to-digital high-voltage reference source
VSSAD
VCCAD
V
VADREFLO
Analog-to-digital low-voltage reference source
VSSAD
VCCAD
V
VSLEW
Maximum positive slew rate for VCCIO, VCCAD and
VCPP supplies
Vhys
Input hysteresis
All inputs
180
VIL
Low-level input voltage
All inputs
–0.3
0.8
VIH
High-level input voltage
All inputs
2
VCCIO + 0.3
V
TA
Operating free-air temperature
–40
105
°C
TJ
Operating junction temperature (2)
–40
130
°C
(1)
(2)
1 V/μs
mV
V
All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD
Reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105°C junction temperature.
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Input/Output Electrical Characteristics Over Recommended Operating Conditions (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
IOL = IOLmax
VOL
Low-level output voltage
IOL = 50 µA, standard output mode
0.2
IOL = 50 µA, low-EMI output mode
(see Section 7.1.2.1)
0.2VCCIO
IOH = IOHmax
VOH
IIC
II
High-level output voltage
Input current (I/O pins)
V
0.8VCCIO
IOH = 50 µA, standard output mode
VCCIO - 0.3
IOH = 50 µA, low-EMI output mode
(see Section 7.1.2.1)
0.8VCCIO
VI < VSSIO - 0.3 or
VI > VCCIO + 0.3
Input clamp current (I/O pins)
MAX UNIT
0.2VCCIO
V
–3.5
3.5
5
40
40
195
IIH Pulldown 20 µA
VI = VCCIO
IIH Pulldown 100 µA
VI = VCCIO
IIL Pullup 20 µA
VI = VSS
–40
–5
IIL Pullup 100 µA
VI = VSS
–195
–40
All other pins
No pullup or pulldown
–1
mA
µA
1
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
(1)
38
Source currents (out of the device) are negative while sink currents (into the device) are positive.
Specifications
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5.6
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Power Consumption Over Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
ICCREFHI
ICCP
(1)
(2)
(3)
(4)
MAX UNIT
260 (2)
fHCLK = 180 MHz
170 (1)
310 (2)
VCC digital supply current (LBIST/PBIST mode)
LBIST/PBIST clock
frequency =
100 MHz
290
(1)
460 (3) (4)
mA
VCCIO digital supply current (operating mode)
No DC load, VCCmax
15
mA
Single ADC
operational,
VCCADmax
15
Both ADCs
operational,
VCCADmax
30
Single ADC
operational,
ADREFHImax
3
Both ADCs
operational,
ADREFHImax
6
ICC
ICCAD
TYP
120 (1)
VCC digital supply current (operating mode)
fVCLK = fHCLK/2; Flash in pipelined mode; VCCmax
ICCIO
MIN
fHCLK = 120 MHz
VCCAD supply current (operating mode)
ADREFHI supply current (operating mode)
Read from 1 bank
and program
another bank,
VCCPmax
VCCP supply current
mA
mA
mA
55
mA
The typical value is the average current for the nominal process corner and junction temperature of 25°C.
The maximum ICC, value can be derated
• linearly with voltage
• by 0.85 mA/MHz for lower operating frequency when fHCLK= 2 * fVCLK
• for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
88 - 0.005 e0.024 TJK
The maximum ICC, value can be derated
• linearly with voltage
• by 0.85 mA/MHz for lower operating frequency
• for lower junction temperature by the equation below where TJK is the junction temperature in Kelvin and the result is in milliamperes.
88 - 0.005 e0.024 TJK
LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the
device and the voltage regulator.
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Thermal Resistance Characteristics
Table 5-1 shows the thermal resistance characteristics for the QFP - PGE mechanical package.
Table 5-2 shows the thermal resistance characteristics for the QFP - PZ mechanical package.
Table 5-1. Thermal Resistance Characteristics (PGE Package)
°C/W
RΘJA
Junction-to-free air thermal resistance, still
air using JEDEC 2S2P test board
37.5
RΘJB
Junction-to-board thermal resistance
19.7
RΘJC
Junction-to-case thermal resistance
9.4
ΨJT
Junction-to-package top, Still air
0.40
Table 5-2. Thermal Resistance Characteristics (PZ Package)
°C/W
40
RΘJA
Junction-to-free air thermal resistance, still
air using JEDEC 2S2P test board
43.5
RΘJB
Junction-to-board thermal resistance
21.6
RΘJC
Junction-to-case thermal resistance
11.2
ΨJT
Junction-to-package top, Still air
0.50
Specifications
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5.8
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Timing and Switching Characteristics
5.8.1
5.8.1.1
SYSCLK (Frequencies)
Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 5-3. Clock Domain Timing Specifications
PARAMETER
DESCRIPTION
CONDITIONS
fGCLK
GCLK - CPU clock frequency
fVCLK4
VCLK4 - Secondary peripheral clock
frequency
PZ
fHCLK
HCLK - System clock frequency
PGE
MIN
MAX
UNIT
fHCLK
MHz
150
MHz
Pipeline mode enabled
120
MHz
Pipeline mode disabled
50
MHz
Pipeline mode enabled
180
MHz
Pipeline mode disabled
50
MHz
fVCLK
VCLK - Primary peripheral clock
frequency
100
MHz
fVCLK2
VCLK2 - Secondary peripheral clock
frequency
100
MHz
fVCLKA1
VCLKA1 - Primary asynchronous
peripheral clock frequency
100
MHz
fRTICLK
RTICLK - Clock frequency
fVCLK
MHz
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Wait States Required - PGE and PZ Packages
RAM
Address Wait States
0
0 MHz
fHCLK(max)
Data Wait States
0
0 MHz
fHCLK(max)
Flash (Main Memory)
Address Wait States
0
1
0 MHz
RWAIT Setting
150MHz
0
0 MHz
Flash (Data Memory)
EWAIT Setting
1
2
50MHz
2
1
0 MHz
45MHz
3
100MHz
3
60MHz
fHCLK(max)
4
75MHz
5
90MHz
6
105MHz
7
120MHz
150MHz
fHCLK(max)
150MHz
9
10
165MHz fHCLK(max)
8
135MHz
Figure 5-1. Wait States Scheme — PGE, 180 MHz
RAM
Address Wait States
0
0 MHz
fHCLK(max)
0
Data Wait States
0 MHz
fHCLK(max)
Flash (Main Memory)
Address Wait States
0
0 MHz
RWAIT Setting
fHCLK(max)
1
0
0 MHz
Flash (Data Memory)
EWAIT Setting
1
0 MHz
2
50MHz
100MHz
2
45MHz
3
60MHz
4
75MHz
fHCLK(max)
5
90MHz
105MHz
6
fHCLK(max)
Figure 5-2. Wait States Scheme — PZ, 120 MHz
As shown in Figure 5-1 and Figure 5-2, the TCM RAM can support program and data fetches at full CPU
speed without any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in
nonpipelined mode. The flash supports a maximum CPU clock speed of 180 MHz in pipelined mode for
the PGE Package, and 120 MHz for the PZ package.
The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data
wait state.
42
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SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
6 System Information and Electrical Specifications
6.1
Device Power Domains
The device core logic is split up into multiple power domains to optimize the power for a given application
use case. There are five core power domains: PD1, PD2, PD3, PD5, and RAM_PD1. See Section 1.4 for
more information.
PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains
can be turned ON/OFF one time during device initialization as per the application requirement. Refer to
the Power Management Module (PMM) chapter of the device technical reference manual for more details.
NOTE
The clocks to a module must be turned off before powering down the core domain that
contains the module.
6.2
Voltage Monitor Characteristics
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the
requirement for a specific sequence when powering up the core and I/O voltage supplies.
6.2.1
Important Considerations
•
•
6.2.2
The voltage monitor does not eliminate the need of a voltage supervisor circuit to ensure that the device is held in
reset when the voltage supplies are out of range.
The voltage monitor only monitors the core supply (VCC) and the I/O supply (VCCIO). The other supplies are not
monitored by the VMON. For example, if the VCCAD or VCCP are supplied from a source different from that for
VCCIO, then there is no internal voltage monitor for the VCCAD and VCCP supplies.
Voltage Monitor Operation
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO
signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when
the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and
PGMCU signals being low isolates the core logic as well as the I/O controls during power up or power
down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When
the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output
pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device
enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing
information on this glitch filter.
Table 6-1. Voltage Monitoring Specifications
PARAMETER
VMON
Voltage monitoring
thresholds
MIN
TYP
MAX
VCC low - VCC level below this
threshold is detected as too low.
0.75
0.9
1.13
VCC high - VCC level above this
threshold is detected as too high.
1.40
1.7
2.1
VCCIO low - VCCIO level below this
threshold is detected as too low.
1.85
2.4
2.9
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UNIT
V
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Supply Filtering
The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the
maximum specification cannot be filtered.
Table 6-2. VMON Supply Glitch Filtering Capability
PARAMETER
6.3
6.3.1
MIN
MAX
UNIT
Width of glitch on VCC that can be filtered
250
1000
ns
Width of glitch on VCCIO that can be filtered
250
1000
ns
Power Sequencing and Power-On Reset
Power-Up Sequence
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The powerup sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for
more details), core voltage rising above the minimum core supply threshold and the release of power-on
reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The
oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The
different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Table 6-3. Power-Up Phases
Oscillator start-up and validity check
1032 oscillator cycles
eFuse autoload
1160 oscillator cycles
Flash pump power-up
688 oscillator cycles
Flash bank power-up
617 oscillator cycles
Total
3497 oscillator cycles
The CPU reset is released at the end of the above sequence and fetches the first instruction from address
0x00000000.
6.3.2
Power-Down Sequence
The different supplies to the device can be powered down in any order.
44
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6.3.3
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Power-On Reset: nPORRST
This is the power-on reset. This reset must be asserted by an external circuitry whenever any power
supply is outside the specified recommended range. This signal has a glitch filter on it. It also has an
internal pulldown.
6.3.3.1
nPORRST Electrical and Timing Requirements
Table 6-4. Electrical Requirements for nPORRST
NO.
MIN
MAX
UNIT
VCCPORL
VCC low supply level when nPORRST must be active during power up
VCCPORH
VCC high supply level when nPORRST must remain active during power
up and become active during power down
0.5
V
VCCIOPORL
VCCIO / VCCP low supply level when nPORRST must be active during
power up
VCCIOPORH
VCCIO / VCCP high supply level when nPORRST must remain active
during power up and become active during power down
VIL(PORRST)
Low-level input voltage of nPORRST VCCIO > 2.5 V
0.2 * VCCIO
V
Low-level input voltage of nPORRST VCCIO < 2.5 V
0.5
V
1.14
V
1.1
V
3.0
V
3
tsu(PORRST)
Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during
power up
6
th(PORRST)
Hold time, nPORRST active after VCC > VCCPORH
1
7
tsu(PORRST)
Setup time, nPORRST active before VCC < VCCPORH during power down
2
µs
8
th(PORRST)
Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH
1
ms
9
th(PORRST)
Hold time, nPORRST active after VCC < VCCPORL
0
ms
tf(nPORRST)
Filter
time
nPORRST
pin;
pulses less than MIN will be filtered out, pulses greater than MAX will
generate a reset.
3.3 V
VCCIOPORH
0
ms
ms
475
2000
ns
VCCIOPORH
VCCIO / VCCP
8
1.2 V
VCC
VCCPORH
6
VCCPORH
7
6
VCCIOPORL
7
VCCPORL
VCCPORL
VCCIOPORL
VCC (1.2 V)
VCCIO / VCCP (3.3 V)
3
nPORRST
A.
9
VIL(PORRST)
VIL
VIL
VIL
VIL
VIL(PORRST)
Figure 6-1 shows that there is no timing dependency between the ramp of the VCCIO and the VCC supply voltages.
Figure 6-1. nPORRST Timing Diagram(A)
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Warm Reset (nRST)
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset
condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the
output buffer is implemented as an open drain (drives low only). To ensure an external reset is not
arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
6.4.1
Causes of Warm Reset
Table 6-5. Causes of Warm Reset
DEVICE EVENT
SYSTEM STATUS FLAG
Power-Up Reset
Exception Status Register, bit 15
Oscillator fail
Global Status Register, bit 0
PLL slip
Global Status Register, bits 8 and 9
Watchdog exception / Debugger reset
Exception Status Register, bit 13
CPU Reset (driven by the CPU STC)
Exception Status Register, bit 5
Software Reset
Exception Status Register, bit 4
External Reset
Exception Status Register, bit 3
6.4.2
nRST Timing Requirements
Table 6-6. nRST Timing Requirements (1)
MIN
Valid time, nRST active after nPORRST inactive
tv(RST)
tf(nRST)
(1)
46
Valid time, nRST active (all other System reset
conditions)
MAX
UNIT
2256tc(OSC)
ns
32tc(VCLK)
Filter
time
nRST
pin;
pulses less than MIN will be filtered out, pulses greater
than MAX will generate a reset
475
2000
ns
Specified values do not include rise/fall times. For rise and fall timings, see Table 7-2.
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6.5
6.5.1
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
ARM Cortex-R4F CPU Information
Summary of ARM Cortex-R4F CPU Features
The features of the ARM Cortex-R4F CPU include:
• An integer unit with integral EmbeddedICE-RT logic.
• High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI)
for Level two (L2) master and slave interfaces.
• Floating-Point Coprocessor
• Dynamic branch prediction with a global history buffer, and a 4-entry return stack
• Low interrupt latency.
• Nonmaskable interrupt.
• A Harvard Level one (L1) memory system with:
– Tightly-Coupled Memory (TCM) interfaces with support for error correction or parity checking
memories
– ARMv7-R architecture Memory Protection Unit (MPU) with 12 regions
• Dual core logic for fault detection in safety-critical applications.
• An L2 memory interface:
– Single 64-bit master AXI interface
– 64-bit slave AXI interface to TCM RAM blocks
• A debug interface to a CoreSight Debug Access Port (DAP).
• Six Hardware Breakpoints
• Two Watchpoints
• A Performance Monitoring Unit (PMU).
• A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4F CPU, see www.arm.com.
6.5.2
ARM Cortex-R4F CPU Features Enabled by Software
The following CPU features are disabled on reset and must be enabled by the application if required.
• ECC On Tightly-Coupled Memory (TCM) Accesses
• Hardware Vectored Interrupt (VIC) Port
• Floating-Point Coprocessor
• Memory Protection Unit (MPU)
6.5.3
Dual Core Implementation
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCMR4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two
clock cycles as shown in Figure 6-2.
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Output + Control
CCM-R4
2 cycle delay
CCM-R4
compare
CPU1CLK
CPU 1
compare
error
CPU 2
2 cycle delay
CPU2CLK
Input + Control
Figure 6-2. Dual Core Implementation
The CPUs have a diverse CPU placement given by following requirements:
different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation
dedicated guard ring for each CPU
North
F
Flip West
F
•
•
Figure 6-3. Dual-CPU Orientation
6.5.4
Duplicate Clock Tree After GCLK
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU
running at the same frequency and in phase to the clock of CPU1. See Figure 6-2.
6.5.5
ARM Cortex-R4F CPU Compare Module (CCM) for Safety
This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in
the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in
a different way as shown in Figure 6-2.
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of
both CPUs before the registers are used, including function calls where the register values are pushed
onto the stack.
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6.5.6
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test as well as running few intervals at a time
• Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
• Complete isolation of the self-tested CPU core from rest of the system during the self-test run
• Ability to capture the Failure interval number
• Time-out counter for the CPU self-test run as a fail-safe feature
6.5.6.1
1.
2.
3.
4.
5.
6.
7.
Application Sequence for CPU Self-Test
Configure clock domain frequencies.
Select number of test intervals to be run.
Configure the time-out period for the self-test run.
Enable self-test.
Wait for CPU reset.
In the reset handler, read CPU self-test status to identify any failures.
Retrieve CPU state if required.
For more information see the device Technical Reference Manual.
6.5.6.2
CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is HCLKmax/2. The STCCLK is divided down from the CPU
clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the device-specific Technical Reference Manual.
6.5.6.3
CPU Self-Test Coverage
Table 6-7 lists the CPU self-test coverage achieved for each self-test interval. It also lists the cumulative
test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock
period.
Table 6-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
STCCLK CYLCES
0
0
0
1
62.13
1365
2
70.09
2730
3
74.49
4095
4
77.28
5460
5
79.28
6825
6
80.90
8190
7
82.02
9555
8
83.10
10920
9
84.08
12285
10
84.87
13650
11
85.59
15015
12
86.11
16380
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Table 6-7. CPU Self-Test Coverage (continued)
50
INTERVALS
TEST COVERAGE, %
STCCLK CYLCES
13
86.67
17745
14
87.16
19110
15
87.61
20475
16
87.98
21840
17
88.38
23205
18
88.69
24570
19
88.98
25935
20
89.28
27300
21
89.50
28665
22
89.76
30030
23
90.01
31395
24
90.21
32760
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6.6
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Clocks
6.6.1
Clock Sources
Table 6-8 lists the available clock sources on the device. Each clock source can be enabled or disabled
using the CSDISx registers in the system module. The clock source number in the table corresponds to
the control bit in the CSDISx register for that clock source.
Table 6-8 also shows the default state of each clock source.
Table 6-8. Available Clock Sources
CLOCK
SOURCE NO.
NAME
0
OSCIN
1
PLL1
DEFAULT STATE
Main oscillator
Enabled
Output from PLL1
Disabled
Reserved
Disabled
External clock input 1
Disabled
2
Reserved
3
EXTCLKIN1
4
LFLPO
Low-frequency output of internal reference oscillator
Enabled
HFLPO
High-frequency output of internal reference
oscillator
Enabled
Reserved
Disabled
External clock input 2
Disabled
5
6.6.1.1
DESCRIPTION
6
Reserved
7
EXTCLKIN2
Main Oscillator
The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors
across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single-stage
inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test
measurement and low power modes.
NOTE
TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine which load
capacitors will best tune their resonator/crystal to the microcontroller device for optimum
start-up and operation over temperature and voltage extremes.
An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving
the OSCOUT pin unconnected (open) as shown in Figure 6-4.
OSCIN
(see Note B)
Kelvin_GND
C1
OSCIN
OSCOUT
OSCOUT
C2
(see Note A)
External
Clock Signal
(toggling 0 V to 3.3 V)
Crystal
(a)
(b)
Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Note B: Kelvin_GND should not be connected to any other GND.
Figure 6-4. Recommended Crystal/Clock Connection
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6.6.1.1.1 Timing Requirements for Main Oscillator
Table 6-9. Timing Requirements for Main Oscillator
MIN
NOM
MAX
UNIT
200
ns
tc(OSC)
Cycle time, OSCIN (when using a sine-wave input)
50
tw(OSCIL)
Pulse duration, OSCIN low (when input to the OSCIN
is a square wave)
15
ns
tw(OSCIH)
Pulse duration, OSCIN high (when input to the OSCIN
is a square wave)
15
ns
6.6.1.2
Low-Power Oscillator
The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single
macro.
6.6.1.2.1 Features
The main features of the LPO are:
• Supplies a clock at extremely low power for power-saving modes. This is connected as clock source 4
of the Global Clock Module (GCM).
• Supplies a high-frequency clock for non-timing-critical systems. This is connected as clock source 5 of
the GCM.
• Provides a comparison clock for the crystal oscillator failure detection circuit.
BIAS_EN
LFLPO
LFEN
LF_TRIM
HFEN
Low-Power
Oscillator
HF_TRIM
HFLPO
HFLPO_VALID
nPORRST
Figure 6-5. LPO Block Diagram
Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low-power oscillator (LPO)
and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.
52
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6.6.1.2.2 LPO Electrical and Timing Specifications
Table 6-10. LPO Specifications
PARAMETER
Clock detection
LPO - HF oscillator
MIN
TYP
MAX
UNIT
1.375
2.4
4.875
MHz
Oscillator fail frequency - higher threshold, using untrimmed
LPO output
22
38.4
78
MHz
Untrimmed frequency
5.5
9
19.5
MHz
8
9.6
11
MHz
10
µs
Oscillator fail frequency - lower threshold, using untrimmed
LPO output
Trimmed frequency
Start-up time from STANDBY (LPO BIAS_EN high for at
least 900 µs)
Cold start-up time
LPO - LF oscillator
Untrimmed frequency
36
900
µs
180
kHz
100
µs
2000
µs
85
Start-up time from STANDBY (LPO BIAS_EN high for at
least 900 µs)
Cold start-up time
6.6.1.3
Phase-Locked Loop (PLL) Clock Module
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
• Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1.
• Configurable frequency multipliers and dividers
• Built-in PLL Slip monitoring circuit
• Option to reset the device on a PLL slip detection
6.6.1.3.1 Block Diagram
Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.
OSCIN
/NR
INTCLK
VCOCLK
PLL
/1 to /64
/OD
/R
post_ODCLK
/1 to /8
/NF
PLLCLK
/1 to /32
fPLLCLK = (fOSCIN / NR) * NF / (OD * R)
/1 to /256
Figure 6-6. PLL Block Diagram
6.6.1.3.2 PLL Timing Specifications
Table 6-11. PLL Timing Specifications
PARAMETER
fINTCLK
PLL1 Reference Clock frequency
fpost_ODCLK
Post-ODCLK – PLL1 Post-divider input clock frequency
fVCOCLK
VCOCLK – PLL1 Output Divider (OD) input clock frequency
MIN
MAX
UNIT
1
20
MHz
400
MHz
550
MHz
150
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External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square-wave input.
Table 6-12 specifies the electrical and timing requirements for these clock inputs. The external clock
sources are not checked for validity. They are assumed valid when enabled.
Table 6-12. External Clock Timing and Electrical Specifications
PARAMETER
MIN
MAX
UNIT
80
MHz
fEXTCLKx
External clock input frequency
tw(EXTCLKIN)H
EXTCLK high-pulse duration
6
ns
tw(EXTCLKIN)L
EXTCLK low-pulse duration
6
ns
viL(EXTCLKIN)
Low-level input voltage
–0.3
0.8
V
viH(EXTCLKIN)
High-level input voltage
2
VCCIO + 0.3
V
6.6.2
Clock Domains
6.6.2.1
Clock Domain Descriptions
Table 6-13 lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Table 6-13. Clock Domain Descriptions
CLOCK
DOMAIN
DEFAULT
SOURCE
SOURCE
SELECTION
REGISTER
HCLK
OSCIN
GHVSRC
GCLK
OSCIN
GHVSRC
SPECIAL CONSIDERATIONS
•
•
Is disabled through the CDDISx registers bit 1
Used for all system modules including DMA,
ESM
•
•
•
Always the same frequency as HCLK
In phase with HCLK
Is disabled separately from HCLK through the
CDDISx registers bit 0
Can be divided by 1 up to 8 when running CPU
self-test (LBIST) using the CLKDIV field of the
STCCLKDIV register at address 0xFFFFE108
•
GCLK2
VCLK
VCLK2
OSCIN
OSCIN
OSCIN
GHVSRC
GHVSRC
GHVSRC
•
•
•
•
Always the same frequency as GCLK
2 cycles delayed from GCLK
Is disabled along with GCLK
Gets divided by the same divider setting as
that for GCLK when running CPU self-test
(LBIST)
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the
CDDISx registers bit 2
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Frequency must be an integer multiple of
VCLK frequency
Is disabled separately from HCLK through the
CDDISx registers bit 3
•
VCLK4
54
OSCIN
GHVSRC
•
•
•
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK through the
CDDISx registers bit 9
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Table 6-13. Clock Domain Descriptions (continued)
CLOCK
DOMAIN
DEFAULT
SOURCE
SOURCE
SELECTION
REGISTER
VCLKA1
VCLK
VCLKASRC
RTICLK
VCLK
SPECIAL CONSIDERATIONS
•
•
Defaults to VCLK as the source
Is disabled through the CDDISx registers bit 4
•
•
Defaults to VCLK as the source
If a clock source other than VCLK is selected
for RTICLK, then the RTICLK frequency must
be less than or equal to VCLK/3
– Application can ensure this by
programming the RTI1DIV field of the
RCLKSRC register, if necessary
Is disabled through the CDDISx registers bit 6
RCLKSRC
•
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Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in Figure 6-7 .
GCM
0
OSCIN
PLL #1
/1..64
X1..256
Low-Power
Oscillator
/1..32
/1..8
1
*
80 kHz
4
10 MHz
5
/1..16
3
EXTCLKIN1
/1..16
VCLK2 (to N2HETx and HTUx)
/1..16
VCLK4 (ePWM, eQEP, eCAP)
0
1
3
4
5
6
7
VCLK
7
EXTCLKIN2
HCLK (to SYSTEM)
VCLK _peri (VCLK to peripherals on PCR1)
VCLK_sys (VCLK to system modules)
6
Reserved
* the frequency at this node must not
exceed the maximum HCLK specification.
GCLK, GCLK2 (to CPU)
(FMzPLL)
0
1
3
4
5
6
7
VCLKA1 (to DCANx)
/1, 2, 4, or 8
RTICLK (to RTI, DWWD)
VCLK
VCLKA1
VCLK
VCLK2
VCLK2
/1,2,..1024
/1,2,..256
/2,3..224
/1,2..32
/1,2..65536
HRP
/1..64
/1,2..256
N2HETx
TU
Prop_seg
Phase_seg2
SPI
Baud Rate
LIN / SCI
Baud Rate
ADCLK
ECLK
I2C baud
rate
LIN, SCI
MibADCx
External Clock
I2C
Phase_seg1
SPIx,MibSPIx
EXTCLKIN
1
CAN Baud Rate
DCANx
Reserved
Reserved
Reserved
NTU[3]
NTU[2]
NTU[1]
RTI
LRP
/20 ..2 5
Loop
High
Resolution Clock
N2HETx
NTU[0]
Figure 6-7. Device Clock Domains
56
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6.6.3
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Clock Test Mode
The RM4x platform architecture defines a special mode that allows various clock signals to be selected
and output on the ECLK pin and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very
useful for debugging purposes and can be configured through the CLKTEST register in the system
module. See Table 6-14 for the CLKTEST bits value and signal selection.
Table 6-14. Clock Test Mode Options
SEL_ECP_PIN
=
CLKTEST[4-0]
SIGNAL ON ECLK
SEL_GIO_PIN
=
CLKTEST[11-8]
SIGNAL ON N2HET1[12]
00000
Oscillator
0000
Oscillator Valid Status
00001
Main PLL free-running clock output
0001
Main PLL Valid status
00010
Reserved
0010
Reserved
00011
EXTCLKIN1
0011
Reserved
00100
LFLPO
0100
Reserved
00101
HFLPO
0101
HFLPO Valid status
00110
Reserved
0110
Reserved
00111
EXTCLKIN2
0111
Reserved
01000
GCLK
1000
LFLPO
01001
RTI Base
1001
Oscillator Valid status
01010
Reserved
1010
Oscillator Valid status
01011
VCLKA1
1011
Oscillator Valid status
01100
Reserved
1100
Oscillator Valid status
01101
Reserved
1101
Reserved
01110
Reserved
1110
Reserved
01111
Reserved
1111
Oscillator Valid status
10000
Reserved
10001
HCLK
10010
VCLK
10011
VCLK2
10100
Reserved
10101
VCLK4
10110
Reserved
10111
Reserved
11000
Reserved
Others
Reserved
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6.7
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Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.
The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp
mode clock).
The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.
6.7.1
Clock Monitor Timings
For more information on LPO and Clock detection, see Table 6-10.
fail
lower
threshold
1.375
upper
threshold
pass
4.875
22
fail
78
f[MHz]
Figure 6-8. LPO and Clock Detection, Untrimmed HFLPO
6.7.2
External Clock (ECLK) Output Functionality
The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock.
This output can be externally monitored as a safety diagnostic.
6.7.3
Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
An additional use of this module is to measure the frequency of a selectable clock source, using the input
clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a
fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width
pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1
does not reach 0 within the counting window generated by counter 0.
6.7.3.1
•
•
•
•
58
Features
Takes two different clock sources as input to two independent counter blocks.
One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
Each counter block is programmable with initial, or seed values.
The counter blocks start counting down from their seed values at the same time; a mismatch from the expected
frequency for the clock under test generates an error signal which is used to interrupt the CPU.
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6.7.3.2
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Mapping of DCC Clock Source Inputs
Table 6-15. DCC1 Counter 0 Clock Sources
CLOCK SOURCE[3:0]
CLOCK NAME
Others
Oscillator (OSCIN)
0x5
High-frequency LPO
0xA
Test clock (TCK)
Table 6-16. DCC1 Counter 1 Clock Sources
KEY[3:0]
CLOCK SOURCE[3:0]
Others
–
N2HET1[31]
0x0
Main PLL free-running clock
output
0xA
CLOCK NAME
0x1
Reserved
0x2
Low-frequency LPO
0x3
High-frequency LPO
0x4
Reserved
0x5
EXTCLKIN1
0x6
EXTCLKIN2
0x7
Reserved
0x8 - 0xF
VCLK
Table 6-17. DCC2 Counter 0 Clock Sources
CLOCK SOURCE [3:0]
CLOCK NAME
Others
Oscillator (OSCIN)
0xA
Test clock (TCK)
Table 6-18. DCC2 Counter 1 Clock Sources
KEY [3:0]
CLOCK SOURCE [3:0]
CLOCK NAME
Others
–
N2HET2[0]
0xA
00x0 - 0x7
Reserved
0x8 - 0xF
VCLK
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Glitch Filters
A glitch filter is present on the following signals.
Table 6-19. Glitch Filter Timing Specifications
PIN
60
MIN
MAX
UNIT
tf(nPORRST)
Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses
greater than MAX will generate a reset (1)
475
2000
ns
nRST
tf(nRST)
Filter time nRST pin; pulses less than MIN will be filtered out, pulses
greater than MAX will generate a reset
475
2000
ns
TEST
tf(TEST)
Filter time TEST pin; pulses less than MIN will be filtered out, pulses
greater than MAX will pass through
475
2000
ns
nPORRST
(1)
PARAMETER
The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump,
I/O pins, and so forth) without also generating a valid reset signal to the CPU.
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6.9
6.9.1
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Device Memory Map
Memory Map Diagram
Figure 6-9 shows the device memory map.
0xFFFFFFFF
SYSTEM Modules
0xFFF80000
Peripherals - Frame 1
0xFF000000
0xFE000000
CRC
RESERVED
0xFCFFFFFF
0xFC000000
Peripherals - Frame 2
RESERVED
0xF07FFFFF
Flash Module Bus2 Interface
(Flash ECC, OTP and
EEPROM Emulation accesses)
0xF0000000
RESERVED
0x200FFFFF
Flash (1MB) (Mirrored Image)
0x20000000
RESERVED
0x0841FFFF
0x08400000
RAM - ECC
RESERVED
0x0801FFFF
0x08000000
RAM (128KB)
RESERVED
0x000FFFFF
Flash (1MB)
0x00000000
Figure 6-9. Memory Map
The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash
image is 0x2000 0000.
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Memory Map Table
See Figure 1-1 for block diagrams showing the devices interconnect.
Table 6-20. Device Memory Map
FRAME ADDRESS RANGE
MODULE NAME
FRAME CHIP
SELECT
TCM Flash
CS0
0x0000_0000
0x00FF_FFFF
16MB
1MB
TCM RAM + RAM ECC
CSRAM0
0x0800_0000
0x0BFF_FFFF
64MB
128KB
Mirrored Flash
Flash mirror frame
0x2000_0000
0x20FF_FFFF
16MB
1MB
START
END
FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
Memories tightly coupled to the ARM Cortex-R4F CPU
Abort
Flash Module Bus2 Interface
Customer OTP, TCM
Flash Banks
0xF000_0000
0xF000_1FFF
8KB
4KB
Customer OTP,
Bank 7
0xF000_E000
0xF000_FFFF
8KB
1KB
Customer OTP–ECC,
TCM Flash Banks
0xF004_0000
0xF004_03FF
1KB
512B
Customer OTP–ECC,
Bank 7
0xF004_1C00
0xF004_1FFF
1KB
128B
TI OTP, TCM Flash
Banks
0xF008_0000
0xF008_1FFF
8KB
4KB
TI OTP,
Bank 7
0xF008_E000
0xF008_FFFF
8KB
1KB
TI OTP–ECC, TCM
Flash Banks
0xF00C_0000
0xF00C_03FF
1KB
512B
TI OTP–ECC,
Bank 7
0xF00C_1C00
0xF00C_1FFF
1KB
128B
Bank 7 – ECC
0xF010_0000
0xF013_FFFF
256KB
8KB
Bank 7
0xF020_0000
0xF03F_FFFF
2MB
64KB
Flash Data Space ECC
0xF040_0000
0xF04F_FFFF
1MB
128KB
Abort
SCR5: Enhanced Timer Peripherals
ePWM1
0xFCF7_8C00
0xFCF7_8CFF
256B
256B
Abort
ePWM2
0xFCF7_8D00
0xFCF7_8DFF
256B
256B
Abort
ePWM3
0xFCF7_8E00
0xFCF7_8EFF
256B
256B
Abort
ePWM4
0xFCF7_8F00
0xFCF7_8FFF
256B
256B
Abort
ePWM5
0xFCF7_9000
0xFCF7_90FF
256B
256B
Abort
ePWM6
0xFCF7_9100
0xFCF7_91FF
256B
256B
Abort
ePWM7
0xFCF7_9200
0xFCF7_92FF
256B
256B
Abort
eCAP1
0xFCF7_9300
0xFCF7_93FF
256B
256B
Abort
eCAP2
0xFCF7_9400
0xFCF7_94FF
256B
256B
Abort
eCAP3
0xFCF7_9500
0xFCF7_95FF
256B
256B
Abort
eCAP4
0xFCF7_9600
0xFCF7_96FF
256B
256B
Abort
eCAP5
0xFCF7_9700
0xFCF7_97FF
256B
256B
Abort
eCAP6
0xFCF7_9800
0xFCF7_98FF
256B
256B
Abort
eQEP1
0xFCF7_9900
0xFCF7_99FF
256B
256B
Abort
eQEP2
0xFCF7_9A00
0xFCF7_9AFF
256B
256B
Abort
Cyclic Redundancy Checker (CRC) Module Registers
CRC
CRC frame
0xFE00_0000
0xFEFF_FFFF
16MB
512B
Accesses above 0x200 generate abort.
Peripheral Memories
62
MIBSPI5 RAM
PCS[5]
0xFF0A_0000
0xFF0B_FFFF
128KB
2KB
Abort for accesses above 2KB
MIBSPI3 RAM
PCS[6]
0xFF0C_0000
0xFF0D_FFFF
128KB
2KB
Abort for accesses above 2KB
MIBSPI1 RAM
PCS[7]
0xFF0E_0000
0xFF0F_FFFF
128KB
2KB
Abort for accesses above 2KB
DCAN3 RAM
PCS[13]
0xFF1A_0000
0xFF1B_FFFF
128KB
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
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Table 6-20. Device Memory Map (continued)
MODULE NAME
FRAME CHIP
SELECT
START
FRAME ADDRESS RANGE
END
FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
DCAN2 RAM
PCS[14]
0xFF1C_0000
0xFF1D_FFFF
128KB
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
DCAN1 RAM
PCS[15]
0xFF1E_0000
0xFF1F_FFFF
128KB
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
MIBADC2
Look-Up Table
384B
Look-Up Table for ADC2 wrapper. Starts
at address offset 0x2000 and ends at
address offset 0x217F. Wrap around for
accesses between offsets 0x0180 and
0x3FFF. Abort generated for accesses
beyond offset 0x4000.
MIBADC1 RAM
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
384B
Look-Up Table for ADC1 wrapper. Starts
at address offset 0x2000 and ends at
address offset 0x217F. Wrap around for
accesses between offsets 0x0180 and
0x3FFF. Abort generated for accesses
beyond offset 0x4000.
MIBADC2 RAM
PCS[29]
PCS[31]
0xFF3A_0000
0xFF3E_0000
0xFF3B_FFFF
0xFF3F_FFFF
128KB
128KB
MibADC1
Look-Up Table
N2HET2 RAM
PCS[34]
0xFF44_0000
0xFF45_FFFF
128KB
16KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
N2HET1 RAM
PCS[35]
0xFF46_0000
0xFF47_FFFF
128KB
16KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
N2HET2 TU2 RAM
PCS[38]
0xFF4C_0000
0xFF4D_FFFF
128KB
1KB
Abort
N2HET1 TU1 RAM
PCS[39]
0xFF4E_0000
0xFF4F_FFFF
128KB
1KB
Abort
Debug Components
CoreSight Debug ROM
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
4KB
Reads return zeros, writes have no effect
Cortex-R4F Debug
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4KB
4KB
Reads return zeros, writes have no effect
Peripheral Control Registers
HTU1
PS[22]
0xFFF7_A400
0xFFF7_A4FF
256B
256B
Reads return zeros, writes have no effect
HTU2
PS[22]
0xFFF7_A500
0xFFF7_A5FF
256B
256B
Reads return zeros, writes have no effect
N2HET1
PS[17]
0xFFF7_B800
0xFFF7_B8FF
256B
256B
Reads return zeros, writes have no effect
N2HET2
PS[17]
0xFFF7_B900
0xFFF7_B9FF
256B
256B
Reads return zeros, writes have no effect
GIO
PS[16]
0xFFF7_BC00
0xFFF7_BDFF
512B
256B
Reads return zeros, writes have no effect
MIBADC1
PS[15]
0xFFF7_C000
0xFFF7_C1FF
512B
512B
Reads return zeros, writes have no effect
MIBADC2
PS[15]
0xFFF7_C200
0xFFF7_C3FF
512B
512B
Reads return zeros, writes have no effect
I2C
PS[10]
0xFFF7_D400
0xFFF7_D4FF
256B
256B
Reads return zeros, writes have no effect
DCAN1
PS[8]
0xFFF7_DC00
0xFFF7_DDFF
512B
512B
Reads return zeros, writes have no effect
DCAN2
PS[8]
0xFFF7_DE00
0xFFF7_DFFF
512B
512B
Reads return zeros, writes have no effect
DCAN3
PS[7]
0xFFF7_E000
0xFFF7_E1FF
512B
512B
Reads return zeros, writes have no effect
LIN
PS[6]
0xFFF7_E400
0xFFF7_E4FF
256B
256B
Reads return zeros, writes have no effect
SCI
PS[6]
0xFFF7_E500
0xFFF7_E5FF
256B
256B
Reads return zeros, writes have no effect
MibSPI1
PS[2]
0xFFF7_F400
0xFFF7_F5FF
512B
512B
Reads return zeros, writes have no effect
SPI2
PS[2]
0xFFF7_F600
0xFFF7_F7FF
512B
512B
Reads return zeros, writes have no effect
MibSPI3
PS[1]
0xFFF7_F800
0xFFF7_F9FF
512B
512B
Reads return zeros, writes have no effect
SPI4
PS[1]
0xFFF7_FA00
0xFFF7_FBFF
512B
512B
Reads return zeros, writes have no effect
MibSPI5
PS[0]
0xFFF7_FC00
0xFFF7_FDFF
512B
512B
Reads return zeros, writes have no effect
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Table 6-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
MODULE NAME
FRAME CHIP
SELECT
START
DMA RAM
PPCS0
0xFFF8_0000
END
FRAME
SIZE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
System Modules Control Registers and Memories
VIM RAM
PPCS2
0xFFF8_2000
0xFFF8_0FFF
4KB
4KB
Abort
0xFFF8_2FFF
4KB
1KB
Wrap around for accesses to
unimplemented address offsets between
1KB and 4KB.
Flash Module
PPCS7
0xFFF8_7000
0xFFF8_7FFF
4KB
4KB
Abort
eFuse Controller
PPCS12
0xFFF8_C000
0xFFF8_CFFF
4KB
4KB
Abort
Power Management
Module (PMM)
PPSE0
0xFFFF_0000
0xFFFF_01FF
512B
512B
Abort
PCR registers
PPS0
0xFFFF_E000
0xFFFF_E0FF
256B
256B
Reads return zeros, writes have no effect
System Module Frame 2
(see device TRM)
PPS0
0xFFFF_E100
0xFFFF_E1FF
256B
256B
Reads return zeros, writes have no effect
PBIST
PPS1
0xFFFF_E400
0xFFFF_E5FF
512B
512B
Reads return zeros, writes have no effect
STC
PPS1
0xFFFF_E600
0xFFFF_E6FF
256B
256B
Generates address error interrupt, if
enabled
IOMM Multiplexing
Control Module
PPS2
0xFFFF_EA00
0xFFFF_EBFF
512B
512B
Reads return zeros, writes have no effect
DCC1
PPS3
0xFFFF_EC00
0xFFFF_ECFF
256B
256B
Reads return zeros, writes have no effect
DMA
PPS4
0xFFFF_F000
0xFFFF_F3FF
1KB
1KB
Reads return zeros, writes have no effect
DCC2
PPS5
0xFFFF_F400
0xFFFF_F4FF
256B
256B
Reads return zeros, writes have no effect
ESM
PPS5
0xFFFF_F500
0xFFFF_F5FF
256B
256B
Reads return zeros, writes have no effect
CCMR4
PPS5
0xFFFF_F600
0xFFFF_F6FF
256B
256B
Reads return zeros, writes have no effect
RAM ECC even
PPS6
0xFFFF_F800
0xFFFF_F8FF
256B
256B
Reads return zeros, writes have no effect
RAM ECC odd
PPS6
0xFFFF_F900
0xFFFF_F9FF
256B
256B
Reads return zeros, writes have no effect
RTI + DWWD
PPS7
0xFFFF_FC00
0xFFFF_FCFF
256B
256B
Reads return zeros, writes have no effect
VIM Parity
PPS7
0xFFFF_FD00
0xFFFF_FDFF
256B
256B
Reads return zeros, writes have no effect
VIM
PPS7
0xFFFF_FE00
0xFFFF_FEFF
256B
256B
Reads return zeros, writes have no effect
System Module Frame 1
(see device TRM)
PPS7
0xFFFF_FF00
0xFFFF_FFFF
256B
256B
Reads return zeros, writes have no effect
6.9.3
Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an
imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to
handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program
status register (CPSR).
64
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6.9.4
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Master/Slave Access Privileges
Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that
can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. Yes indicates that the module listed in
the MASTERS column can access that slave module.
Table 6-21. Master / Slave Access Matrix
MASTERS
ACCESS MODE
SLAVES ON MAIN SCR
Flash Module
Bus2 Interface:
OTP, ECC, Bank
7
Non-CPU
Accesses to
Program Flash
and CPU Data
RAM
CRC
Slave Interfaces
Peripheral
Control
Registers, All
Peripheral
Memories, And
All System
Module Control
Registers And
Memories
CPU READ
User/Privilege
Yes
Yes
Yes
Yes
Yes
CPU WRITE
User/Privilege
No
Yes
Yes
Yes
Yes
DMA
User
Yes
Yes
Yes
Yes
Yes
6.9.5
DAP
Privilege
Yes
Yes
Yes
Yes
Yes
HTU1
Privilege
No
Yes
Yes
Yes
Yes
HTU2
Privilege
No
Yes
Yes
Yes
Yes
Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned off.
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6.10 Flash Memory
6.10.1 Flash Memory Configuration
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a
customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense
amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical
construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or
erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
Table 6-22. Flash Memory Banks and Sectors
MEMORY ARRAYS (OR BANKS)
BANK0 (1MB) (1)
BANK7 (64KB) for EEPROM emulation (3) (4) (5)
(1)
(2)
(3)
(4)
(5)
66
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
16KB
0x0000_0000
0x0000_3FFF
1
16KB
0x0000_4000
0x0000_7FFF
2
16KB
0x0000_8000
0x0000_BFFF
3
16KB
0x0000_C000
0x0000_FFFF
4
16KB
0x0001_0000
0x0001_3FFF
5
16KB
0x0001_4000
0x0001_7FFF
6
32KB
0x0001_8000
0x0001_FFFF
7
128KB
0x0002_0000
0x0003_FFFF
8
128KB
0x0004_0000
0x0005_FFFF
9
128KB
0x0006_0000
0x0007_FFFF
10
128KB
0x0008_0000
0x0009_FFFF
11
128KB
0x000A_0000
0x000B_FFFF
12 (2)
128KB
0x000C_0000
0x000D_FFFF
13 (2)
128KB
0x000E_0000
0x000F_FFFF
0
4KB
0xF020_0000
0xF020_0FFF
1
4KB
0xF020_1000
0xF020_1FFF
2
4KB
0xF020_2000
0xF020_2FFF
3
4KB
0xF020_3000
0xF020_3FFF
4
4KB
0xF020_4000
0xF020_4FFF
5
4KB
0xF020_5000
0xF020_5FFF
6
4KB
0xF020_6000
0xF020_6FFF
7
4KB
0xF020_7000
0xF020_7FFF
8
4KB
0xF020_8000
0xF020_8FFF
9
4KB
0xF020_9000
0xF020_9FFF
10
4KB
0xF020_A000
0xF020_AFFF
11
4KB
0xF020_B000
0xF020_BFFF
12
4KB
0xF020_C000
0xF020_CFFF
13
4KB
0xF020_D000
0xF020_DFFF
14
4KB
0xF020_E000
0xF020_EFFF
15
4KB
0xF020_F000
0xF020_FFFF
Flash bank0 is a 144-bit-wide bank with ECC support.
Sectors 12 and 13 are not accessible or included in the RM44L520 configuration.
Flash bank7 is a 72-bit-wide bank with ECC support.
The flash bank7 can be programmed while executing code from flash bank0.
Code execution is not allowed from flash bank7.
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6.10.2 Main Features of Flash Module
•
•
•
•
•
•
Support for multiple flash banks for program and/or data storage
Simultaneous read access on a bank while performing program or erase operation on any other bank
Integrated state machines to automate flash erase and program operations
Pipelined mode operation to improve instruction access interface bandwidth
Support for Single Error Correction Double Error Detection (SECDED) block inside Cortex-R4F CPU
– Error address is captured for host system debugging
Support for a rich set of diagnostic features
6.10.3 ECC Protection for Flash Accesses
All accesses to the program flash memory are protected by SECDED logic embedded inside the CPU.
The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash
memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with
the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while
a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling
mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance
Monitor Control Register, c9.
MRC
ORR
MCR
MRC
p15,#0,r1,c9,c12,#0
r1, r1, #0x00000010
p15,#0,r1,c9,c12,#0
p15,#0,r1,c9,c12,#0
;Enabling Event monitor states
;Set 4th bit (‘X’) of PMNC register
The application must also explicitly enable the ECC checking of the CPU for accesses on the CPU ATCM
and BTCM interfaces. These are connected to the program flash and data RAM, respectively. ECC
checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN, and ATCMPCEN
bits of the System Control Coprocessor Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000
DMB
MCR p15, #0, r1, c1, c0, #1
;Enable ECC checking for ATCM and BTCMs
6.10.4 Flash Access Speeds
For information on flash memory access speeds and the relevant wait states required, see
Section 5.8.1.2.
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6.10.5 Program Flash
Table 6-23. Timing Requirements for Program Flash
MIN
tprog(144bit)
Wide Word (144-bit) programming time
NOM
MAX
UNIT
40
300
µs
11
s
5.5
s
8
s
2
4
s
0.03
4
s
16
100
ms
1000
cycles
–40°C to 105°C
tprog(Total)
1MByte programming time (1)
tprog(Total)
768KB programming time (1)
terase(bank0)
Sector/Bank erase time (2)
twec
Write/erase cycles with 15-year Data Retention
–40°C to 105°C
requirement
0°C to 60°C, for first
25 cycles
2.8
–40°C to 105°C
0°C to 60°C, for first
25 cycles
–40°C to 105°C
(1)
(2)
0°C to 60°C, for first
25 cycles
This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 144 bits at a time at the maximum specified operating frequency.
During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase
a sector.
6.10.6 Data Flash
Table 6-24. Timing Requirements for Data Flash
MIN
tprog(144bit)
Wide Word (72-bit) programming time
EEPROM Emulation (bank 7) 64KByte
programming time (1)
terase(bank7)
Sector/Bank erase time, EEPROM Emulation
(bank 7)
twec
Write/erase cycles with 15-year Data Retention
–40°C to 105°C
requirement
68
MAX
UNIT
47
310
µs
2.6
s
–40°C to 105°C
tprog(Total)
(1)
NOM
0°C to 60°C, for first
25 cycles
775
1435
–40°C to 105°C
0.2
8
0°C to 60°C, for first
25 cycles
14
100
100000
ms
s
ms
cycles
This programming time includes overhead of state machine, but does not include data transfer time. The programming time assumes
programming 72 bits at a time at the maximum specified operating frequency.
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6.11 Tightly Coupled RAM Interface Module
Figure 6-10 shows the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.
36 Bit
36 Bit
wide
Upper 32-bits data 36-bit-wide
RAM
and 4 ECC bits RAM
Cortex R4)Œ
TCM BUS
B0
TCM
TCRAM
Interface 1
72-bit data + ECC
36 Bit
36 Bit
wide
36-bit-wide
RAM
Lower 32-bits data
RAM
RAM
and 4 ECC bits
Upper 32-bits data
and 4 ECC bits
TCM BUS
B1
TCM
72-bit data + ECC
TCRAM
Interface 2
Lower 32-bits data
and 4 ECC bits
36 Bit
36wide
Bit
36-bit-wide
RAM
RAM
36 Bit
36 Bit
wide
wide
36-bit-wide
RAM
RAM
RAM
Figure 6-10. TCRAM Block Diagram
6.11.1 Features
The features of the Tightly Coupled RAM (TCRAM) Module are:
•
•
•
•
•
•
•
•
•
Acts as slave to the BTCM interface of the Cortex-R4F CPU
Supports CPU internal ECC scheme by providing 64-bit data and 8-bit ECC code
Monitors CPU Event Bus and generates single-bit or multibit error interrupts
Stores addresses for single-bit and multibit errors
Supports RAM trace module
Provides CPU address bus integrity checking by supporting parity checking on the address bus
Performs redundant address decoding for the RAM bank chip select and ECC select generation logic
Provides enhanced safety for the RAM addressing by implementing two 36-bit-wide byte-interleaved RAM banks
and generating independent RAM access control signals to the two banks
Supports auto-initialization of the RAM banks along with the ECC bits
6.11.2 TCRAMW ECC Support
The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. The
TCRAMW also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to
the RAM. The TCRAMW monitors the CPU event bus and provides registers for indicating single-bit or
multibit errors and also for identifying the address that caused the single or multi-bit error. The event
signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information, see the device-specific Technical Reference Manual.
6.12
Parity Protection for Accesses to Peripheral RAMs
Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the
parity is calculated based on the data read from the peripheral RAM and compared with the good parity
value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates
a parity error signal that is mapped to the Error Signaling Module. The module also captures the
peripheral RAM address that caused the parity error.
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The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
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6.13 On-Chip SRAM Initialization and Testing
6.13.1 On-Chip SRAM Self-Test Using PBIST
6.13.1.1 Features
•
•
•
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
6.13.1.2 PBIST RAM Groups
Table 6-25. PBIST RAM Grouping
Test Pattern (Algorithm)
MEMORY
(2)
(3)
TEST CLOCK
MEM
TYPE
TRIPLE READ TRIPLE READ
SLOW READ
FAST READ
ALGO MASK
0x1
ALGO MASK
0x2
ROM
24578
8194
19586
6530
MARCH 13N (1) MARCH 13N (1)
TWO PORT
SINGLE PORT
(cycles)
(cycles)
ALGO MASK
0x4
PBIST_ROM
1
ROM CLK
STC_ROM
2
ROM CLK
ROM
DCAN1
3
VCLK
Dual port
25200
DCAN2
4
VCLK
Dual port
25200
DCAN3
5
VCLK
Dual port
25200
ESRAM1
(1)
RAM
GROUP
(2)
6
HCLK
Single port
MIBSPI1
7
VCLK
Dual port
33440
MIBSPI3
8
VCLK
Dual port
33440
MIBSPI5
9
VCLK
Dual port
33440
VIM
10
VCLK
Dual port
12560
MIBADC1
11
VCLK
Dual port
4200
ALGO MASK
0x8
266280
DMA
12
HCLK
Dual port
18960
N2HET1
13
VCLK
Dual port
31680
HET TU1
14
VCLK
Dual port
6480
MIBADC2
18
VCLK
Dual port
4200
N2HET2
19
VCLK
Dual port
31680
HET TU2
20
VCLK
Dual port
6480
ESRAM5 (3)
21
HCLK
Single port
266280
Several memory testing algorithms are stored in the PBIST ROM. However, TI recommends the March13N algorithm for application
testing of RAM.
ESRAM1: Address 0x08000000 - 0x0800FFFF
ESRAM5: Address 0x08010000 - 0x0801FFFF
The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK NMI => nERROR
2.6
B0 TCM (even) address bus parity error
User/Privilege
ESM => NMI => nERROR
2.10
B1 TCM (odd) ECC single error (correctable)
User/Privilege
ESM
1.28
B1 TCM (odd) ECC double error (uncorrectable)
User/Privilege
Abort (CPU), ESM =>
nERROR
3.5
B1 TCM (odd) uncorrectable error (that is, redundant address
decode)
User/Privilege
ESM => NMI => nERROR
2.8
B1 TCM (odd) address bus parity error
User/Privilege
ESM => NMI => nERROR
2.12
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to Bank 7)
User/Privilege
ESM
1.6
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
User/Privilege
Abort (CPU), ESM =>
nERROR
3.7
FMC uncorrectable error - address parity error on Bus1
accesses
User/Privilege
ESM => NMI => nERROR
2.4
FMC correctable error - Accesses to Bank 7
User/Privilege
ESM
1.35
FMC uncorrectable error - Accesses to Bank 7
User/Privilege
ESM
1.36
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
ESM
1.13
Memory access permission violation
User/Privilege
ESM
1.2
Memory parity error
User/Privilege
ESM
1.3
NCNB (Strongly Ordered) transaction with slave error response
User/Privilege
Interrupt => VIM
N/A
External imprecise error (Illegal transaction with ok response)
User/Privilege
Interrupt => VIM
N/A
Memory access permission violation
User/Privilege
ESM
1.9
Memory parity error
User/Privilege
ESM
1.8
NCNB (Strongly Ordered) transaction with slave error response
User/Privilege
Interrupt => VIM
N/A
External imprecise error (Illegal transaction with ok response)
User/Privilege
Interrupt => VIM
N/A
Memory access permission violation
User/Privilege
ESM
1.9
Memory parity error
User/Privilege
ESM
1.8
ERROR SOURCE
CPU TRANSACTIONS
SRAM
FLASH WITH CPU BASED ECC
DMA TRANSACTIONS
HET TU1 (HTU1)
HET TU2 (HTU2)
(1)
The Undefined Instruction TRAP is not detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of
the CPU.
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Table 6-32. Reset/Abort/Error Sources (continued)
CPUMODE
ERROR RESPONSE
ESM HOOKUP
GROUP.CHANNE
L
User/Privilege
ESM
1.7
User/Privilege
ESM
1.34
MibSPI1 memory parity error
User/Privilege
ESM
1.17
MibSPI3 memory parity error
User/Privilege
ESM
1.18
MibSPI5 memory parity error
User/Privilege
ESM
1.24
MibADC1 memory parity error
User/Privilege
ESM
1.19
MibADC2 memory parity error
User/Privilege
ESM
1.1
DCAN1 memory parity error
User/Privilege
ESM
1.21
DCAN2 memory parity error
User/Privilege
ESM
1.23
DCAN3 memory parity error
User/Privilege
ESM
1.22
User/Privilege
ESM
1.10
User/Privilege
ESM
1.11
DCC1 error
User/Privilege
ESM
1.30
DCC2 error
User/Privilege
ESM
1.62
ERROR SOURCE
N2HET1
Memory parity error
N2HET2
Memory parity error
MIBSPI
MIBADC
DCAN
PLL
PLL slip error
CLOCK MONITOR
Clock monitor interrupt
DCC
CCM-R4
Self-test failure
User/Privilege
ESM
1.31
Compare failure
User/Privilege
ESM => NMI => nERROR
2.2
User/Privilege
ESM
1.15
N/A
Reset
N/A
User/Privilege
ESM
1.27
User/Privilege
ESM
1.37
PSCON compare error
User/Privilege
ESM
1.38
PSCON self-test error
User/Privilege
ESM
1.39
eFuse Controller Autoload error
User/Privilege
ESM => nERROR
3.1
eFuse Controller - Any bit set in the error status register
User/Privilege
ESM
1.40
eFuse Controller self-test error
User/Privilege
ESM
1.41
N/A
ESM => NMI => nERROR
2.24
VIM
Memory parity error
VOLTAGE MONITOR
VMON out of voltage range
CPU SELF-TEST (LBIST)
Cortex-R4F CPU self-test (LBIST) error
PIN MULTIPLEXING CONTROL
Mux configuration error
POWER DOMAIN CONTROL
eFuse CONTROLLER
WINDOWED WATCHDOG
WWD Nonmaskable Interrupt exception
ERRORS REFLECTED IN THE SYSESR REGISTER
Power-Up Reset
N/A
Reset
N/A
Oscillator fail / PLL slip (2)
N/A
Reset
N/A
(2)
Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
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Table 6-32. Reset/Abort/Error Sources (continued)
CPUMODE
ERROR RESPONSE
ESM HOOKUP
GROUP.CHANNE
L
Watchdog exception
N/A
Reset
N/A
CPU Reset (driven by the CPU STC)
N/A
Reset
N/A
Software Reset
N/A
Reset
N/A
External Reset
N/A
Reset
N/A
ERROR SOURCE
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6.19 Digital Windowed Watchdog
This device includes a Digital Windowed Watchdog (DWWD) module that protects against runaway code
execution (see Figure 6-13).
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or an ESM group2 error signal in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.
Down
Counter
0
DWWD Preload
100%
Window
50%
Window
WindowOpen
Open
Window
WindowOpen
Open
Window
Down Counter
Window Open
=
Window Open
25%
Window
W Open
W Open
12.5%
Window
Op
Op
RESET
6.25%
Window
O
O
3.125%
Window
O
O
Digital
Digital
Windowed INTERRUPT
Windowed
Watchdog
Watch
Watchdog
Dog
ESM
Figure 6-13. Digital Windowed Watchdog Example
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6.20 Debug Subsystem
6.20.1 Block Diagram
The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see
Figure 6-14).
Boundary Scan
BSR/BSDL
Boundary Scan
Interface
TRST
TMS
TCK
RTCK
TDI
TDO
Debug
ROM1
Debug APB
Secondary Tap 0
DAP
APB Mux
AHB-AP
POM
ICEPICK_C
To
SCR1
through A2A
APB slave
Cortex
R4F
From
PCR Bridge
Secondary Tap 2
AJSM
Test Tap 0
eFuse Farm
Test Tap 1
PSCON
Figure 6-14. Debug Subsystem Block Diagram
6.20.2 Debug Components Memory Map
Table 6-33. Debug Components Memory Map
MODULE
NAME
FRAME CHIP
SELECT
FRAME ADDRESS RANGE
ACTUAL
SIZE
RESPONSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS
IN FRAME
START
END
FRAME
SIZE
CoreSight Debug ROM
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
4KB
Reads return zeros, writes have no effect
Cortex-R4F Debug
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4KB
4KB
Reads return zeros, writes have no effect
6.20.3 JTAG Identification Code
The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID
Code per silicon revision, see Table 6-34.
Table 6-34. JTAG ID Code
88
SILICON REVISION
ID
Rev 0
0x0BB0302F
Rev A
0x1BB0302F
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6.20.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-35).
Table 6-35. Debug ROM Table
ADDRESS
DESCRIPTION
VALUE
0x000
Pointer to Cortex-R4F
0x0000 1003
0x001
Reserved
0x0000 2002
0x002
Reserved
0x0000 3002
0x003
Reserved
0x0000 4003
0x004
end of table
0x0000 0000
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6.20.5 JTAG Scan Interface Timings
Table 6-36. JTAG Scan Interface Timing (1)
NO.
(1)
PARAMETER
MIN
fTCK
TCK frequency (at HCLKmax)
fRTCK
RTCK frequency (at TCKmax and HCLKmax)
1
td(TCK -RTCK)
Delay time, TCK to RTCK
2
tsu(TDI/TMS - RTCKr)
Setup time, TDI, TMS before RTCK rise (RTCKr)
3
th(RTCKr -TDI/TMS)
4
th(RTCKr -TDO)
5
td(TCKf -TDO)
Delay time, TDO valid after RTCK fall (RTCKf)
MAX
UNIT
12
MHz
10
MHz
24
ns
26
ns
Hold time, TDI, TMS after RTCKr
0
ns
Hold time, TDO after RTCKf
0
ns
12
ns
Timings for TDO are specified for a maximum of 50-pF load on TDO.
TCK
RTCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 6-15. JTAG Timing
90
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6.20.6 Advanced JTAG Security Module
This device includes a an Advanced JTAG Security Module (AJSM) module. The AJSM provides
maximum security to the memory content of the device by letting users secure the device after
programming.
Flash Module Output
OTP Contents
(example)
H
L
H
...
...
L
Unlock By Scan
Register
Internal Tie-Offs
(example only)
L
L
H
H
L
H
H
L
H
H
L
L
UNLOCK
128-bit comparator
Internal Tie-Offs
(example only)
H
L
L
H
H
L
L
H
Figure 6-16. AJSM Unlock
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000. The OTP contents are XOR-ed with the contents of the "Unlock By Scan" register.
The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of
this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the
UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least 1 bit in the visible unlock code from 1 to 0. Changing a
0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP)
flash region. Also, changing all 128 bits to zeros is not a valid condition and will permanently secure the
device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on
the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-ByScan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap 2 of the
ICEPick module. All other secondary taps, test taps, and the boundary scan interface are not accessible in
this state.
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6.20.7 Boundary Scan Chain
The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary
scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-17).
Device Pins (conceptual)
RTCK
TDI
TDO
IC E P ICK
TRST
TMS
TCK
Boundary Scan Interface
Boundary
Scan
TDI
TDO
BSDL
Figure 6-17. Boundary Scan Implementation (Conceptual Diagram)
Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.
92
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7 Peripheral Information and Electrical Specifications
7.1
I/O Timings
7.1.1
Input Timings
t pw
Input
V IH
VCCIO
VIH
VIL
V IL
0
Figure 7-1. TTL-Level Inputs
Table 7-1. Timing Requirements for Inputs (1)
MIN
Input minimum pulse width
tin_slew
Time for input signal to go from VIL to VIH or from VIH to VIL
(1)
(2)
MAX
UNIT
tc(VCLK) + 10 (2)
tpw
ns
1
ns
tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
The timing shown above is only valid for pin used in general-purpose input mode.
7.1.2
Output Timings
Table 7-2. Switching Characteristics for Output Timings versus Load Capacitance (CL)
PARAMETER
Rise time, tr
8 mA low-EMI pins
(see Table 4-40)
MIN
2.5
CL = 50 pF
4
CL = 100 pF
7.2
CL = 150 pF
12.5
CL = 15 pF
2.5
CL = 50 pF
Fall time, tf
Rise time, tr
4 mA low-EMI pins
(see Table 4-40)
Fall time, tf
Rise time, tr
2 mA-z low-EMI pins
(see Table 4-40)
Fall time, tf
MAX
CL = 15 pF
UNIT
4
CL = 100 pF
7.2
CL = 150 pF
12.5
CL = 15 pF
5.6
CL = 50 pF
10.4
CL = 100 pF
16.8
CL = 150 pF
23.2
CL = 15 pF
5.6
CL= 50 pF
10.4
CL = 100 pF
16.8
CL = 150 pF
23.2
CL = 15 pF
8
CL = 50 pF
15
CL = 100 pF
23
CL = 150 pF
33
CL = 15 pF
8
CL = 50 pF
15
CL = 100 pF
23
CL = 150 pF
33
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ns
ns
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Table 7-2. Switching Characteristics for Output Timings versus Load Capacitance (CL) (continued)
PARAMETER
MIN
CL = 15 pF
8mA mode
4
CL = 100 pF
7.2
CL = 150 pF
12.5
CL = 15 pF
2.5
CL = 50 pF
Fall time, tf
Selectable 8 mA / 2 mA-z pins
(see Table 4-40)
Rise time, tr
2mA-z mode
Fall time, tf
7.2
CL = 150 pF
12.5
CL = 15 pF
8
CL = 50 pF
15
CL = 100 pF
23
CL = 150 pF
33
CL = 15 pF
8
CL = 50 pF
15
CL = 100 pF
23
CL = 150 pF
33
VOL
ns
tf
V OH
Output
4
CL = 100 pF
tr
UNIT
2.5
CL = 50 pF
Rise time, tr
MAX
VCCIO
VOH
VOL
0
Figure 7-2. CMOS-Level Outputs
Table 7-3. Timing Requirements for Outputs (1)
MIN
td(parallel_out)
(1)
94
Delay between low-to-high, or high-to-low transition of general-purpose output
signals that can be configured by an application in parallel, for example, all signals in
a GIOA port, or all N2HET1 signals, and so forth
MAX
6
UNIT
ns
This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check
Table 4-40 for output buffer drive strength information on each signal.
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7.1.2.1
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Low-EMI Output Buffers
The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of
emissions from the pins which they drive. This is accomplished by adaptively controlling the output buffer
impedance, and is particularly effective with capacitive loads.
This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the
system module GPCR1 register for the desired module or signal, as shown in Table 7-4. The adaptive
impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates
two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of
VCCIO, respectively.
Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then
the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal
ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing,
for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which try to
pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer so as to
maintain the output voltage at or below VREFLOW.
Conversely, once the output buffer has driven the output to a high level, if the output voltage is above
VREFHIGH then the output buffer impedance will again increase to Hi-Z. A high degree of decoupling
between internal power bus ad output pin will occur with capacitive loads or any loads in which no current
is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the buffer
which try to pull the output voltage below VREFHIGH will be opposed by the output buffer impedance so
as to maintain the output voltage at or above VREFHIGH.
The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance
control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this
manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.
Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will
allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a
negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an
issue because the actual clamp current capability is always greater than the IOH / IOL specifications.
The low-EMI output buffers are automatically configured to be in the standard buffer mode when the
device enters a low-power mode.
Table 7-4. Low-EMI Output Buffer Hookup
LOW-EMI OUTPUT BUFFER SIGNAL HOOKUP
MODULE or SIGNAL NAME
LOW-POWER MODE (LPM)
STANDARD BUFFER ENABLE (SBEN)
Module: MibSPI1
GPREG1.0
Reserved
GPREG1.1
Module: MibSPI3
GPREG1.2
Reserved
GPREG1.3
Module: MibSPI5
GPREG1.4
Reserved
GPREG1.5
Reserved
Reserved
GPREG1.6
LPM signal from SYS module
GPREG1.7
Signal: TMS
GPREG1.8
Reserved
GPREG1.9
Signal: TDO
GPREG1.10
Signal: RTCK
GPREG1.11
Reserved
GPREG1.12
Signal: nERROR
GPREG1.13
Reserved
GPREG1.14
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Enhanced PWM Modules (ePWM)
Figure 7-3 shows the connections between the seven ePWM modules (ePWM1–ePWM7) on the device.
PINMMR36[25]
NHET1_LOOP_SYNC
EPWMSYNCI
VIM
EPWM1TZINTn
VIM
EPWM1INTn
EPWM1A
EPWM1B
ADC Wrapper
TZ1/2/3n
Mux
Selector
SOCA1, SOCB1
EPWM1
VBus32
EQEP1 + EQEP2 EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
System Module OSC FAIL or PLL Slip
Debug Mode Entry
CPU
TZ4n
VCLK4, SYS_nRST
EPWM1ENCLK
TBCLKSYNC
TZ5n
TZ6n
VIM
EPWM2/3/4/5/6TZINTn
VIM
EPWM2/3/4/5/6INTn
EPWM2/3/4/5/6A
TZ1/2/3n
ADC Wrapper
Mux
Selector
SOCA2/3/4/5/6
SOCB2/3/4/5/6
EQEP1 + EQEP2 EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
System Module OSC FAIL or PLL Slip
VBus32
TZ4n
VCLK4, SYS_nRST
EPWM2/3/4/5/6ENCLK
TZ5n
Debug Mode Entry
CPU
EPWM
2/3/4/5/6
IOMUX
EPWM2/3/4/5/6B
TBCLKSYNC
TZ6n
VIM
EPWM7TZINTn
VIM
EPWM7INTn
EPWM7A
EPWM7B
ADC Wrapper
EQEP1 + EQEP2
System Module
Mux
Selector
EQEP1ERR / EQEP2ERR /
EQEP1ERR or EQEP2ERR
OSC FAIL or PLL SLip
Debug Mode Entry
CPU
TZ1/2/3n
SOCA7, SOCB7
EPWM
7
VBus32
TZ4n
VCLK4, SYS_nRST
EPWM7ENCLK
TBCLKSYNC
TZ5n
TZ6n
Pulse
Stretch, EPWMSYNCO
8 VCLK4
cycles
VBus32 / VBus32DP
VIM
A.
ECAP1INTn
ECAP
1
ECAP1
For more detail on the input synchronization selection of the TZ1/TZ2/TZ3n pins to each ePWMx module, see
Figure 7-4.
Figure 7-3. ePWMx Module Interconnections
Figure 7-4 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double-synchronous + filter width) for ePWMx.
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double
sync
TZxn
(x = 1, 2, or 3)
ePWMx
(x = 1 through 7)
6 VCLK4
Cycles Filter
Figure 7-4. ePWMx Input Synchronization Selection Detail
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ePWM Clocking and Reset
Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active-low, the clock
enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When
SYS_nRST goes in-active high, the state of clock enable is respected.
Table 7-5. ePWMx Clock Enable Control
ePWM MODULE INSTANCE
CONTROL REGISTER TO
ENABLE CLOCK
DEFAULT VALUE
ePWM1
PINMMR37[8]
1
ePWM2
PINMMR37[16]
1
ePWM3
PINMMR37[24]
1
ePWM4
PINMMR38[0]
1
ePWM5
PINMMR38[8]
1
ePWM6
PINMMR38[16]
1
ePWM7
PINMMR38[24]
1
The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means
that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can
choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control
register bit.
7.2.2
Synchronization of ePWMx Time-Base Counters
A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM
module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The
input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-3 shows the
synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or
ignore the synchronization input. For more information, see the ePWM chapter in the device-specific
Technical Reference Manual (TRM).
7.2.3
Synchronizing all ePWM Modules to the N2HET1 Module Time Base
The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented
as shown in Figure 7-5.
N2HET1
N2HET1_LOOP_SYNC
EXT_LOOP_SYNC
2 VCLK4 cycles
Pulse Stretch
N2HET2
SYNCI
ePWM1
EPWM1SYNCI
double
sync
PINMMR36[25]
6 VCLK4
Cycles Filter
PINMMR47[8,9,10]
Figure 7-5. Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules
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7.2.4
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM
modules on a device. This bit is implemented as PINMMR37 register bit 1.
When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default
condition.
When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.
For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must
be set identically. The proper procedure for enabling the ePWM clocks is as follows:
1. Enable the individual ePWM module clocks (if disable) using the control registers shown in Table 7-5.
2. Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
3. Configure the prescaler values and desired ePWM modes.
4. Configure TBCLKSYNC = 1.
7.2.5
ePWM Synchronization with External Devices
The output sync from the ePWM1 module is also exported to a device output terminal so that multiple
devices can be synchronized together. The signal pulse is stretched by eight VCLK4 cycles before being
exported on the terminal as the EPWM1SYNCO signal.
7.2.6
ePWM Trip Zones
7.2.6.1
Trip Zones TZ1n, TZ2n, TZ3n
These three trip zone inputs are driven by external circuits and are connected to device-level inputs.
These signals are either connected asynchronously to the ePWMx trip zone inputs, or doublesynchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter
before connecting to the ePWMx (see Figure 7-4). By default, the trip zone inputs are asynchronously
connected to the ePWMx modules.
Table 7-6. Connection to ePWMx Modules for Device-Level Trip Zone Inputs
TRIP ZONE
INPUT
(1)
CONTROL FOR
ASYNCHRONOUS
CONNECTION TO ePWMx
CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO ePWMx
CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO
ePWMx (1)
TZ1n
PINMMR46[18:16] = 001
PINMMR46[18:16] = 010
PINMMR46[18:16] = 100
TZ2n
PINMMR46[26:24] = 001
PINMMR46[26:24] = 010
PINMMR46[26:24] = 100
TZ3n
PINMMR47[2:0] = 001
PINMMR47[2:0] = 010
PINMMR47[2:0] = 100
The filter width is 6 VCLK4 cycles.
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Trip Zone TZ4n
This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device.
Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control
registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on
the requirements of the application.
Table 7-7. TZ4n Connections for ePWMx Modules
ePWMx
CONTROL FOR TZ4n =
NOT(EQEP1ERR OR EQEP2ERR)
CONTROL FOR TZ4n =
NOT(EQEP1ERR)
CONTROL FOR TZ4n =
NOT(EQEP2ERR)
ePWM1
PINMMR41[2:0] = 001
PINMMR41[2:0] = 010
PINMMR41[2:0] = 100
ePWM2
PINMMR41[10:8] = 001
PINMMR41[10:8] = 010
PINMMR41[10:8] = 100
ePWM3
PINMMR41[18:16] = 001
PINMMR41[18:16] = 010
PINMMR41[18:16] = 100
ePWM4
PINMMR41[26:24] = 001
PINMMR41[26:24] = 010
PINMMR41[26:24] = 100
ePWM5
PINMMR42[2:0] = 001
PINMMR42[2:0] = 010
PINMMR42[2:0] = 100
ePWM6
PINMMR42[10:8] = 001
PINMMR42[10:8] = 010
PINMMR42[10:8] = 100
ePWM7
PINMMR42[18:16] = 001
PINMMR42[18:16] = 010
PINMMR42[18:16] = 100
7.2.6.3
Trip Zone TZ5n
This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted
whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip
zone input for each ePWMx module to prevent the external system from going out of control when the
device clocks are not within expected range (system running at limp clock).
The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the
system module. These level signals are set until cleared by the application.
7.2.6.4
Trip Zone TZ6n
This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled,
the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the
external system from going out of control when the CPU is stopped.
7.2.7
Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
A special scheme is implemented to select the actual signal used for triggering the start of conversion on
the two ADCs on this device. This scheme is defined in Section 7.5.2.3.
100
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SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
Table 7-8. ePWMx Timing Requirements
TEST CONDITIONS
MIN
Asynchronous
tw(SYNCIN)
Synchronization input pulse width
UNIT
2 tc(VCLK4)
Synchronous
2 tc(VCLK4)
Synchronous, with input filter
(1)
MAX
cycles
2 tc(VCLK4) + filter width (1)
The filter width is 6 VCLK4 cycles
Table 7-9. ePWMx Switching Characteristics
TEST
CONDITIONS
PARAMETER
tw(PWM)
Pulse duration, ePWMx output high or low
tw(SYNCOUT)
Synchronization Output Pulse Width
td(PWM)tza
Delay time, trip input active to PWM forced high, or
Delay time, trip input active to PWM forced low
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
MIN
MAX
UNIT
33.33
ns
8 tc(VCLK4)
No pin load
cycles
25
ns
20
ns
MAX
UNIT
Table 7-10. ePWMx Trip-Zone Timing Requirements
TEST CONDITIONS
Asynchronous
tw(TZ)
Pulse duration, TZn input low
Synchronous
Synchronous, with input filter
(1)
MIN
2 * HSPCLKDIV * CLKDIV *
tc(VCLK4) (1)
2 tc(VCLK4)
cycles
2 tc(VCLK4) + filter width
For more information on the clock divider fields: HSPCLKDIV and CLKDIV, see the ePWM chapter of the device-specific Technical
Reference Manual (TRM).
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Enhanced Capture Modules (eCAP)
Figure 7-6 shows how the eCAP modules are interconnected on this microcontroller.
EPWM1SYNCO
ECAP1SYNCI
ECAP1
VIM
ECAP1INTn
ECAP1
VBus32
VCLK4, SYS_nRST
ECAP1ENCLK
ECAP1SYNCO
ECAP2SYNCI
VIM
ECAP2INTn
ECAP
2/3/4/5
IOMUX
ECAP2
VBus32
VCLK4, SYS_nRST
ECAP2SYNCO
ECAP2ENCLK
ECAP6
VIM
ECAP6INTn
ECAP
6
VBus32
VCLK4, SYS_nRST
ECAP6ENCLK
A.
For more detail on the input synchronization selection of the ECAPx pins to each eCAPx module, see Figure 7-7.
Figure 7-6. eCAPx Module Connections
Figure 7-7 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double-synchronous + filter width) for eCAPx.
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ECAPx
(x = 1, 2, 3, 4, 5, or 6)
double
sync
eCAPx
6 VCLK4
Cycles Filter
(x = 1 through 6)
Figure 7-7. eCAPx Input Synchronization Selection Detail
7.3.1
Clock Enable Control for eCAPx Modules
Each of the eCAPx modules have a clock enable (ECAPxENCLK). These signals must be generated from
a device-level control register. When SYS_nRST is active-low, the clock enables are ignored and the
ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the
state of clock enable is respected.
Table 7-11. eCAPx Clock Enable Control
eCAP MODULE INSTANCE
CONTROL REGISTER TO
ENABLE CLOCK
DEFAULT VALUE
eCAP1
PINMMR39[0]
1
eCAP2
PINMMR39[8]
1
eCAP3
PINMMR39[16]
1
eCAP4
PINMMR39[24]
1
eCAP5
PINMMR40[0]
1
eCAP6
PINMMR40[8]
1
The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that
the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose
to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register
bit.
7.3.2
PWM Output Capability of eCAPx
When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM
output. This is called the Auxiliary PWM (APWM) mode of operation of the eCAPx modules. For more
information, see the eCAP module chapter of the device-specific TRM.
7.3.3
Input Connection to eCAPx Modules
The input connection to each of the eCAPx modules can be selected between a double-VCLK4synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12.
Table 7-12. Device-Level Input Connection to eCAPx Modules
CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO eCAPx
INPUT SIGNAL
(1)
CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO eCAPx (1)
eCAP1
PINMMR43[2:0] = 001
PINMMR43[2:0] = 010
eCAP2
PINMMR43[10:8] = 001
PINMMR43[10:8] = 010
eCAP3
PINMMR43[18:16] = 001
PINMMR43[18:16] = 010
eCAP4
PINMMR43[26:24] = 001
PINMMR43[26:24] = 010
eCAP5
PINMMR44[2:0] = 001
PINMMR44[2:0] = 010
eCAP6
PINMMR44[10:8] = 001
PINMMR44[10:8] = 010
The filter width is 6 VCLK4 cycles.
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Enhanced Capture Module (eCAP) Electrical Data/Timing
Table 7-13. eCAPx Timing Requirements
TEST CONDITIONS
tw(CAP)
(1)
Pulse width, capture input
MIN
Synchronous
MAX
2 tc(VCLK4)
Synchronous with input filter
UNIT
cycles
2 tc(VCLK4) + filter width (1)
The filter width is 6 VCLK4 cycles.
Table 7-14. eCAPx Switching Characteristics
PARAMETER
tw(APWM)
104
Pulse duration, APWMx output high or low
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
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7.4
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Enhanced Quadrature Encoder (eQEP)
Figure 7-8 shows the eQEP module interconnections on the device.
VBus32
EQEP1A
EQEP1B
EQEP1ENCLK
VCLK4
SYS_nRST
EPWM1/../7
EQEP1
Module
EQEP1INTn
VIM
EQEP1ERR
EQEP1I
EQEP1IO
EQEP1IOE
TZ4n
EQEP1S
EQEP1SO
EQEP1SOE
IO
Mux
VBus32
EQEP2A
EQEP2B
EQEP2ENCLK
VCLK4
SYS_nRST
Connection
Selection
Mux
A.
EQEP2
Module
EQEP2INTn
VIM
EQEP2ERR
EQEP2I
EQEP2IO
EQEP2IOE
EQEP2S
EQEP2SO
EQEP2SOE
For more detail on the eQEP input synchronization selection of the EQEPxA/B pins to each eQEPx module, see
Figure 7-9.
Figure 7-8. eQEP Module Interconnections
Figure 7-9 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double-synchronous + filter width) for eQEPx.
double
sync
EQEPxA or EQEPxB
(x = 1 or 2)
eQEPx
6 VCLK4
Cycles Filter
(x = 1 or 2)
Figure 7-9. eQEPx Input Synchronization Selection Detail
7.4.1
Clock Enable Control for eQEPx Modules
Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST
is active-low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper
state. When SYS_nRST goes in-active high, the state of clock enable is respected.
The default value of the control registers to enable the clocks to the eQEPx modules is 1 (see Table 7-15).
This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The
application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the
respective control register bit.
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Table 7-15. eQEPx Clock Enable Control
eQEP MODULE INSTANCE
CONTROL REGISTER TO
ENABLE CLOCK
DEFAULT VALUE
eQEP1
PINMMR40[16]
1
eQEP2
PINMMR40[24]
1
7.4.2
Using eQEPx Phase Error to Trip ePWMx Outputs
The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs
EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection
multiplexer. This multiplexer is defined in Table 7-7. As shown in Figure 7-3, the output of this selection
multiplexer is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection
allows the application to define the response of each ePWMx module on a phase error indicated by the
eQEP modules.
7.4.3
Input Connections to eQEPx Modules
The input connections to each of the eQEP modules can be selected between a double-VCLK4synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-16.
Table 7-16. Device-Level Input Connection to eQEPx Modules
CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO eQEPx
INPUT SIGNAL
(1)
CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO eQEPx (1)
eQEP1A
PINMMR44[18:16] = 001
PINMMR44[18:16] = 010
eQEP1B
PINMMR44[26:24] = 001
PINMMR44[26:24] = 010
eQEP1I
PINMMR45[2:0] = 001
PINMMR45[2:0] = 010
eQEP1S
PINMMR45[10:8] = 001
PINMMR45[10:8] = 010
eQEP2A
PINMMR45[18:16] = 001
PINMMR45[18:16] = 010
eQEP2B
PINMMR45[26:24] = 001
PINMMR45[26:24] = 010
eQEP2I
PINMMR46[2:0] = 001
PINMMR46[2:0] = 010
eQEP2S
PINMMR46[10:8] = 001
PINMMR46[10:8] = 010
The filter width is 6 VCLK4 cycles.
7.4.4
Enhanced Quadrature Encoder Pulse (eQEPx) Timing
Table 7-17. eQEPx Timing Requirements (1)
TEST CONDITIONS
tw(QEPP)
QEP input period
Synchronous
Synchronous with input filter
tw(INDEXH)
QEP Index Input High Time
Synchronous
Synchronous with input filter
tw(INDEXL)
QEP Index Input Low Time
Synchronous
Synchronous with input filter
tw(STROBH)
QEP Strobe Input High Time
Synchronous
Synchronous with input filter
tw(STROBL)
QEP Strobe Input Low Time
Synchronous
Synchronous with input filter
(1)
106
MIN
2 tc(VCLK4)
2 tc(VCLK4) + filter width
2 tc(VCLK4)
2 tc(VCLK4) + filter width
2 tc(VCLK4)
2 tc(VCLK4) + filter width
2 tc(VCLK4)
2 tc(VCLK4) + filter width
2 tc(VCLK4)
2 tc(VCLK4) + filter width
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
The filter width is 6 VCLK4 cycles.
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Table 7-18. eQEPx Switching Characteristics
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
PARAMETER
MIN
4 tc(VCLK4)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
6 tc(VCLK4)
cycles
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12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
The MibADC has a separate power bus for its analog circuitry that enhances the Analog-to-Digital (A-to-D)
performance by preventing digital switching noise on the logic circuitry which could be present on VSS and
VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO, unless otherwise noted.
Table 7-19. MibADC Overview
DESCRIPTION
7.5.1
VALUE
Resolution
12 bits
Monotonic
Assured
Output conversion code
00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
7.5.2
12-bit resolution
ADREFHI and ADREFLO pins (high and low reference voltages)
Total Sample/Hold/Convert time: 600 ns Minimum at 30 MHz ADCLK
One memory region per conversion group is available (Event Group, Group 1, and Group 2)
Allocation of channels to conversion groups is completely programmable
Supports flexible channel conversion order
Memory regions are serviced either by interrupt or by DMA
Programmable interrupt threshold counter is available for each group
Programmable magnitude threshold interrupt for each group for any one channel
Option to read either 8-, 10-, or 12-bit values from memory regions
Single or continuous conversion modes
Embedded self-test
Embedded calibration logic
Enhanced power-down mode
– Optional feature to automatically power down ADC core when no conversion is in progress
External event pin (ADxEVT) programmable as general-purpose I/O
Event Trigger Options
The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these
three groups can be configured to be triggered by a hardware event. In that case, the application can
select the trigger, from among eight event sources, to convert a group.
7.5.2.1
MibADC1 Event Trigger Hookup
Table 7-20 lists the event sources that can trigger the conversions for the MibADC1 groups.
108
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Table 7-20. MibADC1 Event Trigger Hookup
TRIGGER EVENT SIGNAL
GROUP SOURCE SELECT
(G1SRC, G2SRC, OR EVSRC)
000
EVENT NO.
1
PINMMR30[0] = 1
(DEFAULT)
AD1EVT
PINMMR30[0] = 0 AND PINMMR30[1] = 1
OPTION A
CONTROL FOR
OPTION A
OPTION B
CONTROL FOR
OPTION B
AD1EVT
—
AD1EVT
—
PINMMR30[8] = 0 and
PINMMR30[9] = 1
001
2
N2HET1[8]
N2HET2[5]
PINMMR30[8] = 1
ePWM_B
010
3
N2HET1[10]
N2HET1[27]
—
N2HET1[27]
—
PINMMR30[16] = 0 and
PINMMR30[17] = 1
011
4
RTI Compare 0 Interrupt
RTI Compare 0 Interrupt
PINMMR30[16] = 1
ePWM_A1
100
5
N2HET1[12]
N2HET1[17]
—
N2HET1[17]
—
101
6
N2HET1[14]
N2HET1[19]
PINMMR30[24] = 1
N2HET2[1]
PINMMR30[24] = 0 and
PINMMR30[25] = 1
110
7
GIOB[0]
N2HET1[11]
PINMMR31[0] = 1
ePWM_A2
PINMMR31[0] = 0 and
PINMMR31[1] = 1
111
8
GIOB[1]
N2HET2[13]
PINMMR32[16] = 1
ePWM_AB
PINMMR31[8] = 0 and
PINMMR31[9] = 1
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NOTE
If ADEVT, N2HET1, or GIOB is used as a trigger source, the connection to the MibADC1
module trigger input is made from the output side of the input buffer. This way, a trigger
condition can be generated either by configuring the function as output onto the pad (through
the mux control), or by driving the function from an external trigger source as input. If the
mux control module is used to select different functionality instead of the ADEVT, N2HET1[x]
or GIOB[x] signals, then care must be taken to disable these signals from triggering
conversions; there is no multiplexing on the input connections.
If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11],
N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made
directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered
without having to enable the signal from being output on a device terminal.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
7.5.2.2
MibADC2 Event Trigger Hookup
Table 7-21 lists the event sources that can trigger the conversions for the MibADC2 groups.
110
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Table 7-21. MibADC2 Event Trigger Hookup
TRIGGER EVENT SIGNAL
GROUP SOURCE SELECT
(G1SRC, G2SRC, OR EVSRC)
000
EVENT NO.
1
PINMMR30[0] = 1
(DEFAULT)
AD2EVT
PINMMR30[0] = 0 and PINMMR30[1] = 1
OPTION A
CONTROL FOR
OPTION A
OPTION B
CONTROL FOR
OPTION B
AD2EVT
—
AD2EVT
—
PINMMR31[16] = 0 and
PINMMR31[17] = 1
001
2
N2HET1[8]
N2HET2[5]
PINMMR31[16] = 1
ePWM_B
010
3
N2HET1[10]
N2HET1[27]
—
N2HET1[27]
—
PINMMR31[24] = 0 and
PINMMR31[25] = 1
011
4
RTI Compare 0 Interrupt
RTI Compare 0 Interrupt
PINMMR31[24] = 1
ePWM_A1
100
5
N2HET1[12]
N2HET1[17]
—
N2HET1[17]
—
101
6
N2HET1[14]
N2HET1[19]
PINMMR32[0] = 1
N2HET2[1]
PINMMR32[0] = 0 and
PINMMR32[1] = 1
110
7
GIOB[0]
N2HET1[11]
PINMMR32[8] = 1
ePWM_A2
PINMMR32[8] = 0 and
PINMMR32[9] = 1
111
8
GIOB[1]
N2HET2[13]
PINMMR32[16] = 1
ePWM_AB
PINMMR32[16] = 0 and
PINMMR32[17] = 1
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Notes
If AD2EVT, N2HET1, or GIOB is used as a trigger source, the connection to the MibADC2
module trigger input is made from the output side of the input buffer. This way, a trigger
condition can be generated either by configuring the function as output onto the pad (through
the mux control), or by driving the function from an external trigger source as input. If the
mux control module is used to select different functionality instead of the AD2EVT,
N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from
triggering conversions; there is no multiplexing on the input connections.
If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11],
N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made
directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered
without having to enable the signal from being output on a device terminal.
NOTE
For the RTI compare 0 interrupt source, the connection is made directly from the output of
the RTI module. That is, the interrupt condition can be used as a trigger source even if the
actual interrupt is not signaled to the CPU.
7.5.2.3
Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
As shown in Figure 7-10, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are
used to generate four signals – ePWM_B, ePWM_A1, ePWM_A2, and ePWM_AB, that are available to
trigger the ADC based on the application requirement.
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SOCAEN, SOCBEN bits
inside ePWMx modules
Controlled by PINMMR
EPWM1SOCA
EPWM1
module
EPWM1SOCB
EPWM2SOCA
EPWM2
module
EPWM2SOCB
EPWM3SOCA
EPWM3
module
EPWM3SOCB
EPWM4SOCA
EPWM4
module
EPWM4SOCB
EPWM5SOCA
EPWM5
module
EPWM5SOCB
EPWM6SOCA
EPWM6
module
EPWM6SOCB
EPWM7SOCA
EPWM7
module
EPWM7SOCB
ePWM_B
ePWM_A1
ePWM_A2 ePWM_AB
Figure 7-10. ADC Trigger Source Generation from ePWMx
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Table 7-22. Control Bit to SOC Output
CONTROL BIT
SOC OUTPUT
PINMMR35[0]
SOC1A_SEL
PINMMR35[8]
SOC2A_SEL
PINMMR35[16]
SOC3A_SEL
PINMMR35[24]
SOC4A_SEL
PINMMR36[0]
SOC5A_SEL
PINMMR36[8]
SOC6A_SEL
PINMMR36[16]
SOC7A_SEL
The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-10. This switch
is implemented by using the control registers in the PINMMR module. Figure 7-11 shows an example of
the implementation for the switch on SOC1A. The switches on the other SOCA signals are implemented in
the same way.
0
SOC1A
ePWM1
0
1
PINMMR164[0]
EPWM1SOCA
From switch on
SOC2A
when PINMMR164[8] = 1
0
0
1
From switch on
SOC2A
when PINMMR164[8] = 0
Figure 7-11. ePWM1SOC1A Switch Implementation
The logic equations ( Equation 1, Equation 2, Equation 3, and Equation 4) for the four outputs from the
combinational logic shown in Figure 7-10 are:
ePWM_B = SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B
(1)
ePWM_A1 = [ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or
[ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or
[ SOC7A and not(SOC7A_SEL) ]
(2)
ePWM_A2 = [ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or
[ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or
[ SOC7A and SOC7A_SEL ]
ePWM_AB = ePWM_B or ePWM_A2
114
(3)
(4)
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7.5.3
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
ADC Electrical and Timing Specifications
Table 7-23. MibADC Recommended Operating Conditions
PARAMETER
MIN
MAX
(1)
V
V
ADREFHI
A-to-D high-voltage reference source
ADREFLO
VCCAD
ADREFLO
A-to-D low-voltage reference source
VSSAD (1)
ADREFHI
VAI
Analog input voltage
ADREFLO
ADREFHI
IAIC
Analog input clamp current (2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
–2
2
(1)
(2)
UNIT
V
mA
For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
Table 7-24. MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions
MAX
UNIT
Rmux
Analog input mux on-resistance
PARAMETER
See Figure 7-12
250
Ω
Rsamp
ADC sample switch on-resistance
See Figure 7-12
250
Ω
Cmux
Input mux capacitance
See Figure 7-12
16
pF
Csamp
ADC sample capacitance
See Figure 7-12
13
pF
IAIL
VCCAD = 3.6 V
maximum
Analog off-state input leakage current
IAIL
VCCAD = 5.25 V
maximum
Analog off-state input leakage current
IAOSB1 (1)
IAOSB2 (1)
IAOSB1 (1)
IAOSB2 (1)
IADREFHI
ICCAD
(1)
DESCRIPTION/CONDITIONS
VCCAD = 3.6 V
maximum
ADC1 Analog on-state input bias current
VCCAD = 3.6 V
maximum
ADC2 Analog on-state input bias current
VCCAD = 5.25 V
maximum
ADC1 Analog on-state input bias current
VCCAD = 5.25 V
maximum
ADC2 Analog on-state input bias current
ADREFHI input current
VSSAD ≤ VIN < VSSAD + 100 mV
–300
200
VSSAD + 100 mV ≤ VIN ≤ VCCAD – 200 mV
–200
200
VCCAD – 200 mV < VIN ≤ VCCAD
–200
500
VSSAD ≤ VIN < VSSAD + 300 mV
–1000
250
VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV
–250
250
VCCAD – 300 mV < VIN ≤ VCCAD
–250
1000
VSSAD ≤ VIN < VSSAD + 100 mV
–8
2
VSSAD + 100 mV < VIN < VCCAD – 200 mV
–4
2
VCCAD – 200 mV < VIN < VCCAD
–4
12
VSSAD ≤ VIN < VSSAD + 100 mV
–7
2
VSSAD + 100 mV ≤ VIN ≤ VCCAD – 200 mV
–4
2
VCCAD - 200 mV < VIN ≤ VCCAD
–4
10
VSSAD ≤ VIN < VSSAD + 300 mV
–10
3
VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV
–5
3
VCCAD – 300 mV < VIN ≤ VCCAD
–5
14
VSSAD ≤ VIN < VSSAD + 300 mV
–8
3
VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV
–5
3
VCCAD – 300 mV < VIN ≤ VCCAD
–5
12
ADREFHI = VCCAD, ADREFLO = VSSAD
Normal operating mode
Static supply current
MIN
ADC core in power down mode
nA
nA
µA
µA
µA
µA
3
mA
15
mA
5
µA
If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSB1 + IAOSB2.
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Smux
Rmux
Smux
Rmux
Pin
VS1
IAOSB
Cext
On-State
Bias Current
Rext
Pin
VS2
IAIL
Cext
IAIL
IAIL
Off-State
Leakages
Rext
Pin
Smux
Rmux
Ssamp
Rsamp
VS24
IAIL
Csamp
Cmux
Cext
IAIL
IAIL
Figure 7-12. MibADC Input Equivalent Circuit
Table 7-25. MibADC Timing Specifications
PARAMETER
tc(ADCLK) (1)
td(SH)
(2)
MIN
Cycle time, MibADC clock
Delay time, sample and hold time
td(PU-ADV)
Delay time from ADC power on until first input can be sampled
NOM
MAX
UNIT
0.033
µs
0.2
µs
1
µs
12-BIT MODE
td(C)
Delay time, conversion time
0.4
µs
td(SHC) (3)
Delay time, total sample/hold and conversion time
0.6
µs
Delay time, conversion time
0.33
µs
Delay time, total sample/hold and conversion time
0.53
µs
10-BIT MODE
td(C)
td(SHC)
(1)
(2)
(3)
116
(3)
The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register
bits 4:0.
The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the ADSAMP register for each
conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as
well as the internal impedance of the ADC.
This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors (for
example, the prescale settings).
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Table 7-26. MibADC Operating Characteristics Over Full Ranges of Recommended Operating
Conditions (1) (2)
PARAMETER
DESCRIPTION/CONDITIONS
MIN NOM MAX UNIT
CR
Conversion range over which
specified accuracy is maintained
ADREFHI – ADREFLO
ZSET
Zero Scale Offset
Difference between the first ideal transition (from
code 000h to 001h) and the actual transition
10-bit mode
1
12-bit mode
2
2
Full Scale Offset
Difference between the range of the measured
code transitions (from first to last) and the range of
the ideal code transitions
10-bit mode
FSET
12-bit mode
3
EDNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value (see Figure 7-13).
10-bit mode
± 1.5
12-bit mode
±2
±2
Integral nonlinearity error
Maximum deviation from the best straight line
through the MibADC. MibADC transfer
characteristics, excluding the quantization error.
10-bit mode
EINL
12-bit mode
±2
ETOT
Total unadjusted error
Maximum value of the difference between an
analog value and the ideal midstep value.
10-bit mode
±2
12-bit mode
±4
(1)
(2)
3
5.25
V
LSB
LSB
LSB
LSB
LSB
1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode
1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode
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Performance (Accuracy) Specifications
7.5.4.1
MibADC Nonlinearity Errors
The differential nonlinearity error shown in Figure 7-13 (sometimes referred to as differential linearity) is
the difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ... 100
0 ... 011
Differential Linearity
Error (–½ LSB)
1 LSB
0 ... 010
Differential Linearity
Error (–½ LSB)
0 ... 001
1 LSB
0 ... 000
0
A.
1
3
4
2
Analog Input Value (LSB)
5
1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-13. Differential Nonlinearity (DNL) Error(A)
118
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The integral nonlinearity error shown in Figure 7-14 (sometimes referred to as linearity error) is the
deviation of the values on the actual transfer function from a straight line.
0 ... 111
0 ... 110
Ideal
Transition
Digital Output Code
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(–½ LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (–1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
A.
12
1 LSB = (ADREFHI – ADREFLO)/2
Figure 7-14. Integral Nonlinearity (INL) Error(A)
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MibADC Total Error
The absolute accuracy or total error of an MibADC as shown in Figure 7-15 is the maximum value of the
difference between an analog value and the ideal midstep value.
0 ... 111
0 ... 110
Digital Output Code
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
A.
1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-15. Absolute Accuracy (Total) Error(A)
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7.6
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
General-Purpose Input/Output
The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and
bit-programmable. Both GIOA and GIOB support external interrupt capability.
7.6.1
Features
The GPIO module has the following features:
• Each I/O pin can be configured as:
– Input
– Output
– Open drain
• The interrupts have the following characteristics:
– Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
– Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
– Individual interrupt flags (set in GIOFLG register)
– Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers,
respectively
– Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
• Internal pullup/pulldown allows unused I/O pins to be left unconnected
For information on input and output timings see Section 7.1.1 and Section 7.1.2.
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7.7
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Enhanced High-End Timer (N2HET)
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. The N2HET is especially well suited for applications
requiring multiple sensor information and drive actuators with complex and accurate time pulses.
7.7.1
Features
The N2HET module has the following features:
• Programmable timer for input and output timing functions
• Reduced instruction set (30 instructions) for dedicated time and angle functions
• 160 words of instruction RAM protected by parity
• User-defined number of 25-bit virtual counters for timer, event counters, and angle counters
• 7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual
counters
• Up to 32 pins usable for input signal measurements or output signal generation
• Programmable suppression filter for each input pin with adjustable limiting frequency
• Low CPU overhead and interrupt load
• Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU)
or DMA
• Diagnostic capabilities with different loopback mechanisms and pin status readback functionality
7.7.2
N2HET RAM Organization
The timer RAM uses four RAM banks, where each bank has two port access capability. This means that
one RAM address may be written while another address is read. The RAM words are 96 bits wide, which
are split into three 32-bit fields (program, control, and data).
7.7.3
Input Timing Specifications
The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.
1
N2HETx
3
4
2
Figure 7-16. N2HET Input Capture Timings
122
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Table 7-27. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER
MIN
MAX
UNIT
1
Input signal period, PCNT or WCAP for rising edge to
rising edge
(HRP) (LRP) tc(VCLK2) + 2
2
(HRP) (LRP) tc(VCLK2) – 2
ns
2
Input signal period, PCNT or WCAP for falling edge to
falling edge
(HRP) (LRP) tc(VCLK2) + 2
225 (HRP) (LRP) tc(VCLK2) – 2
ns
3
Input signal high phase, PCNT or WCAP for rising edge
to falling edge
2 (HRP) tc(VCLK2) + 2
225 (HRP) (LRP) tc(VCLK2) – 2
ns
4
Input signal low phase, PCNT or WCAP for falling edge
to rising edge
2 (HRP) tc(VCLK2) + 2
225 (HRP) (LRP) tc(VCLK2) – 2
ns
7.7.4
25
N2HET1 to N2HET2 Synchronization
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). An N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the resynchronization signal from the
master, the slave must synchronize itself again.
N2HET1
N2HET2
EXT_LOOP_SYNC
NHET_LOOP_SYNC
NHET_LOOP_SYNC
EXT_LOOP_SYNC
Figure 7-17. N2HET1 to N2HET2 Synchronization Hookup
7.7.5
N2HET Checking
7.7.5.1
Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals, as shown in Figure 7-18. The direction of the monitoring is controlled
by the I/O multiplexing control module.
N2HET1[1,3,5,7,9,11]
IOMM mux control signal x
N2HET1[1,3,5,7,9,11] / N2HET2[8,10,12,14,16,18]
N2HET1
N2HET2[8,10,12,14,16,18]
N2HET2
Figure 7-18. N2HET Monitoring
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Output Monitoring Using Dual Clock Comparator (DCC)
N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure
the frequency of the PWM signal on N2HET1[31].
Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to
measure the frequency of the PWM signal on N2HET2[0].
Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection
to the DCC module is made directly from the output of the N2HETx module (from the input of the output
buffer).
For more information on DCC, see Section 6.7.3.
7.7.6
Disabling N2HET Outputs
Some applications require disabling the N2HET outputs under some fault condition. The N2HET module
provides this capability through the Pin Disable input signal. This signal, when driven low, causes the
N2HET outputs identified by a programmable register (HETPINDIS) to be in a high-impedance (tri-state)
state. For more details on the N2HET Pin Disable feature, see the device-specific Terminal Reference
Manual.
GIOA[5] is connected to the Pin Disable input for N2HET1, and GIOB[2] is connected to the Pin Disable
input for N2HET2.
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7.7.7
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
High-End Timer Transfer Unit (HET)
A High-End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or
from main memory. A Memory Protection Unit (MPU) is built into the HET TU.
7.7.7.1
•
•
•
•
•
•
•
•
•
7.7.7.2
Features
CPU and DMA independent
Master port to access system memory
8 control packets supporting dual buffer configuration
Control packet information is stored in RAM protected by parity
Event synchronization (HET transfer requests)
Supports 32- or 64-bit transactions
Addressing modes for HET address (8- or 16-byte) and system memory address (fixed, 32- or 64-bit)
One shot, circular, and auto-switch buffer transfer modes
Request lost detection
Trigger Connections
For the transfer request line trigger connections to the N2HET TU when an instruction-specific condition is
true, see Table 7-28 and Table 7-29.
Table 7-28. HET TU1 Request Line Connection
MODULES
REQUEST SOURCE
HET TU1 REQUEST
N2HET1
HTUREQ[0]
HET TU1 DCP[0]
N2HET1
HTUREQ[1]
HET TU1 DCP[1]
N2HET1
HTUREQ[2]
HET TU1 DCP[2]
N2HET1
HTUREQ[3]
HET TU1 DCP[3]
N2HET1
HTUREQ[4]
HET TU1 DCP[4]
N2HET1
HTUREQ[5]
HET TU1 DCP[5]
N2HET1
HTUREQ[6]
HET TU1 DCP[6]
N2HET1
HTUREQ[7]
HET TU1 DCP[7]
Table 7-29. HET TU2 Request Line Connection
MODULES
REQUEST SOURCE
HET TU2 REQUEST
N2HET2
HTUREQ[0]
HET TU2 DCP[0]
N2HET2
HTUREQ[1]
HET TU2 DCP[1]
N2HET2
HTUREQ[2]
HET TU2 DCP[2]
N2HET2
HTUREQ[3]
HET TU2 DCP[3]
N2HET2
HTUREQ[4]
HET TU2 DCP[4]
N2HET2
HTUREQ[5]
HET TU2 DCP[5]
N2HET2
HTUREQ[6]
HET TU2 DCP[6]
N2HET2
HTUREQ[7]
HET TU2 DCP[7]
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7.8
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Controller Area Network (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example,
automotive and industrial fields) that require reliable serial communication or multiplexed wiring.
7.8.1
Features
Features of the DCAN module include:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbps
• The CAN kernel can be clocked by the oscillator for baud-rate generation.
• 64 mailboxes on each DCAN
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Message RAM protected by parity
• Direct access to message RAM during test mode
• CAN RX and TX pins configurable as general-purpose I/O pins
• Message RAM Auto Initialization
• DMA support
For more information on the DCAN, see the device-specific TRM.
7.8.2
Electrical and Timing Specifications
Table 7-30. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
td(CANnTX)
Delay time, transmit shift register to CANnTX pin (1)
td(CANnRX)
Delay time, CANnRX pin to receive shift register
(1)
126
MIN
MAX
UNIT
15
ns
5
ns
These values do not include the rise and fall times of the output buffer.
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7.9
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Local Interconnect Network Interface (LIN)
The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is
an SCI. The hardware features of the SCI are augmented to achieve LIN compatibility.
The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn
to zero (NRZ) format. The SCI can be used to communicate, for example, through an RS-232 port or over
a K-line.
The LIN standard is based on the SCI (Universal Asynchronous Receiver/Transmitter [UART]) serial data
link format. The communication concept is single-master/multiple-slave with a message identification for
multicast transmission between any network nodes.
7.9.1
LIN Features
The following are features of the LIN module:
• Compatible to LIN 1.3, 2.0 and 2.1 protocols
• Multibuffered receive and transmit units DMA capability for minimal CPU intervention
• Identification masks for message filtering
• Automatic Master Header Generation
– Programmable Synch Break Field
– Synch Field
– Identifier Field
• Slave Automatic Synchronization
– Synch break detection
– Optional baudrate update
– Synchronization Validation
• 231 programmable transmission rates with 7 fractional bits
• Error detection
• 2 interrupt lines with priority encoding
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7.10 Serial Communication Interface (SCI)
7.10.1 Features
•
•
•
•
•
•
•
•
•
•
•
128
Standard UART communication
Supports full- or half-duplex operation
Standard NRZ format
Double-buffered receive and transmit functions
Configurable frame format of 3 to 13 bits per character based on the following:
– Data word length programmable from 1 to 8 bits
– Additional address bit in address-bit mode
– Parity programmable for 0 or 1 parity bit, odd or even parity
– Stop programmable for 1 or 2 stop bits
Asynchronous or isosynchronous communication modes
Two multiprocessor communication formats allow communication between more than two devices.
Sleep mode is available to free CPU resources during multiprocessor communication.
The 24-bit programmable baud rate supports 224 different baud rates provide high-accuracy baud rate selection.
Four error flags and five status flags provide detailed information regarding SCI events.
Capability to use DMA for transmit and receive data.
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7.11 Inter-Integrated Circuit (I2C) Module
The I2C module is a multimaster communication module providing an interface between the RM4x
microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and
connected by an I2C-bus. This module will support any slave or master I2C compatible device.
7.11.1 Features
The I2C module has the following features:
• Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
– Bit or Byte format transfer
– 7- and 10-bit device addressing modes
– General call
– START byte
– Multimaster transmitter or slave receiver mode
– Multimaster receiver or slave transmitter mode
– Combined master transmit or receive and receive or transmit mode
– Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
• Free data format
• Two DMA events (transmit and receive)
• DMA event enable or disable capability
• Seven interrupts that can be used by the CPU
• Module enable or disable capability
• The SDA and SCL are optionally configurable as general-purpose I/O
• Slew rate control of the outputs
• Open-drain control of the outputs
• Programmable pullup or pulldown capability on the inputs
• Supports Ignore NACK mode
NOTE
This I2C module does not support:
• High-speed (HS) mode
• C-bus compatibility mode
• The combined format in 10-bit address mode (the I2C module sends the slave address
second byte every time it sends the slave address first byte)
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7.11.2 I2C I/O Timing Specifications
Table 7-31. I2C Signals (SDA and SCL) Switching Characteristics (1)
STANDARD MODE
PARAMETER
FAST MODE
UNIT
MIN
MAX
MIN
MAX
75.2
149
75.2
149
ns
0
100
0
400
kHz
tc(I2CCLK)
Cycle time, internal module clock for I2C,
prescaled from VCLK
f(SCL)
SCL clock frequency
tc(SCL)
Cycle time, SCL
10
2.5
µs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
µs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated
START condition)
4
0.6
µs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
100
ns
th(SDA-SCLL)
Hold time, SDA valid after SCL low (for I2C-bus
devices)
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
µs
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for STOP
condition)
4.0
0.6
µs
tw(SP)
Pulse duration, spike (must be suppressed)
Cb (3)
Capacitive load for each bus line
(1)
(2)
(3)
250
0
3.45
(2)
0
0.9
0
400
µs
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum th(SDA-SCLL) for I2C-bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
Cb = The total capacitance of one bus line in pF.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SCLL)
tw(SP)
tsu(SCLH-SDAH)
tw(SCLH)
tr(SCL)
SCL
tc(SCL)
tf(SCL)
th(SCLL-SDAL)
th(SDA-SCLL)
tsu(SCLH-SDAL)
th(SCLL-SDAL)
Stop
Start
Repeated Start
Stop
Figure 7-19. I2C Timings
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NOTE
•
•
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period
(tw(SCLL)) of the SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if
the device does not stretch the low period of the SCL signal (tw(SCLL)). If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line within tr max + tsu(SDA-SCLH). For the rise time, tr max value per load capacitance on the
SDA pin, see Table 7-2, Rise time, tr, 2-mA-z low-EMI pins MAX values.
• Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster falltimes are allowed.
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7.12 Multibuffered / Standard Serial Peripheral Interface
The MibSPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed
length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical
applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers,
and ADCs.
7.12.1 Features
Both standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 11-bit baud clock generator
• SPICLK can be internally generated (master mode) or received from an external clock source (slave
mode)
• Each word transferred can have a unique format
• SPI I/Os not used in the communication can be used as digital I/O signals
Table 7-32. MibSPI/SPI Configurations
MibSPIx/SPIx
I/Os
MibSPI1
MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA
MibSPI3
MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5
MIBSPI5SIMO[3:0], MIBSPI5SOMI[3:0], MIBSPI5CLK, MIBSPI5nCS[3:0], MIBSPI5nENA
SPI2
SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4
SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA
7.12.2 MibSPI Transmit and Receive RAM Organization
The multibuffer RAM is comprised of 128 buffers. Each entry in the multibuffer RAM consists of four parts:
a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx
module supports eight transfer groups.
7.12.3 MibSPI Transmit Trigger Events
Each transfer group can be configured individually. For each transfer group, a trigger event and a trigger
source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a
selectable trigger source. For example, up to 15 trigger sources are available which can be used by each
transfer group. These trigger options are listed in Table 7-33 and Section 7.12.3.2 for MibSPI1 and
MibSPI3, respectively.
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7.12.3.1 MibSPI1 Event Trigger Hookup
Table 7-33. MibSPI1 Event Trigger Hookup
EVENT NO.
TGxCTRL TRIGSRC[3:0]
TRIGGER
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
N2HET1[8]
EVENT9
1010
N2HET1[10]
EVENT10
1011
N2HET1[12]
EVENT11
1100
N2HET1[14]
EVENT12
1101
N2HET1[16]
EVENT13
1110
N2HET1[18]
EVENT14
1111
Intern Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI1 transfers; there is no multiplexing on the input connections.
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7.12.3.2 MibSPI3 Event Trigger Hookup
Table 7-34. MibSPI3 Event Trigger Hookup
EVENT NO.
TGxCTRL TRIGSRC[3:0]
TRIGGER
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
N2HET1[8]
EVENT9
1010
N2HET1[10]
EVENT10
1011
N2HET1[12]
EVENT11
1100
N2HET1[14]
EVENT12
1101
N2HET1[16]
EVENT13
1110
N2HET1[18]
EVENT14
1111
Intern Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI3 transfers; there is no multiplexing on the input connections.
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7.12.3.3 MibSPI5 Event Trigger Hookup
Table 7-35. MibSPI5 Event Trigger Hookup
EVENT NO.
TGxCTRL TRIGSRC[3:0]
TRIGGER
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
N2HET1[8]
EVENT9
1010
N2HET1[10]
EVENT10
1011
N2HET1[12]
EVENT11
1100
N2HET1[14]
EVENT12
1101
N2HET1[16]
EVENT13
1110
N2HET1[18]
EVENT14
1111
Intern Tick counter
NOTE
For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made
from the input side of the output buffer (at the N2HET1 module boundary). This way, a
trigger condition can be generated even if the N2HET1 signal is not selected to be output on
the pad.
NOTE
For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from
the output side of the input buffer. This way, a trigger condition can be generated either by
selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving
the GIOx pin from an external trigger source. If the mux control module is used to select
different functionality instead of the GIOx signal, then care must be taken to disable GIOx
from triggering MibSPI5 transfers; there is no multiplexing on the input connections.
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7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-36. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
1
PARAMETER
MIN
MAX
40
256tc(VCLK)
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
td(SPCH-SIMO)M
Delay time, SPISIMO valid before
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 6
td(SPCL-SIMO)M
Delay time, SPISIMO valid before
SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 6
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf(SPC) – 4
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5tc(SPC)M – tr(SPC) – 4
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
tf(SPC) + 2.2
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
tr(SPC) + 2.2
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
10
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
10
tc(SPC)M
Cycle time, SPICLK (4)
2 (5)
3 (5)
4 (5)
5
6
7
(5)
(5)
(5)
8 (6)
9 (6)
ns
ns
ns
ns
ns
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
- tf(SPICS) + tr(SPC) – 7
(C2TDELAY+2) * tc(VCLK) tf(SPICS) + tr(SPC) + 5.5
CSHOLD = 1
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
- tf(SPICS) + tr(SPC) – 7
(C2TDELAY+3) * tc(VCLK) tf(SPICS) + tr(SPC) + 5.5
Setup time CS active
until SPICLK low
(clock polarity = 1)
CSHOLD = 0
C2TDELAY*tc(VCLK) + 2*tc(VCLK)
- tf(SPICS) + tf(SPC) – 7
(C2TDELAY+2) * tc(VCLK) tf(SPICS) + tf(SPC) + 5.5
CSHOLD = 1
C2TDELAY*tc(VCLK) + 3*tc(VCLK)
- tf(SPICS) + tf(SPC) – 7
(C2TDELAY+3) * tc(VCLK) tf(SPICS) + tf(SPC) + 5.5
Hold time SPICLK low until CS inactive
(clock polarity = 0)
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) + tr(SPICS) - 7
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) + tr(SPICS) + 11
Hold time SPICLK high until CS
inactive (clock polarity = 1)
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) + tr(SPICS) - 7
0.5*tc(SPC)M +
T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) + tr(SPICS) + 11
(C2TDELAY+1) * tc(VCLK) tf(SPICS) – 29
(C2TDELAY+1)*tc(VCLK)
ns
(C2TDELAY+2)*tc(VCLK)
ns
tC2TDELAY
tT2CDELAY
SPIENAn Sample point
11
tSPIENAW
SPIENAn Sample point from write to
buffer
136
ns
CSHOLD = 0
tSPIENA
(5)
(6)
ns
Setup time CS active
until SPICLK high
(clock polarity = 0)
10
(1)
(2)
(3)
(4)
UNIT
ns
ns
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
For rise and fall timings, see Table 7-2.
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
SPISIMO
5
Master Out Data Is Valid
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 7-20. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
Master Out Data Is Valid
8
9
SPICSn
10
11
SPIENAn
Figure 7-21. SPI Master Mode Chip-Select Timing (CLOCK PHASE = 0)
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Table 7-37. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
1
2
3
4
5
6
7
PARAMETER
tc(SPC)M
Cycle time, SPICLK
tw(SPCH)M
MIN
(4)
256tc(VCLK)
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
tv(SIMO-SPCH)M
Valid time, SPICLK high after
SPISIMO data valid (clock polarity
= 0)
0.5tc(SPC)M – 6
tv(SIMO-SPCL)M
Valid time, SPICLK low after
SPISIMO data valid (clock polarity
= 1)
0.5tc(SPC)M – 6
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid
after SPICLK high (clock polarity =
0)
0.5tc(SPC)M – tr(SPC) – 4
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid
after SPICLK low (clock polarity =
1)
0.5tc(SPC)M – tf(SPC) – 4
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
tr(SPC)+ 2.2
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
tf(SPC)+ 2.2
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid
after SPICLK high (clock polarity =
0)
10
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid
after SPICLK low (clock polarity =
1)
10
(5)
(5)
(5)
(5)
(5)
(5)
(1)
(2)
(3)
(4)
(5)
(6)
138
ns
ns
ns
ns
0.5*tc(SPC)M + (C2TDELAY+3) *
tc(VCLK) tf(SPICS) + tr(SPC) – 7
0.5*tc(SPC)M + (C2TDELAY+3) *
tc(VCLK) tf(SPICS) + tr(SPC) + 5.5
CSHOLD =
0
0.5*tc(SPC)M + (C2TDELAY+2) *
tc(VCLK) tf(SPICS) + tf(SPC) – 7
0.5*tc(SPC)M + (C2TDELAY+2) *
tc(VCLK) tf(SPICS) + tf(SPC) + 5.5
CSHOLD =
1
0.5*tc(SPC)M + (C2TDELAY+3) *
tc(VCLK) tf(SPICS) + tf(SPC) – 7
0.5*tc(SPC)M + (C2TDELAY+3) *
tc(VCLK) tf(SPICS) + tf(SPC) + 5.5
Hold time SPICLK low until CS
inactive (clock polarity = 0)
T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) +
tr(SPICS) - 7
T2CDELAY*tc(VCLK) + tc(VCLK) tf(SPC) +
tr(SPICS) + 11
Hold time SPICLK high until CS
inactive (clock polarity = 1)
T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) +
tr(SPICS) - 7
T2CDELAY*tc(VCLK) + tc(VCLK) tr(SPC) +
tr(SPICS) + 11
Setup time CS
active until SPICLK
low (clock polarity =
1)
9 (6)
ns
0.5*tc(SPC)M + (C2TDELAY+2) *
tc(VCLK) tf(SPICS) + tr(SPC) + 5.5
tC2TDELAY
tT2CDELAY
ns
ns
0.5*tc(SPC)M + (C2TDELAY+2) *
tc(VCLK) tf(SPICS) + tr(SPC) – 7
CSHOLD =
Setup time CS
0
active until SPICLK
high (clock polarity =
CSHOLD =
0)
1
8 (6)
MAX UNIT
40
ns
ns
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
For rise and fall timings, see Table 7-2.
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.
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Table 7-37. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3) (continued)
NO.
PARAMETER
MIN
MAX UNIT
(C2TDELAY+1)* tc(VCLK) tf(SPICS) – 29
10
tSPIENA
SPIENAn Sample Point
11
tSPIENAW
SPIENAn Sample point from write
to buffer
(C2TDELAY+1)*tc(VCLK)
ns
(C2TDELAY+2)*tc(VCLK)
ns
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
Master Out Data Is Valid
SPISIMO
6
Data Valid
7
Master In Data
Must Be Valid
SPISOMI
Figure 7-22. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
Master Out Data Is Valid
8
9
SPICSn
10
11
SPIENAn
Figure 7-23. SPI Master Mode Chip-Select Timing (CLOCK PHASE = 1)
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7.12.5 SPI Slave Mode I/O Timings
Table 7-38. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input,
SPISIMO = input, and SPISOMI = output) (1) (2) (3) (4)
NO.
1
2 (6)
3 (6)
PARAMETER
6
7
40
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
14
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
14
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
14
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
14
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
trf(SOMI) + 20
td(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
trf(SOMI) + 20
th(SPCH-SOMI)S
Hold time, SPISOMI data valid after SPICLK high (clock
polarity =0)
2
th(SPCL-SOMI)S
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity
= 0)
4
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock
polarity = 1)
4
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
2
th(SPCH-SIMO)S
Hold time, SPISIMO data valid after S PICLK high
(clock polarity = 1)
2
td(SPCL-SENAH)S
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 0)
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+22
td(SPCH-SENAH)S
Delay time, SPIENAn high after last SPICLK high (clock
polarity = 1)
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+22
td(SCSL-SENAL)S
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
tf(ENAn)
tc(VCLK)+tf(ENAn)+27
(6)
(6)
(6)
8
9
(1)
(2)
(3)
(4)
(5)
(6)
140
MAX
Cycle time, SPICLK (5)
4 (6)
5
MIN
tc(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
For rise and fall timings, see Table 7-2.
tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI Data Is Valid
SPISOMI
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 7-24. SPI Slave Mode External Timing (CLOCK PHASE = 0)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
9
SPICSn
Figure 7-25. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
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Table 7-39. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output) (1) (2) (3) (4)
NO.
PARAMETER
MIN
MAX
UNIT
tc(SPC)S
Cycle time, SPICLK (5)
40
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
14
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
14
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
14
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
14
td(SOMI-SPCL)S
Delay time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
trf(SOMI) + 20
td(SOMI-SPCH)S
Delay time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
trf(SOMI) + 20
th(SPCL-SOMI)S
Hold time, SPISOMI data valid after SPICLK high
(clock polarity =0)
2
th(SPCH-SOMI)S
Hold time, SPISOMI data valid after SPICLK low (clock
polarity =1)
2
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock
polarity = 0)
4
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity
= 1)
4
tv(SPCH-SIMO)S
High time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
2
tv(SPCL-SIMO)S
High time, SPISIMO data valid after SPICLK low (clock
polarity = 1)
2
td(SPCH-SENAH)S
Delay time, SPIENAn high after last SPICLK high
(clock polarity = 0)
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+22
td(SPCL-SENAH)S
Delay time, SPIENAn high after last SPICLK low (clock
polarity = 1)
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+22
9
td(SCSL-SENAL)S
Delay time, SPIENAn low after SPICSn low (if new data
has been written to the SPI buffer)
tf(ENAn)
tc(VCLK)+tf(ENAn)
+27
ns
10
td(SCSL-SOMI)S
Delay time, SOMI valid after SPICSn low (if new data
has been written to the SPI buffer)
tc(VCLK)
2tc(VCLK)+trf(SOMI)+28
ns
1
2 (6)
3 (6)
4
5
6
7
(6)
(6)
(6)
(6)
8
(1)
(2)
(3)
(4)
(5)
(6)
142
ns
ns
ns
ns
ns
ns
ns
ns
The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
For rise and fall timings, see Table 7-2.
tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 7-26. SPI Slave Mode External Timing (CLOCK PHASE = 1)
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
8
SPIENAn
9
SPICSn
10
SPISOMI
Slave Out Data Is Valid
Figure 7-27. SPI Slave Mode Enable Timing (CLOCK PHASE = 1)
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8 Applications, Implementation, and Layout
NOTE
Information in the following sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
8.1
TI Designs or Reference Designs
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jump start your system design, all TI
Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.
Search and download designs at TIDesigns.
144
Applications, Implementation, and Layout
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9 Device and Documentation Support
9.1
Getting Started and Next Steps
To get started using a RM Hercules™ ARM® Cortex®-R Microcontroller (MCU):
1. Purchase a RM LaunchPad Development Kit with the LaunchPAD Quickstart Guide included.
From the LaunchPAD Quickstart Guide, the user can easily determine the correct Code Composer
Studio™ (CCS) Integrated Development Environment (IDE) and Hardware Abstraction Layer Code
Generator (HALCoGen™) GUI-based chip configuration tool for any selected Hercules MCU device(s).
2. Download the latest version of CCS IDE for Safety MCUs for the specified host platform (that is,
Windows, Linux, or MacOS) (free as long as using a LaunchPAD or a Hercules MCU Development Kit
[HDK])
3. Under Order Now, download the HALCOGEN: HAL Code Generator tool.
4. For additional tools and software descriptions, web page links, key docs, and so forth, see Tools and
Software.
The Hercules RM family also has TI BoosterPack™ plug-in modules available that fit on top of a
LaunchPad development kit.
9.2
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of
all devices.Each device has one of three prefixes: X, P, or null (no prefix) (for example, xRM44L920).
These prefixes represent evolutionary stages of product development from engineering prototypes
through fully qualified production devices.
Device development evolutionary flow:
x
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Fully-qualified production device.
x and P devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices have been characterized fully, and the quality and reliability of the device have
been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to
be used.
Figure 9-1 shows the numbering and symbol nomenclature for the RM44Lx20 devices.
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R M 4 4 L 9 2 0 A PGE T R
Shipping Options:
Prefix:
R = Tape and Reel
x = Not Qualified
Removed when qualified
Temperature Range:
RM = Real Time Microcontroller
T = -40 to +105öC
Package Type:
CPU:
PGE = 144-Pin Plastic Quad Flatpack
PZ = 100-Pin Plastic Quad Flatpack
4 = ARM Cortex-R4
Die Revision:
Series Number
Blank = Die Revision 0
A = Die Revision A
Architecture:
L = Lockstep
Frequency:
Flash / RAM Size:
Reserved:
0 = 120 MHz for PZ or 180 MHz for PGE
9 = 1MB flash, 128KB RAM
5 = 768KB flash, 128KB RAM
Figure 9-1. RM44Lx20 Device Numbering Conventions
146
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9.3
SPNS229C – OCTOBER 2014 – REVISED NOVEMBER 2016
Tools and Software
TI offers an extensive line of tools and software for the Hercules™ Safety generation of MCUs including
development tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
9.3.1
Kits and Evaluation Modules for Hercules RM MCUs
The RM Hercules™ ARM® Cortex®-R Microcontrollers (MCUs) offer a variety of hardware platforms to
help speed development. From low-cost LaunchPad™ development kits to full-featured application
developer platforms, the Hercules RM MCUs provide a wide range of hardware development tools
designed to aid development and get customers to market faster.
Hercules™ RM46x LaunchPad™ Development Kit
LAUNCHXL2-RM46 — The Hercules RM46x LaunchPad development kit is a low-cost evaluation platform
that helps users get started quickly in evaluating and developing with the Hercules microcontroller family,
which is specifically designed for IEC 61508 functional safety applications. The LaunchPad features
onboard emulation for programming and debugging; push-buttons; LEDs and ambient light sensor; and
two standard 40-pin BoosterPack expansion connectors. Through the expansion connectors, the
LaunchPad development kit can support a wide range of BoosterPack plug-in modules for added
functionality (such as displays, wireless sensors, and so forth). LaunchPad development kits come
preprogrammed with a demo code that lets the user easily learn the key safety, data acquisition, and
control features of the Hercules MCU platform. For additional software downloads and other resources,
visit the Hercules LaunchPads wiki.
9.3.2
Development Tools
Development tools includes both hardware and software development tools like integrated development
environment (IDE), compilers, and emulators.
Software
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) – Code Composer Studio is
an integrated development environment (IDE) that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features. The intuitive IDE provides a single user
interface taking the user through each step of the application development flow. Familiar tools and
interfaces allow users to get started faster than ever before. Code Composer Studio combines the
advantages of the Eclipse software framework with advanced embedded debug capabilities from TI
resulting in a compelling feature-rich development environment for embedded developers.
CCS Uniflash Standalone Flash Tool for TI Microcontrollers (MCUs) [available free of charge] – CCS
Uniflash is a standalone tool used to program the on-chip flash memory available on TI MCUs. The CCS
Uniflash has a GUI, command line, and scripting interface.
SafeTI™ Compiler Qualification Kit – The SafeTI Compiler Qualification Kit was developed to assist
customers in qualifying their use of the TI ARM or C2000 C/C++ Compiler to functional safety standards
such as IEC 61508 SIL 3 and ISO 26262 ASIL D.
High-End Timer Integrated Development Environment (HET IDE) – The HET module available on the
Hercules MCU devices is a programmable timer coprocessor that enables sophisticated functions for realtime control applications. The HET IDE is a windows-based application that provides an easy way to get
started developing and debugging code for the HET module.
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Hardware
Emulators
Below is a list of some emulators that can be used with the Hercules RM MCU devices. For a full list of
emulators, click on the Emulators link above.
XDS100v2 – Low-cost, low-performance emulator – integrated on Hercules RM MCU Development Kits.
With CCS IDE and IAR support.
XDS200 – The XDS200 is a JTAG emulator for TI embedded processors. Offering a balance of cost and
performance, XDS200 emulator fits between the ultra-low cost XDS100 and the high-performance
XDS560v2 products.
XDS560v2 – The XDS560™ family of emulators is designed to achieve high download speeds and is
ideal for larger applications.
9.3.3
Software
Software includes Real-Time Operating Systems (RTOS), peripheral drivers, libraries, example code, and
connectivity.
Hercules MCU software is designed to simplify and speed development of functional safety applications.
Hardware Abstraction Layer Code Generator (HALCoGen) for Hercules MCUs provides a graphical user
interface that allows the user to configure peripherals, interrupts, clocks, and many other MCU parameters
and can generate driver code which can be easily imported into integrated development environments like
CCS IDE, IAR Workbench, etc. The HALCoGen tool also includes several example projects.
SafeTI HALCoGen Compliance Support Package (CSP) assists customers using HALCoGen to comply
with functional safety standards by providing example documentation, reports, and unit-test capability.
The SafeTI Hercules Diagnostic Library is a software library of functions and response handlers for
various safety features of the Hercules Safety MCUs.
SafeTI Hercules Diagnostic Library CSP assists customers using the SafeTI Diagnostic Library to comply
with functional safety standards by providing documentation and reports.
Hercules™ Safety MCU Cortex®-R4 CMSIS DSP Library. The ARM® Cortex® Microcontroller Software
Interface Standard (CMSIS) includes over 60 functions covering vector operations, matrix computing,
complex arithmetic, filter functions, control functions, PID controller, Fourier transforms, and many other
frequently used DSP algorithms. Most algorithms are available in floating-point and various fixed-point
formats and are optimized for the Cortex-R series processors.
Hercules™ F021 Flash API provides a software library of functions to program, erase, and verify F021 onchip flash memory Hercules devices.
The Hercules™ RM MCUs are supported by many different Real-Time Operating Systems (RTOS) and
Connectivity/Middleware options from various providers, some of which are safety certified.
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Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The following documents describe the processor, related internal peripherals, and other technical collateral
with respect to the RM44Lx microcontroller.
Errata
RM44Lx20 16/32-Bit RISC Flash Microcontroller Silicon Errata (Silicon Revision 0) (SPNZ209)
describes the known exceptions to the functional specifications for the device.
RM44Lx20 16/32-Bit RISC Flash Microcontroller Silicon Errata (Silicon Revision A) (SPNZ231)
describes the known exceptions to the functional specifications for the device.
Technical Reference Manuals
RM44Lx 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU608) details the
integration, the environment, the functional description, and the programming models for each peripheral
and subsystem in the device.
Applications Reports
Compatibility Considerations: Migrating From RM48x or RM46x to RM44Lx20 Safety
Microcontrollers (SPNA206) provides a summary of the differences between the RM44Lx20 versus the
RM48x and RM46x series of microcontrollers.
9.5
Related Links
Table 9-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9-1. Related Links
9.6
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
RM44L920
Click here
Click here
Click here
Click here
Click here
RM44L520
Click here
Click here
Click here
Click here
Click here
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-ro-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
Hercules™ Safety Microcontrollers Forum TI's Hercules™ Safety Microcontrollers Forum was created
under the E2E umbrella to foster collaboration among engineers, ask questions, share
knowledge, explore ideas, and help solve problems, specifically relating to the Hercules
Safety MCUs (that is, TMS570 and RM families).
SafeTI™ Documentation Private E2E Forum A private E2E forum to request access to the safety
analysis report; ask questions; share knowledge; and explore ideas to help resolve problems
relating to the safety analysis report. This forum is closely monitored by the TI Safety
experts. The safety analysis report itself includes detailed device-level Failure Modes,
Effects, and Diagnostics Analysis (FMEDA) for ISO 26262 functional safety applications. The
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report also includes tools for estimating module and device-level failure rates (fault insertion
tests (FIT) rates).
9.7
Trademarks
BoosterPack, Hercules, LaunchPad, XDS560, E2E are trademarks of Texas Instruments.
CoreSight is a trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved.
ARM, Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved.
All other trademarks are the property of their respective owners.
9.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.9
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
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9.10 Device Identification
9.10.1 Device Identification Code Register
The device identification code register at address 0xFFFFFFF0 identifies several aspects of the device
including the silicon version. The details of the device identification code register are shown in Table 9-2.
The device identification code register value for this device is:
• Rev 0 = 0x8052AD05
• Rev A = 0x8052AD0D
Figure 9-2. Device ID Bit Allocation Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CP15
UNIQUE ID
TECH
R-1
R-00000000101001
R-0
15
12
11
2
1
0
TECH
14
13
I/O
VOLT
AGE
PERIPH
PARITY
FLASH ECC
10
9
RAM
ECC
8
7
6
REVISION
5
4
3
1
0
1
R-101
R-0
R-1
R-10
R-1
R-00000
R-1
R-0
R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-2. Device ID Bit Allocation Register Field Descriptions
BIT
FIELD
31
VALUE
Indicates the presence of coprocessor 15
CP15
1
30-17
UNIQUE ID
16-13
TECH
101001
CP15 present
Unique device identification number
This bitfield holds a unique number for a dedicated device configuration (die).
Process technology on which the device is manufactured.
0101
12
I/O VOLTAGE
11
PERIPH PARITY
10-9
DESCRIPTION
FLASH ECC
F021
I/O voltage of the device.
0
I/O are 3.3 V
1
Peripheral Parity
Parity on peripheral memories
Flash ECC
10
Program memory with ECC
Indicates if RAM ECC is present.
8
RAM ECC
7-3
REVISION
Revision of the Device.
2-0
101
The platform family ID is always 0b101
1
ECC implemented
9.10.2 Die Identification Registers
The two die ID registers at addresses 0xFFFFFF7C and 0xFFFFFF80 form a 64-bit dieid with the
information as shown in Table 9-3.
Table 9-3. Die-ID Registers
ITEM
NO. OF BITS
BIT LOCATION
X Coord. on Wafer
12
0xFFFFFF7C[11:0]
Y Coord. on Wafer
12
0xFFFFFF7C[23:12]
Wafer #
8
0xFFFFFF7C[31:24]
Lot #
24
0xFFFFFF80[23:0]
Reserved
8
0xFFFFFF80[31:24]
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9.11 Module Certifications
The following communications modules have received certification of adherence to a standard.
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9.11.1 DCAN Certification
Figure 9-3. DCAN Certification
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9.11.2 LIN Certification
9.11.2.1 LIN Master Mode
Figure 9-4. LIN Certification - Master Mode
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9.11.2.2 LIN Slave Mode - Fixed Baud Rate
Figure 9-5. LIN Certification - Slave Mode - Fixed Baud Rate
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9.11.2.3 LIN Slave Mode - Adaptive Baud Rate
Figure 9-6. LIN Certification - Slave Mode - Adaptive Baud Rate
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10 Mechanical Packaging and Orderable Information
10.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
without revision of this document. For browser-based versions of this data sheet, refer to the left-hand
navigation.
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
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5-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
RM44L520APGET
ACTIVE
LQFP
PGE
144
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
RM44
L520APGET
RM44L520APZT
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
RM44
L520APZT
RM44L520APZTR
ACTIVE
LQFP
PZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
RM44
L520APZT
RM44L920APGET
ACTIVE
LQFP
PGE
144
60
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
RM44
L920APGET
RM44L920APZT
ACTIVE
LQFP
PZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 105
RM44
L920APZT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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