SCAN25100TYA/NOPB

SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 SCAN25100 2457.6, 1228.8, and 614.4 Mbps CPRI SerDes with Auto RE Sync and Precision Delay Calibration Measurement Check for Samples: SCAN25100 FEATURES DESCRIPTION • The SCAN25100 is a 2457.6, 1228.8, and 614.4 Mbps serializer/deseralizer (SerDes) for high-speed bidirectional serial data transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. The SCAN25100 integrates precision delay calibration measurement (DCM) circuitry that measures link delay components to better than ± 800 ps accuracy. 1 2 • • • • • • • • • • • • • • • • Exceeds LV and HV CPRI Voltage and Jitter Requirements 2457.6, 1228.8, and 614.4 Mbps Operation Integrated Delay Calibration Measurement (DCM) Directly Measures T14 and Toffset Delays to ≤ ± 800 ps DCM Also Measures Chip and Other Delays to ≤ ± 1200 ps Accuracy Deterministic Chip Latency Independent Transmit and Receive PLLs for Seamless RE Synchronization Low Noise Recovered Clock Output Requires No Jitter Cleaning in Single-Hop Applications >8 kV ESD on the CML IO, >7 kV on All Other Pins, >2 kV CDM Hot Plug Protection LOS, LOF, 8b/10b Line Code Violation, Comma, and Receiver PLL Lock Reporting Programmable Hyperframe Length and Start of Hyperframe Character Programmable Transmit De-Emphasis and Receive Equalization With On-Chip Termination Advanced Testability Features – IEEE 1149.1 and 1149.6 – At-Speed BIST Pattern Generator/Verifier – Multiple Loopback Modes 1.8V or 3.3V Compatible Parallel Bus Interface 100-pin HTQFP Package with Exposed Dap Industrial –40 to +85° C Temperature Range The SCAN25100 features independent transmit and receive PLLs, on-chip oscillator, and intelligent clock management circuitry to automatically perform remote radio head synchronization and reduce the cost and complexity of external clock networks. The SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable transmitter de-emphasis, receiver equalization, speed rate selection, internal pattern generation/verification, and loop back modes. In addition to at-speed BIST, the SCAN25100 includes IEEE 1149.1 and 1149.6 testability. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated SCAN25100 SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 www.ti.com Block Diagram Rate Select etc. MDIO Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay Calibration (Enable, Measurement) RXCLK CDR Clock Line Loop Back Output FIFO ROUT [0:9] REFCLK Special Local Loop Back TXCLK 8b/10b Encoder 8b/10b Decoder DeEmphasis PLL Parallel to Serial Local Loop Back Input FIFO Pattern Generator Serial to Parrallel DOUT r Special Line Loop Back Pin Control DIN [0:9] REFCLK (30.72 MHz) Equalizer Control RIN r CDR Pattern Verifier Precision Delay Calibration Measurement JTAG LOS SYSCLK (30.72 MHz) GND DIN[9] DIN[8] DIN[7] DIN[6] DIN[5] DIN[4] DIN[3] DIN[2] DIN[1] DIN[0] TXCLK GND ROUT[9] ROUT[8] ROUT[7] ROUT[6] ROUT[5] ROUT[4] ROUT[3] ROUT[2] ROUT[1] ROUT[0] RXCLK IOVDD Pin Diagram 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 38 PIN 101 88 37 89 DAP / GND 36 90 35 91 34 92 33 93 32 ON BOTTOM OF PKG 94 31 95 30 96 29 97 28 98 27 99 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SCAN25100 IOVDD GND GND AVDD18 TRSTB TDI TMS TCK AVDD33 TDO GND GND AVDD18 ADD0 ADD1 ADD2 ADD3 ADD4 AVDD18 MDIO MDC PVDD33 PVDD33 GND GND PVDD33 PVDD33 GND GND GND REFCLKP REFCLKN AVDD33 AVDD18 GND DOUTN DOUTP GND AVDD33 AVDD18 GND RINN RINP GND AVDD18 AVDD33 SYSCLKP SYSCLKN GND GND IOVDD LOCKB LOS CDET VSEL PE[1] PE[0] RES1 RES2 AVDD18 GND IOVDD EQ[0] EQ[1] TXPWDNB RXPWDNB CALIGN_EN RXCLKMODE OPMODE RESETB SPMODE[0] SPMODE[1] TENBMODE LOOP[0] LOOP[1] Figure 1. SCAN25100- Top View 100–Pin HTQFP with Exposed Ground Pad See Package Drawing PFD0100B 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: SCAN25100 SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS (1) Pin # Pin Name I/O, Type Description HIGH SPEED DIFFERENTIAL I/O 12 11 DOUTP DOUTN O, CML Inverting and non-inverting high speed CML differential outputs of the serializer. On-chip termination resistors connect from DO+ and DO− to an internal reference 18 17 RINP RINN I, CML Inverting and non-inverting high speed differential inputs of the deseralizer. On-chip termination resistors connect from RI+ and RI− to an internal reference. On-chip termination resistors are configured for AC-coupled applications. PARALLEL DATA BUS 65 66 67 68 69 70 71 72 73 74 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] 53 54 55 56 57 58 59 60 61 62 ROUT [0] ROUT [1] ROUT [2] ROUT [3] ROUT [4] ROUT [5] ROUT [6] ROUT [7] ROUT [8] ROUT [9] I, LVTTL or 1.8V LVCMOS Internal pull down Transmit data word. In 10-bit mode, the 10-bit code-group at DIN [0–9] is serialized with the internal 8b/10b encoder disabled. Bit 9 is the msb. In 8-bit mode, DIN [0-7] is first converted into 10-bit code-group by the internal 8b/10b encoder before it is serialized. Bit 7 is the msb. DIN [8] is used as K-code select pin and DIN[9] should be tied Low. When DIN [8] is low, DIN [0-7] is mapped to the corresponding 10-bit D-group. When DIN [8] is high, DIN [0-7] is mapped to the corresponding 10-bit K-group. The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 O, LVTTL or 1.8V LVCMOS Internal pull down Deserialized receive data word. In 10-bit mode, ROUT [0-9] is the deserialized received data word in 10-bit code group. Bit 9 is the msb. In 8-bit mode, ROUT [0-7] is the deserialized received data byte. Bit 7 is the msb. ROUT [8] is the K-group indicator. A low at ROUT [8] indicates ROUT [0-7] belongs to the Dgroup, while a high indicates it belongs to the K-group. ROUT [9] is the line code violation (LCV) indicator. ROUT [9] is high for one ROUT cycle when a line code violation occurs. The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 CLOCK SIGNALS 6 7 REFCLKP REFCLKN 64 TXCLK 52 RXCLK 22 23 SYSCLKP SYSCLKN I, LVDS or LVPECL I, LVTTL or 1.8V LVCMOS Internal pull down Inverting and non-inverting differential serializer reference clock . A low jitter clock source should be connected to REFCLKP & REFCLKN. Transmit clock. TXCLK must be synchronous to REFCLK to avoid FIFO over/underflow though it may differ in phase. I/O, LVTTL or 1.8V Write mode: RXCLK is a recovered clock output pin. LVCMOS Read mode: RXCLK is an input pin. ROUT [9:0] are latched out on RXCLK rising and falling edges. RXCLK must be synchronous to the incoming serial data to avoid FIFO over/underflow, though it may differ in phase. See RXCLKMODE pin description for more details. O, LVDS 30.72 MHz output clock. (OPMODE must be low.) LINE STATUS 78 LOS O, LVTTL or 1.8V LVCMOS Receiver CPRI loss of signal (LOS) status (8-bit mode only). 0 = signal detected (per CPRI standard) 1 = signal lost (per CPRI standard) See LOS DETECTION under Functional Description for more details. 77 LOCKB O, LVTTL or 1.8V LVCMOS Receiver PLL lock status 0 = Receiver PLL locked 1 = Receiver PLL not locked 79 CDET O, LVTTL or 1.8V LVCMOS Comma Detect. 0 = no comma yet detected in the incoming serial stream or receiver PLL not locked. 1 = the receiver PLL is locked and a positive or negative comma bit sequence detected in the incoming bit stream. The serial to parallel converter is aligned to the proper 10-bit word boundary when comma alignment is enabled (CALIGN_EN = 1). (1) Note: I= input O = output Internal pull down = input pin is pulled low by an internal resistor pulled high by an internal resistor Internal pull up = input pin is Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: SCAN25100 3 SCAN25100 SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS(1) (continued) Pin # Pin Name I/O, Type Description CONTROL PINS 82 81 88 89 EQ [0] EQ [1] I, LVTTL or 1.8V LVCMOS Internal pull down I, LVTTL or 1.8V LVCMOS Internal pull down Transmitter de-emphasis configuration. Pulling both pins low enables MDIO control, default is no de-emphasis. PE1 PE0 0 0 No de-emphasis 0 1 Low de-emphasis 1 0 Medium de-emphasis 1 1 Maximum de-emphasis Receive input equalization configuration. Pulling both pins low enables MDIO control, default is no receive equalization. EQ1 EQ0 0 0 No receive equalization 0 1 Low receive equalization 1 0 Medium receive equalization 1 1 Maximum receive equalization 90 91 TXPWDNB RXPWDNB I, LVTTL or 1.8V LVCMOS Internal pull down Power down control signals. TXPWDNB 0 = Transmitter is powered down and DOUT± pins are high impedance. 1 = Transmitter is powered up. RXPWDNB 0 = Receiver is powered down and ROUT [9:0] as well as LOS, LOCKB, CDET, RXCLK, and SYSCLK are high impedance. 1 = Receiver is powered up. 92 CALIGN_EN I, LVTTL or 1.8V LVCMOS Internal pull down Comma alignment enable. 0 = comma alignment circuitry disabled. Receiver will not realign 10-bit data based on incoming comma characters. CDET pin still flags comma detection. 1 = comma detect and alignment circuitry enabled. Receiver aligns 10-bit data to incoming comma character and flags comma detect through CDET pin. 93 RXCLKMODE I, LVTTL or 1.8V LVCMOS Internal pull down Receiver recovered clock mode 0 = Write mode. RXCLK pin is a recovered clock output. (RXCLK = output pin) 1 = Read mode. RXCLK pin is ROUT [9:0] bus read input strobe. (RXCLK = input pin) 80 VSEL I, LVTTL or 1.8V LVCMOS Internal pull down Selects whether single-ended data and control pins are 3.3V LVTTL or 1.8V LVCMOS. 0 = 1.8V LVCMOS. Tie VSEL to ground and power IOVDD at 1.8 V. 1 = 3.3V LVTTL. Tie VSEL to IOVDD supply and power IOVDD at 3.3 V. 94 OPMODE I, LVTTL or 1.8V LVCMOS Internal pull down Selects SerDes mode. I, LVTTL or 1.8V LVCMOS Internal pull down Hardware SerDes reset. Resets PLLs and MDIO registers. I, LVTTL or 1.8V LVCMOS Internal pull down Speed mode configuration. (OPMODE must be low) Pulling both pins low enables MDIO control. 95 96 97 98 4 PE [0] PE [1] RESETB SPMODE [0] SPMODE [1] TENBMODE I, LVTTL or 1.8V LVCMOS, Internal pull down 0 = Base station mode 1 = Reserved for future use 0 = Hardware SerDes reset 1 = Normal operation SPMODE [1] SPMODE [0] 0 0 Rate selected via MDIO 0 1 614.4 Mbps rate mode 1 0 1228.8 Mbps rate mode 1 1 2457.6 Mbps rate mode Enable 10-bit mode The 8B/10B specification is defined in IEEE 802.3-2000 section 36.2.2 0 = Selects 8-bit mode. Enables the internal 8b/10b encoder and decoder. 1 = Selects 10-bit mode. Bypasses internal 8b/10b encoder and decoder. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: SCAN25100 SCAN25100 www.ti.com SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS(1) (continued) Pin # 99 100 Pin Name LOOP [0] LOOP [1] I/O, Type I, LVTTL or 1.8V LVCMOS, Internal pull down Description Loop back configuration. Pulling both pins low enables MDIO control. Note: During Special line (remote) loop back mode, the output de-emphasis control is disabled. LOOP [1] LOOP [0] 0 0 Normal mode—no loop back 0 1 Line (remote) loop back mode 1 0 Local loop back mode 1 1 Special line (remote) loop back mode MDC/MDIO 30 31 37 36 35 34 33 MDC MDIO ADD0 ADD1 ADD2 ADD3 ADD4 3.3V LVTTL Internal pull up on ADDR pins MDC/MDIO configuration bus. Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not 1.2V signal compatible. 3.3V LVTTL Internal pull up on TDI, TMS, and TRSTB JTAG test bus for IEEE 1149.1 and 1149.6 support. IEEE 1149.1 (JTAG) 45 41 44 43 46 TDI TDO TMS TCK TRSTB RESERVED PINS 83 84 RES1 RES2 I Reserved. Tie with 5 KΩ resistor to ground. POWER 9, 15, 20, AVDD18 32, 38, 47, 85 I, Power 1.8V analog supply. 8, 14, 21, 42 AVDD33 I, Power 3.3V analog supply. 1, 2, 28, 29 PVDD33 I, Power 3.3V PLL supply (minimize supply noise to < 100 mV peak-to-peak). I, Power 1.8V or 3.3V parallel I/O bus and control pin supply. See VSEL pin description for additional information. I, Ground Device ground. I, Ground Device ground. Pad must be soldered and contected to GND plane with a minimum of 8 thermal vias to achieve specified thermal performance. 50, 51, 76, IOVDD 87 GROUND 3, 4, 5, 10, GND 13, 16, 19, 24, 25, 26, 27, 39, 40, 48, 49, 63, 75, 86 GROUND DAP 101 GND Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: SCAN25100 5 SCAN25100 SNLS223C – SEPTEMBER 2006 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (AVDD18) −0.3V to +2.0V Supply Voltage (PVDD, IOVDD) −0.3V to +3.6V Supply Voltage (AVDD33) −0.3V to +3.6V −0.3V to (IOVDD + 0.5V) LVCMOS Input Voltage −0.3V to (IOVDD + 0.5V) LVCMOS Output Voltage MDC/MDIO/ADD[0:4],VSEL Input Voltage −0.3V to (AVDD33 + 0.5V) MDIO Output Voltage −0.3V to (AVDD33 + 0.5V) CML Receiver Input Voltage −0.3V to (AVDD + 0.3V) CML Receiver Output Voltage −0.3V to (AVDD + 0.3V) Junction Temperature +125°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 10–20 sec) 235 °C Lead-free +260°C flow is available Maximum Package Power Dissipation at 25°C 100-pin HTQFP with Exposed Pad 4.16 W Derating above 25°C 41.6 mW/°C Thermal Resistance , θJA (0 airflow) ESD Rating 24.0°C/W CML RIN/DOUT Pins HBM, 1.5 kΩ, 100 pF >8 kV EIAJ, 0Ω, 200 pF >250V CDM All Other Pins >2 kV HBM, 1.5 kΩ, 100 pF >7 kV EIAJ, 0Ω, 200 pF >250V CDM (1) (2) (3) >2 kV “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. This is the maximum HTQFP-100 package power dissipation capability. For SCAN25100 power dissipation, see the information in the Electrical Characteristics section. Recommended Operating Conditions Min Typ Max Unit 1.7 1.8 1.9 V Supply Voltage AVDD18 AVDD33, PVDD33 3.135 3.3 3.465 V IOVDD (1.8V Mode) 1.7 1.8 1.9 V IOVDD (3.3V Mode) 3.135 3.3 3.465 V -40 25 85 °C Temperature Junction temperature 125 °C Supply Noise (Peak-to-Peak)