SCAN90004EVK

SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis Check for Samples: SCAN90004 FEATURES DESCRIPTION • • The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flowthrough pinout minimize internal device jitter and simplify board layout, while configurable preemphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes. 1 2 • • • • • • • • • • • • 1.5 Gbps Maximum Data Rate Per Channel Configurable Pre-emphasis Drives Lossy Backplanes and Cables Low Output Skew and Jitter LVDS/CML/LVPECL Compatible Input, LVDS Output On-chip 100Ω Input and Output Termination 12 kV ESD Protection on LVDS Outputs IEEE 1149.1 JTAG Interface IEEE 1149.6 Limited Capability Fault Insertion Single 3.3V Supply Very Low Power Consumption Industrial -40 to +85°C Temperature Range Small TQFP Package Footprint See DS90LV004 for Non-JTAG Version Integrated testability circuitry supports IEEE1149.1 (JTAG) on single-ended LVTTL/CMOS I/O and limited IEEE1149.6 capability on high-speed differential LVDS interconnects. The 3.3V supply, CMOS process, and LVDS I/O ensure stable high performance at low power over the entire industrial 40 to +85°C temperature range. Typical Application LVDS I/O FPGA or ASIC Cable or Backplane LVDS I/O FPGA or ASIC SCAN90004 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated SCAN90004 SNLS182P – MAY 2005 – REVISED APRIL 2013 www.ti.com Pre-emphasis and Control IN0+ IN0- GND GND OUT3- OUT3+ OUT2- OUT2+ GND GND OUT1- OUT1+ PEM0 PEM1 PWDN OUT0- OUT0+ Block and Connection Diagrams 48 47 46 45 44 43 42 41 40 39 38 37 PEM0 1 36 N/C OUT0+ PEM1 2 35 TDO OUT0- VDD 3 34 TDI VDD 4 33 VDD 32 VDD 31 N/C 30 N/C VDD 5 IN1+ OUT1+ N/C 6 IN1- OUT1- VDD 7 GND 8 29 VDD GND 9 28 VDD VDD 10 27 TMS VDD 11 26 TCK PWDN 12 25 TRST IN2+ OUT2+ IN2- OUT2- SCAN90004 (TQFP) TDI IEEE 1149.1 TAP (JTAG) & 1149.6 GND IN3- GND IN3+ IN2- IN2+ GND IN1- GND OUT3- IN1+ IN3- IN0- OUT3+ IN0+ 13 14 15 16 17 18 19 20 21 22 23 24 IN3+ TDO TCK TMS TRST Figure 1. SCAN90004 Block Diagram Figure 2. Pinout - Top View Pin Descriptions Pin Name TQFP Pin Number I/O, Type Description DIFFERENTIAL INPUTS IN0+ IN0− 13 14 I, LVDS Channel 0 inverting and non-inverting differential inputs. IN1+ IN1− 15 16 I, LVDS Channel 1 inverting and non-inverting differential inputs. IN2+ IN2− 19 20 I, LVDS Channel 2 inverting and non-inverting differential inputs. IN3+ IN3− 21 22 I, LVDS Channel 3 inverting and non-inverting differential inputs. OUT0+ OUT0− 48 47 O, LVDS Channel 0 inverting and non-inverting differential outputs. (1) OUT1+ OUT1− 46 45 O, LVDS Channel 1 inverting and non-inverting differential outputs. (1) OUT2+ OUT2− 42 41 O, LVDS Channel 2 inverting and non-inverting differential outputs. (1) OUT3+ OUT3- 40 39 O, LVDS Channel 3 inverting and non-inverting differential outputs. (1) I, LVTTL A logic low at PWDN activates the hardware power down mode. DIFFERENTIAL OUTPUTS DIGITAL CONTROL INTERFACE PWDN (1) 2 12 The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90004 device have been optimized for point-to-point backplane and cable applications. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 Pin Descriptions (continued) Pin Name TQFP Pin Number I/O, Type Description PEM0 PEM1 1 2 I, LVTTL Pre-emphasis Control Inputs (affects all Channels) TDI 34 I, LVTTL Test Data Input to support IEEE 1149.1 features TDO 35 O, LVTTL Test Data Output to support IEEE 1149.1 features TMS 27 I, LVTTL Test Mode Select to support IEEE 1149.1 features TCK 26 I, LVTTL Test Clock to support IEEE 1149.1 features TRST 25 I, LVTTL Test Reset to support IEEE 1149.1 features VDD 3, 4, 5, 7, 10, 11, 28, 29, 32, 33 I, Power VDD = 3.3V, ±5% GND 8, 9, 17, 18, 23, 24, 37, 38, 43, 44 I, Power Ground N/C 6, 30, 31, 36 POWER No Connect These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) Supply Voltage (VDD) −0.3V to +4.0V CMOS Input Voltage -0.3V to (VDD+0.3V) LVDS Input Voltage (2) -0.3V to (VDD+0.3V) LVDS Output Voltage -0.3V to (VDD+0.3V) LVDS Output Short Circuit Current +40 mA Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Solder, 4sec) 260°C Max Pkg Power Capacity @ 25°C 1.64W Thermal Resistance (θJA) 76°C/W Package Derating above +25°C 13.2mW/°C ESD Last Passing Voltage (LVDS output pins) HBM, 1.5kΩ, 100pF 12kV EIAJ, 0Ω, 200pF 250V ESD Last Passing Voltage (All other pins) HBM, 1.5kΩ, 100pF 8kV EIAJ, 0Ω, 200pF (1) (2) 250V Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI does not recommend operation of products outside of recommended operation conditions. VID max < 2.4V Recommended Operating Conditions Supply Voltage (VDD) Input Voltage (VI) 3.15V to 3.45V (1) 0V to VDD Output Voltage (VO) 0V to VDD −40°C to +85°C Operating Temperature (TA) Industrial (1) VID max < 2.4V Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 3 SCAN90004 SNLS182P – MAY 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (1) Max Units V LVTTL DC SPECIFICATIONS (PWDN, PEM0, PEM1, TDI, TDO, TCK, TMS, TRST) VIH High Level Input Voltage 2.0 VDD VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA IILR Low Level Input Current TDI, TMS, TRST -40 -200 µA CIN1 Input Capacitance Any Digital Input Pin to VSS COUT1 Output Capacitance Any Digital Output Pin to VSS VCL Input Clamp Voltage ICL = −18 mA VOH High Level Output Voltage (TDO) IOH = −12 mA, VDD = 3.15 V 2.4 IOH = −100 µA, VDD = 3.15 V VDD-0.2 VOL Low Level Output Voltage (TDO) IOL = 12 mA, VDD = 3.15 V 0.5 IOL = 100 µA, VDD = 3.15 V 0.2 V IOS Output Short Circuit Current TDO −15 −125 mA IOZ Output TRI-STATE Current TDO −10 +10 µA 100 mV −1.5 3.5 pF 5.5 pF −0.8 V V V V LVDS INPUT DC SPECIFICATIONS (INn±) VTH Differential Input High Threshold VCM = 0.8V to 3.4V, VDD = 3.45V VTL Differential Input Low Threshold (2) VCM = 0.8V to 3.4V, VDD = 3.45V −100 VID Differential Input Voltage VCM = 0.8V to 3.4V, VDD = 3.45V 100 VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.45V 0.05 CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.45V, VDD = VDDMAX −10 +10 µA VIN = 0V, VDD = VDDMAX −10 +10 µA 600 mV 35 mV 1.475 V 35 mV −90 mA (2) 0 0 mV 2400 3.40 5.2 mV V pF LVDS OUTPUT DC SPECIFICATIONS (OUTn±) VOD Differential Output Voltage, 0% Pre-emphasis (2) RL = 100Ω external resistor between OUT+ and OUT− ΔVOD Change in VOD between Complementary States VOS Offset Voltage ΔVOS Change in VOS between Complementary States IOS Output Short Circuit Current OUT+ or OUT− Short to GND −60 COUT2 Output Capacitance OUT+ or OUT− to GND when TRI-STATE 5.5 All inputs and outputs enabled and active, terminated with external differential load of 100Ω between OUT+ and OUT-, 0% pre-emphasis 117 140 mA 2.7 6 mA 210 300 ps 210 300 ps 250 500 -35 (3) 1.05 1.18 -35 pF SUPPLY CURRENT (Static) ICC ICCZ Supply Current Supply Current - Power Down Mode PWDN = L, 0% pre-emphasis SWITCHING CHARACTERISTICS—LVDS OUTPUTS tLHT Differential Low to High Transition Time tHLT Differential High to Low Transition Time (1) (2) (3) (4) 4 Use an alternating 1 and 0 pattern at 200 Mb/s, measure between 20% and 80% of VOD. (4) Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew |tPLHD–tPHLD| tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or tPHLD) among all output channels. (4) tSKP Part to Part Skew tJIT Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% VOD between input to output. (4) Jitter (0% Pre-emphasis) (4) Typ (1) Max Units 2.0 3.2 ns 2.0 3.2 ns 25 80 ps 50 125 ps 1.1 ns 1.1 1.5 psrms 43 62 psp-p 35 85 psp-p Common edge, parts at same temp and VCC (4) (5) RJ - Alternating 1 and 0 at 750 MHz DJ - K28.5 Pattern, 1.5 Gbps (6) (7) TJ - PRBS 223-1 Pattern, 1.5 Gbps (8) tON LVDS Output Enable Time Time from PWDN to OUT± change from TRI-STATE to active. 300 ns tOFF LVDS Output Disable Time Time from PWDN to OUT± change from active to TRI-STATE. 12 ns SWITCHING CHARACTERISTICS—SCAN FEATURES fMAX Maximum TCK Clock Frequency tS TDI to TCK, H or L tH tS 25.0 MHz 3.0 ns TDI to TCK, H or L 0.5 ns TMS to TCK, H or L 2.5 ns tH TMS to TCK, H or L 0.5 ns tW TCK Pulse Width, H or L 10.0 ns tW TRST Pulse Width, L 2.5 ns tREC Recovery Time, TRST to TCK 1.0 ns (5) (6) (7) (8) RL = 500Ω, CL = 35 pF Jitter is not production tested, but specified through characterization on a sample basis. Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 750MHz, tr = tf = 50ps (20% to 80%). Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%). Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 5 SCAN90004 SNLS182P – MAY 2005 – REVISED APRIL 2013 www.ti.com FEATURE DESCRIPTIONS INTERNAL TERMINATIONS The SCAN90004 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external component count resulting in space savings. OUTPUT CHARACTERISTICS The output characteristics of the SCAN90004 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. POWERDOWN MODE The PWDN input activates a hardware powerdown mode. When the powerdown mode is active (PWDN=L), all input and output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in powerdown mode. JTAG Circuitry is active per the IEEE standard, but does not switch unless TCK is toggling. When exiting powerdown mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Characteristics Upon asserting the power down function (PWDN = Low), and if the Pre-emphasis feature is enable, it is possible for the driver output to source current for a short amount of time lifting the output common mode to VDD. To prevent this occurrence, a load discharge pull down path can be used on either output (1 kΩ to ground recommended). Alternately, a commonly deployed external failsafe network will also provide this path (see INPUT FAILSAFE BIASING). The occurrence of this is application dependant, and parameters that will affect if this is of concern include: AC coupling, use of the powerdown feature, presence of the discharge path, presence of the failsafe biasing, the usage of the pre-emphasis feature, and input characteristics of the downstream LVDS Receiver. PRE-EMPHASIS Pre-emphasis dramatically reduces ISI jitter from long or lossy transmission media. Two pins are used to select the pre-emphasis level for all outputs: off, low, medium, or high. Table 1. Pre-emphasis Control Selection Table PEM1 PEM0 Pre-Emphasis 0 0 Off 0 1 Low 1 0 Medium 1 1 High INPUT FAILSAFE BIASING Failsafe biasing of the LVDS link should be considered if the downstream Receiver is ON and enabled when the source is in TRI-STATE, powered off, or removed. This will set a valid known input state to the active receiver. This is accomplished by using a pull up resistor to VDD on the ‘plus’ line, and a pull down resistor to GND on the ‘minus’ line. Resistor values are in the 750 Ω to several k Ω range. The exact value depends upon the desired common mode bias point, termination resistor(s) and desired input differential voltage setting. Please refer to application note AN-1194 (SNLA051) “Failsafe Biasing of LVDS interfaces” for more information and a general discussion. 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 Design-for-Test (DfT) Features IEEE 1149.1 (JTAG) SUPPORT The SCAN90004 supports a fully compliant IEEE 1149.1 interface. The Test Access Port (TAP) provides access to boundary scan cells at each LVTTL I/O on the device for interconnect testing. Differential pins are included in the same boundary scan chain but instead contain IEEE1149.6 cells. IEEE1149.6 is the improved IEEE standard for testing high-speed differential signals. Refer to the BSDL file located on TI’s website for the details of the SCAN90004 IEEE 1149.1 implementation. IEEE 1149.6 SUPPORT AC-coupled differential interconnections on very high speed (1+ Gbps) data paths are not testable using traditional IEEE 1149.1 techniques. The IEEE 1149.1 structures and methods are intended to test static (DCcoupled), single ended networks. IEEE 1149.6 is targeted for the testing of high-speed differential (including AC coupled) networks. The SCAN90004 includes circuitry to support AC-coupled testing on all differential inputs and outputs and offers limited test capability. The limitations are due to several application specific factors (board layout, capacitor value, data rate etc.), and also IO compliance (LVDS links in general are DC coupled). The SCAN90004 has not been tested for full compliance or full compatibility to the IEEE1149.6 standard. Testing of the device in the targeted application with the appropriate JTAG software will determine what extent of IEEE 1149.6 support is provided by the device. FAULT INSERTION Fault Insertion is a technique used to assist in the verification and debug of diagnostic software. During system testing faults are "injected" to simulate hardware failure and thus help verify the monitoring software can detect and diagnose these faults. In the SCAN90004 an IEEE1149.1 "stuck-at" instruction can create a stuck-at condition, either high or low, on any pin or combination of pins. A more detailed description of the stuck-at feature can be found in TI Applications note AN-1313 (SNLA060). Application Information INPUT INTERFACING The SCAN90004 accepts differential signals and allow simple AC or DC coupling. With a wide common mode range, the SCAN90004 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the SCAN90004 inputs are internally terminated with a 100Ω resistor. LVDS Driver SCAN90004 Receiver 100: Differential T-Line OUT+ IN+ 100: OUT- IN- Figure 3. Typical LVDS Driver DC-Coupled Interface to SCAN90004 Input Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 7 SCAN90004 SNLS182P – MAY 2005 – REVISED APRIL 2013 www.ti.com CML3.3V or CML2.5V Driver VCC 50: SCAN90004 Receiver 100: Differential T-Line 50: OUT+ IN+ 100: IN- OUT- Figure 4. Typical CML Driver DC-Coupled Interface to SCAN90004 Input LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 5. Typical LVPECL Driver DC-Coupled Interface to SCAN90004 Input OUTPUT INTERFACING The SCAN90004 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common differential receivers. Figure 6 illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. SCAN90004 Driver Differential Receiver 100: Differential T-Line OUT+ IN+ CML or LVPECL or LVDS 100: 100: IN- OUT- Figure 6. Typical SCAN90004 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 Typical Performance Characteristics Power Supply Current vs. Bit Data Rate Total Jitter (TJ) vs. Bit Data Rate 120 Clock, Max PRE 300 100 PRBS-23, Max PRE TOTAL JITTER - tJ (ps) POWER SUPPLY CURRENT (mA) 350 250 200 150 Clock, 0% PRE 100 PRBS-23, 0% PRE VCM = 0.25V 80 VCM = 2.4V 60 VCM = 1.2V 40 20 50 VCM = 0.5V 0 VCM = 3.05V 0 0 0.25 0.5 0.75 1.0 1.25 0 1.5 BIT DATA RATE (Gbps) 1.0 1.5 2.0 BIT DATA RATE (Gbps) Dynamic power supply current was measured while running a clock or PRBS 223-1 pattern with all 4 channels active. VCC = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V Figure 7. Total Jitter measured at 0V differential while running a PRBS 223-1 pattern with a single channel active. VCC = 3.3V, TA = +25°C, VID = 0.5V, 0% Pre-emphasis Figure 8. Total Jitter (U.I.) vs. Bit Data Rate SCAN90004 as Driver Total Jitter (U.I.) vs. Bit Data Rate SCAN90004 as Receiver Total Jitter measured while SCAN90004 output is driving a PRBS 27-1 NRZ pattern with a single active channel across a Belden 1700A cable. VCC = 3.3V, TA = +25°C, VID = 0.5V, 0% Pre-emphasis. Data measured at end of specified cable length. Figure 9. 0.5 Total Jitter measured at SCAN90004 receiver outputs after receiving a PRBS 27-1 NRZ pattern over the specified cable length. VCC = 3.3V, TA = +25°C, VID = 0.5V, data collected at receiver outputs, receiver located at end of specified Belden 1700A cable length. Figure 10. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 9 SCAN90004 SNLS182P – MAY 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Total Jitter (TJ) vs. Temperature Positive Edge Transition vs. Pre-emphasis Level 80 100 mV/Div 100% 50% 25% 0% TOTAL JITTER - tJ (ps) 70 60 50 40 30 20 10 200 ps/Div 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) Total Jitter measured at 0V differential while running a PRBS 223-1 pattern with a single channel active. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate, 0% Pre-emphasis Figure 11. 10 Figure 12. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 SCAN90004 www.ti.com SNLS182P – MAY 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision O (April 2013) to Revision P • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: SCAN90004 11 PACKAGE OPTION ADDENDUM www.ti.com 23-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty SCAN90004TVS ACTIVE TQFP PFB 48 SCAN90004TVS/NOPB ACTIVE TQFP PFB 48 250 Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TBD Call TI Call TI -40 to 85 SCAN 90004TVS Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 SCAN 90004TVS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated