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SCAN90CP02
1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis
and IEEE 1149.6
General Description
Features
The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint
switch. High speed data paths and flow-through pinout minimize internal device jitter, while configurable 0/25/50/100%
pre-emphasis overcomes external ISI jitter effects of lossy
backplanes and cables. The differential inputs interface to
LVDS and Bus LVDS signals such as those on National's 10-,
16-, and 18- bit Bus LVDS SerDes, as well as CML and
LVPECL. The SCAN90CP02 can also be used with ASICs
and FPGAs. The non-blocking crosspoint architecture is pinconfigurable as a 1:2 clock or data splitter, 2:1 redundancy
mux, crossover function, or dual buffer for signal booster and
stub hider applications.
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports
testability of both single-ended LVTTL/CMOS and differential
LVDS PCB interconnect. The 3.3V supply, CMOS process,
and LVDS I/O ensure high performance at low power over the
entire industrial -40 to +85°C temperature range.
■
■
■
■
■
■
■
■
■
■
■
■
1.5 Gbps per channel
Low power: 70 mA in dual repeater mode @1.5 Gbps
Low output jitter
Configurable 0/25/50/100% pre-emphasis drives lossy
backplanes and cables
Non-blocking architecture allows 1:2 splitter, 2:1 mux,
crossover, and dual buffer configurations
Flow-through pinout
LVDS/BLVDS/CML/LVPECL inputs, LVDS Outputs
IEEE 1149.1 and 1149.6 compliant
Single 3.3V supply
Separate control of inputs and outputs allows for power
savings
Industrial -40 to +85°C temperature range
28-lead LLP package, or 32-lead LQFP package
Block Diagram
20071401
FIGURE 1. SCAN90CP02 Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation
200714
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SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6
March 9, 2009
SCAN90CP02
Pin Descriptions
Pin
Name
LLP Pin
Number
LQFP
Pin
Number
I/O, Type
Description
DIFFERENTIAL INPUTS COMMON TO ALL MUXES
IN0+
IN0−
9
10
9
10
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
IN1+
IN1−
12
13
13
14
I, LVDS
Inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL
compatible.
SWITCHED DIFFERENTIAL OUTPUTS
OUT0+
OUT0−
27
26
32
31
O, LVDS
Inverting and non-inverting differential outputs. OUT0± can be connected to any
one pair IN0±, or IN1±. LVDS compatible (Note 2).
OUT1+
OUT1−
24
23
28
27
O, LVDS
Inverting and non-inverting differential outputs. OUT1± can be connected to any
one pair IN0±, or IN1±. LVDS compatible (Note 2).
DIGITAL CONTROL INTERFACE
SEL0,
SEL1
6
5
7
6
I, LVTTL
Select Control Inputs
EN0, EN1
7
15
8
17
I, LVTTL
Output Enable Inputs
PEM00,
PEM01
4
3
4
3
I, LVTTL
Channel 0 Output Pre-emphasis Control Inputs
PEM10,
PEM11
2
1
2
1
I, LVTTL
Channel 1 Output Pre-emphasis Control Inputs
TDI
19
22
I, LVTTL
Test Data Input to support IEEE 1149.1 features
TDO
20
23
O, LVTTL
Test Data Output to support IEEE 1149.1 features
TMS
18
21
I, LVTTL
Test Mode Select to support IEEE 1149.1 features
TCK
17
19
I, LVTTL
Test Clock to support IEEE 1149.1 features
TRST
21
24
I, LVTTL
Test Reset to support IEEE 1149.1 features
N/C
8, 28
Not Connected
POWER
VDD
GND
11, 14,
12, 16,
16, 22, 25 18, 25, 29
(Note 1)
5, 11, 15,
20, 26, 30
I, Power
VDD = 3.3V ±0.3V. At least 4 low ESR 0.01 µF bypass capacitors should be
connected from VDD to GND plane.
Ground reference to LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the
device. The DAP is the exposed metal contact at the bottom of the LLP-28
package. It should be connected to the ground plane with at least 4 vias for optimal
AC and thermal performance.
Note 1: Note that for the LLP package GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the LLP package.
Note 2: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN90CP02 device have been optimized
for point-to-point backplane and cable applications.
www.national.com
2
SCAN90CP02
Connection Diagrams
20071404
LQFP Top View
20071403
LLP Top View
DAP = GND
Configuration Select Truth Table
SEL0
SEL1
EN0
EN1
OUT0
OUT1
Mode
0
0
0
0
IN0
IN0
1:2 Splitter (IN1 powered down)
0
1
0
0
IN0
IN1
Dual Channel Repeater
1
0
0
0
IN1
IN0
Dual Channel Switch
1
1
0
0
IN1
IN1
1:2 Splitter (IN0 powered down)
0
1
0
1
IN0
PD
Single Channel Repeater (Channel 1 powered down)
1
1
0
1
IN1
PD
Single Channel Switch (IN0 and OUT1 powered down)
0
0
1
0
PD
IN0
Single Channel Switch (IN1 and OUT0 powered down)
0
1
1
0
PD
IN1
Single Channel Repeater (Channel 0 powered down)
X
X
1
1
PD
PD
Both Channels in Power Down Mode
0
0
0
1
Invalid State*
1
0
0
1
Invalid State*
1
0
1
0
Invalid State*
1
1
1
0
Invalid State*
PD = Power Down mode to minimize power consumption
X = Don't Care
* Entering these states is not forbidden, however device operation is not defined in these states.
Pre-emphasis Control Selection Table
Pre-Emphasis
Channel 0
The pre-emphasis is used to compensate for long or lossy
transmission media. Separate pins are provided for each output to minimize power consumption. Pre-emphasis is programmable to be off or to preset values per the Pre-emphasis
Control Selection Table.
Output Characteristics
Channel 1
Pre-emphasis
PEM01
PEM00
PEM11
PEM10
0
0
0
0
0%
0
1
0
1
25%
1
0
1
0
50%
1
1
1
1
100%
The output characteristics of the SCAN90CP02 device have
been optimized for point-to-point backplane and cable applications.
3
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SCAN90CP02
Applications Information
20071402
FIGURE 2. SCAN90CP02 Configuration Select Decode
www.national.com
4
11.8 mW/°C
Thermal Resistance, θJA
LLP-28
LQFP-32
ESD Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
−0.3V to +4.0V
CMOS Input Voltage
−0.3V to (VDD +0.3V)
LVDS Receiver Input Voltage
−0.3V to +3.6V
LVDS Driver Output Voltage
−0.3V to +3.6V
LVDS Output Short Circuit Current
40mA
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
Lead Temperature
(Soldering, 4sec.)
+260°C
Maximum Package Power Dissipation at 25°C
LLP-28
4.31 W
LQFP-32
1.47 W
Derating above 25°C
LLP-28
34.5 mW/°C
29°C/W
85°C/W
HBM, 1.5 kΩ, 100 pF
6.5 kV
EIAJ, 0Ω, 200 pF
>250V
Recommended Operating
Conditions
Supply Voltage (VDD– GND)
Receiver Input Voltage
Operating Free Air
Temperature
Junction Temperature
Min
3.0
0
Typ
3.3
−40
25
Max Unit
3.6
V
3.6
V
85
150
°C
°C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(Note 4)
Max
Units
LVTTL DC SPECIFICATIONS (SEL0, SEL1, EN1, EN2, PEM00, PEM01, PEM10, PEM11, TDI, TCK, TMS, TRST)
VIH
High Level Input Voltage
2.0
VDD
V
VIL
Low Level Input Voltage
GND
0.8
V
IIH
High Level Input Current
VIN = VDD = VDDMAX
−10
+10
µA
IIL
Low Level Input Current
VIN = VSS, VDD = VDDMAX
−10
+10
µA
IILR
Low Level Input Current
TDI, TMS, TRST
-40
-200
µA
CIN1
Input Capacitance
Any Digital Input Pin to VSS
COUT1
Output Capacitance
Any Digital Output Pin to VSS
VCL
Input Clamp Voltage
ICL = −18 mA
VOH
High Level Output Voltage
(TDO)
IOH = −12 mA, VDD = 3.0 V
2.4
V
IOH = −100 µA, VDD = 3.0 V
VDD-0.2
V
Low Level Output Voltage
(TDO)
IOL = 12 mA, VDD = 3.0 V
0.5
V
IOL = 100 µA, VDD = 3.0 V
0.2
V
Output Short Circuit Current
TDO
-125
mA
100
mV
VOL
IOS
−1.5
3.5
pF
5.5
pF
−0.8
V
-15
LVDS INPUT DC SPECIFICATIONS (IN0±, IN1±)
VTH
Differential Input High Threshold
(Note 5)
VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V
VTL
Differential Input Low Threshold
VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V
−100
VID
Differential Input Voltage
VCM = 0.8V to 3.55V, VDD = 3.6V
100
VCMR
Common Mode Voltage Range
VID = 150 mV, VDD = 3.6V
0.05
CIN2
Input Capacitance
IN+ or IN− to VSS
IIN
Input Current
VIN = 3.6V, VDD = VDDMAX or 0V
−10
+10
µA
VIN = 0V, VDD = VDDMAX or 0V
−10
+10
µA
0
0
mV
mV
3.55
3.5
5
V
pF
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SCAN90CP02
LQFP-32
Absolute Maximum Ratings (Note 3)
SCAN90CP02
Symbol
Parameter
Conditions
Min
Typ
(Note 4)
Max
Units
250
400
575
mV
35
mV
1.475
V
35
mV
-90
mA
LVDS OUTPUT DC SPECIFICATIONS (OUT0±, OUT1±)
RL = 100Ω between OUT+ and OUT−
VOD
Differential Output Voltage,
0% Pre-emphasis (Note 5)
ΔVOD
Change in VOD between
Complementary States
−35
VOS
Offset Voltage (Note 6)
1.09
ΔVOS
Change in VOS between
Complementary States
−35
IOS
Output Short Circuit Current, One
Complementary Output
OUT+ or OUT− Short to GND
COUT2
Output Capacitance
OUT+ or OUT− to GND when TRISTATE®
5.5
All inputs and outputs enabled and
active, terminated with differential load of
100Ω between OUT+ and OUT-.
42
60
mA
1.25
−60
pF
SUPPLY CURRENT (Static)
ICC0
Supply Current
ICC1
Supply Current - one channel
powered down
Single channel crossover switch or single
channel repeater modes (1 channel
active, one channel in power down mode)
22
30
mA
ICC2
Supply Current - one input powered Splitter mode (One input powered down,
down
both outputs active)
30
40
mA
ICCZ
TRI-STATE Supply Current
1.4
2.5
mA
70
150
215
ps
50
135
180
ps
0.5
2.4
3.5
ns
0.5
2.4
3.5
ns
55
120
ps
130
315
ps
Both input/output Channels in Power
Down Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS (Figures 3, 4)
tLHT
Differential Low to High Transition
Time
tHLT
Differential High to Low Transition
Time
tPLHD
Differential Low to High Propagation Use an alternating 1 and 0 pattern at 200
Delay
Mb/s, measure at 50% VOD between
Differential High to Low Propagation input to output.
Delay
tPHLD
Use an alternating 1 and 0 pattern at 200
Mb/s, measure between 20% and 80% of
VOD.
tSKD1
Pulse Skew
|tPLHD–tPHLD|
tSKCC
Output Channel to Channel Skew
Difference in propagation delay (tPLHD or
tPHLD) among all output channels in
Splitter mode (any one input to all
outputs).
tJIT
Jitter (0% Pre-emphasis)
(Note 7)
RJ - Alternating 1/0 @ 750 MHz (Note 8)
1.4
2.5
psrms
DJ - K28.5 Pattern
LQFP
110
140
psp-p
LLP
42
75
psp-p
LQFP
113
148
psp-p
LLP
93
126
psp-p
110
150
ns
5
12
ns
110
150
ns
1.5 Gbps (Note 9)
TJ - PRBS 223-1 Pattern
1.5 Gbps (Note 10)
tON
LVDS Output Enable Time
Time from ENx to OUT± change from
TRI-STATE to active.
tOFF
LVDS Output Disable Time
Time from ENx to OUT± change from
active to TRI-STATE.
tSW
LVDS Switching Time
SELx to OUT±
Time from configuration select (SELx) to
new switch configuration effective for
OUT±.
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0
6
50
Symbol
Parameter
Conditions
Min
Typ
Max
Units
fMAX
Maximum TCK Clock Frequency
MHz
TDI to TCK, H or L
RL = 500Ω,
CL = 35 pF
25.0
tS
1.0
ns
tH
TDI to TCK, H or L
2.0
ns
tS
TMS to TCK, H or L
2.0
ns
tH
TMS to TCK, H or L
1.5
ns
tW
TCK Pulse Width, H or L
10.0
ns
tW
TRST Pulse Width, L
2.5
ns
tREC
Recovery Time, TRST to TCK
2.0
ns
Note 3: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 4: Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested.
Note 5: Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−).
Note 6: Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 7: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 8: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at
750MHz, tr = tf = 50ps (20% to 80%).
Note 9: Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 1.5 Gbps,
tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 10: Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input
voltage = VID = 500mV, 223-1 PRBS pattern at 1.5 Gbps, tr = tf = 50ps (20% to 80%).
Timing Diagrams
20071415
FIGURE 3. LVDS Signals
7
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SCAN90CP02
SCAN Circuitry Timing Requirements
SCAN90CP02
20071416
FIGURE 4. LVDS Output Transition Time
20071417
FIGURE 5. LVDS Output Propagation Delay
20071420
FIGURE 6. Configuration and Output Enable/Disable Timing
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8
The SCAN90CP02 accepts differential signals and allow simple AC or DC coupling. With a wide common mode range, the
20071421
Typical LVDS Driver DC-Coupled Interface to SCAN90CP02 Input
20071422
Typical CML Driver DC-Coupled Interface to SCAN90CP02 Input
20071423
Typical LVPECL Driver DC-Coupled Interface to SCAN90CP02 Input
9
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SCAN90CP02
SCAN90CP02 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The following three
figures illustrate typical DC-coupled interface to common differential drivers.
Input Interfacing
SCAN90CP02
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
Output Interfacing
The SCAN90CP02 outputs signals that are compliant to the
LVDS standard. Their outputs can be DC-coupled to most
common differential receivers. The following figure illustrates
typical DC-coupled interface to common differential receivers
20071424
Typical SCAN90CP02 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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10
SCAN90CP02
Typical Performance Characteristics for LLP Package
Power Supply Current vs. Bit Data Rate
Total Jitter (TJ) vs. Bit Data Rate
20071441
20071442
Dynamic power supply current was measured while running a PRBS 223-1 patternTotal Jitter measured at 0V differential while running a PRBS 223-1 pattern in
in dual channel repeater mode. VCC = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2Vsingle channel repeater mode. VCC = 3.3V, TA = +25°C, VID = 0.5V, 0% Preemphasis
Total Jitter (TJ) vs. Temperature
Positive Edge Transition vs. Pre-emphasis Level
20071455
20071443
Total Jitter measured at 0V differential while running a PRBS 223-1 pattern in dual
channel repeater mode. VCC = 3.3V, VID = 0.5V, VCM = 1.2V, 1.5 Gbps data rate,
0% Pre-emphasis
FIGURE 7. Typical Performance Characteristics
11
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SCAN90CP02
Design-For-Test (DfT) Features
IEEE 1149.1 SUPPORT
The SCAN90CP02 supports a fully compliant IEEE 1149.1
interface. The Test Access Port (TAP) provides access to
boundary scan cells at each LVTTL I/O on the device for interconnect testing. Differential pins are included in the same
boundary scan chain but instead contain IEEE1149.6 cells.
IEEE1149.6 is the improved IEEE standard for testing highspeed differential signals.
Refer to the BSDL file located on National's website for the
details of the SCAN90CP02 IEEE 1149.1 implementation.
IEEE 1149.6 SUPPORT
AC-coupled differential interconnections on very high speed
(1+ Gbps) data paths are not testable using traditional IEEE
1149.1 techniques. The IEEE 1149.1 structures and methods
are intended to test static (DC-coupled), single ended networks. IEEE1149.6 is specifically designed for testing highspeed differential, including AC coupled networks.
The SCAN90CP02 is intended for high-speed signalling up to
1.5 Gbps and includes IEEE1149.6 on all differential inputs
and outputs.
FAULT INSERTION
Fault Insertion is a technique used to assist in the verification
and debug of diagnostic software. During system testing
faults are "injected" to simulate hardware failure and thus help
verify the monitoring software can detect and diagnose these
faults. In the SCAN90004 an IEEE1149.1 "stuck-at" instruction can create a stuck-at condition, either high or low, on any
pin or combination of pins.
A more detailed description of the stuck-at feature can be
found in NSC Applications note AN-1313.
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12
SCAN90CP02
Physical Dimensions inches (millimeters) unless otherwise noted
LLP, Plastic, QUAD,
Order Number SCAN90CP02SP (1000 piece Tape and Reel),
SCAN90CP02SPX (4500 piece Tape and Reel)
NS Package Number SPA28A
13
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SCAN90CP02
LQFP, Plastic, Quad
Order Number SCAN90CP02VY (250 piece Tray)
SCAN90CP02VYX (1000 piece Tape and Reel)
NS Package Number VBE32A
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14
SCAN90CP02
Notes
15
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SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch with Pre-Emphasis and IEEE 1149.6
Notes
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