SCAN921821TSM/NOPB

SCAN921821 www.ti.com SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 SCAN921821 Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1 (JTAG), and At-Speed BIST Check for Samples: SCAN921821 FEATURES DESCRIPTION • The SCAN921821 is a dual channel 18-bit serializer featuring signal conditioning, boundary SCAN, and atspeed BIST. Each serializer block transforms an 18bit parallel LVCMOS/LVTTL data bus into a single Bus LVDS data stream with embedded clock. This single serial data stream with embedded clock simplifies PCB design and reduces PCB cost by narrowing data paths that in turn reduce PCB size and layers. The single serial data stream also reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew. 1 2 • • • • • • • • • • • • • • 15-66 MHz Dual 18:1 Serializer with 2.376 Gbps Total Throughput 8-level Selectable Pre-emphasis on Each Channel Drives Lossy Cables and Backplanes >15kV HBM ESD Protection on Bus LVDS I/O Pins Robust BLVDS Serial Data Transmission with Embedded Clock for Exceptional Noise Immunity and Low EMI Power Saving Control Pin for Each Channel IEEE 1149.1 "JTAG" Compliant At-Speed BIST - PRBS Generation No External Coding Required Internal PLL, No External PLL Components Required Single +3.3V Power Supply Low Power: 260 mW (typ) Per Channel at 66 MHz with PRBS-15 Pattern Single 3.3 V Supply Fabricated with Advanced CMOS Process Technology Industrial −40 to +85°C Temperature Range Compact 100-ball NFBGA Package Each channel also has an 8-level selectable preemphasis feature that significantly extends performance over lossy interconnect. Each channel also has its own powerdown pin that saves power by reducing supply current when the channel is not being used. The SCAN921821 also incorporates advanced testability features including IEEE 1149.1 and atspeed BIST PRBS pattern generation to facilitate verification of board and link integrity 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2013, Texas Instruments Incorporated SCAN921821 SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 www.ti.com Block Diagram DINA PWDNA Input Latch 18 Parallel to Serial 3 SYNCA PEMA DOUTAP DOUTAN ENA PWDNB SYNCB TxCLK PEMB DOUTBP DOUTBN ENB Timing and Control PLL BISTA BIST DINB Input Latch 18 Parallel to Serial 3 BISTB TCK TDO TMS IEEE 1149.1 Test Access Port TDI TRST These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +4V Supply Voltage (VDD) Supply Voltage (VDD) Ramp Rate < 30 V/ms LVCMOS/LVTTL Input Voltage −0.3V to (VDD +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VDD +0.3V) −0.3V to +3.9V Bus LVDS Driver Output Voltage Bus LVDS Output Short Circuit Duration 10ms Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 seconds) Maximum Package Power Dissipation at 25°C +220°C NFBGA-100 Derating Above 25°C Thermal resistance ESD Rating HBM, 1.5 KΩ, 100 pF 35°C/W θJC 11.1°C/W All pins Bus LVDS pins 2 >8 kV >15 kV >1200 V CDM (2) 28.57 mW/°C θJA MM, 0Ω, 200 pF (1) 3.57 W >2 kV “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 SCAN921821 www.ti.com SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 Recommended Operating Conditions Supply Voltage (VDD) Operating Free Air Temperature (TA) Clock Rate Min Nom Max 3.15 3.3 3.45 V −40 +25 +85 °C 66 MHz 100 mV p-p 15 Supply Noise Units DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL Input DC Specifications VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −1.5 -0.7 IINH High Level Input Current VIN = VDD = VDDMAX −20 ±2 +20 μA IINL Low Level Output Current VIN = VSS, VDD = VDDMAX −10 ±2 +10 μA V 1149.1 (JTAG) DC Specifications VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage ICL = −18 mA −1.5 IINH High Level Input Current VIN = VDD = VDDMAX -20 +20 μA IINL Low Level Output Current VIN = VSS, VDD = VDDMAX -200 +200 μA VOH High Level Output Voltage IOH = −9 mA 2.3 VDD mV VOL Low Level Output Voltage IOL = 9 mA GND 0.5 mV IOS Output Short Circuit Current VOUT = 0 V -100 -50 mA IOZ Output Tri-state Current PWDN or EN = 0.8V, VOUT = 0 V -10 +10 μA PWDN or EN = 0.8V, VOUT = VDD -30 +30 μA See Figure 10, RL = 100Ω 450 500 550 mV 2 15 mV 1.2 1.25 V 2.7 15 mV -0.7 -80 V Bus LVDS Output DC Specifications (1) (2) VOD Output Differential Voltage (DO+) - (DO-) ΔVOD Output Differential Voltage Unbalance VOS Offset Voltage ΔVOS Offset Voltage Unbalance 1.05 Typical values are given for VCC = 3.3V and TA = +25°C. Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 3 SCAN921821 SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2) Symbol QPOV Parameter Pre-Emphasis Output Voltage Ratio | VODPRE / VOD | Output Short Circuit Current IOS Min Typ Max Pre-Emphasis Level = 1 1.10 1.24 1.35 Pre-Emphasis Level = 2 1.35 1.47 1.55 Pre-Emphasis Level = 3 1.55 1.70 1.80 Pre-Emphasis Level = 4 1.80 1.91 1.95 Pre-Emphasis Level = 5 1.95 2.08 2.20 Pre-Emphasis Level = 6 2.10 2.21 2.35 Pre-Emphasis Level = 7 2.15 2.30 2.50 -10 -25 -75 mA -10 ±1 +10 µA -55 ±6 +55 µA f = 66 MHz, PRBS-15 Pattern 160 225 mA f = 66 MHz, Worst Case Pattern (Checker-Board Pattern) 180 mA f = 66 MHz, PRBS-15 Pattern 240 mA f = 66 MHz, Worst Case Pattern (Checker-Board Pattern) 280 325 mA 1.0 3.0 mA DO = 0V, Din = H, PWDN and EN = 2.4V PWDN or EN = 0.8V, DO = 0V TRI-STATE Output Current IOZ Conditions (3) PWDN or EN = 0.8V, DO = VDD (3) Units Power Supply Current (DVDD, PVDD and AVDD Pins) Total Supply Current (includes load current) IDD Total Supply Current with Pre-Emphasis (includes load current) IDDP CL = 15pF, RL = 100 Ω Supply Current Powerdown IDDX (3) CL = 15pF, RL = 100 Ω PWDN = 0.8V, EN = 0.8V IOZ is measured at each pin. The DOUT pin not under test is floated to isolate the TRI-STATE current flow. Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter Min Typ Max Units tTCP Transmit Clock Period 15.2 T 66.7 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 3 6 ns 80 ps (RMS) tJIT (1) (2) (3) 4 TCLK Input Jitter Conditions See (3) Typical values are given for VCC = 3.3V and TA = +25°C. Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Specified by design using statistical analysis. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 SCAN921821 www.ti.com SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) Symbol Parameter Conditions Min Typ Max Units 0.3 0.4 ns 0.3 0.4 ns Serializer AC Specifications tLLHT Bus LVDS Low-to-High Transition Time tLHLT Bus LVDS High-to-Low Transition Time tDIS DIN (0-17) Setup to TCLK tDIH DIN (0-17) Hold from TCLK tHZD DO ± HIGH to TRI-STATE Delay tLZD DO ± LOW to TRISTATE Delay tZHD DO ± TRI-STATE to HIGH Delay tZLD DO ± TRI-STATE to LOW Delay tSPW SYNC Pulse Width See Figure 7, RL = 100Ω tPLD Serializer PLL Lock Time tSD Serializer Delay tSKCC Channel to Channel Skew tRJIT Random Jitter tDJIT Deterministic Jitter Figure 9, (3) See Figure 2, (3) RL = 100Ω, CL=10pF to GND See Figure 4, (3) RL = 100Ω, CL=10pF to GND 1.9 ns 0.6 ns 3.9 10 ns 3.5 10 ns 3.2 10 ns 2.4 10 ns 5*tTCP 6*tTCP ns See Figure 6, RL = 100Ω 510*tTCP 1024*tTCP ns See Figure 8 , RL = 100Ω tTCP + 2.5 tTCP + 6.5 ns See Figure 5 RL = 100Ω, CL=10pF to GND Room Temperature, VDD = 3.3V, 66 MHz tTCP + 4.5 70 ps 6.1 ps (RMS) 15 MHz -390 320 ps 66 MHz -60 30 ps 1149.1 (JTAG) AC Specifications (1) (2) (3) fMAX Maximum TCK Clock Frequency 25 MHz tS TDI or TMS Setup to TCK, H or L 2.4 ns tH TDI or TMS Hold from TCK, H or L 2.8 ns tW1 TCK Pulse Width, H or L 10 ns CL = 15pF, RL = 500 Ω tW2 TRST Pulse Width, L 10 ns tREC Recovery Time, TRST to TCK 2 ns Typical values are given for VCC = 3.3V and TA = +25°C. Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Specified by design using statistical analysis. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 5 SCAN921821 SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 www.ti.com AC Timing Diagrams and Test Circuits Figure 1. “Worst Case” Serializer IDD Test Pattern Figure 2. Serializer Bus LVDS Distributed Output Load and Transition Times Figure 3. Serializer Input Clock Transition Time Figure 4. Serializer Setup/Hold Times 6 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 SCAN921821 www.ti.com SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 Figure 5. Serializer TRI-STATE Test Circuit and Timing Figure 6. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 7 SCAN921821 SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 www.ti.com Figure 7. SYNC Timing Delay Figure 8. Serializer Delay 8 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 SCAN921821 www.ti.com SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 Figure 9. Deterministic Jitter and Ideal Bit Position VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Figure 10. VOD Diagram Pre-emphasis Truth Table PEM LEVEL PEM2 PEM1 PEM0 0 L L L 1 L L H 2 L H L 3 L H H 4 H L L 5 H L H 6 H H L 7 H H H Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 9 SCAN921821 SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 www.ti.com Pin Diagram Figure 11. SCAN921821TVV Top View 10 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BISTB PVSS DOUTBN AVDD ENB AVDD DOUTAN DOUTAP AVDD ENA B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DINB16 SYNCB AVDD DOUTBP AVDD PEMB1 AVSS PEMB0 PEMA1 BISTA C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 DINB14 DVDD DVSS AVSS AVSS AVSS AVDD PEMA2 SYNCA DINA16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DINB13 DINB12 DINB17 DVDD PVDD PEMA0 AVSS DINA17 DINA15 DINA13 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 DINB11 DINB9 DINB15 DVSS DINB8 PEMB2 DVSS DINA14 DINA12 DINA9 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 DINB10 DINB7 DINB5 DVSS PVDD DINA11 DVSS DINA4 DINA10 DINA8 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 DINB6 DINB4 DINB2 DVSS DVDD DVDD DINA1 DINA2 DINA7 DINA6 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 DINB3 DINB1 TxCLK DVSS TCK PVDD PVSS DVSS DINA0 DINA5 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 DINB0 PWDNA DVDD TRST PVDD PVSS PVDD NC DVDD DINA3 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 DVSS TDI TMS DVSS TDO DVDD PVSS PVSS PWDNB DVDD Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 SCAN921821 www.ti.com SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 Pin Descriptions Pin Name Pin Count I/O, Type Description I, LVCMOS Transmitter inputs. There is a pull-down circuitry on each of these pins which are active if respective PWDNA or PWDNB pin is pulled high. DATA PINS DINA0-17 18 DINB0-17 18 DOUTAP 1 DOUTAN 1 DOUTBP 1 DOUTAN 1 O,BLVDS Inverting and non-inverting differential transmitter outputs. TIMING AND CONTROL PINS TxCLK 1 ENA 1 ENB 1 PWDNA 1 PWDNB 1 SYNCA 1 SYNCB 1 I, LVCMOS Transmitter reference clock. Used to strobe data at the inputs and to drive the transmitter PLL. There is a pull-up circuitry on this pin which is always active. I, LVCMOS Transmitter outputs enable pins. There is a pull-down circuitry on each of these pins that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are set to LOW, the transmitter outputs will be disabled. The PLL will remain locked. I, LVCMOS Stand-by mode pins. There is a pull-down circuitry on each of these pins that are always active. When these pins are set to LOW, the transmitter will be put in low power mode and the PLL will lose lock. I, LVCMOS Transmitter synchronization pins. There is a pull-down circuitry on each of these pins that are active if corresponding PWDNA or PWDNB pin is pulled high. When these pins are set to HIGH, the transmitter will ignore incoming data and send SYNC patterns to provide a locking reference to receiver(s). I, LVCMOS 8-level pre-emphasis selection pins. There is a pull-down circuitry on each of these pins which are active if corresponding PWDNA or PWDNB pin is pulled high. PRE-EMPHASIS PINS PEMA0-2 3 PEMB0-2 3 JTAG PINS TDI 1 I, LVCMOS Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. TDO 1 O, LVCMOS Test Data Output to support IEEE 1149.1. TMS 1 I, LVCMOS Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. TCK 1 I, LVCMOS Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin. TRST 1 I, LVCMOS Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin which is always active. I, LVCMOS BIST selection pins. These pins select which transmitter will generate a PRBS like data. There is a pull-down circuitry on these pins which are active if corresponding PWDNA or PWDNB pin is pulled high. BIST PINS BISTA BISTB 1 1 POWER PINS AVDD 6 I, POWER Power Supply for the LVDS circuitry. DVDD 8 I, POWER Power Supply for the digital circuitry. PVDD 5 I, POWER Power Supply for the PLL and BG circuitry. AVSS 5 I, POWER Ground reference for the LVDS circuitry. DVSS 10 I, POWER Ground reference for the digital circuitry. PVSS 5 I, POWER Ground reference for the PLL and BG circuitry. 1 N/A OTHER PINS NC Not connected. Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 11 SCAN921821 SNLS173C – SEPTEMBER 2004 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Product Folder Links: SCAN921821 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SCAN921821TSM/NOPB ACTIVE NFBGA NZD 100 240 RoHS & Green SNAGCU Level-4-260C-72 HR -40 to 85 SCAN921821 TSM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of