SCANSTA112
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SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer
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FEATURES
DESCRIPTION
•
The SCANSTA112 extends the IEEE Std. 1149.1 test
bus into a multidrop test bus environment. The
advantage of a multidrop approach over a single
serial scan chain is improved test throughput and the
ability to remove a board from the system and retain
test access to the remaining modules. Each
SCANSTA112 supports up to 7 local IEEE1149.1
scan chains which can be accessed individually or
combined serially.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
True IEEE 1149.1 Hierarchical and Multidrop
Addressable Capability
The 8 Address Inputs Support up to 249
Unique Slot Addresses, an Interrogation
Address, Broadcast Address, and 4 Multi-Cast
Group Addresses (Address 000000 is
Reserved)
7 IEEE 1149.1-Compatible Configurable Local
Scan Ports
Bi-directional Backplane and LSP0 Ports are
Interchangeable Slave Ports
Capable of Ignoring TRST of the Backplane
Port when it Becomes the Slave.
Stitcher Mode Bypasses Level 1 and 2
Protocols
Mode Register0 Allows Local TAPs to be
Bypassed, Selected for Insertion into the Scan
Chain Individually, or Serially in Groups of
Two or Three
Transparent Mode can be Enabled with a
Single Instruction to Conveniently Buffer the
Backplane IEEE 1149.1 Pins to Those on a
Single Local Scan Port
General Purpose Local Port Pass Through Bits
are Useful for Delivering Write Pulses for Flash
Programming or Monitoring Device Status.
Known Power-Up State
TRST on all Local Scan Ports
32-bit TCK Counter
16-bit LFSR Signature Compactor
Local TAPs can Become TRI-STATE via the OE
Input to Allow an Alternate Test Master to Take
Control of the Local TAPs (LSP0-3 have a TRISTATE Notification Output)
3.0-3.6V VCC Supply Operation
Supports Live Insertion/Withdrawal
Addressing is accomplished by loading the instruction
register with a value matching that of the Slot inputs.
Backplane and inter-board testing can easily be
accomplished by parking the local TAP Controllers in
one of the stable TAP Controller states via a Park
instruction. The 32-bit TCK counter enables built in
self test operations to be performed on one port while
other scan chains are simultaneously tested.
The STA112 has a unique feature in that the
backplane port and the LSP0 port are bidirectional.
They can be configured to alternatively act as the
master or slave port so an alternate test master can
take control of the entire scan chain network from the
LSP0 port while the backplane port becomes a slave.
1
2
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
SCANSTA112
SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
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LSP0
Buffer with
JTAG
LSP1
LSP2
FPGA
vendor1
with JTAG
FPGA
vendor2
with JTAG
Buffer with
JTAG
Backplane
IEEE 1149.1
Test Bus
ASIC
with
JTAG
LSP3
Buffer with
JTAG
LSP4
SCANSTA112
Processor
with JTAG
Flash
Memory
R/W
STA112
STA112
STA112
STA112
STA112
STA112
Figure 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.
Backplane IEEE
1149.1
Test Bus
Figure 2. Example of SCANSTA112 in a multidrop addressable backplane.
Introduction
The SCANSTA112 is the third device in a series that enable multi-drop address and multiplexing of IEEE-1149.1
scan chains. The SCANSTA112 is a superset of its predecessors - the SCANPSC110 and the SCANSTA111.
The STA112 has all features and functionality of these two previous devices.
The STA112 is essentially a support device for the IEEE 1149.1 standard. It is primarily used to partition scan
chains into managable sizes, or to isolate specific devices onto a seperate chain (Figure 1). The benefits of
multiple scan chains are improved fault isolation, faster test times, faster programiing times, and smaller vector
sets.
In addition to scan chain partitioning, the device is also addressable for use in a multidrop backplane
environment (Figure 2). In this configuration, multiple IEEE-1149.1 accessible cards with an STA112 on board
can utilize the same backplane test bus for system-level IEEE-1149.1 access. This approach facilitates a systemwide commitment to structural test and programming throughout the entire system life sycle.
Architecture
Figure 3 shows the basic architecture of the 'STA112. The device's major functional blocks are illustrated here.
The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and
various test data registers can be scanned to exercise the various functions of the 'STA112 (these registers
behave as defined in IEEE Std. 1149.1).
2
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The 'STA112 selection controller provides the functionality that allows the 1149.1 protocol to be used in a multidrop environment. It primarily compares the address input to the slot identification and enables the 'STA112 for
subsequent scan operations.
The Local Scan Port Network (LSPN) contains multiplexing logic used to select different port configurations. The
LSPN control block contains the Local Scan Port Controllers (LSPC) for each Local Scan Port (LSP0, LSP1 ...
LSPn). This control block receives input from the 'STA112 instruction register, mode registers, and the TAP
controller. Each local port contains all four boundary scan signals needed to interface with the local TAPs plus
the optional Test Reset signal (TRST).
The TDI/TDO Crossover Master/Slave logic is used to define the bidirectional B0 and B1 ports in a Master/Slave
configuration.
Block Diagram
OE
TDIB1, A0B1 A1B1
TDI/TDO
Crossover
Master/
Slave
Logic
A0B0, A1B0
Y0B0, Y1B0
TDOB0
TMSB1 TCKB1 TRSTB1
TDOB1 TRISTB1Y0B1 Y1B1
TCKB0
TMSB0
TRSTB0
Master/
Slave
Logic
S0-7
ADDMASK
TDO01 TCK01 TMS01
TRST01 Y001 Y101 TRIST01
TAP
Controller
TDI/TDO
Crossover
Local
Scan
Port
Network
Selection
Control
Instruction
TDIB0
TDI01 A001 A101
TDO02-03 TCK02_03 TMS02-03
TRST02-03 TRIST02-03
TDI02-03
TRISTB0
Boundary
MstrPortSel
SGPIO
TDO04-06 TCK04-06
TMS04-06 TRST04-06
32-bit Counter
MultiCast
RESET
TDI04-06
LFSR
ByPass
ID
Control
Mode0-3
Mode0-3
LSP
Controller
PortEnable
LSPSel0-6
MPSelB1/B0
SB/S
TRANS
TLR_TRST
TLR_TRST6
/2
Figure 3. SCANSTA112 Block Diagram
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Connection Diagrams
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
S0
TCK06
TDO06
VCC
TMS05
GND
TCK04
TMS04
VCC
TDO03
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
GND
S1
GND
TDI06
TCK05
TDO05
TRST04
TCK03
TMS03
TRIST02
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
S7
S3
VCC
TMS06
TRST05
TDO04
TDI04
GND
VCC
TCK02
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
ADDMASK
TRANS
S5
S4
TRST06
TRST03
TRIST03
TRST02
TMS02
GND
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
VCC
LSPsel0
S6
S2
LSPsel1
TDI05
TDI03
TDO02
TDI02
A101
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
OE
LSPsel2
LSPsel3
SB/S
A0B1
A001
RESET
TCK01
Y001
VCC
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
GND
LSPsel4
LSPsel6
TRSTB0
A0B0
A1B1
TDO01
TMS01
Y101
TRIST01
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
LSPsel5
VCC
GND
TMSB0
A1B0
TRSTB1
TRISTB1
VCC
TDI01
TRST01
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
MPselB1/B0
TDOB0
TCKB0
Y1B0
TDOB1
TCKB1
TMSB1
GND
TLRTRST6
GND
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
TDIB0
VCC
TRISTB0
Y0B0
GND
TDIB1
VCC
Y1B1
Y0B1
TLRTRST
Figure 4. (NFBGA Top view)
4
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Figure 5. TQFP pinout
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PIN DESCRIPTIONS
No.
Pins
I/O
VCC
10
N/A
Power
GND
10
N/A
Ground
RESET
1
I
RESET Input: will force a reset of the device regardless of the current state.
ADDMASK
1
I
ADDRESS MASK input: Allows masking of lower slot input pins.
MPselB1/B0
1
I
MASTER PORT SELECTION: Controls selection of LSPB0 or LSPB1 as the backplane port. The
unselected port becomes LSP00. A value of "0" will select LSPB0 as the master port.
SB/S
1
I
Selects ScanBridge or Stitcher Mode.
LSPsel (0-6)
7
I
In Stitcher Mode these inputs define which LSP's are to be included in the scan chain
TRANS
1
I
Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit of the
control register at power-up. This value is used to control the presence of registers and pad-bits in
the scan chain while in the stitcher mode.
TLR_TRST
1
I
Sets the driven value of TRST0-5 when LSP TAPs are in TLR and the device is not being reset.
During RESET = "0" or TRSTB = "0" (IgnoreReset = "0") TRSTn = "0". This pin is to be tied low to
match the function of the SCANSTA111
TLR_TRST6
1
I
This pin affects TRST of LSP6 only. This pin is to be tied low to match the function of the
SCANSTA111
TDIB0, TDIB1
2
I
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the 'STA112 through this
input pin. MPselB1/B0 determines which port is the master backplane port and which is LSP00. This
input has a 25KΩ internal pull-up resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (VDD floating), this input appears to be a capacitive
load to ground (1). When VDD = 0V (i.e.; not floating but tied to VSS) this input appears to be a
capacitive load with the pull-up to ground.
TMSB0, TMSB1
2
I/O
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
'STA112. Also controls sequencing of the TAPs which are on the local scan chains. MPselB1/B0
determines which port is the master backplane port and which is LSP00. This bidirectional TRISTATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no ESD clamp
diode (ESD is controlled with an alternate method). When the device is power-off (VDD floating), this
input appears to be a capacitive load to ground (1). When VDD = 0V (i.e.; not floating but tied to VSS)
this input appears to be a capacitive load with the pull-up to ground.
TDOB0, TDOB1
2
I/O
BACKPLANE TEST DATA OUTPUT: This output drives test data from the 'STA112 and the local
TAPs, back toward the scan master controller. This bidirectional TRI-STATE pin has 12mA of drive
current. MPselB1/B0 determines which port is the master backplane port and which is LSP00. Output
is sampled during interrogation addressing. When the device is power-off (VDD = 0V or floating), this
output appears to be a capacitive load (1).
TCKB0, TCKB1
2
I/O
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls all
scan operations of the 'STA112 and of the local scan ports. MPselB1/B0 determines which port is the
master backplane port and which is LSP00. These bidirectional TRI-STATE pins have 24mA of drive
current with hysterisis. This input has no pull-up resistor and no ESD clamp diode (ESD is controlled
with an alternate method). When the device is power-off (VDD floating), this input appears to be a
capacitive load to ground (1). When VDD = 0V (i.e.; not floating but tied to VSS) this input appears to
be a capacitive load to ground.
TRSTB0, TRSTB1
2
I/O
TEST RESET: An asynchronous reset signal (active low) which initializes the 'STA112 logic.
MPselB1/B0 determines which port is the master backplane port and which is LSP00. This
bidirectional TRI-STATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no
ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (VDD
floating), this pin appears to be a capacitive load to ground (1). When VDD = 0V (i.e.; not floating but
tied to VSS) this input appears to be a capacitive load with the pull-up to ground.
TRISTB0, TRISTB1,
TRIST(01-03)
5
O
TRI-STATE NOTIFICATION OUTPUT: This signal is asserted high when the associated TDO is
TRI-STATEd. Associated means TRISTB0 is for TDOB0, TRIST01 is for TDO01, etc. This output has
12mA of drive current.
A0B0, A1B0, A0B1,
A1B1
4
I
BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Yn of a
single selected LSP. (Not available when multiple LSPs are selected). This input has a 25KΩ
internal pull-up resistor. MPselB1/B0 determines which port is the master backplane port and which is
LSP00.
Y0B0, Y1B0, Y0B1,
Y1B1
4
O
BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the An of
a single selected LSP. (Not available when multiple LSPs are selected). This TRI-STATE output has
12mA of drive current. MPselB1/B0 determines which port is the master backplane port and which is
LSP00.
Pin Name
(1)
6
Description
Refer to the IBIS model on our website for I/O characteristics.
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PIN DESCRIPTIONS (continued)
No.
Pins
I/O
S(0-7)
8
I
SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique
address to) each 'STA112 on the system backplane
OE
1
I
OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control signal
TRI-STATEs all local scan ports on the 'STA112, to enable an alternate resource to access one or
more of the local scan chains.
TDO(01-06)
6
O
TEST DATA OUTPUTS: Individual output for each of the local scan ports . These TRI-STATE
outputs have 12mA of drive current.
TDI(01-06)
6
I
TEST DATA INPUTS: Individual scan data input for each of the local scan ports. This input has a
25KΩ internal pull-up resistor.
TMS(01-06)
6
O
TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMSn does not
provide a pull-up resistor (which is assumed to be present on a connected TMS input, per the IEEE
1149.1 requirement) . These TRI-STATE outputs have 24mA of drive current.
TCK(01-06)
6
O
LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These are
buffered versions of TCKB . These TRI-STATE outputs have 24mA of drive current.
TRST(01-06)
6
O
LOCAL TEST RESETS: A gated version of TRSTB. These TRI-STATE outputs have 24mA of drive
current.
A001, A101
2
I
LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the backplane
pin YB. (Only on LSP0 and LSP1. Only available when a single LSP is selected) . These inputs have
a 25KΩ internal pull-up resistor.
Y001, Y101
2
O
LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the
backplane pin AB. (Only on LSP0 and LSP1. Only available when a single LSP is selected) . These
TRI-STATE outputs have 12mA of drive current.
Pin Name
Description
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APPLICATION OVERVIEW
ADDRESSING SCHEME
The SCANSTA112 architecture extends the functionality of the IEEE 1149.1 Standard by supplementing that
protocol with an addressing scheme which allows a test controller to communicate with specific 'STA112s within
a network of 'STA112s. That network can include both multi-drop and hierarchical connectivity. In effect, the
'STA112 architecture allows a test controller to dynamically select specific portions of such a network for
participation in scan operations. This allows a complex system to be partitioned into smaller blocks for testing
purposes. The 'STA112 provides two levels of test-network partitioning capability. First, a test controller can
select individual 'STA112s, specific sets of 'STA112s (multi-cast groups), or all 'STA112s (broadcast). This
'STA112-selection process is supported by a Level-1 communication protocol. Second, within each selected
'STA112, a test controller can select one or more of the chip's seven local scan-ports. That is, individual local
ports can be selected for inclusion in the (single) scan-chain which a 'STA112 presents to the test controller. This
mechanism allows a controller to select specific scan-chains within the overall scan network. The port-selection
process is supported by a Level-2 protocol.
HIERARCHICAL SUPPORT
Multiple SCANSTA112's can be used to assemble a hierarchical boundary-scan tree. In such a configuration, the
system tester can configure the local ports of a set of 'STA112s so as to connect a specific set of local scanchains to the active scan chain. Using this capability, the tester can selectively communicate with specific
portions of a target system. The tester's scan port is connected to the backplane scan port of a root layer of
'STA112s, each of which can be selected using multi-drop addressing. A second tier of 'STA112s can be
connected to this root layer, by connecting a local port (LSP) of a root-layer 'STA112 to the backplane port of a
second-tier 'STA112. This process can be continued to construct a multi-level scan hierarchy. 'STA112 local
ports which are not cascaded into higher-level 'STA112s can be thought of as the terminal leaves of a scan tree.
The test master can select one or more target leaves by selecting and configuring the local ports of an
appropriate set of 'STA112s in the test tree.
STANDARD SCANBRIDGE MODE
ScanBridge mode refers to functionality and protocol that has been used since the introduction of the PSC110 in
1993. This functionality consists of a multidrop addressable IEEE1149.1 switch. This enables one (or more)
device to be selected from many that are connected to a parallel IEEE1149.1 bus or backplane. The second
function that ScanBridge mode accomplishes is to act as a mux for multiple IEEE1149.1 local scan chains. The
Local Scan Ports (LSP) of the device creates a connection between one or more of the local scan chains to the
backplane bus.
To accomplish this functionality the ScanBridge has two levels of protocol and an operational mode. Level 1
protocol refers to the required actions to address/select the desired ScanBridge. Level 2 protocol is required to
configuring the mux'ing function and enable the connection (UNPARK) between the local scan chain and the
backplane bus via an LSP. Upon completion of level 1 and 2 protocols the ScanBridge is prepared for its
operational mode. This is where scan vectors are moved from the backplane bus to the desired local scan
chain(s).
STITCHER MODE
Stitcher Mode is a method of skipping level 1 and 2 protocol of the ScanBridge mode of operation. This is
accomplished via external pins. When in stitcher mode the SCANSTA112 will go directly to the operational mode.
TRANSPARENT MODE
Transparent mode refers to a condition of operation in which there are no pad-bits or SCANSTA112 registers in
the scan chain. The Transparent mode of operation is available in both ScanBridge and Stitcher modes. Only the
activation method differs. Once transparent mode has been activated there is no difference in operation.
Transparent mode allows for the use of vectors that have been generated for a chain where these bits were not
included.
Check with your ATPG tool vendor to ensure support of these features.
For details regarding the internal operation of the SCANSTA112 device, refer to applications note AN1259(SNLA055) SCANSTA112 Designers Reference.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
−0.3V to +4.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK) VI = −0.5V
−20 mA
−0.5V to +3.9V
DC Input Voltage (VI)
DC Output Diode Current (IOK) VO = −0.5V
−20 mA
−0.3V to +3.9V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
±50 mA
DC VCC or Ground Current per Output Pin
±50 mA
DC Latchup Source or Sink Current
±300 mA
Junction Temperature (Plastic)
+150°C
−65°C to +150°C
Storage Temperature
Lead Temperature (Solder, 4sec)
100L NFBGA
Max Package Power Capacity @ 25°C
220°C
100L TQFP
220°C
100L NFBGA
3.57W
100L TQFP
Thermal Resistance (θJA)
2.11W
100L NFBGA
35°C/W
100L TQFP
Package Derating above +25°C
59.1°C/W
100L NFBGA
28.57mW/°C
100L TQFP
16.92mW/°C
ESD Last Passing Voltage (HBM Min)
(1)
2500V
Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met,
without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI
does not recommend operation of SCAN STA products outside of recommended operation conditions.
RECOMMENDED OPERATING CONDITIONS
Supply Voltage (VCC) 'STA112
3.0V to 3.6V
Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
−40°C to +85°C
Operating Temperature (TA) Industrial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating supply voltage and temperature ranges unless otherwise specified
Symbol
VIH
Parameter
Conditions
Minimum High Input Voltage
VOUT = 0.1V or
Min
Max
2.1
Units
V
VCC −0.1V
VIL
Maximum Low Input Voltage
VOUT = 0.1V or
VOH
Minimum High Output Voltage
IOUT = −100 μA
All Outputs and I/O Pins
VIN = VIH or VIL
Minimum High Output Voltage
IOUT = −12 mA
TDOB0, TDOB1, TRISTB0, TRISTB1, Y0B0, Y1B0, Y0B1,
Y1B1, TDO(01-06), Y001, Y101, TRIST(01-03)
All Outputs Loaded
Minimum High Output Voltage
IOUT = −24mA
0.8
V
VCC −0.1V
VOH
VOH
VCC - 0.2v
V
2.4
V
2.2
V
TMSB0, TMSB1, TCKB0, TCKB1, TRSTB0, TRSTB1,
TMS(01-06), TCK(01-06), TRST(01-06)
VOL
Maximum Low Output Voltage
IOUT = +100 μA
All Outputs and I/O Pins
VIN = VIH or VIL
0.2
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DC ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified
Symbol
VOL
Parameter
Conditions
Maximum Low Output Voltage
Min
Max
Units
IOUT = +12 mA
0.4
V
IOUT = +24mA
0.55
V
TDOB0, TDOB1, TRISTB0, TRISTB1, Y0B0, Y1B0, Y0B1,
Y1B1, TDO(01-06), Y001, Y101, TRIST(01-03)
VOL
Maximum Low Output Voltage
TMSB0, TMSB1, TCKB0, TCKB1, TRSTB0, TRSTB1,
TMS(01-06), TCK(01-06), TRST(01-06)
VIKL
Maximum Input Clamp Diode Voltage
IIK = -18mA
-1.2
V
IIN
Maximum Input Leakage Current
VIN = VCC or GND
±5.0
μA
-200
µA
(non-resistor input pins)
IILR
Input Current Low
VIN = GND
-45
(Input and I/O pins with pull-up resistors: TDIB0, TDIB1,
TMSB0, TMSB1, TRSTB0, TRSTB1, A0B0, A1B0, A0B1,
A1B1, TDI(01-06), A001, A101)
IIH
Input High Current
(Input and I/O pins with pull-up resistors: TDIB0, TDIB1,
TMSB0, TMSB1, TRSTB0, TRSTB1, A0B0, A1B0, A0B1,
A1B1, TDI(01-06), A001, A101)
VIN = VCC
5.0
µA
IOFF
Power-off Leakage Current
Outputs and I/O pins without pull-up resistors
VCC = 0V, VIN = 3.6V (1)
±5.0
μA
Outputs and I/O pins with pull-up resistors
±200
μA
Maximum TRI-STATE Leakage Current
±5.0
μA
IOZ
Outputs and I/O pins without pull-up resistors
ICC
Maximum Quiescent Supply Current
VIN = VCC or GND
3.8
mA
ICCD
Maximum Dynamic Supply Current
VIN = VCC or GND, Input
Freq = 25MHz
68
mA
Typ
Max
Units
8.5
13.5
ns
8.5
14.0
ns
7.5
12.5
ns
7.5
13.0
ns
8.0
12.0
ns
8.0
12.0
ns
8.0
12.0
ns
8.0
12.0
ns
8.0
12.0
ns
(1)
Specified by equivalent test method.
AC ELECTRICAL CHARACTERISTICS: SCAN BRIDGE MODE
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1).
Symbol
Parameter
tPHL,
Propagation Delay
tPLH
TCKB0 to TDOB0 or TDOB1
tPHL,
Propagation Delay
tPLH
TCKB1 to TDOB0 or TDOB1
tPHL,
Propagation Delay
tPLH
TCKB0 to TDO(01-06)
tPHL,
Propagation Delay
tPLH
TCKB1 to TDO(01-06)
tPHL,
Propagation Delay
tPLH
TMSB0 to TMSB1
tPHL,
Propagation Delay
tPLH
TMSB1 to TMSB0
tPHL,
Propagation Delay
tPLH
TMSB0 to TMS(01-06)
tPHL,
Propagation Delay
tPLH
TMSB1 to TMS(01-06)
tPHL,
Propagation Delay
tPLH
TCKB0 to TCKB1
(1)
10
Conditions
RL = 500Ω to GND, CL = 50pF to GND, tR/tF = 2.5ns, Frequency = 25MHz, VM = 1.5V
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SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
AC ELECTRICAL CHARACTERISTICS: SCAN BRIDGE MODE (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified(1).
Symbol
Parameter
tPHL,
Propagation Delay
tPLH
TCKB1 to TCKB0
tPHL,
Propagation Delay
tPLH
TCKB0 to TCK(01-06)
tPHL,
Propagation Delay
tPLH
TCKB1 to TCK(01-06)
tPHL,
Propagation Delay
tPLH
TCKB0 to TRSTB1
tPHL,
Propagation Delay
tPLH
TCKB1 to TRSTB0
tPHL,
Propagation Delay
tPLH
TCKB0 to TRST(01-06)
tPHL,
Propagation Delay
tPLH
TCKB1 to TRST(01-06)
tPHL
Propagation Delay
Conditions
Typ
Max
Units
8.0
12.0
ns
7.5
12.0
ns
7.5
12.0
ns
11.5
18.0
ns
11.5
18.0
ns
12.0
18.5
ns
12.0
18.5
ns
8.5
12.5
ns
8.0
12.0
ns
9.0
14.5
ns
6.0
9.0
ns
Max
Units
TCKBn to TRISTBn
tPHL
Propagation Delay
TCKBn to TRIST(01-03)
tPZL,
Propagation Delay
tPZH
TCKBn to TDOBn or TDO(01-06)
tPHL,
Propagation Delay
tPLH
An to Yn
AC TIMING CHARACTERISTICS: SCAN BRIDGE MODE
Over recommended operating supply voltage and temperature ranges unless otherwise specified (1) (2).
Symbol
tS
Parameter
Conditions
Setup Time
Min
2.5
TMSBn to TCKBn
tH
Hold Time
1.5
TMSBn to TCKBn
tS
Setup Time
3.0
TDIBn to TCKBn
tH
Hold Time
2.0
TDIBn to TCKBn
tS
Setup Time
1.0
TDI(01-06) to TCKBn
tH
Hold Time
3.5
TDI(01-06) to TCKBn
(1)
(2)
ns
ns
ns
ns
ns
ns
Specified by Design (GBD) by statistical analysis
RL = 500Ω to GND, CL = 50pF to GND, tR/tF = 2.5ns, Frequency = 25MHz, VM = 1.5V
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SCANSTA112
SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
www.ti.com
AC TIMING CHARACTERISTICS: SCAN BRIDGE MODE (continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified(1)(2).
Symbol
tREC
Parameter
Conditions
Recovery Time
Min
Max
1.0
ns
TCKBn from TRSTBn
tW
Clock Pulse Width
Units
tR/tF = 1.0ns
10.0
ns
tR/tF = 1.0ns
2.5
ns
tR/tF = 1.0ns
25
MHz
TCKBn(H or L)
tWL
Reset Pulse Width
TRSTBn(L)
Maximum Clock Frequency (3)
FMAX
(3)
When sending vectors one-way to a target device on an LSP (such as in FPGA/PLD configuration/programming), the clock frequency
may be increased above this specification. In Scan Mode (expecting to capture returning data at the LSP), the FMAX must be limited to
the above specification.
AC ELECTRICAL CHARACTERISTICS: STITCHER TRANSPARENT MODE
Over recommended operating supply voltage and temperature ranges unless otherwise specified
Symbol
Parameter
Conditions
tPHL,
Propagation Delay
tPLH
TDIB0 to TDOB1, TDIB1 to TDOB0
tPHL,
Propagation Delay
tPLH
TDIB0 to TDO01, TDIB1 to TDO01
tPHL,
Propagation Delay
tPLH
TDILSPn to TDOLSPn+1
tPHL,
Propagation Delay
tPLH
TMSB0 to TMSB1, TMSB1 to TMSB0
tPHL,
Propagation Delay
tPLH
TMSB0 to TMS(01-06), TMSB1 to TMS(01-06)
tPHL,
Propagation Delay
tPLH
TRSTB0 to TRSTB1, TRSTB1 to TRSTB0
tPHL,
Propagation Delay
tPLH
TRSTB0 to TRST(01-06), TRSTB1 to TRST(01-06)
(1)
12
(1)
.
Typ
Max
Units
12.5
ns
12.5
ns
12.5
ns
12.5
ns
12.5
ns
12.5
ns
12.5
ns
RL = 500Ω to GND, CL = 50pF to GND, tR/tF = 2.5ns, Frequency = 25MHz, VM = 1.5V
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SCANSTA112
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SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
TEST CIRCUIT DIAGRAMS
Figure 6. Waveforms for an Unparked STA112 in the Shift-DR (IR) TAP Controller State
Figure 7. Reset Waveforms
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Product Folder Links: SCANSTA112
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SCANSTA112
SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
www.ti.com
Figure 8. Output Enable Waveforms
Capacitance & I/O Characteristics
Refer to TI's website for IBIS models at www.ti.com.com/lsds/ti/analog/interface.page
14
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SCANSTA112
www.ti.com
SNLS161I – DECEMBER 2002 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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15
PACKAGE OPTION ADDENDUM
www.ti.com
11-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
SCANSTA112SM
ACTIVE
NFBGA
NZD
100
240
Non-RoHS
& Green
Call TI
Level-3-235C-168 HR
-40 to 85
SCANSTA112
SM
SCANSTA112SM/NOPB
ACTIVE
NFBGA
NZD
100
240
RoHS & Green
SNAGCU
Level-4-260C-72 HR
-40 to 85
SCANSTA112
SM
SCANSTA112SMX
NRND
NFBGA
NZD
100
1000
Non-RoHS
& Green
Call TI
Level-3-235C-168 HR
-40 to 85
SCANSTA112
SM
SCANSTA112SMX/NOPB
ACTIVE
NFBGA
NZD
100
1000
RoHS & Green
SNAGCU
Level-4-260C-72 HR
-40 to 85
SCANSTA112
SM
SCANSTA112VS
ACTIVE
TQFP
NEZ
100
90
Non-RoHS
& Green
Call TI
Level-3-260C-168 HR
-40 to 85
SCANSTA112
VS
SCANSTA112VS/NOPB
ACTIVE
TQFP
NEZ
100
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
SCANSTA112
VS
SCANSTA112VSX/NOPB
ACTIVE
TQFP
NEZ
100
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
SCANSTA112
VS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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