SD021-3EVK

CLC021 www.ti.com SNLS068H – MAY 2000 – REVISED APRIL 2013 CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion Check for Samples: CLC021 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • (1) SMPTE 259M Serial Digital Video Standard Compliant Supports All NTSC and PAL Standard Component and Composite Serial Video Data Rates No External Serial Data Rate Setting or VCO Filtering Components Required (1) Fast VCO Lock Time: 500Ω). If the Lock Detect output is to be externally monitored, the attached monitoring circuit should present a DC resistance greater than 5 kΩ so as not to affect Lock Detect indicator operation. Connect LOCK DETECT to TPG ENABLE for test pattern generator function. Remove RP1 & RP3 and replace RP2 & RP4 with 50Ω resistor packs for coax interfacing. Install RP1-4 when using ribbon cable for input interfacing. This board is designed for use with TTL power supplies only. Figure 10. SD021EVK Schematic Diagram 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H – MAY 2000 – REVISED APRIL 2013 MEASURING JITTER The test method used to obtain the timing jitter value given in the AC Electrical Specification table is based on procedures and equipment described in SMPTE RP 192-1996. The recommended practice discusses several methods and indicator devices. An FFT method performed by standard video test equipment was used to obtain the data given in this data sheet. As such, the jitter characteristics (or jitter floor) of the measurement equipment, particularly the measurement analyzer, become integral to the resulting jitter value. The method and equipment were chosen so that the test can be easily duplicated by the design engineer using most standard digital video test equipment. In so doing, similar results should be achieved. The intrinsic jitter floor of the CLC021's PLL is approximately 25% of the typical jitter given in the electrical specifications. In production, device jitter is measured on automatic IC test equipment (ATE) using a different method compatible with that equipment. Jitter measured using this ATE yields values approximately 50% of those obtained using the video test equipment. The jitter test setup used to obtain values quoted in the data sheet consists of: • Texas Instruments SD021-5EVK (SD021-3EVK), CLC021 evaluation kit • Tektronix TG2000 signal generation platform with DVG1 option • Tektronix VM700T Option 1S Video Measurement Set • Tektronix TDS 794D, Option C2 oscilloscope • Tektronix P6339A passive probe • 75Ω coaxial cable, 3 ft., Belden 8281 or RG59 (2 required) • ECL-to-TTL/CMOS level converter/amplifier see Figure 12. Apply the black-burst reference clock from the TG2000 signal generator's BG1 module 27 MHz clock output to the level converter input. The clock amplitude converter schematic is shown in Figure 12. Adjust the input bias control to give a 50% duty cycle output as measured on the oscilloscope/probe system. Connect the level translator to the SD021EVK board, connector P1, PCLK pins (the outer-most row of pins is ground). Configure the SD021EVK to operate in the NTSC colour bars, BIST mode. Configure the VM700T to make the jitter measurement in the jitter FFT mode at the frame rate with 1 kHz filter bandwidth and Hanning window. Configure the setup as shown in Figure 11. Switch the test equipment on (from standby mode) and allow all equipment temperatures stabilize per manufacturer's recommendation. Measure the jitter value after allowing the instrument's reading to stabilize (about 1 minute). Consult the VM700T Video Measurement Set Option 1S Serial Digital Measurements User Manual (document number 071-0074-00) for details of equipment operation. The VM700T measurement system's jitter floor specification at 270 Mbps is given as 200 ps ±20% (100 ps ±5% typical) of actual components from 50 Hz to 1 MHz and 200 ps +60%, -30% of actual components from 1 MHz to 10 MHz. To obtain the actual residual jitter of the CLC021, a root-sum-square adjustment of the jitter reading must be made to compensate for the measurement system's jitter floor specification. For example, if the jitter reading is 250 ps, the CLC021 residual jitter is the square root of (2502 − 2002) = 150 ps. The accuracy limits of the reading as given above apply. Figure 11. Jitter Test Circuit Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 17 CLC021 SNLS068H – MAY 2000 – REVISED APRIL 2013 www.ti.com Figure 12. ECL-to-TTL/CMOS Level Converter/Amplifer 18 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H – MAY 2000 – REVISED APRIL 2013 Figure 13. Jitter Plots PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuit board layout and stack-up for the CLC021 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the CLC021 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 19 CLC021 SNLS068H – MAY 2000 – REVISED APRIL 2013 www.ti.com The outer layers of the PCB may be flooded with additional VSS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the VSS power supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. In especially noisy power supply environments, such as is often the case when using switching power supplies, separate filtering may be used at the CLC021's VCO and output driver power pins. The CLC021 was designed for this situation. The digital section, VCO and output driver power supply feeds are independent (see and CONNECTION DIAGRAM for details). Supply filtering may take the form of L-section or pi-section, L-C filters in series with these VDD inputs. Such filters are available in a single package from several manufacturers. Despite being independent feeds, all device power supplies should be applied simultaneously as from a common source. The CLC021 is free from power supply latch-up caused by circuit-induced delays between the device's three separate power feed systems. 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H – MAY 2000 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision G (April 2013) to Revision H • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC021 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CLC021AVGZ-3.3/NOPB ACTIVE QFP PGB 44 96 RoHS & Green SN Level-3-260C-168 HR 0 to 70 CLC021A VGZ-3.3 CLC021AVGZ-5.0/NOPB ACTIVE QFP PGB 44 96 RoHS & Green SN Level-3-260C-168 HR 0 to 70 CLC021A VGZ-5.0 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of