SD394EVK
National Semiconductor
EVK User Manual
LMH0394 Evaluation Board
User Guide
October 14, 2010
Overview
The SD394 Evaluation Kit (EVK) enables evaluation of the LMH0394 3G/HD/SD SDI Adaptive Cable Equalizer.
Evaluation Kit Contents
The EVK contains the following parts:
• SD394EVK board assembly with the LMH0394 cable equalizer
• SD394EVK User Guide
Evaluation Board Description
Figure 1 shows the SD394 evaluation board and highlights some of its features.
FIGURE 1. SD394 Evaluation Board
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SDI Input and SDO Output
The SDI input connector (J1) is a 75Ω BNC connector. The SDI input should conform to the SMPTE 424M,
SMPTE 292M, or SMPTE 259M standards.
The SDO output connectors (J2 and J3) are 50Ω SMA connectors. The SDO output connectors have onboard
4.7uF AC coupling capacitors (C3 and C7). When using only one side of the output pair, the other side should be
terminated with a 50Ω SMA termination. For example, when only using the SDO output, ¯¯¯¯
SDO should be
terminated with a 50Ω SMA termination.
DC Power Connectors
The VCC and GND power connectors, PS1 and PS2 respectively, should be powered with a DC input voltage of
2.5V ± 5%.
SPI Mode / Pin Mode Select (JP6 – JP9)
JP6, JP7, JP8, and JP9 are used to select between SPI Mode or Pin Mode. To select Pin Mode, set these jumpers
in the down position as shown in Figure 2. To select SPI Mode, set these jumpers in the up position as shown in
Figure 3. For proper operation, either Pin Mode or SPI Mode must be selected. Do not leave JP6-JP9 open.
FIGURE 2. Pin Mode Select
FIGURE 3. SPI Mode Select
MUTEREF (JP5)
JP5 allows control of the MUTEREF function and may be used in either Pin Mode or SPI Mode. MUTEREF is an
input voltage used to set the threshold for ¯¯¯
CD . The MUTEREF DC input voltage should be between 0V and 2.5V.
Refer to the LMH0394 datasheet for details. Leave JP5 unconnected for normal operation.
Pin Mode Controls (JP2 – JP4)
JP2, JP3, and JP4 are used to control the ¯¯¯
CD and Mute, Bypass, and Auto Sleep functions while the device is
configured in Pin Mode. Do not place jumpers on JP2, JP3, or JP4 while the device is configured for SPI
Mode.
¯¯¯
CD and MUTE (JP2)
¯¯¯ ) monitoring and MUTE control. ¯¯¯
JP2 allows Carrier Detect (CD
CD is high when no input signal is present. MUTE
may be used to force the outputs on or off, or tied to ¯¯¯
CD to allow automatic mute operation if the SDI signal is not
present. To activate mute and force the outputs into a muted condition, set the jumper to pull MUTE to VCC. To
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turn off mute so that the outputs will never mute, set the jumper to tie MUTE to GND. For normal operation, set the
jumper to tie ¯¯¯
CD to MUTE for automatic mute control. The MUTE pin has an internal pulldown (to disable mute),
so JP2 may be left unconnected and the device will never mute.
BYPASS (JP3)
JP3 allows control of the equalization BYPASS function. To put the device into bypass mode, set the jumper to pull
BYPASS to VCC. To turn off bypass (for normal operation) set the jumper to pull BYPASS to GND. The BYPASS
pin has an internal pulldown (to disable bypass), so JP2 may be left unconnected for normal operation.
AUTO SLEEP (JP4)
JP4 allows control of the AUTO SLEEP function. To put the device into auto sleep mode in which it will power
down when no input is detected, set the jumper to pull AUTO SLEEP to VCC. To turn off auto sleep and prevent
the LMH0394 from automatically powering down, set the jumper to pull AUTO SLEEP to GND. The AUTO SLEEP
pin has an internal pullup (to enable auto sleep), so JP4 may be left unconnected to enable auto sleep mode.
SPI Header (JP1)
JP1 is the SPI (Serial Peripheral Interface) header. It allows access to the SPI pins (¯¯¯
SS , MISO, MOSI, and SCK)
while the LMH0394 is in SPI mode. These pins may be connected to a standard SPI controller to access the
LMH0394 SPI registers. Refer to the LMH0394 datasheet for details.
Carrier Detect LED (D1)
D1 shows the status of Carrier Detect. This LED is GREEN when an input signal has been detected, and OFF
when no input is detected. D1 shows the status of Carrier Detect while in Pin Mode or SPI Mode.
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Typical Performance
Equalizer Output
Figures 4, 5, and 6 show output waveforms for the SD394 with various Belden 1694A cable lengths. The input
signal is a 2.97 Gbps PRBS10, and the output signal is measured on the Agilent DCA-J 86100C oscilloscope.
FIGURE 4. SD394 Output Waveform at 2.97 Gbps with 160m Belden 1694A Cable
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FIGURE 5. SD394 Output Waveform at 1.485 Gbps with 200m Belden 1694A Cable
FIGURE 6. SD394 Output Waveform at 270 Mbps with 400m Belden 1694A Cable
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Input Return Loss
Figure 7 shows input return loss of the LMH0394 as measured at the BNC on the SD394. The return loss is
measured using the Agilent 8722ES VNA with a 75Ω BNC to 75Ω Type N connector on the input. Note that return
loss is layout dependent.
SMPTE LIMIT
FIGURE 7. SD394 Input Return Loss
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SD394 Bill of Materials
Reference Designator
C1, C2, C12
C3, C7, C9, C16
C5, C6
C10, C11
D1
J1
J2, J3
JP1
JP2
JP3, JP4, JP6, JP7, JP8, JP9
JP5
L1
PST1, PST2
R1
R2, R3
R4
R5, R7, R9
R6, R8, R10
R11
U2
Qty
3
4
2
2
1
1
2
1
1
6
1
1
2
1
2
1
3
3
1
1
Description
Capacitor, 0.01uF, 16V, X7R, 0402
Capacitor, 4.7uF, 6.3V, X5R, 0402
Capacitor, 1uF, 6.3V, X5R, 0402
Capacitor, 0.1uF, 16V, X7R, 0402
LED, Green, 0603
BNC, 75-ohm, Amphenol, edge launch
SMA, 50-ohm, edge launch
Header, 6x1, 0.1"
Header, 3x2, 0.1"
Header, 3x1, 0.1"
Header, 2x1, 0.1"
Inductor, 5.6nH, 0402
Power Supply Terminal
Resistor, 300-ohm, 1/10W, 5%, 0603
Resistor, 75-ohm, 1/16W, 1%, 0402
Resistor, 37.4-ohm, 1/16W, 1%, 0402
Resistor, 3.16k-ohm, 1/10W, 1%, 0402
Resistor, 9.76k-ohm, 1/10W, 1%, 0402
Resistor, 0-ohm, 1/10W, 5%, 0402
LMH0394 Cable Equalizer, LLP-16
Manufacturer
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
Kemet
Lite-On
Amphenol
Johnson Components
3M/ESD
3M/ESD
3M/ESD
3M/ESD
Murata
Keystone
Panasonic - ECG
Yageo America
Vishay/Dale
Panasonic - ECG
Panasonic - ECG
Panasonic - ECG
National Semiconductor
Schematic (next page)
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© 2010, National Semiconductor Corp.
Manufacturer Part No.
ECJ-0EB1C103K
ECJ-0EB0J475M
ECJ-0EB0J105M
C0402C104K9RACTU
LTST-C190GKT
031-6009
142-0701-851
929647-01-06-I
929665-01-03-I
929647-01-36-I
929647-01-02-I
LQP15MN5N6B02D
1287-ST
ERJ-3GEYJ301V
RC0402FR-0775RL
CRCW040237R4FKED
ERJ-2RKF3161X
ERJ-2RKF9761X
ERJ-2GE0R00X
LMH0394SQ
A
B
C
D
GND
PST2
0
1
1
VCC
0
1
PST1
2
R7
R5
VCC(PST1)
3.16K
3.16K
3.16K
2.5V
Do Not Load
Do Not Load
0
0
0
3.3V
LMH0384
R9
9.76K
LMH0394
R6
Do Not Load
R5
3.16K
MUTE/SCK
GND
C12
0.01UF
VCC
9.76K
C11
0.1UF
9.76K
2
3.16K
R9
MOSI
VEE/SSb
9.76K
R8
GND
9.76K
R10
GND
SPI_Connector_SSb
3.16K
R7
GND
SPI_Connector_MOSI
9.76K
R6
Z75_n: W=20MIL, ZO=75+/-5%
LAYOUT NOTE:
C10
0.1UF
R8
C9
4.7UF
R10
AUTOSLP/MISO
SPI_Connector_SCK
Power_Supply_Terminal
GND
Z75_1
Power_Supply_Terminal
J1
1
2
3
4
5
6
BNC_EDGE
SDI
GND
JP1
GND
SCK
MOSI
MISO
SS
GND
HDR_6
LMH0394_LMH0384 SPI Header
1
SPI Mode
Pin Mode
VCC
D1
LED
3
L1
R1
300
R2
5.6nH
75
VCC
GND
R11
0
R3
75
GND
1
2
3
R4
37.4
CDb
C5
1UF
C6
1UF
1
2
3
JP2
1
3
5
GND
C1
0.01UF
CD/MUTE
JP8
GND
C16
4.7UF
SPI_EN
CDb
BYPASS
2
4
6
4
1
2
3
4
VCC
GND
VCC
C8
1UF
BYPASS
VCC
C2
0.01UF
GND
5
AUTOSLP/MISO
VCC
GND
4.7UF
C7
4.7UF
C3
JP4
3
2
1
SMA_R_EDGE
J3
J2
SMA_R_EDGE
AUTO SLEEP ENABLE
ZDIFF100N_12
GND
ZDIFF100P_12
LAYOUT NOTE:
Z50_n: W=40MIL, ZO=50+-5%
5
ZDIFF100N_1
ZDIFF100P_1
HDR_2
MUTEREF
1
2
JP5
U2
LMH0394
12
11
10
9
GND
VEE/SSb
MUTEREF
ASLP/MISO
SDO
SDO
VEE/SS
GND
3
2
1
JP3
Do not place JP2-JP4 in SPI Mode
1
2
3
GND
BYPASS
MUTE/SCK
VEE
SDI
SDI
SPI_EN
JP9
BYPASS/CDb
MOSI
CDb/MOSI
CDb
4
LMH0394-LMH0384 SPI Mode / Pin Mode Select (JP6-JP9)
JP7
Place C1,C16, & C2 as close to U2 pin as possibleVCC
1
2
3
SPI_EN
JP6
3
CDb/MOSI
16
15
14
13
VCC
CD/MOSI
MUTE/SCK
VCC
AEC+
AECBYPASS/CD
MUTEREF
5
6
7
8
17
DAP
6
6
A
B
C
D
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