SD395EVK/NOPB

SD395EVK National Semiconductor EVK User Manual LMH0395 Evaluation Board User Guide October 20, 2010 Overview The SD395 Evaluation Kit (EVK) enables evaluation of the LMH0395 3G/HD/SD SDI Dual Output Adaptive Cable Equalizer. Evaluation Kit Contents The EVK contains the following parts: • SD395EVK board assembly with the LMH0395 cable equalizer • SD395EVK User Guide Evaluation Board Description Figure 1 shows the SD395 evaluation board and highlights some of its features. FIGURE 1. SD395 Evaluation Board SD395 EVK User Guide Rev 1.0 1 of 8 © 2010, National Semiconductor Corp. SDI Input and SDO Output The SDI input connector (J1) is a 75Ω BNC connector. The SDI input should conform to the SMPTE 424M, SMPTE 292M, or SMPTE 259M standards. The SDO0 and SDO1 output connectors (J2, J3, J4, and J5) are 50Ω SMA connectors. The SDO0 and SDO1 output connectors have onboard 4.7uF AC coupling capacitors (C3, C7, C17, and C18). When using only one side of an output pair, the other side should be terminated with a 50Ω SMA termination. For example, when only using the SDO0 output, ¯¯¯¯¯ SDO0 should be terminated with a 50Ω SMA termination. DC Power Connectors The VCC and GND power connectors, PS1 and PS2 respectively, should be powered with a DC input voltage of 2.5V ± 5%. SPI Mode / Pin Mode Select (JP6 – JP9) JP6, JP7, JP8, and JP9 are used to select between SPI Mode or Pin Mode. To select Pin Mode, set these jumpers in the down position as shown in Figure 2. To select SPI Mode, set these jumpers in the up position as shown in Figure 3. For proper operation, either Pin Mode or SPI Mode must be selected. Do not leave JP6-JP9 open. FIGURE 2. Pin Mode Select FIGURE 3. SPI Mode Select MUTEREF (JP5) JP5 allows control of the MUTEREF function and may be used in either Pin Mode or SPI Mode. MUTEREF is an input voltage used to set the threshold for ¯¯¯ CD . The MUTEREF DC input voltage should be between 0V and 2.5V. Refer to the LMH0395 datasheet for details. Leave JP5 unconnected for normal operation. SDO1_ENABLE (JP10) JP10 allows control of the SDO1_DISABLE function and may be used in either Pin Mode or SPI Mode. When this jumper is set, the SDO1 output is enabled. When this jumper is removed, the SDO1 output is disabled (high impedance). SD395 EVK User Guide Rev 1.0 2 of 8 © 2010, National Semiconductor Corp. Pin Mode Controls (JP2 – JP4) JP2, JP3, and JP4 are used to control the ¯¯¯ CD and Mute, Bypass, and Auto Sleep functions while the device is configured in Pin Mode. Do not place jumpers on JP2, JP3, or JP4 while the device is configured for SPI Mode. ¯¯¯ CD and MUTE (JP2) ¯¯¯ ) monitoring and MUTE control. ¯¯¯ JP2 allows Carrier Detect (CD CD is high when no input signal is present. MUTE may be used to force the outputs on or off, or tied to ¯¯¯ CD to allow automatic mute operation if the SDI signal is not present. To activate mute and force the outputs into a muted condition, set the jumper to pull MUTE to VCC. To turn off mute so that the outputs will never mute, set the jumper to tie MUTE to GND. For normal operation, set the jumper to tie ¯¯¯ CD to MUTE for automatic mute control. The MUTE pin has an internal pulldown (to disable mute), so JP2 may be left unconnected and the device will never mute. BYPASS (JP3) JP3 allows control of the equalization BYPASS function. To put the device into bypass mode, set the jumper to pull BYPASS to VCC. To turn off bypass (for normal operation) set the jumper to pull BYPASS to GND. The BYPASS pin has an internal pulldown (to disable bypass), so JP2 may be left unconnected for normal operation. AUTO SLEEP (JP4) JP4 allows control of the AUTO SLEEP function. To put the device into auto sleep mode in which it will power down when no input is detected, set the jumper to pull AUTO SLEEP to VCC. To turn off auto sleep and prevent the LMH0395 from automatically powering down, set the jumper to pull AUTO SLEEP to GND. The AUTO SLEEP pin has an internal pullup (to enable auto sleep), so JP4 may be left unconnected to enable auto sleep mode. SPI Header (JP1) JP1 is the SPI (Serial Peripheral Interface) header. It allows access to the SPI pins (¯¯¯ SS , MISO, MOSI, and SCK) while the LMH0395 is in SPI mode. These pins may be connected to a standard SPI controller to access the LMH0395 SPI registers. Refer to the LMH0395 datasheet for details. Carrier Detect LED (D1) D1 shows the status of Carrier Detect. This LED is GREEN when an input signal has been detected, and OFF when no input is detected. D1 shows the status of Carrier Detect while in Pin Mode or SPI Mode. SD395 EVK User Guide Rev 1.0 3 of 8 © 2010, National Semiconductor Corp. Typical Performance Equalizer Output Figures 4, 5, and 6 show output waveforms for the SD395 with various Belden 1694A cable lengths. The input signal is a 2.97 Gbps PRBS10, and the output signal is measured on the Agilent DCA-J 86100C oscilloscope. FIGURE 4. SD395 Output Waveform at 2.97 Gbps with 160m Belden 1694A Cable SD395 EVK User Guide Rev 1.0 4 of 8 © 2010, National Semiconductor Corp. FIGURE 5. SD395 Output Waveform at 1.485 Gbps with 200m Belden 1694A Cable FIGURE 6. SD395 Output Waveform at 270 Mbps with 400m Belden 1694A Cable SD395 EVK User Guide Rev 1.0 5 of 8 © 2010, National Semiconductor Corp. Input Return Loss Figure 7 shows input return loss of the LMH0395 as measured at the BNC on the SD395. The return loss is measured using the Agilent 8722ES VNA with a 75Ω BNC to 75Ω Type N connector on the input. Note that return loss is layout dependent. SMPTE LIMIT FIGURE 7. SD395 Input Return Loss SD395 EVK User Guide Rev 1.0 6 of 8 © 2010, National Semiconductor Corp. SD395 Bill of Materials Reference Designator C1, C2, C12 C3, C7, C9, C16, C17, C18 C5, C6 C10, C11 D1 J1 J2, J3, J4, J5 JP1 JP2 JP3, JP4, JP6, JP7, JP8, JP9 JP5, JP10 L1 PST1, PST2 R1 R2, R3 R4 R5, R7, R9 R6, R8, R10 U2 Qty 3 6 2 2 1 1 4 1 1 6 2 1 2 1 2 1 3 3 1 Description Capacitor, 0.01uF, 25V, X7R, 0402 Capacitor, 4.7uF, 6.3V, X5R, 0402 Capacitor, 1uF, 6.3V, X5R, 0402 Capacitor, 0.1uF, 16V, X7R, 0402 LED, Green, 0603 BNC, 75-ohm, Amphenol, edge launch SMA, 50-ohm, edge launch Header, 6x1, 0.1" Header, 3x2, 0.1" Header, 3x1, 0.1" Header, 2x1, 0.1" Inductor, 5.6nH, 0402 Power Supply Terminal Resistor, 300-ohm, 1/10W, 5%, 0603 Resistor, 75-ohm, 1/16W, 1%, 0402 Resistor, 37.4-ohm, 1/16W, 1%, 0402 Resistor, 3.16k-ohm, 1/10W, 1%, 0402 Resistor, 9.76k-ohm, 1/10W, 1%, 0402 LMH0395 Cable Equalizer, LLP-24 Manufacturer Kemet Panasonic - ECG Panasonic - ECG Kemet Lite-On Amphenol Johnson Components 3M/ESD 3M/ESD 3M/ESD 3M/ESD Murata Keystone Panasonic - ECG Yageo America Vishay/Dale Panasonic - ECG Panasonic - ECG National Semiconductor Schematic (next page) SD395 EVK User Guide Rev 1.0 7 of 8 © 2010, National Semiconductor Corp. Manufacturer Part No. C0402C103J3RACTU ECJ-0EB0J475M ECJ-0EB0J105M C0402C104K9RACTU LTST-C190GKT 031-6009 142-0701-851 929647-01-06-I 929665-01-03-I 929647-01-36-I 929647-01-02-I LQP15MN5N6B02D 1287-ST ERJ-3GEYJ301V RC0402FR-0775RL CRCW040237R4FKED ERJ-2RKF3161X ERJ-2RKF9761X LMH0395SQ + 2.5V 0 1 PST1 1 GND JP1 SDI 1 2 3 4 5 6 HDR_6 J1 Z75_1 GND BNC_EDGE SPI Header GND SCK MOSI MISO SS GND VCC PST2 Power_Supply_Terminal LAYOUT NOTE: 2 C11 0.1UF R7 3.16K VCC D1 LED C14 Do Not Load C13 Do Not Load MUTE/SCK 9.76K R6 9.76K R8 C15 Do Not Load VEE/SSb 9.76K R10 GND SPI_Connector_SSb 3.16K R9 GND VCC C12 0.01UF GND MOSI GND SPI_Connector_MOSI 3.16K R5 Z75_n: W=20MIL, ZO=75+/-5% C10 0.1UF SPI_Connector_SCK AUTOSLP/MISO C9 4.7UF 2 R1 300 SPI Mode Pin Mode 3 Do not place JP2-JP4 in SPI Mode L1 5.6nH R2 75 VCC GND R3 75 GND 1 2 3 R4 37.4 CDb C5 1UF C6 1UF JP2 1 3 5 4 C1 0.01UF CD/MUTE VCC C16 4.7UF 1 2 3 GND GND 2 4 6 GND 1 2 3 4 5 6 JP10 VCC GND GND GND C8 JP9 1 2 3 VCC GND GND JP3 3 2 1 U2 1 2 JP5 5 5 GND VCC JP4 3 2 1 C17 4.7UF C18 6 -SDO1 +SDO1 SMA_R_EDGE ZDIFF100P_13 J4 GND 6 +SDO0 -SDO0 SMA_R_EDGE J3 J2 SMA_R_EDGE ZDIFF100N_13 J5 ZDIFF100P_12 4.7UF C3 GND ZDIFF100N_12 4.7UF C7 4.7UF Z50_n: W=40MIL, ZO=50+-5% LAYOUT NOTE: ZDIFF100N_1 ZDIFF100P_1 ZDIFF100N_2 ZDIFF100P_2 GNDAUTO SLEEP ENABLE AUTOSLP/MISO HDR_2 MUTEREF 18 17 16 15 14 13 BYPASS C2 0.01UF GND VEE/SSb MUTEREF SDO1 SDO1 VEE SDO0 SDO0 VEE/SSbar GND VCC GND BYPASS MUTE/SCK VEE VEE SDI SDI VEE SPI_EN MOSI CDb/MOSI CDb BYPASS/CDb Do Not Load C8 HDR_2 2 1 GND LMH0395_SQA24A JP8 4 Output1_Disable (Do Not Place JP10) SPI_EN CDb BYPASS SPI / Pin Mode Select (JP6-JP9) JP7 Place C1,C16, & C2 as close to U2 pin as possible 1 2 3 SPI_EN JP6 3 DRV2_DIS AEC+ AECBYPASS MUTEref VEE 7 8 9 10 11 12 A B C D 0 1 Power_Supply_Terminal GND 1 24 23 22 CDb/MOSI 21 20 19 VCC VEE CDbar MUTE VCC AUTOSLEEP 25 DAP A B C D IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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