SD3GDAEVK

SD3GDAEVK User's Guide Literature Number: SNLU130 April 2013 Contents 1 2 Introduction ........................................................................................................................ 5 Setup ................................................................................................................................. 5 3 4 5 ................................................................................................. 5 ................................................................................................................. 6 Board Layout ...................................................................................................................... 7 Schematic ......................................................................................................................... 10 Bill of Materials ................................................................................................................. 11 2 Table of Contents 2.1 Connector Descriptions 2.2 Operation SNLU130 – April 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated www.ti.com List of Figures 1 Top Assembly Layer ........................................................................................................ 7 2 Top Layer .................................................................................................................... 8 3 GND Layer ................................................................................................................... 8 4 VCC Layer ................................................................................................................... 9 5 Bottom Layer 6 ................................................................................................................ Schematic .................................................................................................................. 9 10 List of Tables 1 Bill of Materials............................................................................................................. 11 SNLU130 – April 2013 Submit Documentation Feedback List of Figures Copyright © 2013, Texas Instruments Incorporated 3 User's Guide SNLU130 – April 2013 SD3GDAEVK The Texas Instruments SD3GDAEVK evaluation kit (EVK) helps designers evaluate the operation and performance of the LMH0344 3 Gbps HD/SD SDI Adaptive Cable Equalizer, LMH0346 3 Gbps HD/SD SDI Reclocker, and LMH0302 3 Gbps HD/SD SDI Cable Driver in a distribution amplifier configuration. 4 SD3GDAEVK SNLU130 – April 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Introduction www.ti.com 1 Introduction The Texas Instruments SD3GDAEVK evaluation kit (EVK) helps designers evaluate the operation and performance of the LMH0344 3 Gbps HD/SD SDI Adaptive Cable Equalizer, LMH0346 3 Gbps HD/SD SDI Reclocker, and LMH0302 3 Gbps HD/SD SDI Cable Driver in a distribution amplifier configuration. 2 Setup This section describes the connectors and jumpers on the board as well as how to properly connect, set up, and use the SD3GDAEVK. 2.1 Connector Descriptions Conn6, Conn7 – VCC, GND are the DC power connectors. Conn6 and Conn7 should be powered with a DC voltage of 3.3V ± 5%. Conn5 – SDI is the 75Ω BNC input connector for the LMH0344 data input. This input is intended to receive a single-ended input signal via a 75Ω coaxial cable (SMPTE 424M, SMPTE 292M, or SMPTE 259M standard levels and impedances). Conn1, Conn2 – SDO, SDO are the 75Ω BNC output connectors for the LMH0302 data outputs. These outputs have onboard 4.7 µF AC-coupling capacitors (C3 and C4), and are SMPTE 424M, SMPTE 292M, or SMPTE 259M standard levels and impedances. The LMH0302 has a differential output driver, and when using only one output (one half of the differential pair), the unused output should be terminated with a 75Ω BNC termination. Conn3, Conn4 – SCO/SDO2, SCO/SDO2 are the 50Ω SMA output connectors for the LMH0346 secondary clock/data outputs. These outputs have onboard 4.7 µF AC-coupling capacitors (C15 and C16). The LMH0346 has a differential 50Ω CML output driver, and when using only one output (one half of the differential pair), the unused output should be terminated with a 50Ω SMA termination. 2.1.1 LMH0344 Cable Equalizer Controls and Indicators J2 – CD , MUTE is the jumper for monitoring CD and controlling MUTE. CD is asserted high when no signal is present at the LMH0344 input. MUTE may be used to force the LMH0344 outputs on or off, or tied to CD to allow automatic mute operation. To force the outputs off, set the jumper to tie MUTE to VCC. To force the outputs to be always on, set the jumper to tie MUTE to GND. For normal operation, set the jumper to tie CD to MUTE for automatic mute control. J6 – BYPASS is the jumper for controlling the equalization bypass function. To put the equalizer into bypass mode, set this jumper to tie BYPASS to VCC. For normal operation (bypass turned off), leave J6 open. D1 – CD is the LED for the CD status. This LED is GREEN when an input signal has been detected at the LMH0344 input, and OFF when no input signal is detected. 2.1.2 LMH0346 Reclocker Controls and Indicators J1 – RATE0, RATE1 are the jumpers for controlling the reclocker serial data rate. These (two) jumpers may be set in any of the following three configurations: 1. RATE0=RATE1=GND for auto-rate mode (default mode if jumper is not set). 2. RATE0=VCC, RATE1=GND for 270 Mbps (SD) mode. 3. RATE0=GND, RATE1=VCC for 2967/2970 Mbps or 1483/1485 Mbps (HD/3G) mode. J3 – SCO_EN is the jumper for selecting the function for the secondary output of the reclocker (SCO/SDO2). To select the serial clock, set the jumper to tie SCO_EN to VCC. To select the serial data output, set the jumper to tie SCO_EN to GND. The default selection (if jumper is not set) is for a second data output. SNLU130 – April 2013 Submit Documentation Feedback SD3GDAEVK Copyright © 2013, Texas Instruments Incorporated 5 Setup www.ti.com J4 – BYPASS/AUTO BYPASS is the jumper for selecting the bypass mode of the reclocker. Bypass mode (VCC) forces the device to output the data without reclocking it. Auto bypass (GND) is the default condition in which the device locks to and reclocks the data at supported data rates while automatically bypassing the reclocking function for unsupported data rates. The default selection (jumper is not set) is for auto bypass mode. J8 – OUTPUT MUTE is the jumper for muting or enabling the reclocker outputs. To mute the outputs, set this jumper to tie OUTPUT MUTE to GND. To enable the outputs (normal operation), set the jumper to tie OUTPUT MUTE to VCC. The default selection (jumper is not set) is for the outputs to be enabled. J10 – LOCK DETECT is the jumper for monitoring the reclocker lock detect status. This output provides an indication that the PLL is locked when high. J9 – SD/HD is the jumper for monitoring the SD/HD output. This output indicates that the locked data rate is SD when high, and HD/3G when low. This output is only valid when the PLL is locked, and defaults to HD/3G (low) when the PLL is unlocked. D2 – LOCK is the LED for the reclocker lock detect status. This LED is GREEN when the PLL is locked to the incoming data, and OFF when the PLL is not locked. D3, D4 – SD/HD are the LEDs for the locked data rate. D4 is RED when the reclocker is locked to SD data. D3 is GREEN when the reclocker is locked to HD or 3G data. 2.1.3 LMH0302 Cable Driver Controls and Indicators J5, J7 – SD/HD are the jumpers for controlling the slew rate of the cable driver output. The output complies with SMPTE 259M when high and SMPTE 424M / 292M when low. Two methods are provided to set the cable driver slew rate: 1. Auto Mode: Set J5 and leave J7 open. The LMH0346 will automatically detect the incoming data rate and control the LMH0302 slew rate. If the LMH0346 does not recognize the incoming data or is in Bypass mode, the slew rate will default to HD/3G. 2. Manual Mode: Pull J5 and set the J7 jumper to either SD or HD/3G to manually set the LMH0302 slew rate. J11 – ENABLE is the jumper for controlling the cable driver power down function. Set this jumper to disable the cable driver. Leave this jumper open for normal operation. 2.2 Operation Begin by applying 3.3V DC power to the Conn6 and Conn7 connectors on the board. Set the control jumpers as desired. For default operation, set the following jumpers: 1. J2 set to tie CD to MUTE for automatic equalizer mute control. 2. J5 set to automatic LMH0346 control of the LMH0302 output slew rate. All other jumpers may be left open if desired. Apply a test signal via 75Ω coaxial cable to the Conn5 75Ω BNC input connector. The signal characteristics should be within the LMH0344 input specifications (typically the signal going into the cable will be a SMPTE 424M, SMPTE 292M, or SMPTE 259M compliant serial SDI signal). The LMH0344 equalizer will automatically adjust its gain to reverse the effects of the cable loss and restore the original signal. The LMH0346 reclocker receives this signal and retimes it to reduce jitter. The primary reclocker output is sent to the LMH0302 cable driver, which drives SMPTE 424M, SMPTE 292M, or SMPTE 259M compliant serial SDI signals to the Conn1 and Conn2 75Ω BNC output connectors. Connect 75Ω coaxial cable to Conn1 and/or Conn2 to observe the single-ended output. If only one output is used, the other output should be terminated with a 75Ω BNC termination. The secondary reclocker output may be observed via the Conn3 or Conn4 50Ω SMA output connector. Connect a matched pair of 50Ω SMA cables to Conn3 and Conn4 to observe the differential output, or connect the cable to either Conn3 or Conn4 to view the single-ended output. If only one output is used, the other output should be terminated with a 50Ω SMA termination. 6 SD3GDAEVK SNLU130 – April 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Board Layout www.ti.com To evaluate only the LMH0346 reclocker, set the J6 jumper to bypass equalization, and monitor the reclocker SCO/SDO2 outputs on Conn3 and Conn4. 3 Board Layout Figure 1, Figure 2, Figure 3, Figure 4, and Figure 5 show the board layout for the SD3GDAEVK. The SD3GDAEVK is a 4-layer board (TOP / GND / VCC / BOTTOM). Figure 1. Top Assembly Layer SNLU130 – April 2013 Submit Documentation Feedback SD3GDAEVK Copyright © 2013, Texas Instruments Incorporated 7 Board Layout www.ti.com Figure 2. Top Layer Figure 3. GND Layer 8 SD3GDAEVK SNLU130 – April 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Board Layout www.ti.com Figure 4. VCC Layer Figure 5. Bottom Layer SNLU130 – April 2013 Submit Documentation Feedback SD3GDAEVK Copyright © 2013, Texas Instruments Incorporated 9 Schematic 4 www.ti.com Schematic Figure 6. Schematic 10 SD3GDAEVK SNLU130 – April 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Bill of Materials www.ti.com 5 Bill of Materials Table 1. Bill of Materials Reference Designator Description Manufacturer Part Number C1, C2 Capacitor, 1µF, 10V, X5R, 0402 Murata GRM155R61A105KE15D C11 Capacitor, 56nF, 16V, X7R, 0603 Murata GRM188R71C563KA01D C13 Capacitor, 4.7µF, 16V, X7R, 1206 TDK C3216X7R1C475K160AB C17, C18 Capacitor, 39pF, 50V, NP0, 0603 TDK C1608C0G1H390J080AA C3, C4, C15, C16 Capacitor, 4.7µF, 6.3V, X5R, 0603 Murata GRM188R60J475KE19D C5 Capacitor, 1µF, 16V, X5R, 0603 Murata GRM188R61C105KA93D C6, C7, C8, C9, C10, C12, C24, C25 Capacitor, 0.1µF, 25V, X7R, 0603 Kemet C0603C104J3RACTU Conn3, Conn4 SMA, 50Ω, Edge Launch Johnson 142-0701-851 Conn1, Conn2, Conn5 BNC, 75Ω, Edge Launch Trompeter UCBJE20-1 Conn6, Conn7 Power Supply Terminal Keystone 1287-ST D1, D2, D3 LED, Green, 0603 Lite-On LTST-C190GKT D4 LED, Red, 0603 Lite-On LTST-C190KRKT J1, J2 Header, 2x3, 0.1" 3M 929836-02-36-RK J3, J4, J7, J8 Header, 1x2, 0.1" 3M 929834-02-36-RK J5, J6, J9, J10, J11 Header, 1x3, 0.1" 3M 929834-02-36-RK L1, L2, L3 Inductor, 6.8nH, 0402 Murata LQP15MN6N8B02D R1, R2, R3, R4, R5, R6 Resistor, 75Ω, 1%, 0402 Yageo America RC0402FR-0775RL R13, R26 Resistor, 0.0Ω 5%, 0603 Panasonic ECG ERJ-3GEY0R00V R12, R14, R15 Resistor, 750Ω, 5%, 0603 Panasonic ECG ERJ-3GEYJ751V R17 Resistor, 1kΩ, 1%, 0603 Yageo America RC0603FR-071KL R18, R19 Resistor, 330Ω, 5%, 0603 Panasonic ECG ERA-V15J331V R7 Resistor, 37.4Ω, 1%, 0402 Panasonic ECG ERJ-2RKF37R4X R8 Resistor, 300Ω, 5%, 0603 Panasonic ECG ERJ-3GEYJ301V R9, R10 Resistor, 100Ω, 1%, 0603 Panasonic ECG ERJ-3EKF1000V U1 IC, SDI Cable Equalizer, LLP-16 TI LMH0344SQ U2 IC, SDI Reclocker, eTSSOP-20 TI LMH0346MH U3 IC, SDI Cable Driver, LLP-16 TI LMH0302SQ U4 IC, 3-state buffer, SOT-23 Fairchild Semi NC7SZ125M X1 Crystal, 27MHz Abracon ABMM-27.000MHZ-B2-T SNLU130 – April 2013 Submit Documentation Feedback SD3GDAEVK Copyright © 2013, Texas Instruments Incorporated 11 EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. 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