SDM872K

® FPO FPO 46% 43% SDM862 SDM863 SDM872 SDM873 16 Single Ended/8 Differential Input 12-BIT DATA ACQUISITION SYSTEMS FEATURES q COMPLETE 12-BIT DATA ACQUISITION SYSTEM IN A MINIATURE PACKAGE q INPUT RANGES SELECTABLE FOR UNIPOLAR OR BIPOLAR OPERATION 872/3 q THROUGHPUT RATES: 862/3 8-BIT ACCURACY: 45kHz 67kHz 12-BIT ACCURACY: 33kHz 50kHz q SELECTABLE GAINS OF 1, 10, AND 100 q FULL MICROPROCESSOR COMPATIBLE INTERFACE q GUARANTEED NO MISSING CODES OVER TEMPERATURE q SURFACE-MOUNT OR PIN GRID ARRAY PACKAGE OPTIONS q HIGH RELIABILITY SCREENED VERSIONS AVAILABLE q FULL SPECIFICATION OVER THREE TEMPERATURE RANGES: 0 to +70°C, –25 to +85°C, –55 to +125°C q EVERY UNIT SUPPLIED WITH ELECTRICAL TEST DATA q POWER PLANT MONITORING q SECURITY SYSTEMS MONITORING q AUTOMATIC TEST EQUIPMENT DESCRIPTION 16 Single-Ended Inputs: 8 Differential Inputs: 33kHz Throughput Rate: 50kHz Throughput Rate: SDM862 SDM863 SDM862 SDM872 SDM872 SDM873 SDM863 SDM873 The SDM components are complete, pin-compatible, data acquisition systems housed in a hermetically sealed 1"-square leadless chip carrier or a 1.1"-square pin grid array. The small package outlines and low power consumption provide an ideal data acquisition solution when space is at a premium. The devices comprise of an input multiplexer, instrumentation amplifier with selectable gains, sample/hold amplifier and A/D converter with microprocessor interface and three-state buffers. The SDM family will accept unipolar or bipolar voltage inputs in the range 0 to +10V, ±5V and ±10V. For lowlevel signals, jumper-selectable gains of 10 or 100 can be applied. The number of input channels can be expanded by the addition of multiplexers. System integration is simplified by the microprocessor interface and the facility of the sample/hold amplifier being controlled directly by the A/D converter. APPLICATIONS q INDUSTRIAL PROCESS MONITORING q AIRBORNE SYSTEMS MONITORING q ENGINE MONITORING ANALOG 8 CH 16 CH 8 CH MUX INA DIGITAL S/H ADC 12 Bits 862/872 863/873 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1988 Burr-Brown Corporation PDS-686F Printed in U.S.A. August, 1993 Output MUX* S/H Output Hold Capacitor S/H Output SDM862, SDM872 SDM863, SDM873 CH0 or + –– CH0 + CH7 CH0 16 Single-Ended or 8 Differential Input Multiplexer + Inst Amp – S/H Amp 12-Bit A/D Converter Digital Data Outputs CH 15 – CH7 SPECIFICATIONS ELECTRICAL At +25°C, VCC = ±15V, VDD = 5V, external sample/hold capacitor of 4700pF. All grades are burned-in at +125°C for 48 hours min. SDM862/863/872/873 J, A, R PARAMETER RESOLUTION INPUT ANALOG Voltage Ranges: Bipolar Unipolar Input Impedance: On Channel Off Channel Input Capacitance: On Channel Off Channel CMRR (20VDC to 1kHz) Crosstalk (20Vp-p, 1kHz) (1) Feedthrough (at 1kHz) (1) Offset (channel to channel) G = 1 (2) Input Bias Current/Channel Input Voltage Range (3) DIGITAL (7, 8) MUX Input Channel Select: Logic ‘1’ Logic ‘0’ MUX Input: Logic High Logic Low S/H Command: Logic ‘1’ Logic ‘0’ ADC Section: Logic ‘1’ Logic ‘0’ TRANSFER CHARACTERISTICS ACCURACY Integral Linearity (4) Differential Linearity (4) No Missing Codes Gain Error (5): G = 1 G = 100 Unipolar Offset Error (5) Bipolar Offset Error (5) Noise Error (Measured at S/H Output) G = 1 Droop Rate Temperature Coefficients: Unipolar Offset Bipolar Offset Full-Scale Calibration ±0.024 ±0.024 Over Operating Temperature Range 0.5 0.9 16 50 0.5 50 1 500 20 30 60 ±0.012 * * * * * * * * * 15 25 35 ±5, ±10 0-10 1010 1010 20 20 85 –85 –85 30 1 +11 –15 5 5 4.0 0.8 0.2 5 30 10 10 * * * * * * * * * * * * * * * * * * * * V V Ω Ω pF pF dB dB dB µV nA V V µA µA V V nA µA µA µA MIN TYP MAX 12 SDM862/863/872/873 K, B, S MIN TYP MAX * UNITS Bits 80 * –80 –80 100 5 * * 30 30 Data Mode Byte Select Chip Select Chip Enable Read/Convert Status S/H Control S/H Common Input Channel Select Enable *(Output MUX Minus) Only on SDM863/873 Reference Sense Bipolar Offset Reference In Reference Out Amp Output S/H Input Input Range Input Amp Gain Select * * * * +10 –10 * * %FSR %FSR % % mV mV mVp-p µV/ms ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ® SDM862/863/872/873 2 SPECIFICATIONS ELECTRICAL At +25°C, VCC = ±15V, VDD = 5V, external sample/hold capacitor of 4700pF. SDM862/863/872/873 J, A, R PARAMETERS SYSTEM TIMINGS ADC Conversion Time: SDM862/SDM863 SDM872/SDM873 S/H Aperture Delay S/H Aperture Uncertainty TIMING Throughput (Serial Mode) SDM862/SDM863 SDM872/SDM873 (Overlap Mode): SDM862/SDM863 SDM872/SDM873 MULTIPLEXER (6) Switching Time (between channels) Settling Time (10V step to 0.02%) Enable Time ‘ON’ ‘OFF’ INSTRUMENTATION AMPLIFIER (6) Settling Time (20V step to 0.01%) G=1 G = 10 G = 100 Slew Rate S/H AMPLIFIER (6) Acquisition (10V step to 0.01%) Aperture Delay Hold Mode Settling Time Slew Rate OUTPUT DIGITAL DATA Output Codes: Unipolar Bipolar Logic Levels: Logic 0 (Sink = 1.6mA) Logic 1 (Source = 500µA) Leakage (Data Bits Only), High-Z State POWER SUPPLY REQUIREMENTS Rated Voltage: Analog (±VCC) Digital (VDD) Supply Drain: +15V –15V +5V Power Dissipation TEMPERATURE RANGE Operating Temperature Range JH, KH/JL, KL AH, BH/AL, BL RH, SH/RL, SL Storage Temperature Range °C °C °C °C 14.25 4.5 15 5 13 22 11 580 15.75 5.5 22 30 15 855 * * * * * * * * * * * * * * VDC VDC mA mA mA mW Unipolar Straight Binary (USB) Bipolar Offset Binary (BOB) +0.4 * +5 * +1.5 2.5 1 0.25 9 9 20 12 50 2 25 15 * * * * * * * * µs µs ns ns MIN TYP MAX SDM862/863/872/873 K, B, S MIN TYP MAX UNITS 22 28 33 50 * * * * * * * * kHz kHz kHz kHz µs µs µs µs 2 0.5 * * 12 5 3 4 17 5 50 1.5 10 12.5 7.5 7.5 * * * * * * * * * * * * µs µs µs V/µs µs ns µs V/µs * * * +2.4 –5 0.1 V V µA 0 –25 –55 –65 70 +85 +125 +150 * * * * * * * * * Specification same as SDM862/863/872/873J, A, R grades. NOTES: (1) Measured at the same and hold output. (2) Measured with all input channels grounded. (3) The range of voltage on any input with respect to common over which accuracy and leakage current is guaranteed. (4) Applicable over full operating temperature range. NO MISSING CODES GUARANTEED OVER TEMPERATURE RANGE. (5) Adjustable to zero using external potentiometer or select-on-test resistor. (6) Specifications are at +25°C and measured at 50% level of transition. (7) When using TTL drivers a 1kΩ pull-up resistor should be used. (8) Muxes operate in a break-before-make manner. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 SDM862/863/872/873 DIGITAL TIMING SYMBOL PARAMETER MIN TYP MAX UNITS CONVERT MODE tdsc Status Delay from CE thec CE Pulse Width tssc CS to CE Setup thsc CS Low During CE High tsrc R/C to CE Setup thrc R/C Low During CE High tsac Byte Select to CE Setup thac Byte Selected Valid During CE High tc 86X Conversion Time: 12 Bit Cycle 8 Bit Cycle tc 87X Conversion Time: 12 Bit Cycle 8 Bit Cycle READ MODE tdd Access Time from CE thd Data Valid after CE Low thl Output Float Delay tssr CS to CE Setup tsrr R/C to CE Setup tsar Byte Select to CE Setup thsr CS Valid after CE Low thrr R/C High after CE Low thar Byte Select Valid after CE Low ths 86X Status Delay after Data Valid ths 87X Status Delay after Data Valid ABSOLUTE MAXIMUM RATINGS(1) +VCC to ACOM .................................................................... –0.5V to +16V –VCC to ACOM ....................................................................... +0.5 to –16V +VDD to DCOM ................................................................... –0.5V to +7.0V Analog Input Signal Range ................................ +VCC +20V to –VCC –20V Digital Input Signal ............................................................... –0.5V to +VDD ACOM to DCOM .................................................................................. ±1V NOTE: (1) Absolute maximum ratings are limiting values applied individually, beyond which the serviceability of the circuit may be impaired. Functions operation under any of these conditions is not necessarily implied. 50 50 50 50 50 0 50 9 6 9 6 100 30 20 20 0 20 0 20 20 13 12 8 75 35 100 0 0 25 0 0 25 500 300 200 25 17 15 10 150 150 ns ns ns ns ns ns ns ns µs µs µs µs ns ns ns ns ns ns ns ns ns ns ns /QM HIGH RELIABILITY SCREENING High Power Internal Visual Inspection .......................................... Burr-Brown Spec. QC2010 Stabilization Bake ............................................................. 24Hr at +150°C Temperature Cycling ...................................... 10 Cycles –65°C to +150°C Constant Acceleration .......................................................... 30kG, Y1 axis Hermeticity Fine Leak ................................................. Helium 5 x 10–8cc/s Hermeticity Gross Leak ......................................................... Fluorocarbon Burn-In ............................................................................ 160Hr at +125°C 25 50 0 50 0 0 50 100 100 1000 600 CONVERSION CYCLE TIMING READ CYCLE TIMING CE tSSC CS tSRC R/C tHRC Byte Select tHSC t HEC CE tSSR CS tHRR tSRR Byte Select tHSR R/C tSAC tSAR tHAC tDSC tC High Impedance tHAR STS tHS DB11– DBO High-Z tDD Data Valid tHL tHD STS DB11– DBO ® SDM862/863/872/873 4 ORDERING INFORMATION(1) Product SDM862J SDM862K SDM862A SDM862B SDM862R SDM862S SDM872J SDM872K SDM872A SDM872B SDM872R SDM872S Input 16SE 16SE 16SE 16SE 16SE 16SE 16SE 16SE 16SE 16SE 16SE 16SE LCC, PGA Accuracy Package (% FSR) L,H L,H L,H L,H L,H L,H L,H L,H L,H L,H L,H L,H ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 Throughput 33kHz 33kHz 33kHz 33kHz 33kHz 33kHz 50kHz 50kHz 50kHz 50kHz 50kHz 50kHz Temperature Range (°C) 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 Product SDM863J SDM863K SDM863A SDM863B SDM863R SDM863S SDM873J SDM873K SDM873A SDM873B SDM873R SDM873S Input 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF 8DIF LCC, PGA Accuracy Package (% FSR) L, H L, H L, H L, H L, H L, H L,H L,H L,H L,H L,H L,H ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 ±0.024 ±0.012 Throughput 33kHz 33kHz 33kHz 33kHz 33kHz 33kHz 50kHz 50kHz 50kHz 50kHz 50kHz 50kHz Temperature Range (°C) 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 0 to +70 0 to +70 –25 to +85 –25 to +85 –55 to +125 –55 to +125 NOTE: (1) 16 single-ended inputs, LCC package, with accuracy of 0.24% FSR. Temp Range of 0°C to +70°C and throughput of 33kHz = SDM862JL. PACKAGE INFORMATION PRODUCT PC862/863-1 PC862/863-2 DESCRIPTION LCC (Socketed) Evaluation PCB(2) PGA Evaluation PCB PACKAGE DRAWING NUMBER(1) 907 906 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Socket is MC0068-1. ® 5 SDM862/863/872/873 PIN CONFIGURATIONS MUX OUT +/AMP IN+ 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 MUX ADD2 MUX ADD1 MUX ADD0 MUX ENABLE CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 S/H IN NC S/H OUT HOLD CAP S/H OUT 51 50 49 48 47 46 45 44 43 42 41 40 39 38 PIN GROUPING BY FUNCTION DOTTED LINE SHOWS SUPPLY SEPARATION MUX INA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AMP OUT AMP REF +15V (1) –15V (1) +5V (2) STATUS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 AMP SENSE MUX ADD3 DCOM (1) AMP IN– CH10 CH11 CH12 CH13 CH14 CH15 G100 CH8 CH9 G10 RG NC TOP VIEW SDM862/SDM872 37 36 35 S/H 15 16 A/D 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 S/H COM (2) S/H CONT BYTE SELECT DATA MODE REF OUT +15V (2) ACOM (2) –15V (2) ADC IN (10V) ADC IN (20V) DCOM (2) CS R/C CE BIP OFF REF IN D0 MUX OUT +/AMP IN+ 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 MUX ADD2 MUX ADD1 MUX ADD0 MUX ENABLE CH0+ CH1+ CH2+ CH3+ 51 50 49 48 47 46 45 44 43 42 41 40 39 38 S/H AMP SENSE MUX OUT– DCOM (1) AMP IN– CH0– CH1– CH2– CH3– CH4– CH5– CH6– CH7– G100 G10 RG NC MUX INA 1 2 3 4 AMP OUT AMP REF +15V (1) –15V (1) +5V (2) STATUS D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 PIN GROUPING BY FUNCTION DOTTED LINE SHOWS SUPPLY SEPARATION 5 6 7 8 9 10 11 12 13 14 15 16 A/D 17 TOP VIEW SDM863/SDM873 CH4+ CH5+ CH6+ CH7+ S/H IN NC S/H OUT HOLD CAP S/H OUT 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 S/H COM (2) S/H CONT BYTE SELECT DATA MODE +15V (2) REF OUT ACOM (2) ADC IN (10V) ADC IN (20V) –15V (2) DCOM (2) CS R/C CE REF IN BIP OFF D0 ® SDM862/863/872/873 6 PIN DESIGNATION CH0 to CH15 CH0 to CH7 (+, –) (PINS 40 to 47, 54 to 61) MUX OUT+/AMP IN+ (PIN 65) MUXOUT (Pin 67) AMP IN (Pin 66) AMP OUT (Pin 1) AMP SENSE (Pin 68) AMP REF (Pin 2) DEFINITION Channel Inputs COMMENTS SDM8X2 = SDM862 OR SDM872 Analog Inputs (Total 16) for single-ended and differential operation. Unused inputs must be connected to analog common. On the SDM8X2 this is the multiplexer output. On the SDM8X3 it is the output of the positive selected inputs. It is connected internally to the positive input of the instrumentation amplifier. This pin is used on the SDM8X3 only. It should be connected to the negative input of the instrumentation amplifier. On the SDM8X2 this should be connected to analog common. On the SDM8X3 it should be connected to Muxout—(Pin 67). This pin should be connected to the input of the S/H amplifier (Pin 39). This pin will normally be connected direct to AMP OUT (Pin 1). This pin will normally be connected to analog common. Care should be taken to minimize tracking and contact resistance to analog common to optimize system accuracy. Two pins are provided to facilitate a guard ring around the hold capacitor pin. These pins should be connected to either ADC in (20V) or ADC in (10V) depending on the desired range. The tracking to the hold capacitor should be as short as possible and a guard ring employed using Pins 35 and 37. Connect to S/H amplifier output. Use appropriate pin for desired range. For Gain = 1, no connections. For Gain = 10, connect G10 to RG. For Gain = 100, connect G100 to RG. This is the reference voltage for the A/D converter. Connect trim potentiometers (or select-on-test resistors) to these pins for unipolar or bipolar operation as shown in Figures 12, 13. Connect to amp out (Pin 1). Logic ‘1’ on this pin will enable a selected channel on the internal multiplexer. Logic ‘0’ de-selects all channels. These address lines select a particular channel as specified in Figure 24. Logic ‘1’ holds an analog value for conversion by the A/D converter. This line may be controlled by the status (Pin 6) of the converter to simplify external timing control. Connect to digital common. The 12- or 8-bit result of a conversion is available as output on these pins (D0-LSB, D11-MSB). This output is at logic ‘1’ while the internal A/D converter is carrying out a conversion. This pin may be used to directly control the S/H amplifier. This input must be at logic ‘1’ to either initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). This input must be at logic ‘0’ to either initiate a conversion or read output data (see Figures 10, 17, 18, 19, 20). Data can be read when this pin is logic ‘1’ or a conversion can be initiated when this pin is logic ‘0’. This pin is typically connected to the R/W control line of a microprocessor-based system (see Figures 10, 17, 18, 19, 20). When data mode is at logic ‘1’ all 12 output data bits are enabled simultaneously. When data mode is at logic ‘0’ MSBs and LSBs are controlled by byte select (Pin 32). When reading output data, byte select at logic ‘0’ enables the 8 MSBs. Byte select at logic ‘1’ enables the 4 LSBs. The 4 LSBs can therefore be connected to four of the MSB lines for inter-connection to an 8-bit bus. In start convert mode, logic ‘0’ enables a 12-bit conversion while logic ‘1’ will short cycle the conversion to 8 bits (see Figure 10). Connect to +15V supply using decoupling as indicated in Figures 15, 16. Connect to –15V supply using decoupling as indicated in Figures 15, 16. Analog common connection. Note that a common (including digital common) should be connected together at one point close to the device. Connect to digital common. Connect to +5V digital supply line with decoupling as in Figures 15, 16. Connect to S/H common at one point close to device. MULTIPLEXER “HI” OUTPUT MULTIPLEXER “LO” OUTPUT Negative input of instrumentation amplifier Output of instrumentation amplifier Output sense line of instrumentation amplifier Reference for amplifier output S/H OUT (Pins 35/37) Output of sample/hold amplifier HOLD CAP (Pin 36) ADC IN (20V); ADC IN (10V) (Pins 21, 22) RG, G10, G100 (Pins 62, 63, 64) REF OUT (PIN 26) REF IN, BIP OFF (Pins 24, 23) S/H IN (Pin 39) MUX ENABLE (Pin 48) MUX ADD0 to MUX ADD3 (Pins 49 to 52) S/H CONT (Pin 33) Connection for hold capacitor on S/H amplifier Inputs to A/D converter Gain settling pins on instrumentation amplifier 10V Reference voltage Reference input and offset input to A/D converter Input to sample/hold amplifier Multiplex enable/disable Address inputs for channel selection Track/Hold control on S/H amplifier S/H COM (Pin 34) D0 to D11 (Pins 7 to 18) STATUS (Pin 6) CE (Pin 28) CS (Pin 31) R/C (Pin 29) Reference for S/H logic control 3-state digital outputs Status of A/D conversion Chip enable Chip select Read/convert DATA MODE (Pin 30) Select 12- or 8-Bit Data BYTE SELECT (Pin 32) Byte address, short cycle +15V(1), +15V(2)(Pins 3, 27) –15V(1), –15V(2)(Pins 4, 20) ACOM(2) (Pin 25) DCOM (1) (Pin 53) +5V (Pin 5) DCOM(2) (Pin 19) NC (Pin 38) Power Supply Power Supply Analog Common Reference for MUX logic control. Logic power supply Reference for A/D converter control lines No internal connection ® 7 SDM862/863/872/873 SYSTEM DESCRIPTION The SDM comprises four circuit elements—an input-protected multiplexer, an instrumentation amplifier, a sample/ hold amplifier, and an analog-to-digital converter. INSTALLATION MULTIPLEXER The SDM family has a choice of input multiplexers (MUX). SDM862 and SDM872: SDM863 and SDM873: 16 single-ended inputs 8 differential inputs to ensure that neither of the differential inputs exceed the maximum input range. Otherwise, signal distortion will result. A return path for the input bias currents must always be provided. This prevents the charging of stray capacitances in applications using floating sources, such as transformers and thermocouples. Multiplexer inputs are protected from overvoltage, as indicated in the electrical specifications, and should be current limited to 20mA. Where high-speed operation is required and channels require rapid sampling, then it is important to buffer the inputs against the effect of current sharing between the MUX output capacitance and the input filter capacitance. See Figure 2. On all models, the analog inputs may be expanded using the enable control. See Figure 1. When the enable is at a logic “0,” the internal MUX is disabled, allowing additional multiplexers to be connected in parallel. The limiting factor for the number of additional multiplexers is the cumulative effect of leakage current flowing in the signal source impedance, causing offset errors. Differential inputs will generally eliminate the noise associated with common system grounds, but care must be taken MUX Cf Cf CM MUX Extern Out A0 A1 A2 A3 A0 A1 A2 A3 A4 D-Com EN FIGURE 2. Filter and MUX Capacitance. All data acquisition systems using a MUX require consideration of the errors that may be introduced by MUX output capacitance. The applications information explains this more fully in the input filtering section. Shown in Figure 3 is an application that demonstrates the flexibility of signal conditioning and gives the opportunity to use a higher bandwidth filter. Diodes shown are low leakage types (1na). The low output impedance of the amplifiers reduces the time taken to charge MUX capacitance CM. INSTRUMENT AMPLIFIER The instrument amplifier (INA) presents a very high input impedance to the signal source, eliminating gain errors introduced by voltage divider action between the source output impedance and SDM input impedance. Where the differential models are used, the INA performs the differential to single-ended conversion required to drive the sample/ hold amplifier. Gains may be set by using external jumpers, to values of 1 (no jumper), 10 and 100. For gains other than these presets, the following formula may be used to find an external resistor value to add in series with the G = 10 or G = 100 jumpers. Rext = 40kΩ G–1 – Ri Where Ri = 4444Ω, G = 10 input. 404Ω, G = 100 input. SDM8X2 53 49 50 51 52 48 65 66 MUX Intern Out A0 A1 A2 A3 INA MUX Extern D-Com EN D-Com EN +Out –Out A0 A1 A2 A0 A1 A2 A3 SDM8X3 53 49 50 51 48 65 67 66 MUX Intern +Out – Out A0 A1 A2 INA FIGURE 1. External Multiplexer Connections for Differential and Single-Ended Operation. ® D-Com EN It should be noted that the internal gain set resistors have a ±20% tolerance and ±20ppm/°C drift. 8 SDM862/863/872/873 MUX FET Input A1 10kΩ 10kΩ Cf Rf Rf – + Cf 10V 10V 4.44kΩ 20kΩ 20kΩ A3 R2 10kΩ A2 10kΩ R1 404Ω Ri – + Rf + Cf – Rf + Cf – Rf FET Input R3 FIGURE 5. Increasing Output Amplifier Gain. Matching of R1 and R3 is required to maintain high common-mode rejection (CMR), R2 sets the gain and may be varied without effect on CMR. To ensure that the effects of temperature are minimized when altering the gain with external components, it is very important to use low tempco resistors. When connecting the output sense, ensure that series resistance is minimized because resistance present will degrade CMR. SETTLING TIME vs GAIN (0.01%, 20V Step) 10 +V Rf + Cf – –V CM FIGURE 3. Example Application Illustrating Flexible Signal Conditioning. FET Input A1 Settling Time (µs) –In 10kΩ 10kΩ Sense 5 4.44kΩ X10 X100 404Ω REXT RG 20kΩ 20kΩ A3 Output 0 10kΩ A2 10kΩ FET Input 120 Common-Mode Rejection (dB) 1 10 Gain (V/V) CMR vs FREQUENCY 100 Ref +In FIGURE 4. Use External Gain Set Resistor. Where it is necessary to keep the input amplifiers from saturating or increasing the overall gain, then the gain of the output amplifier can be increased from unity by using the circuit in Figure 5. The values of the resistors in Figure 5 are in the following table. O/P GAIN 2 5 10 R1 and R3 Ω 1200 1000 1500 R2 Ω 2740 511 340 100 80 Gain = 100 60 Gain = 10 40 Gain = 1 20 0 1 10 100 1k Frequency (Hz) 10k 100k 1M FIGURE 6. Typical INA Settling Time and CMR. ® 9 SDM862/863/872/873 Some applications may require programmable gains. This may be realized with Figure 7. 1 2 6 7 8 SDM8X3 67 PGA 102 3 15 Gain Sel TTL/CMOS 1-10-100 66 MUX INA FIGURE 7. Setting Programmable Gains. SAMPLE/HOLD AMPLIFIER The Sample/Hold amplifier (S/H) is used to track the incoming signal and “hold” the required instantaneous value so that it does not change while the ADC is carrying out its conversion. Timing for the S/H may be derived from the STATUS output of the ADC, with care being taken to comply with the SDM timing considerations. Capacitors with high insulation resistance and low dielectric absorption such as Teflon™, polystyrene or polypropylene should be used as storage elements. (Polystyrene should not be used above +80°C.) Teflon™ is recommended for high temperature operation. Care should be taken in the printed circuit layout to minimize stray capacitance and leakage currents from the capacitor to minimize charge offset and droop errors. The use of a guard ring driven by the S/H output around the pin connecting to the hold capacitor is recommended. (Refer to the application board layout for an example of this.) The value of the external hold capacitor determines the droop rate, charge offset and acquisition time of the S/H, Figure 8. Droop rate for the SDM is specified with a hold capacitor value of 4700pf. There is a trade-off between acquisition time and droop rate, as the hold capacitor is increased in value it takes longer to charge, and hence there is a corresponding increase in acquisition time and reduction in droop rate. The droop rate is determined by the amount of leakage present in the SDM, board leakage and the dielectric absorption of the hold capacitance. The hold capacitor is also a compensation element for the S/H and should not be reduced below 2nf for good stability. The offset error in sample mode is not affected by the hold capacitor. However, during the transition to hold mode there is approximately 5pC of charge injected into the hold capacitor, causing an offset error that has been nulled for use with a 5nf hold capacitor. Any other value for the hold capacitor will cause a minor but fixed hold mode offset to be introduced, and is proportional to the change in value from 5nf. Therefore, the SDM should be offset nulled with the S/H in hold mode. ANALOG-TO-DIGITAL CONVERTER This circuit element converts the analog voltage presented by the sample/hold amplifier to a digital number in binary format under control of the digital signals detailed in Figure 9. The converter can convert unipolar and bipolar signals in the range 10V and 20V. It can be calibrated to remove gain and offset errors from the entire system. The converter contains its own clock, voltage reference, and microprocessor interface with 3-state outputs. The converter will normally be used to digitize signals to 12-bit resolution, but it can be short-cycled to provide 8-bit resolution at higher speed. The digital output is compatible with 8- or 16-bit data buses, the data format being selected by control signals as detailed in Figure 9. DATA MODE X X X X X X X X 1 0 0 BYTE SELECT X X 0 1 0 1 0 1 X 0 1 CE 0 X ◊ ◊ 1 1 1 1 1 1 1 CS X 1 0 0 ◊ ◊ 0 0 0 0 0 R/C X X 0 0 0 0 ◊ ◊ 1 1 1 OPERATION None None Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Initiate 12-bit conversion Initiate 8-bit conversion Enable 12-bit output Enable 8 MSBs only Enable 4 LSBs plus 4 trailing zeros ACQUISITION TIME vs HOLD CAPACITANCE For a 10V Step to ±10mV of Final Value 10 9 Acquisition Time (µs) 8 7 6 5 4 3 4 6 8 10 12 14 16 Hold Capacitance (nF) FIGURE 9. Control Input Truth Table. LINEARITY ERROR Linearity error is defined as the deviation of actual code transition values from the ideal transition values. Ideal transition values lie on a line drawn through zero (or minus full scale for bipolar operation) and plus full scale. The zero value is located at an analog input value 1/2LSB before the first code transition (000H to 001H). The full-scale value is located at an analog value 3/2LSB beyond the last code transition (FFEH to FFFH) (see Figure). Thus, with the SDM connected for bipolar operation and with a full-scale range (or span) of 20V (±10V), the zero value of –10V is 2.44mV FIGURE 8. Acquisition Time vs Hold Capacitance for a 10V Step Settling to ±10mV of Final Value. ® SDM862/863/872/873 10 below the first code transition (000H to 001H at –9.99756V) and the plus full-scale value of +10V is 7.32mV above the last code transition (FFEH to FFFH at +9.99268) (see Figure 13). NO MISSING CODES (DIFFERENTIAL LINEARITY ERROR) A specification which guarantees no missing codes requires that every code combination appear in a monotonicallyincreasing sequence as the analog input is increased throughout the range. Thus, every input code width (quantum) must have a finite width. If an input quantum has a value of zero (a differential linearity error of –1LSB), a missing code will occur. The SDM is guaranteed to have no missing codes to 12-bit resolution over it’s respective specification temperature ranges. UNIPOLAR OFFSET ERROR An SDM connected for unipolar operation has an analog input range of 0V to plus full scale. The first output code transition should occur at an analog input value 1/2LSB above 0V. Unipolar offset error is defined as the deviation of the actual transition value from the ideal value. The unipolar offset temperature coefficient specifies the change of this transition value versus a change in ambient temperature. BIPOLAR OFFSET ERROR A/D converter specifications have historically defined bipolar offset as the first transition value above the minus full- scale value. The SDM specification, however, follows the terminology defined for the 574 converter several years ago. Thus, bipolar offset is located near the midscale value of 0V (bipolar zero) at the output code transition 7FFH to 800H. Bipolar offset error for the SDM is defined as the deviation of the actual transition value from the ideal transition value located 1/2LSB below 0V. The bipolar offset temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. FULL SCALE CALIBRATION ERROR The last output code transition (FFEH to FFFH) occurs for an analog input value 3/2LSB below the nominal full-scale value. The full-scale calibration error is the deviation of the actual analog value at the last transition point from the ideal value. The full-scale calibration temperature coefficient specifies the maximum change of the code transition value versus a change in ambient temperature. OPERATING INSTRUCTIONS OPERATING MODES The SDM can operate in one of two modes, namely serial and overlap, as shown in Figure 10. In serial mode, control of the device is such that a multiplexer channel X is first selected, time is then allowed for the instrumentation amplifier to settle, the sample/hold amplifier is set to HOLD mode and finally a conversion is carried out. This procedure is then repeated for channel Y. Faster throughput can be obtained using overlap mode. While a conversion is being SERIAL MODE Signal Acquisition Conversion MUX Selection (X) Time Instrumentation Amp Settling Sample/ Hold Acquisition A/D Conversion Data Valid MUX Selection (Y) OVERLAP MODE MUX Selection (X) Instrumentation Amp Settling Sample/ Hold Acquisition MUX Selection (Y) Instrumentation Amp Settling Sample/ Hold Acquisition MUX Selection (Z) Signal Acquisition Conversion Signal Acquisition A/D Conversion on Channel (X) Data Valid A/D Conversion on Channel (Y) Time FIGURE 10. Serial and Overlap Modes of Operation. ® 11 SDM862/863/872/873 carried out by the ADC on a voltage from channel X held on the sample/hold, channel Y is selected and the multiplexer and instrumentation amplifier allowed to settle. In this way, the total throughput time is limited only by the sum of the sample/hold acquisition time and the ADC conversion time. CALIBRATION – UNIPOLAR If adjustment of unipolar offset and gain are not required, then the gain set potentiometer in Figure 11 (Unipolar operation) may be replaced with a 50Ω, 1% metal film resistor, and the offset network replaced with a connection from pin 23 to ground. CALIBRATION - GENERAL The input voltage ranges of the ADC are 0-10V, ±5V and ±10V. Calibration in all ranges is achieved by adjusting the offset and gain potentiometers (indicated in Figures 11 and 12) such that the 000 to 001 code transition takes place at +1/2LSB from full-scale negative (–FS) and the FFE to FFF transition takes place at –3/2LSB from full-scale positive (+FS). The procedure is therefore to select the required range from Figure 13, apply the specified (–FS+1/2LSB) voltage to any selected input channel and adjust the offset potentiometer for the 000 to 001 transition. The (+FS–3/2LSB) voltage should then be applied to the same channel and the gain potentiometer adjusted for the FFE to FFF transition. The offset should always be made before the gain adjustment. SDM FULL-SCALE RANGE 21 22 23 24 26 0–10V ±5V ±10V 160Ω 100Ω (Gain) +0.0012V –4.9988V –9.9976V +9.9963V +4.9963V +9.9927V 2.44mV 2.44mV 4.88mV 000 TO 001 TRANSITION VOLT. FFE TO FFF 1LSB TRANSITION VOLT. EQUALS FIGURE 13. Code Transition Ranges. FFFH 20V Span 10V Span 100kΩ +15V FFEH FFDH Inputs Digital Output 100kΩ (Offset) 802H 801H 800H 7FFH 7FEH 002H 001H 000H 1/2LSB Zero (–Full Scale) (Bipolar Offset Transaction) Offset Error Shifts The Line Full-Scale Calibration Error Rotates The Line –15V FIGURE 11. Unipolar Calibration. CALIBRATION - BIPOLAR If adjustment of bipolar offset and gain are not required then the gain set and offset potentiometers in Figure 12 (Bipolar operation) may both be replaced with 50Ω, 1% metal film resistors. Midscale (Bipolar Zero) Zero 1/2LSB (–Full-Scale Calibration Transition) Analog Input 3/2LSB +Full +Full-Scale Scale Calibration Transition SDM FIGURE 14. SDM Transfer Characteristic Terminology. GROUNDING, DECOUPLING AND LAYOUT CONSIDERATIONS It should be noted that the multiplexer/instrumentation amplifier section and sample/hold plus ADC section of the SDM have separate power connections. This is to enable more flexible grounding techniques to be implemented, Figures 15, 16. It also facilitates the use of independent decoupling of the analog front-end power supply, and the ADC plus associated digital circuitry power supply if desired. In this way, a separately decoupled analog front-end can be made to be substantially more immune to power supply noise generated by the ADC circuitry than if the 21 22 23 24 26 100Ω (Gain) 100Ω (Offset) 20V Span 10V Span Inputs FIGURE 12. Bipolar Calibration. ® SDM862/863/872/873 12 power supplies to the two sections were directly connected. This feature is important where low-level signals are in use or high input signal noise immunity is desired. The output section has three grounds: Pin 25 Analog Common, A/D Converter Pin 34 S/H Amp Digital Input Reference Pin 19 Digital Common, A/D Converter The input section has one ground: Pin 53 Common for digital MUX-inputs and power supply decoupling. All grounds have to be interconnected externally to the SDM, and it is recommended that all grounds are connected via one track to a single point as close as possible to the SDM. To check that the grounding structure is correct, the ground tracking should be sketched and a grounding “tree” should result whereby all grounds route to a central point. In general, layout should be such that analog and digital tracks are separated as much as possible with coupling between analog and digital lines minimized by careful layout. For instance, if the lines must cross they should do so at right angles to each other. Parallel analog and digital lines should be separated from each other by a pattern connected to common. Signal-Ref (Single-Ended) Output-Ref SHC GND DCOM (1) DCOM (2) ACOM (2) +15V –15V 66 53 4 3 100µH 2 34 25 19 27 20 +5V +V –V 5 +5V –15V Signal-Ref (1) (1) 100µH +15V (1) (1) (1) NOTE: (1) 10µF tantalum in parallel with 100nF ceramic. FIGURE 15. Recommended Decoupling of Power Supplies. 1/2 SDM ISO100 INA 1 39 2 1/2 SDM –V 4 0 53 +V 3 –V 0 +V 0 +5V 20 25 27 19 5 100µH PWR305 100µH +5V 100µH 100µH 5V 100µH +5V MUX-Address MUX-Address 4 Opto-Couplers FIGURE 16. Galvanic Isolation Between Analog and Digital Signals. ® 13 SDM862/863/872/873 ® Analog-Ref R 100Ω 23 67 65 66 62 63 64 68 1 22 26 44.7nF 39 35 36 37 21 R 100Ω 24 MUX Ref Out Ref In Bip Off FIGURE 17. The SDM Connected to an Input/Output Port. Hold Cap S/H ADC In(10V) In(20V) D4 D5 D6 D7 14 13 12 11 LSB D0 D1 D2 D3 18 17 16 15 (Out) RG –In G10 G100 Sense Out INA Ref In VCC Status AGND DGND SHC Out Gnd Cont D8 D9 D10 MSB D11 +In VEE 54 55 56 57 58 59 60 61 Out A3 A2 EN A1 A0 DCOM 8(0) 9(1) 10(2) 11(3) 12(4) 13(5) 14(6) 15(7) CE R/C Data M. CS Byte S. +15V –15V +5V 28 29 30 31 32 C4 C5 C6 C7 53 48 49 50 51 52 4 3 33 34 2 6 25 19 27 20 5 +5V (12 Bit) A0 A1 A2 A3 A4 A5 A6 A7 +5V +15V –15V +5V 8255 Port SDM862/863/872/873 B0 B1 B2 B3 B4 B5 B6 B7 47 46 45 44 43 42 41 40 CH0 1 2 3 4 5 6 7 10 9 8 7 C0 C1 C2 C3 +5V 1kΩ 14 Fully Controlled Mode Stand Alone Mode .47nF 37 2122 26 24 23 23 R 50Ω R 50Ω 39 35 36 Ref Out Ref In 74244 ADC D0 D1 D2 D3 18 17 16 15 D0 D1 D2 D3 D0 D1 D2 D3 18 17 16 15 Bip Off Bip Off 74244 D0 D1 D2 D3 Hold Cap In S/H In (10V In (20V) 1G 2G D8 D9 D10 MSB D11 Status AGND DGND +15V –5V 1G 2G +5V D15 CS RD 6 25 19 74373 +15V (12 Bit) 27 20 5 5 D0 D1 D2 D3 D Q G OC D4 D5 D6 D7 CE R/C Data M. CS Byte S. 28 29 30 31 32 74244 D8 D9 D10 D11 10 9 8 7 D8 D9 D10 MSB D11 CE R/C Data M. CS Byte S. +5V D4 D5 D6 D7 10 9 8 7 28 29 30 31 32 14 13 12 11 D4 D5 D6 D7 D4 D5 D6 D7 14 13 12 11 74244 FIGURE 18. The SDM Connected to a 16-Bit-BUS. 1G 2G D4 D5 D6 D7 Out SHC Gnd Cont Status MUX S/H Cont A0 A1 A2 A3 MUX A0 A1 A2 A3 D Q G OC 74373 15 WR CS D8 D9 D10 D11 D15 1G 2G CS RD +15V (12 Bit) 34 33 D0 D1 D2 D3 D4 WR CS WR CS SDM862/863/872/873 ® 4.7nF 39 35 36 37 21 22 26 24 R 100Ω 23 R 100Ω Ref Out Ref In Bip Off D0 D1 D2 D3 18 17 16 15 ADC Hold Cap D4 D5 In S/H Out In (20V) D8 SHC Gnd Cont Status AGND DGND CE R/C DATAM. 28 29 30 WR RD D9 D10 MSB D11 10 9 8 7 D4 D5 D6 D7 Z80 In (10V) D6 D7 14 13 12 11 D0 D1 D2 D3 31 CS 32 Bytes +15V –15V +5V Address Decode 34 33 6 25 19 27 20 5 MUX A0 A1 A2 A3 74LS175 D0 D1 D2 D3 AO A1 – A7 IORQ Reset FIGURE 19a. SDM on the Z80 Interface. 4.7nF 39 35 36 37 21 22 26 24 R 100Ω 23 R 100Ω Ref Out Ref In Bip Off D0 D1 D2 D3 18 17 16 15 Data Bus SDM Status Pin 6 D4 D5 14 13 12 11 LS 374 LS 374 ADC Hold Cap In S/H Out In (10V) D6 D7 In (20V) D8 10 9 8 7 SDM Status SHC Gnd Cont Status AGND DGND D9 D10 MSB D11 Address Decode +5V 28 29 30 Address Bus 68000 CE R/C DATAM R/W 31 CS 32 Bytes +15V –15V +5V UDS LOS DTACK 34 33 6 25 19 27 20 5 FIGURE 19b. 68000/SDM Interface. ® SDM862/863/872/873 16 4.7nF 39 35 36 37 21 22 26 24 R 100Ω 23 R 100Ω Ref Out Ref In Bip Off D0 D1 D2 D3 18 17 16 15 ADC Hold Cap D4 D5 In S/H Out In (20V) D8 SHC Gnd Cont Status AGND DGND CE R/C DATAM 28 29 30 IOW IOR D9 D10 MSB D11 10 9 8 7 D4 D5 D6 D7 IBM PC or XT Card Slot In (10V) D6 D7 14 13 12 11 D0 D1 D2 D3 31 CS 32 Bytes +15V –15V +5V Adress Decode 34 33 6 25 19 27 20 5 MUX A0 A1 A2 A3 Reset D0 D1 D2 D3 AO A1 - A9 AEN FIGURE 19c. IBM PC SDM Interface. 4.7nF 39 35 36 37 21 22 26 24 R 100Ω 23 R 100Ω Ref Out Ref In Bip Off D0 D1 D2 D3 18 17 16 15 ADC Hold Cap 14 13 12 11 BUS D0 D1 D2 D3 D4 D5 In S/H Out In (10V) D6 D7 In (20V) D8 10 9 8 7 D4 D5 D6 D7 SHC GND Cont Status AGND DGND D9 D10 MSB D11 CE R/C DATAM 28 29 30 ø2 R/W 31 CS 32 Bytes +15V –15V +5V A0 34 33 6 25 19 27 20 5 8 Bit A4 Select A0 A1 A2 A3 74LS 175 D0 D1 D2 D3 Reset FIGURE 20. SDM on the 6502 BUS. ® 17 SDM862/863/872/873 CONTROLLING THE SDM The Burr-Brown SDM family can be easily interfaced to most microprocessor systems, as shown in Figures 17-20. The microprocessor may control each conversion, or the converter may operate in a stand-alone mode controlled only by the R/C input. STAND-ALONE OPERATION The stand-alone mode is used in systems containing dedicated input ports which do not require full bus interface capability. Control of the converter is accomplished by a single control line connected to R/C. In this mode CS and BYTE SELECT are connected to LOW and CE and DATA MODE are connected to HIGH. The output data are presented as 12-bit words. Conversion is initiated by a High-to-Low transition of R/C. The three-state data output buffers are enabled when R/C is high and STATUS is low. Thus, there are two possible modes of operation; conversion can be initiated with either positive or negative pulses. In each case the R/C pulse must remain low for a minimum of 50ns. Figure 21 illustrates timing when conversion is initiated by an R/C pulse which goes low and returns to the high state during the conversion. In this case, the three-state outputs go to the high-impedance state in response to the falling edge of R/C and are enabled for external access of the data after completion of the conversion. Figure 22 illustrates the timing when conversion is initiated by a positive R/C pulse. In this mode the output data from the previous conversion is enabled during the positive portion of R/C. A new conversion is started on the falling edge of R/C, and the three-state outputs return to the high impedance state until the next occurrence of a high R/C pulse. Table I lists timing specifications for stand-alone operation. FULLY CONTROLLED OPERATION Conversion Length Conversion length (8-bit or 12-bit) is determined by the state of the BYTE SELECT input, which is latched upon receipt of a conversion start transition. BYTE SELECT is latched because it is also involved in enabling the output buffers. No other control inputs are latched. If BYTE SELECT is latched high, the conversion continues for 8 bits. The full 12-bit conversion will occur if BYTE SELECT is low. If all 12 bits are read following an 8-bit conversion, the 3LSBs (DB0DB2) will be low (logic 0) and DB3 will be high (logic 1). SYMBOL tHRL tDS tHDR tHS 86X tHS 87X tHRH tDDR PARAMETER Low R/C Pulse Width STS Delay from R/C Data Valid After R/C Low STS Delay After Data Valid High R/C Pulse Width Data Access Time MIN 50 TYP MAX UNITS ns ns ns ns ns ns ns 200 25 300 100 150 500 300 1000 600 150 TABLE I. Stand-Alone Mode Timing. R/C tHRL tDS Status tHDR DB11–DB0 Data Valid High-Z State tC tHS Data Valid FIGURE 21. R/C Pulse Low—Outputs Enabled After Conversion. R/C tHRH tDS Status tDDR DB11– High-Z DB0 tHDR Data Valid tC High-Z State FIGURE 22. R/C Pulse High—Outputs Enabled Only Where R/C is High. Conversion Start A conversion is initiated by a transition on any of three logic inputs (CE, CS, and R/C)—refer to Figure 9. The last of the three to reach the required state start the conversion and thus all three may be dynamically controlled. If necessary, they may change state simultaneously, and the nominal delay time is independent of which input actually starts the conversion. If it is desired that a particular input establish the actual start of conversion, the other two should be stable a minimum of 50ns prior to the transition of that input. Timing relationships for start of conversion timing are illustrated in Conversion Cycle Timing of the Digital Specifications. Word 1 Processor SDM DB7 DB11 DB6 DB10 DB5 DB9 DB4 DB8 DB3 DB7 DB2 DB6 DB1 DB5 DB0 DB4 DB7 DB3 DB6 DB2 Word 2 DB5 DB1 DB4 DB0 DB3 0 DB2 0 DB1 0 DB0 0 FIGURE 23. 12-Bit Data Format for 8-Bit Systems (connected as Figures 18 and 19). ® SDM862/863/872/873 18 The STATUS output indicates the state of the converter by being high only during a conversion. During this time the three-state output buffers remain in a high-impedance state, and therefore, data is not valid. During this period additional transitions of the three control inputs will be ignored, so that conversion cannot be prematurely terminated or restarted. However, if BYTE SELECT changes state after the beginning of conversion, any additional start conversion transition will latch the new state of BYTE SELECT, possibly resulting in an incorrect conversion length (8 bit versus 12 bits) for that conversion. READING OUTPUT DATA After conversion is initiated, the output data buffers remain in a high-impedance state until the following four conditions are met: R/C high, STATUS low, CE high, and CS low. In this condition the data lines are enabled according to the state of the inputs DATA MODE and BYTE SELECT. See Read Cycle Timing for timing relationships and specification. In most applications the DATA MODE input will be hardwired in either the high or low condition, although it is fully TTL- and CMOS-compatible and may be actively driven if desired. When DATA MODE is high, all 12 outputs lines (DB0-DB11 ) are enabled simultaneously for full data word transfer to a 12-bit or 16-bit bus and the state of the BYTE SELECT is ignored. When DATA MODE is low, the data is presented in the form of two 8-bit bytes, with selection of each byte by the state of BYTE SELECT during the read cycle. The BYTE SELECT input is usually driven by the least significant bit of the address bus, allowing storage of the output data word in two consecutive memory locations. When BYTE SELECT is low, the byte addressed contains the 8MSBs. When BYTE SELECT is high, the byte addressed contains the 4LSBs from the conversion followed by four zeros that have been forced by the control logic. The left-justified formats of the two 8-bit bytes are shown in Figure 23. The design of the SDM guarantees that the BYTE SELECT input may be toggled at any time without damage to the output buffers occurring. In the majority of applications, the read operation will be attempted only after the conversion is complete and the status output has gone low. In those situations requiring the fastest possible access to the data, the read may be started as much as (tDD max + tHS max) before STATUS goes low. Refer to Read Cycle Timing for these timing relationships. 1. DIRECT SURFACE MOUNT ONTO PCB ADVANTAGES Ease of assembly Low cost Low weight Small footprint size DISADVANTAGES Difficult to inspect solder joints Difficult to clean Choice of board material important in wide temperature range applications In wide temperature applications it is important to match the coefficients of thermal expansion of the board and the SDM8XXL. Below is a list of materials and their approximate coefficients of linear thermal expansion. MATERIAL Alumina (96%) - SDM Package Copper-clad-Invar (50% Cu) (30% Cu) (10% Cu) Epoxy-Kevlar (60% Kevlar) Polyimide-Kevlar (40% Kevlar) Beryllia Polyimide-glass (x-axis) (y-axis) Kevlar™ E.I. du Pont de Nemours & Co. (ppm/°C) 6-7 9 6 3 6 6 5 12 14 2. ATTACHMENT OF SURFACE MOUNT EDGE CLIPS ADVANTAGES Ease of Inspection Easy cleaning Thermal expansion taken up by the flexing of the edge clips DISADVANTAGES Extra cost Extra assembly ASSEMBLY The edge clips are attached to the edges of the SDM8XXL as in Figure 24 before the device is mounted on to the board. SDM EDGE CLIP FIGURE 24. Edge Clip Assembly. SUPPLIERS OF EDGE CLIPS USA DIE-TECH INC., R.D. 1, Sipe Road, York Haven, PA 17370 USA PHONE: (717) 938-6771 EUROPE SEMI-DICE (UK) Ltd, Buckingham House, Mineral Lane, Chesham, Bucks. HP5 2AU UK PHONE: 0494 771275 USA NAS Electronics, 381 Park St., Hackensack, NJ 07602 USA PHONE: (201) 343-3156 EUROPE NASBRIT Ltd, Wester Goudi Ind. Est. Dundee DD2 4UX UK PHONE: 0382 622222 APPLICATIONS INFORMATION ASSEMBLY OF SURFACE MOUNT PACKAGES There are several assembly methods for the LCC versions of the SDM8XX. The associated advantages and disadvantages of three methods are outlined below. ® 19 SDM862/863/872/873 3. SURFACE MOUNT SOCKET ADVANTAGES Board thermal expansion not so critical Ease of component replacement DISADVANTAGES Cost Extra height (if critical) However, in following the application guidelines illustrated by the circuitry and accompanying notes, the designer will be able to select and adapt the solutions most suited to their won particular application or problem area. Provisions for the following are made on the LCC PC board: —68 pin LCC socket (Burr-Brown Part No. MC0068). —8 differential or 16 single-ended inputs. —Input filtering with overvoltage protection for each channel. —Socket for quad D-type flip-flop 74175 (MUX address latches). —7 additional I.C. sockets for easy interfacing to various BUS systems (connection by wire wrap techniques). —2 voltage regulators (15V). —LC power supply decoupling. The layout pays particular attention to the requirements when operating with precision analog signals. This requires strict separation of the analog and digital areas. Analog and digital commons are totally separated and connected together only at the commons of the supply voltage. All common lines are low resistance and low inductance. SUPPLY VOLTAGES In order to avoid coupling between the external supply voltage 15V supplies, 2 voltage regulators (78M15, 79L15) are provided on the PC board. The unregulated supply voltage may vary from ±17V to ±25V. The MUX/INA section and SHC/ADC section of the SDM have separate supply lines which can be inductively decoupled. This is recommended in order to suppress the high frequency noise which comes from the ADC during conversion. The power supply rejection of the instrumentation amplifier reduces with increasing frequency. If high frequency noise on the supplies is not decoupled it will be injected into the signal path and cause errors. This effect can be particularly pronounced when using the ‘overlap’ mode since the instru- Below is the name and address of a supplier of a 68-pin surface mountable socket. The part number is: Socket Spring cover USA Methode Electronics INC, Interconnect Products Div. 1700 Hick Road, Rolling Meadows, TX 75050 USA PHONE: (312) 392-3500 212-068-012 CCS-004 EUROPE Lucas Methode Connectors Ltd, Halifax Road Ingrow Bridge, Keighley, Yorkshire BD21 5HR UK PHONE: 0535 603282 General Comments The advantages and disadvantages of all the methods mentioned above are for general use of surface mount components. Every user will find that the importance of these factors will depend on his application and situation. EVALUATION BOARD For the engineer who wishes to evaluate the SDM family, Burr-Brown has designed printed circuit boards on a single ‘Eurocard’ (shown here for LCC only). These boards enable the design engineer to experiment with various accuracy improvement techniques which are described below. Special consideration has been given to the grounding and circuit layout techniques required when dealing with 12-bit analog signals. The printed circuit board has been designed so that the solutions to several of the problems likely to be encountered by the user can be examined. It should not be thought that every user is required to adopt all of the techniques used on the circuit board. In many applications very few external components will be required. SDM862/872 SDM863/873 Channel Pair Selected NONE 0 1 2 3 4 5 6 7 MUX ADD3 X L L L L L L L L H H H H H H H H MUX ADD2 X L L L L H H H H L L L L H H H H MUX ADD1 X L L H H L L H H L L H H L L H H MUX ADD0 X L H L H L H L H L H L H L H L H MUX Enable L H H H H H H H H H H H H H H H H Channel Selected NONE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MUX ADD2 X L L L L H H H H MUX ADD1 X L L H H L L H H MUX ADD0 X L H L H L H L H – – – – – – – – MUX Enable L H H H H H H H H FIGURE 25. Channel Select Truth Table. ® SDM862/863/872/873 20 mentation amplifier is settling to a new analog value while the ADC is still carrying out the previous conversion. The digital supply voltage is +5V and is also LC-filtered. All supply lines are bypassed with a 10µF tantalum and a 100nF ceramic capacitor situated as close as possible to the package. If the voltage regulators for the ±15V are not used, small inductors for decoupling of the supply voltages are recommended. If inductors are not fitted a dynamic ground loop will be created from supply lines via bypass capacitors to analog common. INPUT PROTECTION The multiplexer is protected up to an input voltage which can exceed the supply voltage by a maximum of 20V. This means, that with ±15V supply voltage, the input voltage can be ±35V without damage. This is also the case when the supply voltages are switched off (0V). The maximum input voltage can then be ±20V. For higher overvoltage protection a series resistor has to be used. The current via the multiplexer should be limited to 20mA absolute maximum, 1mA is preferred. For example, a 10kΩ series resistor would give an additional 10V overprotection. For much higher overvoltages (e.g. 100V), high value series resistors cannot be used as offset errors would result. In practice, a combination of series resistors and diodes is used. The diodes are connected to ±15V and will conduct whenever the input voltage exceeds the ±15V supply voltage. The diodes are selected by signal source impedance, as well as filter resistance, as the diode leakage current across the series resistor can cause offset and linearity errors. In this circuit, IN4148 together with 10kΩ are used. INPUT FILTER Processor noise can be induced in the analog ground. Input filtering is therefore recommended for analog data acquisition. Such high frequency noise signals can cause dynamic overload of the instrumentation amplifier resulting in nonlinear behavior. This leads directly to digitizing errors. The design of the filter takes into account the characteristics of the SDM and of the signal source. The following points have to be considered: —The stray capacitance, output capacitance of the multiplexer and input capacitance of the instrument amplifier (up to 80pf in some cases) has to be discharged in order to minimize errors caused by ‘charge sharing.’ —The series resistor limits the current in the protection diodes, but it also has to be selected for the required filter time constant. —The noise rejection of the filter has to be >80db in order to satisfy a 12-bit A/D conversion. As well as considering the above, different calculations have to be carried out for single and differential input signals. Analog In Rf Cg Mux Cm INA FIGURE 26. Single-Ended Measurement Rf limits the maximum input current through the protection diodes. In this case, Rf has been chosen as 10kΩ and together with the capacitor Cg, forms the input filter time constant (Cg = 0.47µF). The time constant must be chosen according to the requirements of the input signal bandwidth and noise rejection. The multiplexer capacitance (Cm) is discharged mainly by Cg. This means Cg has to be sufficiently large compared with Cm or charged via Rf prior to resampling of the signal. Analog In Rf Analog In Rf Cf Cg Mux Cm INA Cg FIGURE 27. Differential Measurement Capacitor Cf, is used for limiting the input signal frequency. The bandwidth is calculated as follows: 1 Ff = 4π R C IF Cf > > Cg ff When selecting the value of Cf, it should be noted that Cm has to be discharged when switching the multiplexer channels. This means that the voltage error of Cf (induced by ‘charge sharing’ with Cm) has to be smaller than 1LSB. Therefore, Cf should have a minimum value of a 0.47µF. The resistors Rf, together with the source impedance, have to be sufficiently small in order to recharge Cf prior to signal sampling. This prevents errors in the signal value caused by the charge stored on Cm by the previously selected channel. The 2 capacitors Cg form together with Rf a common-mode filter. This filter greatly improves accuracy in a noisy environment (decrease of common-mode rejection of instrumentation amplifier with increasing frequency). For good common-mode filter operation, both time constants Rf and Cg should match each other within 2%. Additional errors will be induced by a mismatch. Selected values are: Cf = 0.47µF, Cg = 10nF, Rf = 10kΩ. The filter reduces the signal slew rate so that the instrumentation amplifier can follow the voltage variation of the signal with the noise component eliminated. In general, all measurements which require more than a gain of 10 should be done in differential mode. Single ended ® 21 SDM862/863/872/873 measurements should be limited to applications where current sources are measured via shunts or where signal voltages in the range of some volts are available. Bus-Interface As the outputs of the SDM are BUS compatible, only a few ICs are necessary to interface to various BUS systems. For such interfacing, 20-pin IC sockets are provided. Wiring is by wire wrap to the BUS connector. Setting of Various Modes Circuit Board positions are provided for the connection of ‘jumpers’ as follows: J1, J2—ADC analog input volt age settings. J3—Set for differential (SDM8X3) or single ended (SMD8X2) operation. J4—Instrumentation amplifier gain settings. (a) 16 input channels, single ended: —Use SDM8X2 —Consider single-ended filtering —Connect J3 (pin 66) to common (b) Differential inputs —Use SDM8X3 —Consider differential filtering —Connect J3 (pin 66) to pin 67 (c) Analog input ±10V Connect J1 to pin 21 Connect J2 to pot P2 (100Ω) ±5V Connect J1 to pin 22 Connect J2 to pot P2 (100Ω) 0 to +10V: Connect J1 to pin 22 Connect J2 to junction of R1/R2 (d) Gain of instrumentation amplifier G=1 Jumper J4 open G = 10 Jumper J4 to pin 63 G = 100 Jumper J4 to pin 64 Other gains: use additional resistor between pin 62 and pin 63 (see section on Instrumentation Amplifier) as low tempco resistor is recommended in order to minimize gain drift. ® SDM862/863/872/873 22 INPUT FILTER AND PROTECTION CIRCUITRY SINGLE-ENDED 26-Pin Connector Channel Numbers 0 14 15 Rf R3 10k Ω 1 19 R4 2 23 R5 3 11 R6 4 7 R7 5 3 R8 6 4 R9 7 10 R10 8 17 R11 9 21 R12 10 25 R13 11 13 R14 12 9 R15 13 5 R16 14 6 R17 15 12 R18 D31D32 C16 C15 R9 61 6 6 10 R10 7 12 R18 Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common Pins 1, 2, 8, 14, 16, 18, 20, 22, 24 and 26 are Connected to Common 61 R17 60 40 5 60 4 59 5 R16 59 41 58 57 9 3 R8 R15 58 42 56 4 55 13 7 R7 R14 57 43 D15D16 C8 54 3 40 41 2 25 11 R6 R13 56 44 42 43 21 23 R5 55 45 44 1 D3 D4 D1 D2 C2 45 17 19 R11 C9 54 46 +15V –15V SDM Pins Cg C1 46 47 0.47µF 0 Channel Numbers DIFFERENTIAL 26-Pin Connector 14 Rf +15V 15 1% R3 10k Ω C17 0.47µF Cf –15V Cg SDM Pins 47 C1 10nF 1% ® 23 SDM862/863/872/873 D21 D33 D34 D22 PCB COMPONENT LAYOUT D6 D5 C R5 AAA C30 + B E C33 B B B + IC1 +5V C27 C29 L1 79 D19 10 G 100 INAMUXA0 A2 A1 A3 CL + J3 SDM Pin Out For LCC Socket S/H S/H OUT IN –V B + B C31 C32 J4 D4 D3 RG AA D20 R12 C18 C10 C2 R4 D18 D17 R11 C17 C9 D2 D1 C1 R3 C36 + D24 D23 R14 C20 C D8 D7 C25 C4 R6 D25 R18 R9 R17 C21 C13 P1 J2 BIP P2 C5 D9 D10 R7 C23 R16 R2 R1 UNI D26 C15 C7 C15 20V J1 + C38 10V P3 L3 C39 + C40 IC6 C12 C28 B R10 C8 C16 C24 S/H BS CS DM R/C CE 33 32 31 30 29 28 C6C14 C22 IC4 D16 D32 D15 D31 D14 D30 D13 D29 D12 D28 D11 D27 IC7 C42 C41 SDM862/863/872/873 R13 C11 E B B +V B A C3 C19 C26 B C34 LCC Package 74/75 78 D A A A A A A AA A A A A A A L2 C35 IC2 IC3 C37 A A A A A A A A A A A ST 11 10 9 8 7 6 5 4 3 2 1 0 A A AA A A A A AAAAAAAAA AA AA A AA AA AA AA A AA A A A A A A A AA A A A A A A AA D IC5 ® 24 NOTE: (1) NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 (2) NOT DRAWN TO SCALE R8 ©Burr-Brown Ltd 1989 PC862/863-1 REV B P.C.B. LAYOUT NOTE: NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 NOTE: NOT SUITABLE FOR PGA PACKAGE SEE PC862/863-2 ® 25 SDM862/863/872/873 CIRCUIT DIAGRAM—SDM PC BOARD C34 C33 +V +5V C28 78 L3 L2 79 –V P3 R1 J2 +15V –15V D11 CS +15V D0 P2 BS Data M 23 ADC C31 C32 Status P1 CE 24 + In In 10V 20V RC 26 L1 J1 22 C36 5 35 37 21 In Out SH CH 33 SHC/COM 34 100µH L1 6 29 28 31 27 –15V 20 18 17 16 15 14 13 12 11 10 30 32 R2 19 3 4 9 8 7 J1, J2 = ±10V J3 = 8 Diff Inputs J4 = (G = 10) 1 39 2 62 63 64 68 G100 Out RG RG G10 1kΩ INA +5V 36 C25 INX– IN+ +5V 4700pF C35 + 67 65 66 52 16 C26 Ref 8 74175 91 A2 12 4 A1 = Wirewrap Posts C40 C38 + C30 DCOM ACOM C39 C37 C27 + C29 + A3 A2 15 14 Out– 13 12 11 10 9 8 MUX 7 6 5 Out+ 4 3 DCOM ACOM EN A0 A1 13 15 210 7 50 51 25 49 2 1 0 53 48 A0 61 60 59 58 57 56 55 54 40 41 42 43 44 P.C.B. COMPONENTS PARTS LIST R1 R2 R3...R18 C1...C16 C17...C24 C25 100Ω For 0–10V Settling 100kΩ 10kΩ 1% 0.47µF—Single Ended Input Mode 10nF 1%—Differential Input Mode 0.47µF—Differential Input Mode 4.700pF (Polypropylene, Polystyrene or TeflonTM) C26 C27, C29, C35 C32, C38, C39 C28, C30, C31 C36, C37, C40 C33, C34 P1 P2 10nF Ceramic 10µF Tantalum (Decoupling) 100nF Ceramic (Decoupling) 0.33µF Tantalum 100Ω 100Ω ±5V, ±10V Range Only P3 L1...L3 D1...D32 D33, D34 78 79 74175 LCC Socket 100kΩ 0–10V Range Only 100µH (Decoupling) 1N4148 (Input Protection Diodes) 1N4007 MC78M15CG MC79L15CG 74LS175 MC0068 UNLESS OTHERWISE MARKED—RESISTORS ARE 1/4W, 5%, CAPACITORS ARE 10% Teflon™ E.I. du Pont de Nemours & Co. ® SDM862/863/872/873 26 45 46 47 +5V A3 5 CL +5V J3 Sense Ref Out Bip Off Ref In MECHANICAL (P.G.A.) Package Number 906 TOP VIEW A 1 2 67 68 3 5 7 9 11 13 15 17 18 20 19 22 21 24 23 26 25 28 27 30 29 32 31 65 66 63 64 Bottom VIEW 61 62 59 60 57 58 55 56 53 54 52 51 49 47 45 43 41 39 37 34 33 50 48 46 44 42 40 38 36 35 B Pin 1 Identifier 4 6 8 10 12 14 16 DIM A B C D E F G H J INCHES MIN MAX 1.087 1.109 1.087 1.109 .095 .120 .162 .198 .045 .055 .045 .055 .016 .020 .100 BASIC .100 BASIC MILLIMETERS MIN MAX 27.610 28.169 27.610 28.169 2.413 3.048 4.115 5.029 1.143 1.397 1.143 1.397 .406 .508 2.540 BASIC 2.540 BASIC E J C NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. Numbers may not be marked on package. TERMINATION: Gold plated KOVAR. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 9 grms (0.32 oz) H D F G MECHANICAL (L.C.C.) Package Number 907 — TOP VIEW A D F Pin 1 Identification 67 66 68 1 2 3 L G EB JH DIM A B C D E F G H J K L INCHES MIN MAX .945 .965 .945 .965 .076 .094 .841 .859 .841 .859 .755 .785 .755 .785 .800 BASIC .027 .033 .045 BASIC .050 BASIC MILLIMETERS MIN MAX 24.003 24.511 24.003 24.511 1.934 2.388 21.361 21.819 21.361 21.819 19.177 19.939 19.177 19.939 20.320 BASIC .686 .838 1.143 BASIC 1.270 BASIC NOTE: Leads in true position within 0.01" (0.25mm) R at MMC at seating plane. Pin numbers shown for reference only. TERMINATION: Gold plated nickel on refractory metallization. CASE: Ceramic with gold plated nickel lid. HERMETICITY: Gross leak test. WEIGHT: 4.37 grms (0.124 oz) K C ® 27 SDM862/863/872/873