SG3524DR

SG2524, SG3524 SG2524, SG3524 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 www.ti.com SGx524 Regulating Pulse-Width Modulators 1 Features 3 Description • The SG2524 and SG3524 devices incorporate all the functions required in the construction of a regulating power supply, inverter, or switching regulator on a single chip. They also can be used as the control element for high-power-output applications. The SG2524 and SG3524 were designed for switching regulators of either polarity, transformer-coupled dcto-dc converters, transformerless voltage doublers, and polarity-converter applications employing fixedfrequency, pulse-width modulation (PWM) techniques. The complementary output allows either single-ended or push-pull application. Each device includes an onchip regulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted pass transistors, a high-gain comparator, and currentlimiting and shutdown circuitry. • • Complete Pulse-Width Modulation (PWM) powercontrol circuitry Uncommitted outputs for single-ended or push-pull applications 8-mA (TYP) standby current 2 Applications • • Transformer-coupled DC/DC convertors Switching-regulators of any polarity Device Information PART NUMBER SGx524 PACKAGE (PIN) BODY SIZE (NOM) SOIC (16) 9.90 mm × 3.91 mm PDIP (16) 9.90 mm × 6.35 mm NS (16) 10.30 mm × 5.30 mm Typical Application Schematic An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. 1 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configurations and Functions.................................2 Pin Functions.................................................................... 2 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 7 ...........................................................................................5 7.1 Electrical Characteristics.............................................5 7.2 Electrical Characteristics — Continued, Both Parts....6 7.3 Typical Characteristics................................................ 7 8 Parameter Measurement Information............................ 8 8.1 .................................................................................... 8 9 Detailed Description........................................................9 9.1 Overview..................................................................... 9 9.2 Functional Block Diagram........................................... 9 9.3 Feature Description...................................................10 9.4 Device Functional Modes..........................................11 10 Layout...........................................................................19 10.1 Layout Guidelines................................................... 19 10.2 Layout Example...................................................... 20 11 Device and Documentation Support..........................21 11.1 Related Links.......................................................... 21 11.2 Trademarks............................................................. 21 4 Revision History Changes from Revision E (January 2015) to Revision F (February 2021) Page • Updated text....................................................................................................................................................... 6 Changes from Revision D (February 2003) to Revision E (January 2015) Page • Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1 • Deleted Ordering Information table.....................................................................................................................1 5 Pin Configurations and Functions Pin Functions PIN 2 TYPE DESCRIPTION NAME NO. COL 1 12 O Collector terminal of BJT output 1 COL 2 13 O Collector terminal of BJT output 2 COMP 9 I/O Error amplifier compensation pin CT 7 — Capacitor terminal used to set oscillator frequency CURR LIM+ 4 I Positive current limiting amplifier input CURR LIM- 5 I Negative current limiting amplifier input Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 PIN NAME NO. TYPE DESCRIPTION EMIT 1 11 O Emitter terminal of BJT output 1 EMIT 2 14 O Emitter terminal of BJT output 2 GND 8 — Ground IN+ 2 I Positive error amplifier input IN- 1 I Positive error amplifier input OSC OUT 3 O Oscillator Output REF OUT 16 O Reference regulator output RT 6 — Resistor terminal used to set oscillator frequency SHUTDOWN 10 I VCC 15 — Copyright © 2021 Texas Instruments Incorporated Device shutdown Positive supply Submit Document Feedback 3 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN VCC Supply voltage ICC Collector output current IO(ref) Reference output current Current through CT terminal TJ Maximum junction temperature Tstg Storage temperature range MAX V 100 mA 50 mA –5 mA Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) UNIT 40 –65 150 °C 260 °C 150 °C Stresses beyond those listed under Section 6.1 table may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 table are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 1000 Charged device model (CDM), per JEDEC specification JESD22C101, all pins(2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC MIN MAX Supply Voltage 8 40 V Reference output current 0 50 mA –0.03 –2 mA 1.8 100 kΩ µF Current through CT terminal RT Timing resistor CT Timing capacitor TA Operating free-air temperature 0.001 0.1 SG2524 –25 85 SG3524 0 70 UNIT °C 6.4 Thermal Information SGx524 THERMAL METRIC(1) D N NS UNIT 64 °C/W 16 PINS RθJA (1) (2) (3) 4 Junction-to-ambient thermal resistance(2) (3) 73 67 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operation at the absolute maximum TJ of 150°C can impact reliability. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 7 7.1 Electrical Characteristics over operating free-air temperature range, VCC = 20 V, f = 20 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS(2) SG2524 MIN SG3524 TYP(2) MAX MIN 4.6 UNIT TYP(1) MAX 5 5.4 V 10 30 mV Reference section Output voltage 5 5.2 Input Regulation VCC = 8 V to 40 V 4.8 10 20 Ripple rejection f = 120 Hz 66 Output regulation IO = 0 mA to 20 mA Output voltage change with temperature TA = MIN to MAX Short-circuit output current(3) Vref = 0 100 66 dB 20 50 20 50 0.3% 1% 0.3% 1% 100 mV mA Error Amplifier section VIO Input offset voltage VIC = 2.5 V 0.5 5 2 10 mV IIB Input bias current VIC = 2.5 V 2 10 2 10 µA Open-loop voltage amplification VICR Common-monde input voltage range CMMR Common-mode rejection ratio B1 Unity-gain bandwidth Output swing (1) (2) (3) 72 TA = 25°C TA = 25°C 80 60 1.8 to 3.4 0.5 80 dB 1.8 to 3.4 V 70 70 dB 3 3 MHz 3.8 0.5 3.8 V All typical values, except for temperature coefficients, are at TA = 25°C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. Standard deviation is a measure of the statistical distribution about the mean, as derived from the formula: 2 N å( xn - x s= ) n -1 N -1 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 7.2 Electrical Characteristics — Continued, Both Parts over operating free-air temperature range, VCC = 20 V, f = 20 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS(2) MIN TYP(1) MAX UNIT Oscillator section fOSC ΔfOSC tW Oscillator frequency CT = 0.001 μF, RT = 2 kΩ Standard deviation of frequency(3) All values of voltage, temperature, resistance, and capacitance constant 450 kHz Frequency change with voltage VCC = 8 V to 40 V, TA = 25°C 1% Frequency change with temperature TA = MIN to MAX 2% Output amplitude at OSC OUT TA = 25°C 3.5 V Output pulse duration (width) at OSC OUT CT = 0.01 μF, TA = 25°C 0.5 µs 5 — — Output section V(BR)CE Collector-emitter breakdown voltage Collector off-state current 40 VCE = 40 V Vsat Collector-emitter saturation voltage IC = 50 mA VO Emitter output voltage VC = 20 V, IE = –250 μA tr Turn-off voltage rise time tf Turn-on voltage fall time 17 V 0.01 50 1 2 µA V 18 V RC = 2 kΩ 0.2 µs RC = 2 kΩ 0.1 µs Comparator section Maximum duty cycle, each output VIT Input threshold voltage at COMP IIB Input bias current 45% Zero duty cycle 1 Maximum duty cycle V 3.5 –1 µA Current limiting section VI Input voltage range V(SENSE) Sense voltage at TA = 25°C Temperature coefficient of sense voltage –1 V(IN+)–V(IN–) ≥ 50 mV V(COMP) 2 V 175 1 200 225 0.2 V mV mV/°C Total Device Ist 6 Standby current Submit Document Feedback VCC = 40 V, IN–, CURR LIM+, CT, GND, COMP, EMIT 1, EMIT 2 grounded, IN+ at 2 V, All other inputs and outputs open 8 10 mA Copyright © 2021 Texas Instruments Incorporated www.ti.com SG2524, SG3524 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 7.3 Typical Characteristics Figure 7-1. Open-Loop Voltage Amplification of Error Amplifier vs Frequency Copyright © 2021 Texas Instruments Incorporated Figure 7-2. Oscillator Frequency vs Timing Resistance Submit Document Feedback 7 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 8 Parameter Measurement Information 8.1 Figure 8-1. General Test Circuit Figure 8-2. Switching Times 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com SG2524, SG3524 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 9 Detailed Description 9.1 Overview SGx524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulator operates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT establishes a constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator, providing linear control of the output pulse duration (width) by the error amplifier. The SGx524 contains an onboard 5-V regulator that serves as a reference, as well as supplying the SGx524 internal regulator control circuitry. The internal reference voltage is divided externally by a resistor ladder network to provide a reference within the common-mode range of the error amplifier as shown in Figure 10-5, or an external reference can be used. The output is sensed by a second resistor divider network and the error signal is amplified. This voltage is then compared to the linear voltage ramp at CT. The resulting modulated pulse out of the high-gain comparator then is steered to the appropriate output pass transistor (Q1 or Q2) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to ensure both outputs are never on simultaneously during the transition times. The duration of the blanking pulse is controlled by the value of CT. The outputs may be applied in a push-pull configuration in which their frequency is one-half that of the base oscillator, or paralleled for single-ended applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common input to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from either of these inputs. This common point is pinned out externally via the COMP pin, which can be employed to either control the gain of the error amplifier or to compensate it. In addition, the COMP pin can be used to provide additional control to the regulator. 9.2 Functional Block Diagram A. Resistor values shown are nominal. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 9.3 Feature Description 9.3.1 Blanking The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is controlled by the value of CT as shown in Figure 7-2. If small values of CT are required, the oscillator output pulse duration can be maintained by applying a shunt capacitance from OSC OUT to ground. 9.3.2 Error Amplifier The error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The compensation node (COMP) is a high-impedance node (RL = 5 MΩ). The gain of the amplifier is AV = (0.002 Ω–1)RL and easily can be reduced from a nominal 10,000 by an external shunt resistance from COMP to ground. Refer to Figure 7-1 for data. 9.3.3 Compensation COMP, as previously discussed, is made available for compensation. Since most output filters introduce one or more additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier, introduction of a zero to cancel one of the output filter poles is desirable. This can be accomplished best with a series RC circuit from COMP to ground in the range of 50 kΩ and 0.001 μF. Other frequencies can be canceled by use of the formula f ≈ 1/RC. 9.3.4 Output Circuitry SGx524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA for fast response. 9.3.5 Current Limiting A current-limiting sense amplifier is provided in the SGx524 device. The current-limiting sense amplifier exhibits a threshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range of the inputs is limited to 1 V to –1 V. Caution should be taken to ensure the –1-V limit is not exceeded by either input, otherwise, damage to the device may result. Foldback current limiting can be provided with the network shown in Figure 9-1. The current-limit schematic is shown in Figure 9-2. VOR2 ö æ ç 200 mV + ÷ R1 + R2 ø è 200 mV = RS IO(max) = IOS 1 RS Figure 9-1. Foldback Current Limiting for Shorted Output Conditions 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com SG2524, SG3524 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 Figure 9-2. Current-Limit Schematic 9.4 Device Functional Modes 9.4.1 Synchronous Operation When an external clock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator output terminal. The impedance to ground at this point is approximately 2 kΩ. In this configuration, RTCT must be selected for a clock period slightly greater than that of the external clock. If two or more SGx524 regulators are operated synchronously, all oscillator output terminals must be tied together. The oscillator programmed for the minimum clock period is the master from which all the other SGx524s operate. In this application, the CTRT values of the slaved regulators must be set for a period approximately 10% longer than that of the master regulator. In addition, CT (master) = 2 CT (slave) to ensure that the master output pulse, which occurs first, has a longer pulse duration and, subsequently, resets the slave regulators. 9.4.2 Shutdown Circuitry COMP also can be employed to introduce external control of the SGx524. Any circuit that can sink 200 μA can pull the compensation terminal to ground and, thus, disable the SGx524. In addition to constant-current limiting, CURR LIM+ and CURR LIM– also can be used in transformer-coupled circuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LIM– also can be grounded to convert CURR LIM+ into an additional shutdown terminal. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information There are a wide variety of output configurations possible when considering the application of the SG2524 as a voltage-regulator control circuit. They can be segregated into three basic categories: • • • Capacitor-diode-coupled voltage multipliers Inductor-capacitor-implemented single-ended circuits Transformer-coupled circuits Examples of these categories are shown in Figure 10-1, Figure 10-2, and Figure 10-3, respectively. Section 10.2 demonstrates how to set up the SG2524 for a capacitor-diode output design. The same techniques for setting up the internal circuitry of the IC may also be used for the other two output stage examples shown Section 10.3. Figure 10-1. Capacitor-Diode-Coupled Voltage-Multiplier Output Stages 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 Figure 10-2. Single-Ended Inductor Circuit Figure 10-3. Transformer-Coupled Outputs Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 10.2 Typical Application 10.2.1 Capacitor-Diode Output Figure 10-4. Capacitor-Diode Output Circuit Schematic 10.2.1.1 Design Requirements • • 15-V supply voltage –5-V output voltage 10.2.1.2 Detailed Design Procedure 10.2.1.2.1 Oscillator The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 10-6. f» 1.30 R T RC (1) where • • • RT is in kΩ CT is in μF f is in kHz Practical values of CT fall between 0.001 μF and 0.1 μF. Practical values of RT fall between 1.8 kΩ and 100 kΩ. This results in a frequency range typically from 130 Hz to 722 kHz. 10.2.1.2.2 Voltage Reference The 5-V internal reference can be employed by use of an external resistor divider network to establish a reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 10-5), or an external reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal reference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In this configuration, however, the input voltage is limited to a maximum of 6 V. 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 VO = 2.5 V R1 + R2 R1 æ R2 ö VO = 2.5 V ç 1 R1 ÷ø è Figure 10-5. Error-Amplifier Bias Circuits 10.2.1.3 Application Curves Figure 10-6. Output Dead Time vs Timing Capacitance Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 10.3 Examples of Other Output Stages 10.3.1 Flyback Converter Figure 10-7. Flyback Converter Circuit Schematic 10.3.2 Single-Ended LC Figure 10-8. Single-Ended LC Circuit Schematic 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 10.3.3 Push-Pull Transformer-Coupled Figure 10-9. Push-Pull Transformer-Coupled Circuit Schematic Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 SG2524, SG3524 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 www.ti.com Power Supply Recommendations SGx524 is designed to operate from an input voltage supply range between 8 V and 40 V. This input supply should be well regulated. If the input supply is located more than a few inches from the device, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. A tantalum capacitor with a value of 47 μF is a typical choice, however this may vary depending upon the output power being delivered. 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com SG2524, SG3524 SLVS077F – APRIL 1977 – REVISED JANUARY 2021 10 Layout 10.1 Layout Guidelines Always try to use a low EMI inductor with a ferrite type closed core. Some examples would be toroid and encased E core inductors. Open core can be used if they have low EMI characteristics and are located a bit more away from the low power traces and components. Make the poles perpendicular to the PCB as well if using an open core. Stick cores usually emit the most unwanted noise. 10.1.1 Feedback Traces Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but keeping it away from inductor EMI and other noise sources is the more critical of the two. Run the feedback trace on the side of the PCB opposite of the inductor with a ground plane separating the two. 10.1.2 Input/Output Capacitors When using a low value ceramic input filter capacitor, it should be located as close to the VIN pin of the IC as possible. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner voltage supply. Some designs require the use of a feed-forward capacitor connected from the output to the feedback pin as well, usually for stability reasons. In this case it should also be positioned as close to the IC as possible. Using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into the effective antenna created by through-hole components. 10.1.3 Compensation Components External compensation components for stability should also be placed close to the IC. Surface mount components are recommended here as well for the same reasons discussed for the filter capacitors. These should not be located very close to the inductor either. 10.1.4 Traces and Ground Planes Make all of the power (high-current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor, output capacitors, and output diode should be as close to each other possible. This helps reduce the EMI radiated by the power traces due to the high switching currents through them. This will also reduce lead inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should be connected close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of the PCB. This will reduce noise as well by reducing ground loop errors as well as by absorbing more of the EMI radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to separate the power plane (where the power traces and components are) and the signal plane (where the feedback and compensation and components are) for improved performance. On multi-layer boards the use of vias will be required to connect traces and different planes. It is good practice to use one standard via per 200 mA of current if the trace will need to conduct a significant amount of current from one plane to the other. Arrange the components so that the switching current loops curl in the same direction. Due to the way switching regulators operate, there are two power states. One state when the switch is on and one when the switch is off. During each state there will be a current loop made by the power components that are currently conducting. Place the power components so that during each of the two states the current loop is conducting in the same direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces radiated EMI. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 10.2 Layout Example LEGEND Power or GND Plane VIA to Power Plane VIA to GND Plane OUTPUT IN± REF OUT 16 2 IN+ VCC 15 3 OSC OUT EMIT 2 14 4 CURR LIM+ COL 2 13 5 CURR LIM± COL 1 12 6 RT EMIT 1 11 7 CT SHUTDOWN 10 8 GND COMP 9 + + 1 VCC SG2524 GND Figure 10-1. Layout Example for SG2524 20 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated SG2524, SG3524 www.ti.com SLVS077F – APRIL 1977 – REVISED JANUARY 2021 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 11-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SG2524 Click here Click here Click here Click here Click here SG3524 Click here Click here Click here Click here Click here 11.2 Trademarks All trademarks are the property of their respective owners. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SG2524D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524 SG2524DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524 SG2524DRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524 SG2524DRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -25 to 85 SG2524 SG2524N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -25 to 85 SG2524N SG3524D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524 SG3524DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524 SG3524DRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524 SG3524N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SG3524N SG3524NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SG3524N SG3524NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SG3524 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of