SM320C6701GJCA12EP

 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 D Controlled Baseline D D D D D D D D 1M-Bit On-Chip SRAM − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance up to −40°C to 105°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Highest Performance Floating-Point Digital Signal Processor (DSP) 320C6701 − 8.3-, 6-ns Instruction Cycle Time − 120-, 167-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1 GFLOPS − 320C6201 Fixed-Point DSP Pin-Compatible VelociTI Advanced Very Long Instruction Word (VLIW) C67x CPU Core − Eight Highly Independent Functional Units: − Four ALUs (Floating- and Fixed-Point) − Two ALUs (Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional Instruction Set Features − Hardware Support for IEEE Single-Precision Instructions − Hardware Support for IEEE Double-Precision Instructions − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D D D D D D D D D D D D − 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) − 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM − Glueless Interface to Asynchronous Memories: SRAM and EPROM − 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel 16-Bit Host-Port Interface (HPI) − Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) − Direct Interface to T1/E1, MVIP, SCSA Framers − ST-Bus-Switching Compatible − Up to 256 Channels Each − AC97-Compatible − Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG‡) Boundary-Scan-Compatible 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) 352-Pin Ball Grid Array (BGA) Mechanical Shock-Tolerant Package (Mech~Shock) Option (GJC Suffix) 0.18-µm/5-Level Metal Process − CMOS Technology 3.3-V I/Os, 1.8-V Internal (120-MHz) 3.3-V I/Os, 1.9-V Internal (167-MHz) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. ‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright  2003, Texas Instruments Incorporated   !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 1 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Table of Contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 parameter measurement information . . . . . . . . . . . . . . . 27 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 signal-transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 functional block and CPU diagram . . . . . . . . . . . . . . . . . . . . . 4 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 31 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 33 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 37 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 44 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 45 recommended operating conditions . . . . . . . . . . . . . . . . . . . 26 DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 59 electrical characteristics over recommended ranges of supply voltage and operating case temperature . . . . 26 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 multichannel buffered serial port timing . . . . . . . . . . . . . 48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 GJC (352-PIN BGA) PACKAGE ( BOTTOM VIEW ) description 26 1 The 320C67x DSPs are the floating-point DSP A family in the TMS320C6000 DSP platform. The B SM320C6701-EP and SM320C6701MECH-EP C D (C6701) devices are based on the highE performance, advanced VelociTI very-longF G instruction-word (VLIW) architecture developed H J by Texas Instruments (TI), making this DSP an K excellent choice for multichannel and L M multifunction applications. With performance of N P up to 1 giga floating-point operations per second R (GFLOPS) at a clock rate of 167 MHz, the C6701 T U offers cost-effective solutions to highV W performance DSP programming challenges. The Y C6701 DSP possesses the operational flexibility AA AB of high-speed controllers and the numerical AC AD capability of array processors. This processor has AE 32 general-purpose registers of 32-bit word length AF and eight highly independent functional units. The eight functional units provide four floating-/fixedpoint ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 description (continued) The C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. mechanical shock-tolerant package option Typically, industry-standard non-hermetic plastic ball grid array (PBGA) packages manufactured with a metal heat spreader/lid for die coverage are not designed to be tolerant of high levels of mechanical shock. For systems that experience significant mechanical shock, additional board/module design effort is required to allow for the use of the typical PBGA. Therefore, TI designed the Mech~Shock package for selected C6000 platform DSPs for use in applications that will encounter high levels of mechanical shock (e.g., missiles and self-guided projectiles/munitions). The Mech~Shock package is a mechanical-shock package embodiment qualified to 20,000 Gs of mechanical shock. Qualification testing is per MIL-STD-883E, Method 2002.3, Test Condition F. The Mech~Shock package, while non-hermetic, directly addresses the shock stress-environments of system applications that experience severe shock profiles during operation. Mech~Shock packages incorporate a composite (and lighter) heat spreader/lid. The composite heat spreader has equivalent thermal performance to the heavier, solid copper heat spreaders, but the composite lid is less massive. This composite lid is placed on a standard-footprint PBGA substrate and attached with adhesives that have unique, shock-tolerant characteristics. A Mech~Shock package is footprint compatible with the standard commercial package for the same DSP product. device characteristics Table 1 provides an overview of the C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the C6701 Processors HARDWARE FEATURES Peripherals C6701 EMIF 1 DMA 4-Channel Host-Port Interface (HPI) 1 McBSPs 2 32-Bit Timers 2 Size (Bytes) Internal Program Memory 64K Organization 64K Bytes Cache/Mapped Program Size (Bytes) Internal Data Memory 64K Organization Frequency MHz Cycle Time ns 2 Blocks: Eight 16-Bit Banks per Block 50/50 Split 120, 167 6 ns (6701-167); 8.3 ns (6701-120) 1.8 (6701-120) Voltage Core (V) 1.9 (6701-167) I/O (V) 3.3 PLL Options CLKIN frequency multiplier BGA Package 35 x 35 mm Process Technology µm Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) Bypass (x1), x4 352-pin GJC 0.18 µm POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 PD 3 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 functional block and CPU diagram C6701 Digital Signal Processor Program Bus SDRAM SBSRAM 32 SRAM External Memory Interface (EMIF) ROM/FLASH Internal Program Memory 1 Block Program/Cache (64K Bytes) Program Access/Cache Controller I/O Devices C67x CPU Instruction Fetch Timer 1 Instruction Dispatch 16 Host Port Interface (HPI) Data Bus DMA Buses Multichannel Buffered Serial Port 1 Control Logic Data Path B A Register File B Register File In-Circuit Emulation .D2 .M2† .S2† .L2† Interrupt Control .L1† .S1† .M1† .D1 Direct Memory Access Controller (DMA) (4 Channels) PLL (x1, x4) Data Path A PowerDown Logic Data Access Controller † These functional units execute floating-point instructions. 4 Control Registers Instruction Decode Multichannel Buffered Serial Port 0 Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge + Inverter MC68302 + PAL MPC750 + PAL MPC960 (Jx/Rx) + PAL Timer 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Test Internal Data Memory (64K Bytes) 2 Blocks of 8 Banks Each 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the Functional and CPU Block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all TMS320C62x DSP fixed-point instructions. In addition to the C62x DSP fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. TMS320C62x is a trademark of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 CPU description (continued) ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ src1 .L1† src2 dst long dst long src LD1 32 MSB ST1 8 8 long src long dst dst .S1† src1 Data Path A 32 32 8 8 src2 dst src1 † .M1 src2 LD1 32 LSB ÁÁ ÁÁ ÁÁ ÁÁ DA1 DA2 LD2 32 LSB .D1 .D2 dst src1 src2 1X src2 .M2† src1 dst src2 ÁÁ ÁÁ LD2 32 MSB ST2 long src long dst dst .L2† src2 8 8 8 8 src1 † These functional units execute floating-point instructions. Figure 1. TMS320C67x CPU Data Paths 6 Register File B (B0−B15) .S2† Data Path B POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Register File A (A0−A15) 2X src2 src1 dst src1 dst long dst long src ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á 32 32 Control Register File 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 Boot Mode BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0 Reset and Interrupts RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 Little ENDIAN Big ENDIAN LENDIAN CLOCK/PLL PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF TMS TDO TDI TCK TRST EMU1 EMU0 IEEE Standard 1149.1 (JTAG) Emulation RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0 DMA Status DMAC3 DMAC2 DMAC1 DMAC0 Power-Down Status PD Reserved Control/Status HD[15:0] HCNTL0 HCNTL1 16 Data HPI (Host-Port Interface) Register Select Control HHWIL HBE1 HBE0 Half-Word/Byte Select HAS HR/W HCS HDS1 HDS2 HRDY HINT Figure 2. CPU and Peripheral Signals POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 7 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 signal groups description (continued) 32 ED[31:0] Data CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 HOLD HOLDA Asynchronous Memory Control ARE AOE AWE ARDY Memory Map Space Select 20 Word Address SBSRAM Control SSADS SSOE SSWE SSCLK SDRAM Control SDA10 SDRAS SDCAS SDWE SDCLK Byte Enables HOLD/ HOLDA EMIF (External Memory Interface) TOUT1 Timer 1 Timer 0 TOUT0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Receive Receive CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Transmit Transmit CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 3. Peripheral Signals 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions SIGNAL NAME NO. TYPE† DESCRIPTION CLOCK/PLL CLKIN C10 I Clock Input CLKOUT1 AF22 O Clock output at full device speed CLKOUT2 AF20 O Clock output at half of device speed CLKMODE1 C6 CLKMODE0 C5 PLLFREQ3 A9 PLLFREQ2 D11 PLLFREQ1 PLLV‡ B10 D12 PLLG‡ Clock mode select I I • Selects whether the output clock frequency = input clock frequency x4 or x1 PLL frequency range (3, 2, and 1) • The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. PLL analog VCC connection for the low-pass filter C12 A§ A§ PLLF A11 A§ PLL low-pass filter connection to external components and a bypass capacitor TMS L3 I TDO W2 O/Z TDI R4 I JTAG test-port data in (features an internal pullup) TCK R3 I JTAG test-port clock JTAG test-port reset (features an internal pulldown) PLL analog GND connection for the low-pass filter JTAG EMULATION JTAG test-port mode select (features an internal pullup) JTAG test-port data out TRST T1 I EMU1 Y1 I/O/Z EMU0 W3 I/O/Z RESET K2 I Device reset NMI L2 I Nonmaskable interrupt • Edge-driven (rising edge) EXT_INT7 U3 I External interrupts • Edge-driven (rising edge) O Interrupt acknowledge for all active interrupts serviced by the CPU O Active interrupt identification number • Valid during IACK for all active interrupts (not just external) • Encoding order follows the interrupt-service fetch-packet ordering I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ CONTROL EXT_INT6 V2 EXT_INT5 W1 EXT_INT4 U4 IACK Y2 INUM3 AA1 INUM2 W4 INUM1 AA2 INUM0 AB1 LENDIAN H3 PD D3 O Power-down mode 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 9 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION HOST-PORT INTERFACE (HPI) HINT H26 O Host interrupt (from DSP to host) HCNTL1 F23 I Host control − selects between control, address, or data registers HCNTL0 D25 I Host control − selects between control, address, or data registers HHWIL C26 I Host half-word select − first or second half-word (not necessarily high or low order) HBE1 E23 I Host byte select within word or half-word HBE0 D24 I Host byte select within word or half-word HR/W C23 I Host read or write select HD15 B13 HD14 B14 HD13 C14 HD12 B15 HD11 D15 HD10 B16 HD9 A17 HD8 B17 HD7 D16 HD6 B18 HD5 A19 HD4 C18 HD3 B19 HD2 C19 HD1 B20 I/O/Z Host-port data (used for transfer of data, address, and control) HD0 B21 HAS C22 I Host address strobe HCS B23 I Host chip select HDS1 D22 I Host data strobe 1 HDS2 A24 I Host data strobe 2 HRDY J24 O Host ready (from DSP to host) BOOTMODE4 D8 BOOTMODE3 B4 BOOT MODE BOOTMODE2 A3 BOOTMODE1 D5 I Boot mode BOOTMODE0 C4 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 AE22 O/Z CE2 AD26 O/Z Memory space enables CE1 AB24 O/Z • Enabled by bits 24 and 25 of the word address CE0 AC26 O/Z • Only one asserted during any external data access BE3 AB25 O/Z Byte-enable control BE2 AA24 O/Z • Decoded from the two lowest bits of the internal address BE1 Y23 O/Z • Byte-write enables for most types of memory BE0 AA26 O/Z • Can be directly connected to SDRAM read and write mask signal (SDQM) EA21 J26 EA20 K25 EMIF − ADDRESS EA19 L24 EA18 K26 EA17 M26 EA16 M25 EA15 P25 EA14 P24 EA13 R25 EA12 T26 EA11 R23 EA10 U26 EA9 U25 EA8 T23 EA7 V26 EA6 V25 EA5 W26 EA4 V24 EA3 W25 O/Z External address (word address) EA2 Y26 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF − DATA ED31 AB2 ED30 AC1 ED29 AA4 ED28 AD1 ED27 AC3 ED26 AD4 ED25 AF3 ED24 AE4 ED23 AD5 ED22 AF4 ED21 AE5 ED20 AD6 ED19 AE6 ED18 AD7 ED17 AC8 ED16 AF7 ED15 AD9 ED14 AD10 ED13 AF9 ED12 AC11 ED11 AE10 ED10 AE11 ED9 AF11 ED8 AE14 ED7 AF15 ED6 AE15 ED5 AF16 ED4 AC15 ED3 AE17 ED2 AF18 ED1 AF19 ED0 AC17 I/O/Z External data EMIF − ASYNCHRONOUS MEMORY CONTROL ARE Y24 O/Z Asynchronous memory read enable AOE AC24 O/Z Asynchronous memory output enable AWE AD23 O/Z Asynchronous memory write enable ARDY W23 I Asynchronous memory ready input † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION EMIF − SYNCHRONOUS BURST SRAM CONTROL SSADS AC20 O/Z SBSRAM address strobe SSOE AF21 O/Z SBSRAM output enable SSWE AD19 O/Z SBSRAM write enable SSCLK AD17 O SBSRAM clock EMIF − SYNCHRONOUS DRAM CONTROL SDA10 AD21 O/Z SDRAM address 10 (separate for deactivate command) SDRAS AF24 O/Z SDRAM row-address strobe SDCAS AD22 O/Z SDRAM column-address strobe SDWE AF23 O/Z SDRAM write enable SDCLK AE20 O SDRAM clock EMIF − BUS ARBITRATION HOLD AA25 I Hold request from the host HOLDA A7 O Hold-request-acknowledge to the host TOUT1 H24 O Timer 1 or general-purpose output TINP1 K24 I Timer 1 or general-purpose input TOUT0 M4 O Timer 0 or general-purpose output TINP0 K4 I Timer 0 or general-purpose input DMAC3 D2 DMAC2 F4 DMAC1 D1 DMAC0 E2 TIMERS DMA ACTION COMPLETE O DMA action complete MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1 E25 I CLKR1 H23 I/O/Z External clock source (as opposed to internal) Receive clock CLKX1 F26 I/O/Z Transmit clock DR1 D26 I Receive data DX1 G23 O/Z Transmit data FSR1 E26 I/O/Z Receive frame sync FSX1 F25 I/O/Z Transmit frame sync † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 L4 I CLKR0 M2 I/O/Z External clock source (as opposed to internal) Receive clock CLKX0 L1 I/O/Z Transmit clock DR0 J1 I Receive data DX0 R1 O/Z Transmit data FSR0 P4 I/O/Z Receive frame sync FSX0 P3 I/O/Z Transmit frame sync RESERVED FOR TEST RSV0 T2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV1 G2 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV2 C11 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV3 B9 I Reserved for testing, pullup with a dedicated 20-kΩ resistor RSV4 A6 I Reserved for testing, pulldown with a dedicated 20-kΩ resistor RSV5 C8 O Reserved (leave unconnected, do not connect to power or ground) RSV6 C21 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV7 B22 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV8 A23 I Reserved for testing, pullup with a dedicated 20-kW resistor RSV9 E4 O Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS A10 A15 A18 A21 A22 B7 C1 D17 F3 G24 DVDD G25 S 3.3-V supply voltage H25 J25 L25 M3 N3 N23 R26 T24 U24 W24 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) Y4 AB3 AB4 AB26 AC6 AC10 AC19 AC21 AC22 DVDD AC25 S 3.3-V supply voltage S 1.8-V supply voltage (for 6701-120) 1.9-V supply voltage (for 6701-167) AD11 AD13 AD15 AD18 AE18 AE21 AF5 AF6 AF17 A5 A12 A16 A20 B2 B6 B11 B12 B25 C3 CVDD C15 C20 C24 D4 D6 D7 D9 D14 D18 D20 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) D23 E1 F1 H4 J4 J23 K1 K23 M1 M24 N4 N25 P2 P23 T3 T4 U1 CVDD V4 S 1.8-V supply voltage (for 6701-120) 1.9-V supply voltage (for 6701-167) V23 AC4 AC9 AC12 AC13 AC18 AC23 AD3 AD8 AD14 AD24 AE2 AE8 AE12 AE25 AF12 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS A1 A2 A4 A13 A14 A25 A26 B1 B3 B5 B24 B26 C2 C7 C13 C16 C17 C25 D13 VSS D19 GND Ground pins E3 E24 F2 F24 G3 G4 G26 J3 L23 L26 M23 N1 N2 N24 N26 P1 P26 R24 T25 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION GROUND PINS (CONTINUED) U2 U23 V1 V3 Y3 Y25 AA3 AA23 AB23 AC2 AC5 AC7 AC14 AC16 AD2 AD12 AD16 AD20 VSS AD25 GND Ground pins AE1 AE3 AE7 AE9 AE13 AE16 AE19 AE23 AE24 AE26 AF1 AF2 AF8 AF10 AF13 AF14 AF25 AF26 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground 18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE† DESCRIPTION REMAINING UNCONNECTED PINS A8 B8 C9 D10 D21 NC G1 Unconnected pins H1 H2 J2 K3 R2 † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 19 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 development support TI offers an extensive line of development tools for the TMS320C6000t DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000t DSP-based applications: Software Development Tools: Code Composer Studiot Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000t DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320t DSP family member devices, including documentation. See this document for further information on TMS320t DSP documentation or any TMS320t DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320t DSP-related products from other companies in the industry. To receive TMS320t DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000t DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under “Development Tools”, select “Digital Signal Processors”. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. 20 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 device and development-support tool nomenclature To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SM/SMJ Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GJC), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -167 is 167 MHz). Table 2 identifies the available 320C6701 devices by their associated orderable part numbers (P/Ns) and gives device-specific ordering information (for example, device speeds, core and I/O supply voltage values, and device operating temperature ranges). Figure 4 provides a legend for reading the complete device name for any TMS320 DSP family member. Table 2. 320C6701 Device P/Ns and Ordering Information OPERATING CASE TEMPERATURE RANGE DEVICE SPEED CVDD (CORE VOLTAGE) DVDD (I/O VOLTAGE) SMC6701MECHGJC16EP 167 MHz/1 GFLOPS 1.9 V 3.3 V 0_C to 90_C SM320C6701GJCA12EP 120 MHz/720 MFLOPS 1.8 V 3.3 V −40_C to 105_C DEVICE ORDERABLE P/N POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 21 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 device and development-support tool nomenclature (continued) SM PREFIX TMX = TMP = TMS = SMJ = SM = 320 C 6701 GJC (A) 12 EP Experimental device Prototype device Qualified device MIL-PRF-38535 (QML) Commercial processing ENHANCED PLASTIC DEVICE SPEED RANGE 12 = 120 MHz 16 = 167 MHz DEVICE FAMILY 320 = TMS320 DSP family TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C) Blank = 0°C to 90°C, commercial temperature A = −40°C to 105°C, extended temperature PACKAGE TYPE† N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU = 144-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA MECHGJC = 352-pin mech~shock plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM DEVICE 1x DSP: 10 14 15 16 17 2x DSP: 25 26 2xx DSP: 203 204 206 209 240 3x DSP: 30 31 32 4x DSP: 40 44 5x DSP: † DIP PGA CC QFP TQFP BGA = = = = = = Dual-In-Line Package Pin Grid Array Chip Carrier Quad Flat Package Thin Quad Flat Package Ball Grid Array 50 51 52 53 56 57 541 542 543 545 546 548 6201 6202 6202B 6203 6204 6205 6211 6701 6711 54x DSP: 6x DSP: Figure 4. TMS320 DSP Device Nomenclature (Including SM320C6701) MicroStar BGA is a trademark of Texas Instruments. 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 documentation support Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. TMS320C6000 DSP Host−Post Interface (HPI) Reference Guide (literature number SPRU578) describes the host−port interface (HPI) in the digital signal processors (DSPs) of the TMS320C6000 DSP family that external processors use to access the memory space. TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (literature number SPRU580) describes the operation of the multichannel buffered serial port (McBSP) in the digital signal processors (DSPs) of the TMS320C6000 DSP family. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 23 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 clock PLL All of the internal C67x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3, Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the C67x device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Table 3. CLKOUT1 Frequency Ranges† PLLFREQ3 (A9) PLLFREQ2 (D11) PLLFREQ1 (B10) CLKOUT1 Frequency Range (MHz) 0 0 0 50−140 0 0 1 65−167 0 1 0 130−167 † Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved. Table 4. C6701 PLL Component Selection Table CLKMODE CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 (Ω) C1 (nF) C2 (pF) TYPICAL LOCK TIME (µs)‡ x4 12.5−41.7 50−167 25−83.5 60.4 27 560 75 ‡ Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 clock PLL (continued) PLLFREQ3 PLLFREQ2 PLLFREQ1 3.3V (see Table 3) EMI Filter PLLV C3 10 mF C4 0.1 mF Internal to C6701 PLL CLKMODE0 CLKMODE1 PLLMULT PLLCLK CLKIN CLKIN 1 LOOP FILTER Available Multiply Factors CPU Clock Frequency f(CPUCLOCK) CLKMODE1 CLKMODE0 PLL Multiply Factors 0 0 x1(BYPASS) 1 x f(CLKIN) 0 1 Reserved Reserved 1 0 Reserved Reserved 1 1 x4 4 x f(CLKIN) C2 C1 CPU CLOCK PLLG PLLF 0 R1 NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U. Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode PLLFREQ3 PLLFREQ2 PLLFREQ1 3.3V (see Table 3) PLLV CLKMODE0 CLKMODE1 Internal to C6701 PLLMULT PLL PLLCLK CLKIN CLKIN LOOP FILTER 1 CPU CLOCK PLLG PLLF 0 NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 25 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V Operating case temperature range, TC (Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40_C to 105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55_C to 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX UNIT 6701-120 1.71 1.8 1.89 V 6701-167 1.81 1.9 1.99 V 3.14 3.30 3.46 V 0 0 0 V CVDD Supply voltage, Core‡ DVDD Supply voltage, I/O‡ VSS VIH Supply ground VIL IOH Low-level input voltage 0.8 V High-level output current −12 mA IOL Low-level output current 12 mA 90 _C High-level input voltage 2.0 Default TC V 0 Case temperature A Version −40 105 _C ‡ TI DSP’s do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. For additional power supply sequencing information, see the Power Supply Sequencing Solutions For Dual Supply Voltage DSPs application report (literature number SLVA073). electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER VOH VOL II IOZ TEST CONDITIONS High-level output voltage DVDD = MIN, Low-level output voltage Input current† DVDD = MIN, IOH = MAX IOL = MAX MIN TYP 2.4 UNIT V VI = VSS to DVDD VO = DVDD or 0 V Off-state output current MAX 0.6 V ±10 uA ±10 uA IDD2V IDD2V Supply current, CPU + CPU memory access‡ Supply current, peripherals‡ CVDD = NOM, CPU clock = 120 MHz 380 mA CVDD = NOM, CPU clock = 120 MHz 200 mA IDD3V Ci Supply current, I/O pins‡ DVDD = NOM, CPU clock = 120 MHz 70 Input capacitance mA 10 pF Co Output capacitance 10 pF † TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. ‡ Measured with average activity (50% high / 50% low power). For more detailed information on CPU/peripheral/I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω Vref Output Under Test CT = 30 pF† IOH † Typical distributed load circuit capacitance. signal-transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 27 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN†‡ (see Figure 8) C6701-120 CLKMODE = x4 NO. MIN 1 C6701-167 CLKMODE = x1 MAX MIN MAX CLKMODE = x4 MIN MAX MIN UNIT MAX tc(CLKIN) Cycle time, CLKIN 33.3 8.3 24 6 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.45C 0.4C 0.45C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.45C 0.4C 0.45C ns 4 tt(CLKIN) Transition time, CLKIN 5 0.6 † The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. ‡ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. 1 5 4 2 CLKIN 3 4 Figure 8. CLKIN Timings 28 CLKMODE = x1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 0.6 ns 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1†‡ (see Figure 9) C6701-120 C6701-167 NO. 1 2 3 4 PARAMETER CLKMODE = x4 CLKMODE = x1 UNIT MIN MAX MIN MAX P − 0.7 P + 0.7 P − 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) − 0.5 (P/2) + 0.5 PH − 0.5 PH + 0.5 ns Pulse duration, CLKOUT1 low (P/2) − 0.5 (P/2) + 0.5 PL − 0.5 PL + 0.5 ns 0.6 ns tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 tw(CKO1L) tt(CKO1) Transition time, CLKOUT1 0.6 † P = 1/CPU clock frequency in nanoseconds (ns). ‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. 1 4 2 CLKOUT1 3 4 Figure 9. CLKOUT1 Timings switching characteristics for CLKOUT2§ (see Figure 10) NO. 1 2 3 4 C6701-120 C6701-167 PARAMETER UNIT MIN MAX 2P − 0.7 2P + 0.7 ns tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high P − 0.7 P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low P − 0.7 P + 0.7 ns 0.6 ns Transition time, CLKOUT2 § P = 1/CPU clock frequency in ns. 1 4 2 CLKOUT2 3 4 Figure 10. CLKOUT2 Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 29 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 INPUT AND OUTPUT CLOCKS (CONTINUED) SDCLK, SSCLK timing parameters SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration. switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 11) NO. 1 C6701-120 C6701-167 PARAMETER MAX UNIT Delay time, CLKOUT1 edge to SSCLK edge −0.8 3.4 ns 2 td(CKO1-SSCLK) td(CKO1-SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) −1.0 3.0 ns 3 td(CKO1-CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge −1.5 2.5 ns 4 td(CKO1-SDCLK) Delay time, CLKOUT1 edge to SDCLK edge −1.5 1.9 ns CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1 30 MIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles† (see Figure 12 and Figure 13) C6701-120 C6701-167 NO. MIN 6 7 10 11 UNIT MAX tsu(EDV-CKO1H) th(CKO1H-EDV) Setup time, read EDx valid before CLKOUT1 high 4.5 ns Hold time, read EDx valid after CLKOUT1 high 1.5 ns tsu(ARDY-CKO1H) th(CKO1H-ARDY) Setup time, ARDY valid before CLKOUT1 high 3.5 ns Hold time, ARDY valid after CLKOUT1 high 1.5 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input. switching characteristics for asynchronous memory cycles‡ (see Figure 12 and Figure 13) NO. 1 2 3 4 5 8 9 12 13 14 PARAMETER C6701-120 C6701-167 UNIT MIN MAX −1.0 4.5 ns 4.5 ns td(CKO1H-CEV) td(CKO1H-BEV) Delay time, CLKOUT1 high to CEx valid td(CKO1H-BEIV) td(CKO1H-EAV) Delay time, CLKOUT1 high to BEx invalid td(CKO1H-EAIV) td(CKO1H-AOEV) Delay time, CLKOUT1 high to EAx invalid −1.0 Delay time, CLKOUT1 high to AOE valid −1.0 4.5 ns td(CKO1H-AREV) td(CKO1H-EDV) Delay time, CLKOUT1 high to ARE valid −0.5 4.5 ns 4.5 ns td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to EDx invalid −1.0 Delay time, CLKOUT1 high to AWE valid −1.0 Delay time, CLKOUT1 high to BEx valid −1.0 Delay time, CLKOUT1 high to EAx valid ns 4.5 Delay time, CLKOUT1 high to EDx valid ns ns ns 4.5 ns ‡ The minimum delay is also the minimum output hold after CLKOUT1 high. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 7 6 ED[31:0] 8 8 AOE 9 9 ARE AWE 11 11 10 10 ARDY Figure 12. Asynchronous Memory Read Timing Setup = 2 Not ready = 2 Strobe = 5 HOLD = 1 CLKOUT1 1 1 2 3 4 5 CEx BE[3:0] EA[21:2] 12 13 ED[31:0] AOE ARE 14 14 AWE 11 10 11 10 ARDY Figure 13. Asynchronous Memory Write Timing 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14) NO. 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) C6701-120 C6701-167 MIN MIN MAX MAX UNIT Setup time, read EDx valid before SSCLK high 2.0 2.0 ns Hold time, read EDx valid after SSCLK high 2.9 2.1 ns switching characteristics for synchronous-burst SRAM cycles† (full-rate SSCLK) (see Figure 14 and Figure 15) C6701-120 NO. 1 PARAMETER MIN MAX C6701-167 MIN MAX UNIT tosu(CEV-SSCLKH) toh(SSCLKH-CEV) Output setup time, CEx valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns Output hold time, CEx valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high 0.5P − 1.3 0.5P − 1.6 ns Output hold time, BEx invalid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high 0.5P − 1.3 0.5P − 1.7 ns Output hold time, EAx invalid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns Output hold time, SSADS valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns Output hold time, SSOE valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output setup time, EDx valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 14 Output hold time, EDx invalid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P − 1.3 0.5P − 1.3 ns 2 3 4 5 6 9 10 11 12 13 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P − 2.9 0.5P − 2.3 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 33 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 5 EA[21:2] 8 7 Q1 ED[31:0] 9 Q2 Q3 Q4 10 SSADS 11 12 SSOE SSWE Figure 14. SBSRAM Read Timing (Full-Rate SSCLK) SSCLK 1 2 CEx 3 BE[3:0] BE1 BE2 BE3 4 BE4 A1 A2 A3 6 A4 D3 14 D4 5 EA[21:2] 13 ED[31:0] D1 D2 9 10 15 16 SSADS SSOE SSWE Figure 15. SBSRAM Write Timing (Full-Rate SSCLK) 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16) C6701-120 C6701-167 NO. MIN 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) UNIT MAX Setup time, read EDx valid before SSCLK high 3.6 ns Hold time, read EDx valid after SSCLK high 1.5 ns switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK) (see Figure 16 and Figure 17) NO. 1 PARAMETER C6701-120 C6701-167 MIN MIN 0.5P − 2.5 0.5P − 2 ns 1.5P − 4.5 1.5P − 4.5 ns Output hold time, BEx invalid after SSCLK high 0.5P − 2.5 0.5P − 2 ns tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) Output setup time, EAx valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns Output hold time, EAx invalid after SSCLK high 0.5P − 2.5 0.5P − 2 ns tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) Output setup time, SSADS valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns Output hold time, SSADS valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns tosu(OEV-SSCLKH) toh(SSCLKH-OEV) Output setup time, SSOE valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns Output hold time, SSOE valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns Output setup time, EDx valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 14 tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) Output hold time, EDx invalid after SSCLK high 0.5P − 2.5 0.5P − 2 ns 15 tosu(WEV-SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P − 4.5 1.5P − 4.5 ns 4 5 6 9 10 11 12 13 1.5P − 4.5 Output hold time, CEx valid after SSCLK high tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) Output setup time, BEx valid before SSCLK high UNIT ns 3 Output setup time, CEx valid before SSCLK high MAX 1.5P − 4.5 2 tosu(CEV-SSCLKH) toh(SSCLKH-CEV) MAX 16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P − 2.5 0.5P − 2 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 6 7 Q1 ED[31:0] 8 Q2 9 Q3 Q4 10 SSADS 11 12 SSOE SSWE Figure 16. SBSRAM Read Timing (1/2 Rate SSCLK) SSCLK 1 2 CEx BE[3:0] 3 BE1 BE2 BE3 BE4 4 EA[21:2] 5 A1 A2 A3 A4 ED[31:0] Q1 Q2 Q3 Q4 6 13 14 9 10 15 16 SSADS SSOE SSWE Figure 17. SBSRAM Write Timing (1/2 Rate SSCLK) 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 18) C6701-120 C6701-167 NO. MIN 7 8 tsu(EDV-SDCLKH) th(SDCLKH-EDV) Setup time, read EDx valid before SDCLK high UNIT MAX 1.8 ns 3 ns Hold time, read EDx valid after SDCLK high switching characteristics for synchronous DRAM cycles† (see Figure 18−Figure 23) NO. 1 2 3 4 5 6 PARAMETER tosu(CEV-SDCLKH) toh(SDCLKH-CEV) Output setup time, CEx valid before SDCLK high tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) Output setup time, BEx valid before SDCLK high tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) Output setup time, EAx valid before SDCLK high Output hold time, CEx valid after SDCLK high Output hold time, BEx invalid after SDCLK high UNIT 1.5P − 4 1.5P − 4 ns 0.5P − 1.9 0.5P − 1.5 ns 1.5P − 4 1.5P − 4 ns 0.5P − 1.9 0.5P − 1.5 ns 1.5P − 4 ns ns Output setup time, SDCAS valid before SDCLK high 1.5P − 4 1.5P − 4 ns 0.5P − 1.9 0.5P − 1.5 ns 1.5P − 4 1.5P − 4 ns 0.5P − 1.9 0.5P − 1.5 ns Output hold time, SDCAS valid after SDCLK high toh(SDCLKH-EDIV) tosu(SDWE-SDCLKH) Output hold time, EDx invalid after SDCLK high Output hold time, SDWE valid after SDCLK high 15 toh(SDCLKH-SDWE) tosu(SDA10V-SDCLKH) 16 toh(SDCLKH-SDA10IV) Output hold time, SDA10 invalid after SDCLK high tosu(SDRAS-SDCLKH) Output setup time, SDRAS valid before SDCLK high 17 MAX 0.5P − 1.5 toh(SDCLKH-SDCAS) tosu(EDV-SDCLKH) 14 MIN MAX 1.5P − 4 10 13 MIN 0.5P − 1.9 tosu(SDCAS-SDCLKH) 11 C6701-167 Output hold time, EAx invalid after SDCLK high 9 12 C6701-120 Output setup time, EDx valid before SDCLK high Output setup time, SDWE valid before SDCLK high Output setup time, SDA10 valid before SDCLK high 1.5P − 4 1.5P − 4 ns 0.5P − 1.9 0.5P − 1.5 ns 1.5P − 4 1.5P − 4 ns 0.5P − 1.9 0.5P − 1.5 ns 1.5P − 4 1.5P − 4 ns 18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P − 1.9 0.5P − 1.5 ns † When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) READ READ READ SDCLK 1 2 CEx 3 BE[3:0] 5 EA[15:2] 4 BE1 BE2 CA2 CA3 BE3 6 CA1 7 8 D1 ED[31:0] 15 16 9 10 D2 D3 SDA10 SDRAS SDCAS SDWE Figure 18. Three SDRAM Read Commands WRITE WRITE WRITE SDCLK 1 2 CEx 3 4 BE1 BE[3:0] 5 EA[15:2] BE3 CA2 CA3 D2 D3 6 CA1 11 D1 ED[31:0] BE2 12 15 16 9 10 13 14 SDA10 SDRAS SDCAS SDWE Figure 19. Three SDRAM Write Commands 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV SDCLK 1 2 CEx BE[3:0] 5 Bank Activate/Row Address EA[15:2] ED[31:0] 15 Row Address SDA10 17 18 SDRAS SDCAS SDWE Figure 20. SDRAM ACTV Command DCAB SDCLK 1 2 15 16 17 18 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 SDRAS SDCAS 13 14 SDWE Figure 21. SDRAM DCAB Command POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 39 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 SYNCHRONOUS DRAM TIMING (CONTINUED) REFR SDCLK 1 2 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 18 SDRAS 9 10 SDCAS SDWE Figure 22. SDRAM REFR Command MRS SDCLK 1 2 5 6 CEx BE[3:0] MRS Value EA[15:2] ED[31:0] SDA10 17 18 9 10 13 14 SDRAS SDCAS SDWE Figure 23. SDRAM MRS Command 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 HOLD/HOLDA TIMING timing requirements for the hold/hold acknowledge cycles† (see Figure 24) C6701-120 C6701-167 NO. MIN 1 2 tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) Setup time, HOLD high before CLKOUT1 high 5 Hold time, HOLD low after CLKOUT1 high 2 UNIT MAX ns ns † HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input. switching characteristics for the hold/hold acknowledge cycles‡ (see Figure 24) NO. C6701-120 C6701-167 PARAMETER MIN 3 4 5 6 7 8 4P UNIT MAX § ns 2P ns tR(HOLDL-EMHZ) tR(EMHZ-HOLDAL) Response time, HOLD low to EMIF high impedance tR(HOLDH-HOLDAH) td(CKO1H-HOLDAL) Response time, HOLD high to HOLDA high 4P 7P ns Delay time, CLKOUT1 high to HOLDA valid 1 8 ns td(CKO1H-BHZ) td(CKO1H-BLZ) Delay time, CLKOUT1 high to EMIF Bus high impedance¶ Delay time, CLKOUT1 high to EMIF Bus low impedance¶ 1 8 ns Response time, EMIF high impedance to HOLDA low 1 12 ns tR(HOLDH-BLZ) Response time, HOLD high to EMIF Bus low impedance¶ 3P 6P ns ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. ¶ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. 9 DSP Owns Bus External Requester DSP Owns Bus 5 9 4 3 CLKOUT1 2 2 1 1 HOLD 6 6 HOLDA 7 8 EMIF Bus† ’C6701 Ext Req ’C6701 † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. Figure 24. HOLD/HOLDA Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 41 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 RESET TIMING timing requirements for reset (see Figure 25) C6701-120 C6701-167 NO. MIN 1 tw(RESET) Width of the RESET pulse (PLL stable)† UNIT MAX CLKOUT1 cycles 10 Width of the RESET pulse (PLL needs to sync up)‡ 250 µs † This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. ‡ This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. switching characteristics during reset§¶ (see Figure 25) NO. PARAMETER C6701-120 C6701-167 MIN 2 tR(RESET) Response time to change of value in RESET signal 3 td(CKO1H-CKO2IV) td(CKO1H-CKO2V) Delay time, CLKOUT1 high to CLKOUT2 invalid td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) Delay time, CLKOUT1 high to SDCLK invalid td(CKO1H-SSCKIV) td(CKO1H-SSCKV) Delay time, CLKOUT1 high to SSCLK invalid td(CKO1H-LOWIV) td(CKO1H-LOWV) Delay time, CLKOUT1 high to low group invalid td(CKO1H-HIGHIV) td(CKO1H-HIGHV) Delay time, CLKOUT1 high to high group invalid td(CKO1H-ZHZ) td(CKO1H-ZV) Delay time, CLKOUT1 high to Z group high impedance 4 5 6 7 8 9 10 11 12 13 14 § Low group consists of: High group consists of: Z group consists of: CLKOUT1 cycles −1 ns 10 −1 Delay time, CLKOUT1 high to SDCLK valid −1 −1 ns ns 10 −1 Delay time, CLKOUT1 high to high group valid ns ns 10 Delay time, CLKOUT1 high to low group valid ns ns 10 Delay time, CLKOUT1 high to SSCLK valid ns ns 10 −1 ns ns 10 ns IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. HINT. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ¶ HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. 42 1 Delay time, CLKOUT1 high to CLKOUT2 valid Delay time, CLKOUT1 high to Z group valid UNIT MAX POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 RESET TIMING (CONTINUED) CLKOUT1 1 2 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 CLKOUT2 SDCLK SSCLK LOW GROUP†‡ HIGH GROUP†‡ Z GROUP†‡ † Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. HINT. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. ‡ HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group. Figure 25. Reset Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 43 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles†‡ (see Figure 26) C6701-120 C6701-167 NO. MIN 2 3 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low 2P Width of the interrupt pulse high 2P UNIT MAX ns ns † Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. switching characteristics during interrupt response cycles§ (see Figure 26) NO. C6701-120 C6701-167 PARAMETER MIN 1 tR(EINTH-IACKH) td(CKO2L-IACKV) Response time, EXT_INTx high to IACK high 4 5 td(CKO2L-INUMV) Delay time, CLKOUT2 low to INUMx valid 9P Delay time, CLKOUT2 low to IACK valid −0.5P 6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. ns 13 − 0.5P ns 10 − 0.5P ns −0.5P ns 1 CLKOUT2 2 3 EXT_INTx, NMI Intr Flag 4 4 IACK 6 5 Interrupt Number INUMx Figure 26. Interrupt Timing 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 UNIT MAX 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) C6701-120 C6701-167 NO. MIN 1 2 3 4 10 11 12 tsu(SEL-HSTBL) th(HSTBL-SEL) Setup time, select signals§ valid before HSTROBE low Hold time, select signals§ valid after HSTROBE low tw(HSTBL) tw(HSTBH) tsu(SEL-HASL) th(HASL-SEL) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) 19 UNIT MAX 4 ns 2 ns Pulse duration, HSTROBE low 2P ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals§ valid before HAS low 2P ns 4 ns Hold time, select signals§ valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 3 ns Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 1 ns Setup time, HAS low before HSTROBE low 2 ns Hold time, HAS low after HSTROBE low 2 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. § Select signals include: HCNTRL[1:0], HR/W, and HHWIL. switching characteristics during host-port interface cycles†‡ (see Figure 27, Figure 28, Figure 29, and Figure 30) NO. PARAMETER C6701-120 C6701-167 MIN 5 6 7 8 9 15 16 17 UNIT MAX td(HCS-HRDY) td(HSTBL-HRDYH) Delay time, HCS to HRDY¶ 1 12 ns Delay time, HSTROBE low to HRDY high# 1 12 ns td(HSTBL-HDLZ) td(HDV-HRDYL) Delay time, HSTROBE low to HD low impedance for an HPI read 4 P+3 ns toh(HSTBH-HDV) td(HSTBH-HDHZ) Output hold time, HD valid after HSTROBE high 3 12 ns Delay time, HSTROBE high to HD high impedance 3 12 ns td(HSTBL-HDV) td(HSTBH-HRDYH) Delay time, HSTROBE low to HD valid 3 12 ns Delay time, HSTROBE high to HRDY high|| 1 12 ns Delay time, HD valid to HRDY low P−3 ns 20 td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 12 ns † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. ‡ P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 45 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE† HCS 15 9 7 15 9 16 HD[15:0] (output) 1st half-word 5 2nd half-word 8 17 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 27. HPI Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE† 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 20 8 HRDY (case 2) † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 28. HPI Read Timing (HAS Used) 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 12 12 13 13 HBE[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 4 14 HSTROBE† HCS 12 12 13 13 HD[15:0] (input) 1st half-word 5 17 2nd half-word 5 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Write Timing (HAS Not Used, Tied High) HAS 12 19 13 12 19 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE† 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 5 HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Write Timing (HAS Used) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 47 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP†‡ (see Figure 31) C6701-120 C6701-167 NO. 2 3 tc(CKRX) tw(CKRX) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low 5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low 8 th(CKRL-DRV) Hold time, DR valid after CLKR low 10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKR/X ext MIN 2P§ CLKR/X ext P − 1¶ CLKR int 13 CLKR ext 4 CLKR int 7 CLKR ext 4 CLKR int 10 CLKR ext 1 CLKR int 4 CLKR ext 4 CLKX int 13 CLKX ext 4 CLKX int 7 CLKX ext 3 UNIT MAX ns ns ns ns ns ns ns ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. § The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. ¶ The minimum CLKR/X pulse duration is either (P −1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use 9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P −1) = 11.5 ns as the minimum CLKR/X pulse duration. 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP†‡ (see Figure 31) NO. C6701-120 C6701-167 PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 3 15 2P§¶ C − 1# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X CLKR/X int 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −4 4 CLKX int −4 5 CLKX ext 3 16 9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 13 td(CKXH-DXV) Delay time, CLKX high to DX valid. 14 td(FXH-DXV) Delay time, FSX high to DX valid. ONLY applies when in data delay 0 (XDATDLY = 00b) mode. ns ns CLKX int −3 2 CLKX ext 2 9 CLKX int −2 4 CLKX ext 3 16 FSX int −2 4 FSX ext 2 10 ns ns ns ns † CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ‡ Minimum delay times also represent minimum output hold times. § P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ¶ The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 49 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) Figure 31. McBSP Timing 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 (n-3) 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 32) C6701-120 C6701-167 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) UNIT MAX Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) CLKR/X(needs resync) Figure 32. FSR Timing When GSYNC = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 51 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) C6701-120 C6701-167 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 − 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 33) C6701-120 C6701-167 NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T−4 T+4 L−4 L+4 −4 4 L−2 L+3 MIN MAX ns ns 3P + 1 5P + 17 ns ns P+4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 53 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 34) C6701-120 C6701-167 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 − 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 34) C6701-120 C6701-167 NO. PARAMETER MASTER§ 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low¶ Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 1 6 UNIT SLAVE MIN MAX L−4 L+4 MIN MAX T−4 T+4 −4 4 3P + 1 5P + 17 ns −2 4 3P + 4 5P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H−2 H+3 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 (n-4) 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) C6701-120 C6701-167 NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 − 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 35) C6701-120 C6701-167 NO. PARAMETER MASTER§ 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T−4 T+4 H−4 H+4 −4 4 H−2 H+3 MIN MAX ns ns 3P + 1 5P + 17 ns ns P+4 3P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 55 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 (n-4) 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36) C6701-120 C6701-167 NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX low 4 † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 − 3P ns 5 + 6P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 36) C6701-120 C6701-167 NO. PARAMETER MASTER§ 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high¶ Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 1 6 UNIT SLAVE MIN MAX H−4 H+4 MIN MAX T−4 T+4 −4 4 3P + 1 5P + 17 ns −2 4 3P + 4 5P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L−2 L+3 2P + 1 4P + 13 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 57 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) 5 Bit(n-1) (n-2) (n-3) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 58 POST OFFICE BOX 1443 (n-4) • HOUSTON, TEXAS 77251−1443 (n-4) 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 37) NO. 1 C6701-120 C6701-167 PARAMETER td(CKO1H-DMACV) Delay time, CLKOUT1 high to DMAC valid UNIT MIN MAX 2 11 ns CLKOUT1 1 1 DMAC[0:3] Figure 37. DMAC Timing timing requirements for timer inputs (see Figure 38)† C6701-120 C6701-167 NO. MIN 1 tw(TINPH) Pulse duration, TINP high † P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. UNIT MAX 2P ns switching characteristics for timer outputs (see Figure 38) NO. 2 C6701-120 C6701-167 PARAMETER td(CKO1H-TOUTV) Delay time, CLKOUT1 high to TOUT valid UNIT MIN MAX 1 10 ns CLKOUT1 1 TINP 2 2 TOUT Figure 38. Timer Timing switching characteristics for power-down outputs (see Figure 39) NO. 1 C6701-120 C6701-167 PARAMETER td(CKO1H-PDV) Delay time, CLKOUT1 high to PD valid UNIT MIN MAX 1 9 ns CLKOUT1 1 1 PD Figure 39. Power-Down Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 59 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 40) C6701-120 C6701-167 NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics for JTAG test port (see Figure 40) NO. 2 C6701-120 C6701-167 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid MIN MAX –3 12 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 40. JTAG Test-Port Timing 60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 UNIT ns 
 
     
 

 SGUS042A − MAY 1998 − REVISED APRIL 2004 MECHANICAL DATA GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY 35,20 SQ 34,80 33,20 SQ 32,80 31,75 TYP 1,27 21,00 NOM 0,635 1,27 0,635 21,00 NOM AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 2 Heat Slug 5 4 7 6 9 8 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 See Note E 3,50 MAX 1,00 NOM Seating Plane 0,90 0,60 NOTES: A. B. C. D. E. F. ∅ 0,10 M 0,50 MIN 0,15 4173506-2/D 07/99 All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL). Flip chip application only Possible protrusion in this area, but within 3,50 max package height specification Falls within JEDEC MO-151/BAR-2 thermal resistance characteristics (S-PBGA package) NO 1 °C/W Air Flow LFPM† RΘJC RΘJA Junction-to-case 0.74 N/A Junction-to-free air 11.31 0 RΘJA RΘJA Junction-to-free air 9.60 100 Junction-to-free air 8.34 250 5 RΘJA Junction-to-free air † LFPM = Linear Feet Per Minute 7.30 500 2 3 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 61 PACKAGE OPTION ADDENDUM www.ti.com 27-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SM320C6701GJCA12EP ACTIVE FCBGA GJC 352 24 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 SM320C6701GJCA 12EP 320C6701 V62/03669-01XA ACTIVE FCBGA GJC 352 24 Non-RoHS & Green SNPB Level-4-220C-72 HR -40 to 105 SM320C6701GJCA 12EP 320C6701 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of