SM320VC33PGEA120EP

SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 D Controlled Baseline D D D D D D D D D D D † -- One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of --40°C to 100°C (A Suffix), and --55°C to 125°C (M Suffix) Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† High-Performance Floating-Point Digital Signal Processor (DSP): -- SM320VC33-120EP (PGE Suffix) -- 17-ns Instruction Cycle Time -- 120 Million Floating-Point Operations Per Second (MFLOPS) -- 60 Million Instructions Per Second (MIPS) -- SM320VC33-150EP (GNM Suffix) -- 13-ns Instruction Cycle Time -- 150 Million Floating-Point Operations Per Second (MFLOPS) -- 75 Million Instructions Per Second (MIPS) 34K × 32-Bit (1.1M-bit) On-Chip Words of Dual-Access Static Random-Access Memory (SRAM) Configured in 2 × 16K plus 2 × 1K Blocks to improve Internal Performance x5 Phase-Locked Loop (PLL) Clock Generator Very Low Power: < 200 mW @ 150 MFLOPS 32-Bit High-Performance CPU 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations Four Internally Decoded Page Strobes to Simplify Interface to I/O and Memory Devices D D D D D D D D D D D D D D D D D Boot-Program Loader EDGEMODE Selectable External Interrupts 32-Bit Instruction Word, 24-Bit Addresses Eight Extended-Precision Registers Fabricated Using the 0.18-μm (leff-Effective Gate Length) TImeline™ Technology by Texas Instruments (TI) On-Chip Memory-Mapped Peripherals: -- One Serial Port -- Two 32-Bit Timers -- Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation 144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix) and 144-Pin Non-hermetic Ceramic Ball Grid Array (CBGA) (GNM Suffix) Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) Two Low-Power Modes Two- and Three-Operand Instructions Parallel Arithmetic/Logic Unit (ALU) and Multiplier Execution in a Single Cycle Block-Repeat Capability Zero-Overhead Loops With Single-Cycle Branches Conditional Calls and Returns Interlocked Instructions for Multiprocessing Support Bus-Control Registers Configure Strobe-Control Wait-State Generation 1.8-V (Core) and 3.3-V (I/O) Supply Voltages Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TImeline and SM320C3x are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 1 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 description The SM320VC33-EP DSP is a 32-bit, floating-point processor manufactured in 0.18-μm four-level-metal CMOS (TImeline) technology. The SM320VC33-EP is part of the SM320C3x™ generation of DSPs from Texas Instruments. The SM320C3x internal busing and special digital-signal-processing instruction set have the speed and flexibility to execute up to 150 million floating-point operations per second (MFLOPS). The SM320VC33-EP optimizes speed by implementing functions in hardware that other processors implement through software or microcode. This hardware-intensive approach provides performance previously unavailable on a single chip. The SM320VC33-EP can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are the results of these features. General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The SM320C3x supports a wide variety of system applications from host processor to dedicated coprocessor. High-level-language support is easily implemented through a register-based architecture, large address space, powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic. JTAG scan-based emulation logic The 320VC33 contains a JTAG port for CPU emulation within a chain of any number of other JTAG devices. The JTAG port on this device does not include a pin-by-pin boundary scan for point-to-point board level test. The Boundary Scan tap input and output is internally connected with a single dummy register allowing loop back tests to be performed through that JTAG domain. The JTAG emulation port of this device also includes two additional pins, EMU0 and EMU1, for global control of multiple processors conforming to the TI emulation standard. These pins are open collector type outputs which are wire ORed and tied high with a pullup. Non-TI emulation devices should not be connected to these pins. The VC33 instruction register is 8 bits long. Table 1 shows the instruction code. The uses of SAMPLE and HIGHZ opcodes, though defined, have no meaning for the SM320VC33-EP, which has no boundary scan. For example, HIGHZ affects only the dummy cell (no meaning) and does not put the device pins in a high-impedance state. 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 Table 1. Boundary Scan Instruction Code INSTRUCTION NAME † INSTRUCTION CODE EXTEST 00000000 BYPASS 11111111 SAMPLE 00000010 Boundary is only one dummy cell HIGHZ 00000110 Boundary is only one dummy cell PRIVATE1† 00000011 PRIVATE2† 00100000 PRIVATE3† 00100001 PRIVATE4† 00100010 PRIVATE5† 00100011 PRIVATE6† 00100100 PRIVATE7† 00100101 PRIVATE8† 00100110 PRIVATE9† 00100111 PRIVATE10† 00101000 PRIVATE11† 00101001 Use of Private opcodes could cause the device to operate in an unexpected manner. ORDERING INFORMATION ‡ TC PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING --40°C to 100°C 144-pin low-profile plastic quad flatpack (PGE) SM320VC33PGEA120EP SM320VC33PGEA120EP --55°C to 125°C 144-ball fine pitch Ball Grid Array (GNM) SM320VC33GNMM150EP SM320VC33GNMM150EP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 3 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 pinout 109 111 110 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 74 36 73 DV DD DVDD CLKR0 FSR0 VSS DR0 TRST TMS CVDD TDI TDO TCK VSS EMU0 EMU1 DVDD D0 D1 D2 D3 VSS D4 D5 DVDD D6 D7 CVDD D8 D9 VSS D10 D11 DVDD D12 D13 D14 D15 72 75 35 71 76 34 70 77 33 69 78 32 68 79 31 67 80 30 66 81 29 65 82 28 64 83 27 63 84 26 62 85 25 61 86 24 60 87 23 59 88 22 58 89 21 57 90 20 56 91 19 55 92 18 54 93 17 53 94 16 52 95 15 51 96 14 50 97 13 49 98 12 48 99 11 47 100 10 46 101 9 45 102 8 44 103 7 43 104 6 42 105 5 41 106 4 40 3 39 107 38 108 2 37 1 H1 H3 V SS STRB R/W DV DD IACK RDY CVDD HOLD HOLDA V SS D31 D30 D29 DVDD D28 D27 V SS D26 D25 D24 DV DD D23 D22 V SS D21 D20 CVDD D19 D18 DV DD D17 D16 V SS A20 VSS A19 A18 A17 DVDD A16 A15 VSS A14 A13 CVDD A12 A11 DVDD A10 A9 VSS A8 A7 A6 A5 DVDD A4 VSS A3 A2 CVDD A1 A0 DVDD PAGE3 PAGE2 VSS PAGE1 PAGE0 143 144 A21 DV DD A22 A23 V SS RSV0 RSV1 CVDD CLKMD0 CLKMD1 PLLV SS XIN XOUT PLLV DD EXTCLK DV DD SHZ RESET V SS MCBL/MP EDGEMODE CVDD INT0 INT1 INT2 INT3 V SS XF0 XF1 DV DD TCLK0 TCLK1 V SS DX0 FSX0 CLKX0 PGE PACKAGE†‡ (TOP VIEW) † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively. 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 PGE Terminal Assignments† (Sorted by Signal Name) SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER A0 30 D0 93 A1 29 D1 92 A2 27 D2 A3 26 D3 A4 24 A5 A6 SIGNAL NAME PIN NUMBER 31 R/W 42 37 RDY 45 91 43 RESET 127 90 53 RSV0 139 D4 88 60 RSV1 138 22 D5 87 69 SHZ 128 21 D6 85 77 STRB 41 A7 20 D7 84 86 TCK 98 A8 19 D8 82 94 TCLK0 114 A9 17 D9 81 108 TCLK1 113 A10 16 D10 79 115 TDI 100 A11 14 D11 78 129 TDO 99 A12 13 D12 76 143 TMS 102 A13 11 D13 75 DX0 111 TRST 103 A14 10 D14 74 EDGEMODE 124 2 A15 8 D15 73 EMU0 96 9 A16 7 D16 71 EMU1 95 18 A17 5 D17 70 EXTCLK 130 25 A18 4 D18 68 FSR0 106 34 A19 3 D19 67 FSX0 110 40 A20 1 D20 65 H1 38 49 A21 144 D21 64 H3 39 56 A22 142 D22 62 HOLD 47 A23 141 D23 61 HOLDA 48 CLKMD0 136 D24 59 IACK 44 80 CLKMD1 135 D25 58 INT0 122 89 CLKR0 107 D26 57 INT1 121 97 CLKX0 109 D27 55 INT2 120 105 12 D28 54 INT3 119 112 28 D29 52 MCBL/MP 125 118 46 D30 51 PAGE0 36 126 66 D31 50 PAGE1 35 83 DR0 104 PAGE2 33 XIN 133 6 PAGE3 32 XOUT 132 DVDD 15 PLLVDD‡ 131 XF0 117 23 PLLVSS‡ 134 XF1 116 CVDD 101 123 137 SIGNAL NAME PIN NUMBER DVDD VSS 63 72 140 † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 5 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 PGE Terminal Assignments† (Sorted by Pin Number) PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME 1 A20 37 DVDD 73 D15 109 CLKX0 2 VSS 38 H1 74 D14 110 FSX0 3 A19 39 H3 75 D13 111 DX0 4 A18 40 VSS 76 D12 112 VSS 5 A17 41 STRB 77 DVDD 113 TCLK1 6 DVDD 42 R/W 78 D11 114 TCLK0 7 A16 43 DVDD 79 D10 115 DVDD 8 A15 44 IACK 80 VSS 116 XF1 9 VSS 45 RDY 81 D9 117 XF0 10 A14 46 CVDD 82 D8 118 VSS 11 A13 47 HOLD 83 CVDD 119 INT3 12 CVDD 48 HOLDA 84 D7 120 INT2 13 A12 49 VSS 85 D6 121 INT1 14 A11 50 D31 86 DVDD 122 INT0 15 DVDD 51 D30 87 D5 123 CVDD 16 A10 52 D29 88 D4 124 EDGEMODE 17 A9 53 DVDD 89 VSS 125 MCBL/MP 18 VSS 54 D28 90 D3 126 VSS 19 A8 55 D27 91 D2 127 RESET 20 A7 56 VSS 92 D1 128 SHZ 21 A6 57 D26 93 D0 129 DVDD 22 A5 58 D25 94 DVDD 130 EXTCLK 23 DVDD 59 D24 95 EMU1 131 PLLVDD‡ 24 A4 60 DVDD 96 EMU0 132 XOUT 25 VSS 61 D23 97 VSS 133 XIN 26 A3 62 D22 98 TCK 134 PLLVSS‡ 27 A2 63 VSS 99 TDO 135 CLKMD1 28 CVDD 64 D21 100 TDI 136 CLKMD0 29 A1 65 D20 101 CVDD 137 CVDD 30 A0 66 CVDD 102 TMS 138 RSV1 31 DVDD 67 D19 103 TRST 139 RSV0 32 PAGE3 68 D18 104 DR0 140 VSS 33 PAGE2 69 DVDD 105 VSS 141 A23 34 VSS 70 D17 106 FSR0 142 A22 35 PAGE1 71 D16 107 CLKR0 143 DVDD 36 PAGE0 72 VSS 108 DVDD 144 A21 † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 GNM Terminal Assignments† (Sorted by Signal Name) SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER A0 J2 D0 G12 M1 R/W L4 A1 K2 D1 G10 N1 RDY M5 A2 K1 D2 F13 N4 RESET B7 A3 J4 D3 G11 N7 RSV0 B4 A4 H4 D4 H10 M8 RSV1 D5 A5 H3 D5 H13 A6 H1 D6 H12 A7 G4 D7 J10 A8 G1 D8 A9 G2 D9 A10 F3 D10 K13 A10 TDI E11 A11 F4 D11 K12 A6 TDO D13 A12 F2 D12 K10 A1 TMS E10 A13 E1 D13 M13 DX0 A12 TRST C13 A14 E2 D14 L11 EDGEMODE A7 B1 A15 E4 D15 L12 EMU0 F12 D1 A16 C1 D16 M12 EMU1 E12 G3 A17 C2 D17 L10 EXTCLK C6 J1 A18 D3 D18 K9 FSR0 C12 L2 A19 C3 D19 N11 FSX D10 M3 A20 B2 D20 M11 H1 L3 M6 A21 D4 D21 M10 H3 N2 L7 A22 A2 D22 K8 HOLD N5 A23 B3 D23 N9 HOLDA K5 CLKMD0 C5 D24 M9 IACK K4 K11 CLKMD1 B5 D25 L8 INT0 C8 G13 CLKR0 B13 D26 N8 INT1 B9 E13 CLKX0 B11 D27 M7 INT2 D8 A13 E3 D28 K7 INT3 A9 C11 J3 D29 L6 MCBL/MP B8 C9 L5 D30 N6 PAGE0 M2 C7 L9 D31 K6 PAGE1 N3 J13 DR0 D11 PAGE2 L1 XF0 B10 D2 PAGE3 K3 XF1 D9 F1 PLLVDD‡ A5 XIN B6 H2 PLLVSS‡ A4 XOUT D6 CVDD D12 A8 A3 DVDD SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER N12 SHZ D7 L13 STRB M4 H11 TCK F10 J11 F11 TCLK0 C10 J12 B12 TCLK1 A11 DVDD VSS N10 N13 C4 † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 7 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 GNM Terminal Assignments† (Sorted by Pin Number) PIN NUMBER SIGNAL NAME A1 DVDD A2 A22 A3 CVDD A4 PLLVSS A5 PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME PIN NUMBER SIGNAL NAME C11 VSS G10 D1 L4 R/W C12 FSR0 G11 D3 L5 CVDD C13 TRST G12 D0 L6 D29 D1 VSS G13 VSS L7 VSS PLLVDD D2 DVDD H1 A6 L8 D25 A6 DVDD D3 A18 H2 DVDD L9 CVDD A7 EDGEMODE D4 A21 H3 A5 L10 D17 A8 CVDD D5 RSV1 H4 A4 L11 D14 A9 INT3 D6 XOUT H10 D4 L12 D15 A10 DVDD D7 SHZ H11 DVDD L13 DVDD A11 TCLK1 D8 INT2 H12 D6 M1 DVDD A12 DX D9 XF1 H13 D5 M2 PAGE0 A13 VSS D10 FSX J1 VSS M3 VSS B1 VSS D11 DR0 J2 A0 M4 STRB B2 A20 D12 CVDD J3 CVDD M5 RDY B3 A23 D13 TDO J4 A3 M6 VSS B4 RSV0 E1 A13 J10 D7 M7 D27 B5 CLKMD1 E2 A14 J11 D8 M8 DVDD B6 XIN E3 CVDD J12 D9 M9 D24 B7 RESET E4 A15 J13 CVDD M10 D21 B8 MCBL/MP E10 TMS K1 A2 M11 D20 B9 INT1 E11 TDI K2 A1 M12 D16 B10 XF0 E12 EMU1 K3 PAGE3 M13 D13 B11 CLKX0 E13 VSS K4 IACK N1 DVDD B12 DVDD F1 DVDD K5 HOLDA N2 H3 B13 CLKR F2 A12 K6 D31 N3 PAGE1 C1 A16 F3 A10 K7 D28 N4 DVDD C2 A17 F4 A11 K8 D22 N5 HOLD C3 A19 F10 TCK K9 D18 N6 D30 C4 VSS F11 DVDD K10 D12 N7 DVDD C5 CLKMD0 F12 EMU0 K11 VSS N8 D26 C6 EXTCLK F13 D2 K12 D11 N9 D23 C7 VSS G1 A8 K13 D10 N10 VSS C8 INT0 G2 A9 L1 PAGE2 N11 D19 C9 VSS G3 VSS L2 VSS N12 DVDD C10 TCLK0 G4 A7 L3 H1 N13 VSS † DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU. ‡ PLLV DD and PLLVSS are isolated PLL supply pins that should be externally connected to CVDD and VSS, respectively. 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 Terminal Functions TERMINAL NAME QTY TYPE† DESCRIPTION CONDITIONS WHEN SIGNAL IS Z TYPE‡ PRIMARY-BUS INTERFACE 32-bit data port S Data port bus keepers. (See Figure 8) S D31 D0 D31--D0 32 I/O/Z A23--A0 24 O/Z 24-bit address port H R S H R S H R R/W 1 O/Z Read/write. R/W is high when a read is performed and low when a write is performed over the parallel interface. STRB 1 O/Z Strobe. For all external-accesses S H PAGE0 -PAGE3 1 O/Z Page strobes. Four decoded page strobes for external access S H RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction completion. I Hold. When HOLD is a logic low, any ongoing transaction is completed. A23--A0, D31--D0, STRB, and R/W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until the NOHOLD bit of the primary-bus-control register is set. O/Z Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD. HOLDA indicates that A23--A0, D31--D0, STRB, and R/W are in the high-impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set. HOLD HOLDA 1 1 R S CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. EDGEMODE 1 I Edge mode. Enables interrupt edge mode detection. INT3--INT0 4 I External interrupts IACK 1 O/Z MCBL/MP 1 I Microcomputer Bootloader/microprocessor mode-select Internal acknowledge. IACK is generated by the IACK instruction. IACK can be used to indicate when a section of code is being executed. SHZ 1 I Shutdown high impedance. When active, SHZ places all pins in the high-impedance state. SHZ can be used for board-level testing or to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support interlocked processor instruction. CLKR0 1 I/O/Z CLKX0 1 DR0 DX0 S S R Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 transmitter. S R 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R S R S R SERIAL PORT 0 SIGNALS FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive process using DR0. FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit process using DX0. † I = input, O = output, Z = high-impedance state S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling. Four 0.1 μF for CV DD and eight 0.1 μF for DVDD. ‡ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 9 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 Terminal Functions (Continued) TERMINAL NAME QTY CONDITIONS WHEN SIGNAL IS Z TYPE‡ TYPE† DESCRIPTION S R S R TIMER SIGNALS TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an output, TCLK0 outputs pulses generated by timer 0. TCLK1 1 I/O/Z Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an output, TCLK1 outputs pulses generated by timer 1. H1 1 O/Z External H1 clock S H3 1 O/Z External H3 clock S SUPPLY AND OSCILLATOR SIGNALS CVDD 8 I +VDD. Dedicated 1.8-V power supply for the core CPU. All must be connected to a common supply plane.§ DVDD 16 I +VDD. Dedicated 3.3-V power supply for the I/O pins. All must be connected to a common supply plane.§ VSS 18 I Ground. All grounds must be connected to a common ground plane. PLLVDD 1 I Internally isolated PLL supply. Connect to CVDD (1.8 V) PLLVSS 1 I Internally isolated PLL ground. Connect to VSS EXTCLK 1 I External clock. Logic level compatible clock input. If the XIN/XOUT oscillator is used, tie this pin to ground. XOUT 1 O Clock out. Output from the internal-crystal oscillator. If a crystal is not used, XOUT should be left unconnected. XIN 1 I Clock in. Internal-oscillator input from a crystal. If EXTCLK is used, tie this pin to ground. CLKMD0, CLKMD1 2 I Clock mode select pins RSV0 -- RSV1 2 I Reserved. Use individual pullups to DVDD. EMU1--EMU0 2 I/O TDI 1 I Test data input TDO 1 O Test data output TCK 1 I Test clock TMS 1 I Test mode select TRST 1 I Test reset JTAG EMULATION Emulation pins 0 and 1, use individual pullups to DVDD † I = input, O = output, Z = high-impedance state ‡ S = SHZ active, H = HOLD active, R = RESET active § Recommended decoupling. Four 0.1 μF for CV DD and eight 0.1 μF for DVDD. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 functional block diagram RAM Block 0 (1K × 32) Cache (64 × 32) 32 24 PAGE0 PDATA Bus PAGE1 PAGE2 PAGE3 RDY HOLD HOLDA STRB R/W D31--D0 A23--A0 PADDR Bus RAM Block 1 (1K × 32) 32 24 24 RAM Block 2 (16K × 32) Boot Loader 32 24 32 24 RAM Block 3 (16K × 32) 32 24 32 MUX MUX DDATA Bus DADDR1 Bus DADDR2 Bus DMADATA Bus DMAADDR Bus 32 24 24 32 32 24 24 Peripheral Data Bus DMA Controller Global-Control Register DestinationAddress Register REG1 TransferCounter Register REG2 REG1 CPU1 32 32 40 40 Timer 0 40 32 40 ExtendedPrecision Registers (R7--R0) 40 TCLK0 40 BK Timer 1 24 32 32 Global-Control Register ARAU1 TCLK1 24 24 Auxiliary Registers (AR0--AR7) POST OFFICE BOX 1443 Timer-Counter Register Port Control 32 Other Registers (12) Timer-Period Register 24 32 32 Timer-Period Register Timer-Counter Register DISP0, IR0, IR1 ARAU0 Data-Transmit Register Global-Control Register ALU 40 Receive/Transmit (R/X) Timer Register Data-Receive Register 32-Bit Barrel Shifter Multiplier 40 CLKX0 FSR0 DR0 CLKR0 Peripheral Data Bus Controller CPU2 FSX0 DX0 Serial-Port-Control Register Peripheral Address Bus Source-Address Register CPU1 REG2 JTAG Emulation TCK TMS TRST EXTCLK XOUT XIN H1 H3 CLKMD(0,1) IR PC PLL CLK RSV(0,1) SHZ EDGEMODE RESET INT(3--0) IACK MCBL/MP XF(1,0) TDI TDO EMU0 EMU1 Serial Port 0 MUX STRB-Control Register 32 • HOUSTON, TEXAS 77251--1443 11 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 memory map 0h 03Fh 040h Reset, Interrupt, Trap Vector, and Reserved Locations (64) (External STRB Active) 0h Reserved for Bootloader Operations FFFh 1000h External STRB Active (8M Words -- 64 Words) 400000h Boot 1 Boot 2 7FFFFFh 800000h 7FFFFFh 800000h RAM Block 2 (16K Words Internal) RAM Block 2 (16K Words Internal) 803FFFh 804000h 803FFFh 804000h RAM Block 3 (16K Words Internal) 807FFFh 808000h External STRB Active (8M Words -4K Words) RAM Block 3 (16K Words Internal) Peripheral Bus Memory-Mapped Registers (6K Words Internal) 8097FFh 809800h 807FFFh 808000h 8097FFh 809800h Peripheral Bus Memory-Mapped Registers (6K Words Internal) RAM Block 0 (1K Words Internal) 809BFFh 809C00h RAM Block 0 (1K Words Internal) 809BFFh 809C00h RAM Block 1 (1K Words Internal) RAM Block 1 (1K Words Internal) 809FFFh 80A000h FFFFFFh External STRB Active (8M Words -- 40K Words) (a) Microprocessor Mode User-Program Interrupt and Trap Branch Table 809FC0h 809FC1h 809FFFh 80A000h 63 Words FFF000h Boot 3 FFFFFFh External STRB Active (8M Words -40K Words) (b) Microcomputer/Bootloader Mode NOTE A: STRB is active over all external memory ranges. PAGE0 to PAGE3 are configured as external bus strobes. These are simple decoded strobes that have no configuration registers and are active only during external bus activity over the following ranges: Name PAGE0 PAGE1 PAGE2 PAGE3 STRB Active range 0000000h – 03FFFFFh 0400000h – 07FFFFFh 0800000h – 0BFFFFFh 0C00000h – 0FFFFFFh 0000000h – 0FFFFFFh Figure 1. SM320VC33-EP Memory Maps 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 memory map (continued) 00h Reset 809FC1h 01h INT0 809FC2h 02h INT1 03h INT2 04h INT3 05h XINT0 06h RINT0 809FC6h 08h Reserved 809FC8h 09h TINT0 809FC9h 0Ah TINT1 809FCAh 0Bh DINT 809FCBh 0Ch 1Fh Reserved 809FCCh 809FDFh Reserved 20h TRAP 0 809FE0h TRAP 0 3Bh TRAP 27 809FFBh TRAP 27 3Ch 3Fh Reserved 07h INT0 INT1 809FC3h INT2 809FC4h INT3 809FC5h XINT0 RINT0 809FC7h Reserved TINT0 TINT1 DINT 809FFCh Reserved 809FFFh (a) Microprocessor Mode (b) Microcomputer/Bootloader Mode Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 13 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 memory map (continued) 808000h DMA Global Control 808004h DMA Source Address 808006h DMA Destination Address 808008h DMA Transfer Counter 808020h Timer 0 Global Control 808024h Timer 0 Counter 808028h Timer 0 Period Register 808030h Timer 1 Global Control 808034h Timer 1 Counter 808038h Timer 1 Period Register 808040h Serial Global Control 808042h FSX/DX/CLKX Serial Port Control 808043h FSR/DR/CLKR Serial Port Control 808044h Serial R/X Timer Control 808045h Serial R/X Timer Counter 808046h Serial R/X Timer Period Register 808048h Data-Transmit 80804Ch Data-Receive 808064h Primary-Bus Control NOTE A: Shading denotes reserved address locations. Figure 3. Peripheral Bus Memory-Mapped Registers clock generator The clock generator provides clocks to the VC33 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The PLL circuit generates the device clock by multiplying the reference clock frequency by a x5 scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 PLL and clock oscillator control The clock mode control pins are decoded into four operational modes as shown in Figure 4. These modes control clock divide ratios, oscillator, and PLL power (see Table 2). When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock reference into EXTCLK, or 1--20 MHz crystals and ceramic resonators with the oscillator circuit. The two clock sources include: D A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins and EXTCLK is grounded. D An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT is left unconnected and XIN is grounded. When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL is a simple x5 reference multiplier with bypass and power control. The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOWPOWER), or clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state. A divide-by-two SM320C31 equivalent mode of operation is also provided. In this case, the clock output reference is further divided by two with clock synchronization being determined by the timing of RESET falling relative to the present H1/H3 state. Clock & Crystal OSC PLL Clock Divider MAXSPEED/ LOWPOWER EXTCLK IDLE2 XOUT M U X XOR S1 RF X5 PLL XIN X1, 1/16, Off 1/2 M U X CPU CLOCK Oscillator Enable CLKMD0 CLKMD1 PLL PWR and Bypass SEL C31 DIV2 Mode Figure 4. Clock Generation Table 2. Clock Mode Select Pins CLKMD0 CLKMD1 FEEDBACK PLLPWR 0 0 0 Off Off 1 1 On Off 1/2 Oscillator enabled 1 0 On Off 1 Oscillator enabled 1 1 On On 5 2 mA @ 60 MHz, 1.8-V PLL power. Oscillator enabled POST OFFICE BOX 1443 RATIO NOTES Fully static, very low power • HOUSTON, TEXAS 77251--1443 15 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 PLL and clock oscillator control (continued) Typical crystals in the 8--30 MHz range have a series resistance of 25 Ω, which increases below 8 MHz. To maintain proper filtering and phase relationships, Rd and Zout of the oscillator circuit should be 10x--40x that of the crystal. A series compensation resistor (Rd), shown in Figure 5, is recommended when using lower frequency crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output impedance, C1 load capacitor, and Rd (if present). The crystal and C2 input load capacitor then refilters this signal, resulting in a XIN signal that is 75--85% of the oscillator supply voltage. NOTE: Some ceramic resonators are available in a low-cost, three-terminal package that includes C1 and C2 internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals. NOTE: Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5. A similar filter can be used to isolate the PLLVSS, as shown in Figure 6. PLLVDD can also be directly connected to CVDD. Table 3. Typical Crystal Circuit Loading † FREQUENCY (MHz) Rd (Ω) C1 (pF) C2 (pF) CL† (pF) RL† (Ω) 2 4.7k 18 18 12 200 5 2.2k 18 18 12 60 10 470 15 15 12 30 15 0 15 12 12 25 20 0 9 9 10 25 CL and RL are typical internal series load capacitance and resistance of the crystal. XOUT XIN EXTCLK PLLVSS CVDD PLLVDD Rd 100 Ω Crystal C1 0.1 μF C2 Figure 5. Self-Oscillation Mode 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 0.01 μF SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 PLL isolation The internal PLL supplies can be directly connected to CVDD and VSS (0 Ω case) or fully isolated as shown in Figure 6. The RC network prevents the PLL supplies from turning high frequency noise in the CVDD and VSS supplies into jitter. CVDD 0 --100 Ω PLLVDD 0.1 μF 0.01 μF PLLVSS 0 --100 Ω VSS Figure 6. PLL Isolation Circuit Diagram clock and PLL considerations on initialization On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER or IDLE2, or the PLL could be in an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which the device will synchronously terminate any external activity. The 5x Fclkin PLL of the SM320VC33--EP contains an 8-bit PLL--LOCK counter which will cause the PLL to output a frequency of Fclkin/2 during the initial ramp. This counter, however, does not increment while RESET is low or in the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of reset for the PLL to output to clear this counter. The setup and behavior that is seen is as follows. Power is applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still low) and the PLL appears to lock on to the input clock, producing the expected x5 output frequency. RESET is driven high and the PLL output immediately drops to Fclkin/2 for up to 256 input cycles or 128 of the Fclkin/2 output cycles. The PLL/CPU clock then switches to x5 mode. The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU will run slow for up to the first 128 cycles after reset goes high. Once the PLL has stabilized, the counter will remain cleared and subsequent resets will not exhibit this condition. power sequencing considerations Though an internal ESD and CMOS latchup protection diode exists between CVDD and DVDD, it should not be considered a current-carrying device on power up. An external Schottky diode should be used to prevent CVDD from exceeding DVDD by more than 0.7 V. The effect of this diode during power up is that if CVDD is powered up first, DVDD will follow by one diode drop even when the DVDD supply is not active. Typical systems using LDOs of the same family type for both DVDD and CVDD will track each other during power up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin can be used to asynchronously disable all outputs. RESET should not be used in this case since some signals require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 17 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 EDGEMODE When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the logic-low and logic-high states is sufficient. When EDGEMODE = 0, a logic-low interrupt pin will continually set the corresponding interrupt flag. The CPU or DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine (ISR), effectively lengthening the maximum ISR width. After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload operation. Delay RESET EDGEMODE INTn D Q D Q D Q D Q D Q S Q IF Bit R CPU Reset H1 CPU Set H3 Figure 7. EDGEMODE and Interrupt Flag CIrcuit reset operation When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in progress. This can take as many as 10 CPU cycles, after which, the address, data, and control pins will be in an inactive or high-impedance state. When both RESET and SHZ are applied, the device immediately enters the reset state with the pins held in high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system conflicts. PAGE0 -- PAGE3 select lines To facilitate simpler and higher speed connection to external devices, the SM320VC33-EP includes four predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB and are active only during external accesses over the ranges shown in Table 4. All external bus accesses are controlled by a single bus control register. Table 4. PAGE0 -- PAGE3 Ranges 18 START END PAGE0 0x000000 0x3FFFFF PAGE1 0x400000 0x7FFFFF PAGE2 0x800000 0xBFFFFF PAGE3 0xC00000 0xFFFFFF POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 data bus I/O buffer The circuit shown in Figure 8 is incorporated into each data pin to lightly “hold” the last driven value on the data bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a three-state driver with nominal 15 kΩ output resistance which is fed back to the input in a positive feedback configuration. The resistance isolated driver then pulls the output in one direction or the other keeping the last driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low. R/W 30 Ω Internal Data Bus External Data Bus Pin 15 kΩ SHZ Bus keeper Figure 8. Bus Keeper Circuit For an external device to change the state of these pins, it must be able to drive a small dc current until the driver threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver and assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DVDD supply voltage. The typical output impedance of 30 Ω for all SM320VC33-EP I/O pins is easily capable of meeting this requirement. using external logic with the READY pin The key to designing external wait-state logic is the internal bus control register and associated internal logic that logically combines the external READY pin with the much faster on-chip bus control logic. This essentially allows slow external logic to interact with the bus while easily meeting the READY input timings. It is also relevant to mention that the combined ready signals are sampled on the rising edge of the internal H1 clock. Please refer to Figure 9 for the following examples. example 1 A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the READY pin and selecting the AND option. When the tied back address is low, the bus runs with 0 wait states. When the tied back address is high, the bus is controlled by the internal wait-state counter. By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic to affect the feedback path. example 2 An N--WTCNT minimum wait-state decoder can also be created by tying back an address line to READY and logically ORing it with the internal bank compare and wait count signals. When the address pin is low, bus timing is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the bus can run no faster than the WTCNT counter and is extended as long as READY is held high. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 19 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 A23 A22 PAGE_0 PAGE_1 PAGE_2 PAGE_3 Decode Device Enable Pins Bus_Enable_Strobe, 0 = Active STRB Pin 0 = Bus Idle To C31 Style Decoder (C31 Compatibility) H3 External Bus Interface Abus D Q N--Bit Bank Compare BUS_READY Q D H1 Abus_old H3 R N_Wait Counter 1 2 3 0 R/W R/W Pin Figure 9. Internal Ready Logic, Simplified Diagram 20 READY Pin POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 example 2 (continued) Table 5. MUX Select (Bus Control Register Bits 4 and 3) BIT 4 BIT 3 0 0 Ignore internal wait counter and use only external READY RESULTS 0 1 Use only internal wait counter and ignore ready pin 1 0 Logically AND internal wait counter with ready pin 1 1 Logically OR internal wait counter with ready pin (reset default) posted writes External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes. Therefore, if the application code is executing internally, it can perform a very slow external write with no penalty since the bus acts like it has a one-level-deep write FIFO. data bus I/O buffer The circuit shown in Figure 10 is incorporated into each data pin to lightly “hold” the last driven value on the data bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a three-state driver with nominal 15 kΩ output resistance which is fed back to the input in a positive feedback configuration. The resistance isolated driver then pulls the output in one direction or the other keeping the last driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low. R/W Internal Data Bus 30 Ω External Data Bus Pin 15 kΩ SHZ Bus keeper Figure 10. Bus Keeper Circuit For an external device to change the state of these pins, it must be able to drive a small dc current until the driver threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver and assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DVDD supply voltage. The typical output impedance of 30 Ω for all SM320VC33-EP I/O pins is easily capable of meeting this requirement. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 21 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 bootloader operation When MCBL/MP = 1, an internal ROM is decoded into the address range of 0x000000--0x000FFF. Therefore, when reset occurs, execution begins within the internal ROM program and vector space. No external activity will be evident until one of the boot options is enabled. These options are enabled by pulling an external interrupt pin low, which the boot-load software then detects, causing a particular routine to be executed (see Table 6). Table 6. INT0 -- INT3 Sources ACTIVE INTERRUPT ADDRESS/SOURCE WHERE BOOT DATA IS READ FROM DATA FORMAT INT0 0x001000 8, 16, or 32-bit width INT1 0x400000 8, 16, or 32-bit width INT2 0xFFF000 8, 16, or 32-bit width INT3 Serial Port 32-bit, external clock, and frame synch When MCBL/MP = 1, the reset and interrupt vectors are hard-coded within the internal ROM. Since this is a read-only device, these vectors cannot be modified. To enable user-defined interrupt routines, the internal vectors contain fixed values that point to an internal section of SRAM beginning at 0x809FC1. Code execution begins at these locations so it is important to place branch instructions (to the interrupt routine) at these locations and not vectors. The bootloader program requires a small stack space for calls and returns. Two SRAM locations at 0x809800 and 0x809801 are used for this stack. Data should not be boot loaded into these locations as this will corrupt the bootloader program run-time stack. After the boot-load operation is complete, a program can reclaim these locations. The simplest solution is to begin a program stack or uninitialized data section at 0x809800. For additional detail on bootloader operation including the bootloader source code, see the TMS320C3x User’s Guide (literature number SPRU031). A bit I/O line or external logic can be used to safely disable the MCBL mode after bootloading is complete. However, to ensure proper operation, the CPU should not be currently executing code or using external data as the change takes place. In the following example, the XF0 pin is 3-state on reset, which allows the pullup resistor to place the DSP in MCBL mode. The following code, placed at the beginning of an application then causes the XF0 pin to become an active-logic-low output, changing the DSP mode to MP. The cache-enable and RPTS instructions are used since they cause the LDI instruction to be executed multiple times even though it has been fetched only once (before the mode change). In other words, the RPTS instruction acts as a one-level-deep program cache for externally executed code. If the application code is to be executed from internal RAM, no special provisions are needed. LDI 8000h,ST ; Enable the cache RPTS 4 ; RPTS will fetch the following opcode 1 time LDI 2h, IOF ; Drive MCBL/MP=0 for several cycles allowing ; the pipeline to clear RESET RESET SM320VC33-EP DVDD RPU XF0 MCBL/MP Figure 11. Changing Bootload Select Pin 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 JTAG emulation Though the SM320VC33-EP contains a JTAG debug port which allows multiple JTAG-enabled chips to be daisy-chained, boundary scan of the pins is not supported. If the pin scan path is selected, it is routed through a null register with a length of one. For additional information concerning the emulation interface, see JTAG/MPSD Emulation Technical Reference (literature number SPDU079). designing a target system emulator connector (14-pin header) JTAG target devices support emulation through a dedicated emulation port. This port is a superset of the test access port standard and is accessed by the emulator. To communicate with the emulator, the target system must have a 14-pin header (two rows of seven pins) with the connections that are shown in Figure 12. Table 7 describes the emulation signals. TMS 1 2 TRST TDI 3 4 GND PD (VCC) 5 6 no pin (key)† TDO 7 8 GND TCK_RET † 9 10 GND TCK 11 12 GND EMU0 13 14 EMU1 Header Dimensions: Pin-to-pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in. square post Pin length, 0.235-in. nominal While the corresponding female position on the cable connector is plugged to prevent improper connection, the cable lead for pin 6 is present in the cable and is grounded, as shown in the schematics and wiring diagrams in this document. Figure 12. 14-Pin Header Signals and Header Dimensions Table 7. 14-Pin Header Signal Descriptions SIGNAL DESCRIPTION EMULATOR† STATE TARGET† STATE I TMS‡ Test mode select O TDI Test data input O I TDO Test data output I O TCK Test clock. TCK is a 10.368-MHz clock source from the emulation cable pod. This signal can be used to drive the system test clock O I TRST§ Test reset O I EMU0‡¶ Emulation pin 0 I I/O EMU1‡¶ Emulation pin 1 I I/O PD(VCC) Presence detect. Indicates that the emulation cable is connected and that the target is powered up. PD should be tied to VCC in the target system. I O TCK_RET Test clock return. Test clock input to the emulator. May be a buffered or unbuffered version of TCK. I O GND Ground † I = input; O = output Use 1--50K pullups for TMS, EMU0 and EMU1. § Use 1--50K pulldown for TRST. Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can be left floating. In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on electrical current considerations.) ¶ EMU0 and EMU1 are I/O drivers configured as open-drain (open-collector) drivers. They are used as bidirectional signals for emulation global start and stop. ‡ POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 23 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 designing a target system emulator connector (14-pin header) (continued) Although other headers can be used, recommended parts include: DuPont Connector Systems part numbers: 65610--114 straight header, unshrouded 65611--114 67996--114 67997--114 JTAG emulator cable pod logic Figure 13 shows a portion of the emulator cable pod. The functional features of the pod are as follows: D Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application. By default, these signals are not terminated. D Signal TCK is driven with a 74LVT240 device. Because of the high-current drive (32 mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied to TCK_RET, the parallel terminator in the pod can be used. D Signals TMS and TDI can be generated from the falling edge of TCK_RET, according to the bus slave device timing rules. D Signals TMS and TDI are series-terminated to reduce signal reflections. D A 10.368-MHz test clock source is provided. Other test clocks may be used for greater flexibility. +5 V 180 Ω 74F175 270 Ω Q JP1 D TDO (Pin 7) Q 74LVT240 10.368 MHz Y Y GND (Pins 4,6,8,10,12) A 33 Ω 33 Ω TMS (Pin 1) Y TDI (Pin 3) Y EMU0 (Pin 13) 74AS1034 EMU1 (Pin 14) TCK (Pin 11){ +5 V 180 Ω 270 Ω JP2 TCK_RET (Pin TRST (Pin 2) 74AS1004 9){ PD(VCC) (Pin 5) 100 Ω † RESIN TL7705A The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system test clock source. Figure 13. JTAG Emulator Cable Pod Interface 24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 device and development support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ DSP family devices and support tools. Each TMS320™ DSP member has one of three prefixes: TMX, TMP, or TMS, and each SMJ320™ DSP member has one of three prefixes: SMX, SM, or SMJ. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below. Device development evolutionary flow: SMX Experimental device that is not necessarily representative of the final device’s electrical specifications TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification SM/SMJ Fully-qualified production device Support tool development evolutionary flow: TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer: “Developmental product is intended for internal evaluation purposes.” TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability of the device has been demonstrated fully. TI’s standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GNM) and temperature range (for example, M). Figure 14 provides a legend for reading the complete device name for any TMS320™ DSP family member. TMS320 is a trademark of Texas Instruments. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 25 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 device and development support tool nomenclature (continued) SM PREFIX SMX = TMP = TMS = SMJ = SMQ= SM = 320 VC 33 GNM M 150 EP experimental device prototype device qualified device MIL-PRF-38535 (QML) QML Plastic device Commercial processing ENHANCED PLASTIC SPEED 120 = 120 MFLOPS 150 = 150 MFLOPS DEVICE FAMILY 320 = TMS320 Family TEMPERATURE RANGE A = Extended temperature M = Military TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM LC = Low-Voltage CMOS (3.3 V) VC = Low-Voltage CMOS [3.3 V (2.5 V or 1.8 V core)] UC= Ultra Low-Voltage CMOS [1.8 V (1.5 V core)] PACKAGE TYPE† PGE = 144-pin plastic LQFP HFG = 164-pin ceramic QFP GNM = 144-pin ceramic BGA, non-hermetic DEVICE 3x DSP: 4x DSP: 6x DSP: 30 31 32 33 40 44 6201 6201 6701 6211 NOTE: Not all speed, package, process, and temperature combinations are available. † QFP = Quad Flat Package LQFP = Low-Profile Quad Flat Package BGA = Ball Grid Array Figure 14. TMS320™ DSP Device Nomenclature 26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 absolute maximum ratings over specified temperature range (unless otherwise noted)† Supply voltage range, DVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4 V Supply voltage range, CVDD‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 2.4 V Input voltage range, VI§ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --1 V to 4.6 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.6 V Continuous power dissipation (worst case)¶ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Operating case temperature range, TC (PGE package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 100°C TC (GNM package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 125°C Storage temperature range, Tstg# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 55°C to 150°C † ‡ § ¶ # Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS. Absolute dc input level should not exceed the DVDD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns, < 10 mA, and < 1 V amplitude is permissable. Actual operating power is much lower. This value was obtained under specially produced worst-case test conditions for the SM320VC33-EP, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to the external data and address buses at the maximum possible rate with a capacitive load of 30 pF. See normal (ICC) current specification in the electrical characteristics table and also read TMS320C3x General-Purpose Applications (literature number SPRU194). Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging. recommended operating conditions‡||k MIN CVDD Supply voltage for the core CPUh NOM MAX 1.8 1.89 V 3 3.3 3.6 V pins◊ DVDD Supply voltage for the I/O VSS Supply ground VIH High-level input voltage 0.7 x DVDD DVDD + 0.3§ VIL Low-level input voltage --0.3§ 0.3 x DVDD IOH High-level output current IOL Low-level output current TC Operating case temperature temperat re CL Capacitive load per output pin UNIT 1.71 0 V V V 4 mA 4 mA A suffix --40 100 M suffix --55 125 30 °C pF ‡ All voltage values are with respect to VSS. § Absolute dc input level should not exceed the DV DD or VSS supply rails by more than 0.3 V. An instantaneous low current pulse of < 2 ns, < 10 mA, and < 1 V amplitude is permissable. || All inputs and I/O pins are configured as inputs. k All input and I/O pins use a Schmidt hysteresis inputs except SHZ and D0--D31. Hysteresis is approximately 10% of DVDD and is centered at 0.5 x DVDD. h CVDD should not exceed DVDD by more than 0.7 V. (Use a Schottky clamp diode between these supplies.) ◊ DVDD should not exceed CVDD by more than 2.5 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 27 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)† TEST CONDITIONS‡ PARAMETER VOH High-level output voltage DVDD = MIN, IOH = MAX VOL Low-level output voltage DVDD = MIN, IOL = MAX IZ High-impedance current TC = 25°C, DVDD = MAX II Input current TC = 25°C, VI = VSS to DVDD IIPU Input current (with internal pullup) Inputs with internal pullups¶ IIPD Input current (with internal pulldown) Inputs with internal pulldowns¶ pullup# MIN TYP§ MAX 2.4 V 0.4 V --5 +5 μA --5 +5 μA --600 10 μA 600 --10 μA --600 10 μA 600 --10 μA IBKU Input current (with bus keeper) IBKD Input current (with bus keeper) pulldown# IDDD Supply current, current pins||k TC = 25 25°C, C, DVDD = MAX fx = 60 MHz, VC33-120 20 120 fx = 75 MHz, VC33-150 25 260 IDDC Supply current, current core CPU||k TC = 25 25°C, C, CVDD = MAX fx = 60 MHz, VC33-120 50 80 fx = 75 MHz, VC33-150 60 215 IDD IDLE2, Supply current, IDDD plus IDDC Bus keeper opposes until conditions match PLL enabled, oscillator enabled 2 PLL disabled, oscillator enabled 500 PLL disabled, oscillator disabled, FCLK = 0 Ci Input capacitance Co Output capacitance UNIT mA mA mA μA A 50 All inputs except XIN 10* XIN 10* 10* pF pF * Not production tested † All voltage values are with respect to V . SS ‡ For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. § For VC33, all typical values are at DV DD = 3.3, CVDD = 1.8 V, TC (case temperature) = 25°C. ¶ Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST. # Pins D0--D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 8). || Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the maximum rate possible. See TMS320C3x General-Purpose Applications (literature number SPRU194). k fx is the PLL output clock frequency. PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Ω VLoad CT Output Under Test IOH Where: IOL = 4 mA (all outputs) for dc levels test. IO and IOH are adjusted during ac timing analysis to achieve an ac termination of 50 Ω VLOAD = DVDD/2 CT = 40-pF typical load-circuit capacitance Figure 15. Test Load Circuit 28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows, unless otherwise noted: Lowercase subscripts and their meanings Letters and symbols and their meanings a access time H High c cycle time (period) L Low d delay time V Valid dis disable time Z High Impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) x unknown, changing, or don’t care level Additional symbols and their meaning A Address lines (A23--A0) H H1 and H3 ASYNCH Asynchronous reset signals (XF0, XF1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, TCLK0, and TCLK1) HOLD HOLD CLKX CLKX0 HOLDA HOLDA CLKR CLKR0 IACK IACK CONTROL Control signals INT INT3--INT0 D Data lines (D31--D0) PAGE PAGE0--PAGE3 DR DR RDY RDY DX DX RW R/W EXTCLK EXTCLK RW R/W FS FSX/R RESET RESET FSX FSX0 S STRB FSR FSR0 SCK CLKX/R GPI General-purpose input SHZ SHZ GPIO General-purpose input/output; peripheral pin (CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, TCLK0, and TCLK1) TCLK TCLK0, TCLK1, or TCLKx GPO General-purpose output XF XF0, XF1, or XFx H1 H1 XF0 XF0 H3 H3 XF1 XF1 XIN XIN POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 29 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 phase-locked loop (PLL) circuit timing phase-locked loop characteristics using EXTCLK or on-chip crystal oscillator† PARAMETER MIN MAX UNIT Fpllin Frequency range, PLL input 5* 15* MHz Fpllout Frequency range, PLL output 25* 75* MHz Ipll PLL current, CVDD supply 2* mA Ppll PLL power, CVDD supply 5* mW PLLdc PLL output duty cycle at H1 PLLJ PLLLOCK 45* 55* % PLL output jitter, Fpllout = 25 MHz 400* ps PLL lock time in input cycles 1000 cycles * Not production tested † Duty cycle is defined as 100*t /(t +t )% 1 1 2 To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have an input duty cycle of between 40% and 60% for proper operation. 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 clock circuit timing The following table defines the timing parameters for the clock circuit signals. circuit parameters for on-chip crystal oscillator† (see Figure 16) PARAMETER MIN TYP MAX UNIT 20* MHz 50 60* %VO 300 500* kΩ VO Oscillator internal supply voltage CVDD FO Fundamental mode frequency range Vbias DC bias point (input threshold) 40* Rfbk Feedback resistance 100* Rout Small signal ac output impedance 250* 500 1000* Vxoutac The ac output voltage with test crystal‡ 85 %VO Vxinac The ac input voltage with test crystal‡ 85 %VO Vxoutl Vxin = Vxinh, Ixout = 0, FO=0 (logic input) VSS -- 0.1* VSS + 0.3* V Vxouth Vxin = Vxinl, Ixout = 0, FO=0 (logic input) CVDD -- 0.3* CVDD + 0.1* V Vinl When used for logic level input, oscillator enabled --0.3* 0.2 x VO* V Vinh When used for logic level input, oscillator enabled 0.8 x VO* DVDD + 0.3* V Vxinh When used for logic level input, oscillator disabled 0.7 x DVDD DVDD + 0.3 V Cxout XOUT internal load capacitance 2* 3 5* pF Cxin XIN internal load capacitance 2* 3 5* pF td(XIN-H1) Delay time, XIN to H1 x1 and x0.5 modes 2 5.5 8 ns Iinl Input current, feedback enabled, Vil = 0 50* μA Iinh Input current, feedback enabled, Vil = Vih --50* μA 1* V Ω * Not production tested † This circuit is intended for series resonant fundamental mode operation. ‡ Signal amplitude is dependent on the crystal and load used. Rd XOUT ROUT CXOUT C1 Rfbk Crystal VO XIN CXIN C2 To internal clock generator NOTE A: See Table 3 for value of Rd. Figure 16. On-Chip Oscillator Circuit POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 31 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 clock circuit timing (continued) The following tables define the timing requirements and switching characteristics for EXTCLK. timing requirements for EXTCLK, all modes (see Figure 17 and Figure 18) MIN tr(EXTCLK) Rise time, time EXTCLK tf(EXTCLK) Fall time time, EXTCLK tw(EXTCLKL) tw(EXTCLKH) tdc(EXTCLK) tc(EXTCLK) Fext Pulse duration, EXTCLK low Pulse duration, EXTCLK high Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)] Cycle time, EXTCLK Frequency range, 1/tc(EXTCLK) MAX F = Fmax, x0.5 and x1 modes 1* F < Fmax 4* F = Fmax, x0.5 and x1 modes 1* F < Fmax 4* x5 mode 21* x1 mode 5.5* x0.5 mode 4.0* UNIT ns ns ns x5 mode 21* x1 mode 5.5* x0.5 mode 4.0* x5 PLL mode 40* x1 and x0.5 modes, F = max 45 55 x1 and x0.5 modes, F = 0 Hz 0* 100* 200* ns 60* x5 mode 66.7* x1 mode 13.3 x0.5 mode 10* x5 mode 5* x1 mode 0 75 x0.5 mode 0* 100* % ns 15* MHz * Not production tested switching characteristics for EXTCLK over recommended operating conditions, all modes (see Figure 17 and Figure 18) PARAMETER Vmid MIN Mid-level, used to measure duty cycle TYP MAX 0.5 x DVDD UNIT V x1 mode 2* 4.5 7* x0.5 mode 2* 4.5 7* td(EXTCLK-H) Delay time, EXTCLK to H1 and H3 tr(H) Rise time, H1 and H3 3* ns tf(H) Fall time, H1 and H3 3* ns td(HL-HH) Delay time, from H1 low to H3 high or from H3 low to H1 high 2* ns --1.5* x5 PLL mode tc(H) Cycle time, H1 and H3 32 1/(5 x fext) x1 mode 1/fext x0.5 mode 2/fext * Not production tested POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 ns ns SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 clock circuit timing (continued) tc(EXTCLK) tr(EXTCLK) tw(EXTCLKH) EXTCLK tw(EXTCLKL) tf(EXTCLK) tc(H) H3 td(EXTCLK-H) tf(H) td(EXTCLK-H) H1 tr(H) Figure 17. Divide-By-Two Mode tc(EXTCLK) tr(EXTCLK) tf(EXTCLK) tw(EXTCLKH) EXTCLK tw(EXTCLKL) td(EXTCLK-H) td(EXTCLK-H) H3 tc(H) td(HL-HH) H1 NOTE A: EXTCLK is held low. Figure 18. Divide-By-One Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 33 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 memory read/write timing The following tables define memory read/write timing parameters for STRB. timing requirements for memory read/write† (see Figure 19, Figure 20, and Figure 21) VC33-120 MIN VC33-150 MAX MIN MAX UNIT tsu(D-H1L)R Setup time, Data before H1 low (read) 5* 5* ns th(H1L-D)R Hold time, Data after H1 low (read) --1* --1* ns tsu(RDY-H1H) Setup time, RDY before H1 high 5 5 ns th(H1H-RDY) Hold time, RDY after H1 high --1* --1* td(A-RDY) tv(A-D) Delay time, Address valid to RDY Valid time, Data valid after address PAGEx, or STRB valid P -0 wait state, CL = 30 pF 1 wait state ns 7*‡ P -- 6*‡ ns 9* 6* ns tc(H) + 9* tc(H) + 6* ns * Not production tested † These timings assume a similar loading of 30 pF on all pins. ‡P=t c(H)/2 (when duty cycle equals 50%). switching characteristics over recommended operating conditions for memory read/write† (see Figure 19, Figure 20, and Figure 21) PARAMETER VC33-120 VC33-150 MIN MIN MAX MAX UNIT td(H1L-SL) Delay time, H1 low to STRB low --1* 4 --1* 3 ns td(H1L-SH) Delay time, H1 low to STRB high --1* 4 --1* 3 ns td(H1H-RWL)W Delay time, H1 high to R/W low (write) --1* 4 --1* 3 ns td(H1L-A) Delay time, H1 low to address valid --1* 4 --1* 3 ns td(H1H-RWH)W Delay time, H1 high to R/W high (write) --1* 4 --1* 3 ns td(H1H-A)W Delay time, H1 high to address valid on back-to-back write cycles (write) --1* 4* --1* 3* ns tv(H1L-D)W Valid time, Data after H1 low (write) 5 ns th(H1H-D)W Hold time, Data after H1 high (write) 5 ns 6 0* 5 0* * Not production tested † These timings assume a similar loading of 30 pF on all pins. Output load characteristics for high-speed and low-speed (low-noise) output buffers are shown in Figure 19. High-speed buffers are used on A0 -- A23, PAGE0 -- PAGE3, H1, H3, STRB, and R/W. All other outputs use the low-speed, (low-noise) output buffer. 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 memory read/write timing (continued) 5 Output Delay (ns) LOAD Low-Noise Buffer 0.05 ns/pF 4 High-Speed Buffer 0.04 ns/pF 3 HIGH SPEED LOW NOISE 0 pF 2.0 2.8 15 pF 2.6 3.4 30 pF 3.2 4.4 50 pF 4.0 5.25 2 CLmax = 30 pF 1 10 20 30 40 50 Load Capacitance (pF) Figure 19. Output Load Characteristics, Buffer Only H3 H1 td(H1L-SL) td(H1L-SH) PAGEx, STRB td(H1L-A) R/W tv(A-D) td(H1H-RWL)W A[23:0] td(A-RDY) tsu(D-H1L)R th(H1L-D)R D[31:0] tsu(RDY-H1H) th(H1H-RDY) RDY NOTE A: STRB remains low during back-to-back read operations. Figure 20. Timing for Memory (STRB = 0 and PAGEx = 0) Read POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 35 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 memory read/write timing (continued) H3 H1 td(H1L-SH) td(H1L-SL) PAGEx, STRB td(H1H-RWL)W td(H1H-RWH)W R/W td(H1L-A) td(H1H-A)W A[23:0] th(H1H-D)W tv(H1L-D)W D[31:0] th(H1H-RDY) tsu(RDY-H1H) RDY Figure 21. Timing for Memory (STRB = 0 and PAGEx = 0) Write 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 XF0 and XF1 timing when executing LDFI or LDII The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII. timing requirements for XF0 and XF1 when executing LDFI or LDII (see Figure 22) VC33-120 VC33-150 MIN MIN MAX MAX UNIT tsu(XF1-H1L) Setup time, XF1 before H1 low 5* 4* ns th(H1L-XF1) Hold time, XF1 after H1 low 0* 0* ns * Not production tested switching characteristics over recommended operating conditions for XF0 and XF1 when executing LDFI or LDII (see Figure 22) PARAMETER td(H3H-XF0L) VC33-120 VC33-150 MIN MIN MAX Delay time, H3 high to XF0 low Fetch LDFI or LDII 4 Decode Read MAX 3 UNIT ns Execute H3 H1 PAGEx, STRB R/W A[23:0] D[31:0] RDY td(H3H-XF0L) XF0 tsu(XF1-H1L) th(H1L-XF1) XF1 Figure 22. Timing for XF0 and XF1 When Executing LDFI or LDII POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 37 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 XF0 timing when executing STFI and STII† The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. switching characteristics over recommended operating conditions for XF0 when executing STFI or STII (see Figure 23) PARAMETER td(H3H-XF0H) † VC33-120 VC33-150 MIN MIN Delay time, H3 high to XF0 high† MAX 4 MAX 3 UNIT ns XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from executing, the address of the store is not driven until the store can execute. Fetch STFI or STII Decode Read Execute H3 H1 PAGEx, STRB R/W A[23:0] D[31:0] RDY td(H3H-XF0H) XF0 Figure 23. Timing for XF0 When Executing an STFI or STII 38 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 XF0 and XF1 timing when executing SIGI The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI. timing requirements for XF0 and XF1 when executing SIGI (see Figure 24) VC33-120 VC33-150 MIN MIN MAX MAX UNIT tsu(XF1-H1L) Setup time, XF1 before H1 low 5* 4* ns th(H1L-XF1) Hold time, XF1 after H1 low 0* 0* ns * Not production tested switching characteristics over recommended operating conditions for XF0 and XF1 when executing SIGI (see Figure 24) PARAMETER VC33-120 VC33-150 MIN MIN MAX MAX UNIT td(H3H-XF0L) Delay time, H3 high to XF0 low 4 3 ns td(H3H-XF0H) Delay time, H3 high to XF0 high 4 3 ns Fetch SIGI Decode Read Execute H3 H1 tsu(XF1-H1L) td(H3H-XF0L) td(H3H-XF0H) XF0 th(H1L-XF1) XF1 Figure 24. Timing for XF0 and XF1 When Executing SIGI POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 39 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 loading when XF is configured as an output The following table defines the timing parameter for loading the XF register when the XFx pin is configured as an output. switching characteristics over recommended operating conditions for loading the XF register when configured as an output pin (see Figure 25) PARAMETER tv(H3H-XF) Valid time, XFx after H3 high VC33-120 VC33-150 MIN MIN MAX 4 Fetch Load Instruction Decode Read MAX 3 Execute H3 H1 OUTXFx Bit (see Note A) 1 or 0 tv(H3H-XF) XFx NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register. Figure 25. Timing for Loading XF Register When Configured as an Output Pin 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 UNIT ns SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 changing XFx from an output to an input The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin. timing requirements for changing XFx from output to input mode (see Figure 26) VC33-120 VC33-150 MIN MIN MAX MAX UNIT tsu(XF-H1L) Setup time, XFx before H1 low 5 4 ns th(H1L-XF) Hold time, XFx after H1 low 0 0 ns switching characteristics over recommended operating conditions for changing XFx from output to input mode (see Figure 26) PARAMETER tdis(H3H-XF) Disable time, XFx after H3 high VC33-120 VC33-150 MIN MIN MAX 6* MAX 5* UNIT ns * Not production tested Buffers Go From Output to Output Execute Load of IOF H3 Synchronizer Delay Value on Pin Seen in IOF H1 tsu(XF-H1L) I/OxFx Bit (see Note A) th(H1L-XF) tdis(H3H-XF) XFx Output Data Sampled INXFx Bit (see Note A) Data Seen NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register. Figure 26. Timing for Changing XFx From Output to Input Mode POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 41 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 changing XFx from an input to an output The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin. switching characteristics over recommended operating conditions for changing XFx from input to output mode (see Figure 27) PARAMETER td(H3H-XF) Delay time, H3 high to XFx switching from input to output VC33-120 VC33-150 MIN MIN MAX 4 Execution of Load of IOF H3 H1 I/OxFx Bit (see Note A) td(H3H-XF) XFx NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register. Figure 27. Timing for Changing XFx From Input to Output Mode 42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 MAX 3 UNIT ns SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 reset timing RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay of one clock cycle is possible. The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. Resetting the device initializes the bus control register to seven software wait states and therefore results in slow external accesses until these registers are initialized. HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA is granted. The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 28 correspond with those in the NO. column of the following table. timing requirements for RESET (see Figure 28) VC33-120 MIN tsu(RESET-EXTCLKL) Setup time, RESET before EXTCLK low 6* tsu(RESETH-H1L) Setup time, RESET high before H1 low and after ten H1 clock cycles 6 VC33-150 MAX P--7*† MIN MAX P -- 7*† 5* 5 UNIT ns ns * Not production tested †P=t c(EXTCLK) switching characteristics over recommended operating conditions for RESET (see Figure 28) PARAMETER VC33-120 VC33-150 MIN MIN MAX MAX UNIT td(EXTCLKH-H1H) Delay time, EXTCLK high to H1 high 2* 7* 2* 7* ns td(EXTCLKH-H1L) Delay time, EXTCLK high to H1 low 2* 7* 2* 7* ns td(EXTCLKH-H3L) Delay time, EXTCLK high to H3 low 2* 7* 2* 7* ns td(EXTCLKH-H3H) Delay time, EXTCLK high to H3 high 2* 7* 2* 7* ns high‡ tdis(H1H-DZ) Disable time, Data (high impedance) from H1 7* 6* ns tdis(H3H-AZ) Disable time, Address (high impedance) from H3 high 7* 6* ns td(H3H-CONTROLH) Delay time, H3 high to control signals high 4* 3* ns td(H1H-RWH) Delay time, H1 high to R/W high 4* 3* ns td(H1H-IACKH) Delay time, H1 high to IACK high 4* 3* ns tdis(RESETL-ASYNCH) Disable time, Asynchronous reset signals disabled (high impedance) from RESET low§ 7* 6* ns * Not production tested ‡ High impedance for Dbus is limited to nominal bus keeper Z OUT = 15 kΩ. § Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 43 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 reset timing (continued) EXTCLK tsu(RESET-EXTCLKL) RESET (see Notes A and C) td(EXTCLKH-H1H) t tsu(RESETH-H1L) d(EXTCLKH-H1L) H1 td(EXTCLKH-H3L) H3 Ten H1 Clock Cycles tdis(H1H-DZ) D[31:0] td(EXTCLKH-H3H) tdis(H3H-AZ) PAGEx, A[23:0] td(H3H-CONTROLH) STRB td(H1H-RWH) R/W td(H1H-IACKH) IACK Asynchronous Reset Signals (see Note B) tdis(RESETL-ASYNCH) NOTES: A. Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3. B. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1. C. RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown occurs; otherwise, an additional delay of one clock cycle is possible. D. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the reset vector is fetched twice, with no software wait states. E. The address and PAGE3-PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10--22 kΩ pullup. If not, undesirable spurious reads can occur when these outputs are not driven. Figure 28. RESET Timing 44 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 interrupt response timing The following table defines the timing parameters for the INTx signals. timing requirements for INT3--INT0 response (see Figure 29) VC33-120 MIN tsu(INT-H1L) Setup time, INT3-- INT0 before H1 low th(H1L-INT) Hold time, INT3-- INT0 after H1 low tw(INT) Pulse duration, interrupt to ensure only one interrupt NOM VC33-150 MAX 5* MIN NOM MAX 4* ns 0 P + 5*† 1.5P 2P -- 5*† P + 5*† UNIT 1.5P 0 ns 2P -- 5*† ns * Not production tested †P=t c(H) The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The SM320C3x interrupts are selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The CPU and DMA respond to detected interrupts on instruction-fetch boundaries only. For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set up and held such that a logic-low condition occurs for: D A minimum of one H1 falling edge D No more than two H1 falling edges D Interrupt sources whose edges cannot be specified to meet the H1 falling edge setup and hold times must be further restricted in pulse width as defined by tw(INT) (parameter 51) in the table above. When EDGEMODE=1, the falling edge of the INT0--INT3 pins are detected using synchronous logic (see Figure 7). The pulse low and high time should be two CPU clocks or greater. The SM320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has been cleared. If the specified timings are met, the sequence shown in Figure 29 occurs; otherwise, an additional delay of one clock cycle is possible. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 45 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 interrupt response timing (continued) Reset or Interrupt Vector Read Fetch First Instruction of Service Routine H3 H1 tsu(INT-H1L)‡ th(H1L-INT) tsu(INT-H1L)† tsu(INT-H1L)¶ INT3 --INT0 Pin (EDGEMODE = 0) tw(INT)§ INT3 --INT0 Pin (EDGEMODE = 1) INT3 --INT0 Flag ADDR Vector Address First Instruction Address Data † Falling edge of H1 just detects INTx falling edge. Falling edge of H1 detects second INTx low, however flag clear takes precedence. § Nominal width. ¶ Falling edge of H1 misses previous INTx low as INTx rises. ‡ Figure 29. INT3--INT0 Response Timing 46 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 interrupt-acknowledge timing The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction. The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 30 correspond with those in the NO. column of the table below. NOTE: The IACK instruction can be executed at anytime to signal an event. It is most often used within an interrupt routine to signal which interrupt has occurred. switching characteristics over recommended operating conditions for IACK (see Figure 30) PARAMETER VC33-120 VC33-150 MIN MAX MIN MAX UNIT td(H1H-IACKL) Delay time, H1 high to IACK low --1* 4 --1* 3 ns td(H1H-IACKH) Delay time, H1 high to IACK high --1* 4 --1* 3 ns * Not production tested Fetch IACK Instruction Decode IACK Instruction IACK Data Read H3 H1 td(H1H-IACKL) td(H1H-IACKH) IACK ADDR Data Figure 30. Interrupt Acknowledge (IACK) Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 47 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 serial-port timing parameters The following tables define the timing parameters for the serial port. timing requirements (see Figure 31 and Figure 32) MIN tc(SCK) Cycle time, time CLKX/R tw(SCK) Pulse duration, duration CLKX/R high/low tr(SCK) Rise time, CLKX/R tf(SCK) Fall time, CLKX/R tsu(DR-CLKRL) Setup time, time DR before CLKR low th(CLKRL-DR) Hold time time, DR after CLKR low tsu(FSR-CLKRL) Setup time time, FSR before CLKR low th(SCKL-FS) Hold time time, FSX/R input after CLKX/R low tsu(FSX-CLKX) Setup time, time external FSX before CLKX CLKX/R ext tc(H) x 2.6* CLKX/R int tc(H) x 4*† CLKX/R ext tc(H) + 5 CLKX/R int [tc(SCK)/2] -- 4* CLKR ext 4* CLKR int 5* CLKR ext 3* CLKR int 0* CLKR ext 4* CLKR int 5* CLKX/R ext 3* CLKX/R int 0* MAX tc(H) x 216* [tc(SCK)/2] + 4* UNIT ns ns 3* ns 3* ns ns ns ns ns CLKX ext --[tc(H) -- 6] [tc(SCK)/2] -- 6* CLKX int --[tc(H) -- 10]* tc(SCK)/2* ns * Not production tested † A cycle time of t c(H)*2 is possible when the device is operated at lower CPU frequencies. See the TMS320VC33 Silicon Update (literature number SPRZ176) for further details. switching characteristics over recommended operating conditions (see Figure 31 and Figure 32) PARAMETER td(H1H-SCK) MIN Delay time, H1 high to internal CLKX/R MAX UNIT 4* ns CLKX ext 6 CLKX int 5* CLKX ext 5 CLKX int 4* td(CLKX-DX) Delay time time, CLKX to DX valid td(CLKX-FSX) Delay time, time CLKX to internal FSX high/low td(CLKX-DX)V Delay time, CLKX to first DX bit, FSX precedes CLKX high td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 6 ns tdis(CLKX-DXZ) Disable time, DX high impedance following last data bit from CLKX high 6 ns CLKX ext 4 CLKX int 5* * Not production tested 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 ns ns ns SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 data-rate timing modes Unless otherwise indicated, the data-rate timings shown in Figure 31 and Figure 32 are valid for all serial-port modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s Guide (literature number SPRU031). The serial-port timing parameters are defined in the preceding “serial-port timing parameters” tables. The numbers shown in Figure 31 and Figure 32 correspond with those in the NO. column of each table. tc(SCK) td(H1H-SCK) H1 td(H1H-SCK) tw(SCK) tw(SCK) CLKX/R tf(SCK) td(CLKX--DX) td(CLKX--DX)V th(CLKRL--DR) Bit n-1 DX tr(SCK) tdis(CLKX--DXZ) Bit 0 Bit n-2 tsu(DR--CLKRL) DR Bit n-1 Bit n-2 FSR tsu(FSR--CLKRL) td(CLKX--FSX) td(CLKX--FSX) FSX(INT) th(SCKL--FS) FSX(EXT) th(SCKL--FS) tsu(FSX--CLKX) NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. Figure 31. Fixed Data-Rate Mode Timing CLKX/R td(CLKX--FSX) FSX(INT) tsu(FSX--CLKX) td(FSX--DX)V FSX(EXT) td(CLKX--DX) td(CLKX-DX)V DX Bit n-1 th(SCKL-FS) FSR tdis(CLKX-DXZ) Bit n-2 Bit n-3 Bit 0 tsu(FSR-CLKRL) DR tsu(DR--CLKRL) Bit n-1 Bit n-2 Bit n-3 th(CLKRL-DR) NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0. B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively. C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed data-rate mode. Figure 32. Variable Data-Rate Mode Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 49 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 HOLD timing HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 33 and Figure 34 occurs; otherwise, an additional delay of one clock cycle is possible. The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA signals. The numbers shown in Figure 33 and Figure 34 correspond with those in the NO. column of the table. The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents future hold cycles. Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue (internally) until a second external write is encountered. Figure 33, Figure 34, and the accompanying timings are for a zero wait-state bus configuration. Since HOLD is internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the minimum HOLD width for any bus configuration is, therefore, WTCNT+3. Also, HOLD should not be deasserted before HOLDA has been active for at least one cycle. timing requirements for HOLD/HOLDA (see Figure 33 and Figure 34) VC33-120 MIN tsu(HOLD-H1L) Setup time, HOLD before H1 low tw(HOLD) Pulse duration, HOLD low VC33-150 MAX MIN MAX UNIT 4 3 ns 3tc(H)* 3tc(H)* ns *Not production tested. switching characteristics over (see Figure 33 and Figure 34) recommended operating conditions VC33-120 PARAMETER MIN tv(H1L-HOLDA) Valid time, HOLDA after H1 low tw(HOLDA) Pulse duration, HOLDA low --1* td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD tdis(H1L-S) Disable time, STRB to the high-impedance state from H1 low ten(H1L-S) Enable time, STRB enabled (active) from H1 low tdis(H1L-RW) ten(H1L-RW) HOLD/HOLDA VC33-150 MAX 4* 2tc(H) -- 4* --1 for MIN --1* MAX 3* 2tc(H) -- 4* ns ns 5 4 ns 5 4 ns Disable time, R/W to the high-impedance state from H1 low 5* 5* ns Enable time, R/W enabled (active) from H1 low 5 4 ns tdis(H1L-A) Disable time, Address to the high-impedance state from H1 low 5* 4* ns ten(H1L-A) Enable time, Address enabled (valid) from H1 low 5 5 ns tdis(H1H-D) Disable time, Data to the high-impedance state from H1 high 5* 4* ns 50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 --1 ns 3 * Not production tested 4 UNIT SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 HOLD timing (continued) H3 H1 tsu(HOLD--H1L) HOLD tsu(HOLD--H1L) tw(HOLD) tv(H1L-HOLDA) HOLDA tw(HOLDA) td(H1L-SH)H tv(H1L--HOLDA) ten(H1L-S) tdis(H1L-S) STRB, PAGEx ten(H1L-RW) tdis(H1L-RW) R/W ten(H1L-A) tdis(H1L-A) A[23:0] tdis(H1H-D) D[31:0] Write Data NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high. Figure 33. Timing for HOLD/HOLDA (After Write) H3 H1 tsu(HOLD--H1L) HOLD tv(H1L--HOLDA) HOLDA tsu(HOLD--H1L) tw(HOLD) tw(HOLDA) tv(H1L--HOLDA) td(H1L-SH)H tdis(H1L-S) STRB, PAGEx tdis(H1L-RW) ten(H1L-S) ten(H1L-RW) R/W tdis(H1L-A) ten(H1L-A) A[23:0] D[31:0] Read Data NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high. Figure 34. Timing for HOLD/HOLDA (After Read) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 51 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 general-purpose I/O timing Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal control registers associated with each peripheral define the modes for these pins. peripheral pin I/O timing The following table shows the timing parameters for changing the peripheral pin from a general-purpose output pin to a general-purpose input pin and vice versa. timing requirements for peripheral pin general-purpose I/O (see Note 1, Figure 35, and Figure 36) VC33-120 VC33-150 MIN MIN MAX MAX UNIT tsu(GPIO-H1L) Setup time, general-purpose input before H1 low 4* 3* ns th(H1L-GPIO) Hold time, general-purpose input after H1 low 0* 0* ns * Not production tested NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents of internal-control registers associated with each peripheral. switching characteristics over recommended operating conditions for peripheral pin general-purpose I/O (see Note 1, Figure 35, and Figure 36) PARAMETER VC33-120 VC33-150 MIN MIN MAX MAX UNIT td(H1H-GPIO) Delay time, H1 high to general-purpose output 5 4 ns tdis(H1H) Disable time, general-purpose output from H1 high 7 5 ns NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents of internal-control registers associated with each peripheral. Execution of Store of PeripheralControl Register Buffers Go From Output to Input Synchronizer Delay Value on Pin Seen in PeripheralControl Register H3 H1 tsu(GPIO-H1L) I/O Control Bit Peripheral Pin (see Note A) Data Bit th(H1L-GPIO) tdis(H1H) Output Data Sampled Data Seen NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. Figure 35. Change of Peripheral Pin From General-Purpose Output to Input Mode Timing 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 peripheral pin I/O timing (continued) Execution of Store of PeripheralControl Register H3 H1 I/O Control Bit td(H1H-GPIO) td(H1H-GPIO) Peripheral Pin (see Note A) NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. Figure 36. Change of Peripheral Pin From General-Purpose Input to Output Mode Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 53 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 timer pin timing Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following tables define the timing parameters for the timer pin. timing requirements for timer pin (see Figure 37 and Figure 38) VC33-120 MIN VC33-150 MAX MIN MAX UNIT tsu(TCLK-H1L)† Setup time, TCLK external before H1 low 4* 3* ns th(H1L-TCLK)† Hold time, TCLK external after H1 low 0 0 ns * Not production tested † These requirements are applicable for a synchronous input clock. switching characteristics over recommended operating conditions for timer pin (see Figure 37 and Figure 38) VC33-120 PARAMETER VC33-150 MIN td(H1H-TCLK) Delay time, H1 high to TCLK internal valid tc(TCLK)‡ Cycle time, time TCLK tw(TCLK)‡ Pulse duration, TCLK MAX MIN 4 TCLK ext TCLK int 3 tc(H) x 2.6* tc(H) x 2* TCLK ext tc(H) + 6* TCLK int [tc(TCLK)/2] -- 4* tc(H) x 2.6* tc(H) x 232* tc(H) x 2* [tc(TCLK)/2] -- 4* H3 H1 th(H1L-TCLK) tsu(TCLK-H1L) th(H1L-TCLK) tsu(TCLK-H1L) TCLK as input tc(TCLK) Figure 37. Timer Pin Timing, Input H3 H1 td(H1H-TCLK) TCLK as output Figure 38. Timer Pin Timing, Output 54 POST OFFICE BOX 1443 tc(H) x 232* tc(H) + 5* [tc(TCLK)/2] + 4* * Not production tested ‡ These parameters are applicable for an asynchronous input clock. td(H1H-TCLK) MAX • HOUSTON, TEXAS 77251--1443 tw(TCLK) [tc(TCLK)/2] + 4* UNIT ns ns ns SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 SHZ pin timing The following table defines the timing parameter for the SHZ pin. switching characteristics over recommended operating conditions for SHZ (see Figure 39) PARAMETER tdis(SHZ) Disable time, SHZ low to all outputs, I/O pins disabled (high impedance) MIN MAX 0* 8* UNIT ns * Not production tested SHZ tdis(SHZ) All I/O Pins NOTE A: Enabling SHZ destroys SM320VC33-EP register and memory contents. Assert SHZ = 1 and reset the SM320VC33-EP to restore it to a known condition. Figure 39. Timing for SHZ Test access port timing The following table defines the timing parameter for the test access port. timing for test access port (see Figure 40) VC33--120 VC33--150 MIN MIN MAX MAX UNIT tsu(TMS-TCKH) Setup time, TMS/TDI to TCK high 5* 5* ns th(TCKH-TMS) Hold time, TMS/TDI from TCK high 5* 5* ns td(TCKL-TDOV) Delay time, TCK low to TDO valid 0* 10* ns tr (TCK) Rise time, TCK 3* 3* ns tf (TCK) Fall time, TCK 3* 3* ns 10* 0* * Not production tested TCK tr(TCK) tf(TCK) tsu(TMS-TCKH) TMS/TDI td(TCHL-TDOV) th(TCHK-TMS) TDO Figure 40. Test Access Port Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 55 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 MECHANICAL DATA GNM (S-CBGA-N144) CERAMIC BALL GRID ARRAY 12,15 SQ 11,85 9,60 TYP 0,80 0,80 N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 2,40 MAX 0,56 0,34 Seating Plane 0,55 0,45 ∅ 0,10 M 0,50 0,35 0,12 4201017/B 05/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. 56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 SM320VC33-EP DIGITAL SIGNAL PROCESSOR SGUS037C -- AUGUST 2002 -- REVISED JANUARY 2003 MECHANICAL DATA PGE (S-PQFP-G144) 108 PLASTIC QUAD FLATPACK 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°--7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147/C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 Thermal Resistance Characteristics PARAMETER °C/W RΘJA 56 RΘJC 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 57 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SM320VC33PGEA120EP ACTIVE LQFP PGE 144 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 100 SM320VC33 PGEA120EP V62/03610-01XE ACTIVE LQFP PGE 144 60 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 100 SM320VC33 PGEA120EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of