SM72442MTE/NOPB

SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Programmable Maximum Power Point Tracking Controller for Photovoltaic Solar Panels Check for Samples: SM72442 FEATURES DESCRIPTION • • • The SM72442 is a programmable MPPT controller capable of controlling four PWM gate drive signals for a 4-switch buck-boost converter. The SM72442 also features a proprietary algorithm called Panel Mode which allows for the panel to be connected directly to the output of your power optimizer circuit. Along with the SM72295 (Photovoltaic Full Bridge Driver), it creates a solution for an MPPT configured DC-DC converter with efficiencies up to 99.5%. Integrated into the chip is an 8-channel, 12 bit A/D converter used to sense input and output voltages and currents, as well as board configuration. Externally programmable values include maximum output voltage and current as well as different settings forslew rate, soft-start and Panel Mode. 1 2 • • • • • Renewable Energy Grade Programmable Maximum Power Point Tracking Photovoltaic Solar Panel Voltage and Current Diagnostic Single Inductor Four Switch Buck-Boost Converter Control I2C Interface for Communication VOUT Overvoltage Protection Over-Current Protection Package: TSSOP-28 Block Diagram VDDA AVIN AIN0 AIIN AIN1 AVOUT AIN2 AIOUT AIN3 VDDD D0 D1 HIB LIB Vin Iin MPPT CONTROLLER HIA LIA CS_N SCLK DIN ADC DOUT A0 AIN4 A2 AIN5 ADC CONTROLLER D2 A4 AIN6 A6 AIN7 D3 D4 D5 D6 D7 ADC_C CLK GEN SCL Vout Iout SDA I2C I2C0 I2C1 I2C2 VSSD VSSA Figure 1. Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 PV(+) www.ti.com Vout(+) PM DRIVER Rsen_in Gate 2 Current Sensing Amplifier Gate 4 Vout(-) R 5V 0.01 PF PV(-) 2.2 PF 2.2 PF 5V VDDA VDDD AIIN Current Sensing Amplifier AIOUT Current Sensing Amplifier AVIN RT1 RT2 RT3 NC3 RT4 NC1 0.1 PF 0.1 PF 0.1 PF 0.1 PF RB2 RB3 RB4 10k 2k 2k 10k CONFIGURATION RESISTOR 10k 10k NC2 HIB LIB HIA H-Bridge Driver PWM1 SM72442 Gate 2 Gate 1 5V 60.4k SCL NC4 SDA RST 10k 10k I2C0 VSSA Gate 3 PWM2 LIA I2C1 I2C2 Gate 4 PWM3 PM RFB1 AVOUT PM_OUT PM DRIVER Current sensing Amplifier PWM4 A0 A2 A4 A6 5V RB1 Gate 3 Gate 1 49.9: R 0.01 PF Rsen_out 0.01 PF VSSD RFB2 Figure 2. Typical Application Circuit Connection Diagram Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 RST PM NC1 LIA VDDD HIA VSSD HIB 25 NC2 LIB 24 I2C0 NC4 23 I2C1 SM72442 27 26 22 I2C2 21 SCL AIOUT SDA A6 20 NC3 AIIN 19 VDDA AVOUT VSSA A2 A0 18 A4 PM_OUT 17 16 15 AVIN Figure 3. TSSOP-28 Package See Package Number PW0028A 2 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Description 1 RST Active low signal. External reset input signal to the digital circuit. 2 NC1 Reserved for test only. This pin should be grounded. 3 VDDD Digital supply voltage. This pin should be connected to a 5V supply, and bypassed to VSSD with a 0.1 µF monolithic ceramic capacitor. 4 VSSD Digital ground. The ground return for the digital supply and signals. 5 NC2 No Connect. This pin should be pulled up to the 5V supply using 10k resistor. 6 I2C0 Addressing for I2C communication. 7 I2C1 Addressing for I2C communication. 8 SCL I2C clock. 9 SDA I2C data. 10 NC3 Reserved for test only. This pin should be grounded. 11 PM_OUT 12 VDDA Analog supply voltage. This voltage is also used as the reference voltage. This pin should be connected to a 5V supply, and bypassed to VSSA with a 1 µF and 0.1 µF monolithic ceramic capacitor. 13 VSSA Analog ground. The ground return for the analog supply and signals. 14 A0 15 AVIN 16 A2 17 AVOUT 18 A4 19 AIIN 20 A6 21 AIOUT 22 I2C2 Addressing for I2C communication. 23 NC4 No Connect. This pin should be connected with 60.4k pull-up resistor to 5V. 24 LIB Low side boost PWM output. 25 HIB High side boost PWM output. 26 HIA High side buck PWM output. 27 LIA Low side buck PWM output. 28 PM Panel Mode Pin. Active low. Pulling this pin low will force the chip into Panel Mode. When Panel Mode is active, this pin will output a 400 kHz square wave signal with amplitude of 5V. Otherwise, it stays low. A/D Input Channel 0. Connect a resistor divider to 5V supply to set the maximum output voltage. Please refer to the application section for more information on setting the resistor value. Input voltage sensing pin. A/D Input Channel 2. Connect a resistor divider to a 5V supply to set the condition to enter and exit Panel Mode (PM). Refer to configurable modes for SM72442 in the application section. Output voltage sensing pin. A/D Input Channel 4. Connect a resistor divider to a 5V supply to set the maximum output current. Please refer to the application section for more information on setting the resistor value. Input current sensing pin. A/D Input Channel 6. Connect a resistor divider to a 5V supply to set the output voltage slew rate and various PM configurations. Refer to configurable modes for SM72442 in the application section. Output current sensing pin. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 3 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Absolute Maximum Ratings www.ti.com (1) Analog Supply Voltage VA (VDDA - VSSA) -0.3 to 6.0V Digital Supply Voltage VD (VDDD - VSSD) -0.3 to VA +0.3V max 6.0V Voltage on Any Pin to GND -0.3 to VA +0.3V Input Current at Any Pin (2) Package Input Current ±10 mA (2) ±20 mA Storage Temperature Range ESD Rating (3) (1) (2) (3) -65°C to +150°C Human Body Model 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and associated test conditions, see the Electrical Characteristics tables. Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Recommended Operating Conditions Operating Temperature -40°C to 105°C VA Supply Voltage +4.75V to +5.25V VD Supply Voltage +4.75V to VA Digital Input Voltage 0 to VA Analog Input Voltage 0 to VA Junction Temperature 4 -40°C to 125°C Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Electrical Characteristics Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction temperature range (1) Parameter Test Conditions Min Typ Max Units - 0 to VA - V ANALOG INPUT CHARACTERISTICS AVin, AIin AVout, AIout Input Range IDCL DC Leakage Current CINA Input Capacitance (2) - - ±1 µA Track Mode - 33 - pF Hold Mode - 3 - pF - 0.8 V DIGITAL INPUT CHARACTERISTICS VIL Input Low Voltage - VIH Input High Voltage 2.8 - - V CIND Digital Input Capacitance (2) - 2 4 pF IIN Input Current - ±0.01 ±1 µA VD - 0.5 - - V - - 0.4 V ±1 µA 2 4 pF 4.75 5 5.25 V - 11.5 15 mA 57.5 78.75 mW DIGITAL OUTPUT CHARACTERISTICS VOH Output High Voltage ISOURCE = 200 µA VA = VD = 5V VOL Output Low Voltage ISINK = 200 µA to 1.0 mA VA = VD = 5V IOZH , IOZL Hi-Impedance Output Leakage Current VA = VD = 5V COUT Hi-Impedance Output Capacitance (2) POWER SUPPLY CHARACTERISTICS (CL = 10 pF) VA ,VD Analog and Digital Supply Voltages VA ≥ VD IA + ID Total Supply Current VA = VD = 4.75V to 5.25V PC Power Consumption VA = VD = 4.75V to 5.25V (1) (2) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Not tested. Ensured by design. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 5 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction temperature range(1) Parameter Test Conditions Min Typ Max Units PWM OUTPUT CHARACTERISTICS fPWM 6 PWM switching frequency 220 Submit Documentation Feedback kHz Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Operation Description OVERVIEW The SM72442 is a programmable MPPT controller capable of outputting four PWM gate drive signals for a 4switch buck-boost converter with an independent Panel Mode. The typical application circuit is shown in Figure 2. The SM72442 uses an advanced digital controller to generate its PWM signals. A maximum power point tracking (MPPT) algorithm monitors the input current and voltage and controls the PWM duty cycle to maximize energy harvested from the photovoltaic module. MPPT performance is very fast. Convergence to the maximum power point of the module typically occurs within 0.01s. This enables the controller to maintain optimum performance under fast-changing irradiance conditions. Transitions between buck, boost, and Panel Mode are smoothed and advanced digital PWM dithering techniques are employed to increase effective PWM resolution. Output voltage and current limiting functionality are integrated into the digital control logic. The controller is capable of handling both shorted and no-load conditions and will recover smoothly from both conditions. ƒ RST pin is pulled low RESET ƒ RST pin is pulled low SOFT-START ƒ Iout < Iout_th ƒ Iout >= Iout_th ƒ Iout < Iout_th PM_STARTUP ƒ Iout > Iout_th AND Starting time elapsed PM ƒ PM pin is pulled low ƒ In Buck-Boost mode for x seconds where x can be set on ADC Ch 2 MPPT ƒ Every 60 seconds after going into Panel Mode, MPPT mode will be entered for a maximum of 4 seconds time to check whether or not the converter is operating at maximum power point OR ƒ There is an x% change in power from the power when panel mode was engaged. This percentage can be set on ADC Ch 2 Figure 4. High Level State Diagram for Startup Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 7 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com STARTUP SM72442 has a soft start feature that will ramp its output voltage for a fixed time of 250ms. If no output current is detected during soft-start time, the chip will then be in Panel Mode for 60 seconds. A counter will start once the minimum output current threshold is met (set by ADC input channel 4). During these 60 seconds, any variation on the output power will not cause the chip to enter MPPT mode. Once 60 seconds have elapsed, at a certain power level variation at the output (set by ADC input channel 2) will engage the chip in MPPT mode. If the output current exceeded the current threshold set at A/D Channel 6 (A6) during soft-start, the chip will then engage in MPPT mode. Figure 5. Startup Sequence MAXIMUM OUTPUT VOLTAGE Maximum output voltage on the SM72442 is set by resistor divider ratio on pin A0. (Please refer to Figure 2 Typical Application Circuit). VOUT_MAX = 5 x (RFB1 + RFB2) RB1 x RFB2 RT1 + RB1 where • • RT1 and RB1 are the resistor divider on the ADC pin A0 RFB1 and RFB2 are the output voltage sense resistors. A typical value for RFB2 is about 2 kΩ (1) CURRENT LIMIT SETTING Maximum output current can be set by changing the resistor divider on A4 (pin 18). Refer to Figure 2. Overcurrent at the output is detected when the voltage on AIOUT (pin 21) equals the voltage on A4 (pin 18). The voltage on A4 can be set by a resistor divider connected to 5V whereas the voltage on AIOUT can be set by a current sense amplifier. AVIN PIN AVIN is an A/D input to sense the input voltage of the SM72442. A resistor divider can be used to scale max voltage to about 4V, which is 80% of the full scale of the A/D input. CONFIGURABLE SETTINGS A/D pins A0, A2, A4, and A6 are used to configure the behavior of the SM72442 by adjusting the voltage applied to them. One way to do this is through resistor dividers as shown in Figure 2, where RT1 to RT4 should be in the range of 20 kΩ. 8 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Different conditions to enter and exit Panel Mode can be set on the ADC input channel 2. Listed below are different conditions that a user can select on pin A2. “1:1” refers to the state in which the DC/DC converter operates with its output voltage equal to its input voltage (also referred to as “Buck-Boost” mode in Figure 4.) A2 Entering Panel Mode Exiting Panel Mode 4.69 V 2s in 1:1 Mode 3.1% power variation 4.06 V 1s in 1:1 Mode 3.1% power variation 3.44 V 0.4s in 1:1 Mode 3.1% power variation 2.81 V 0.2s in 1:1 Mode 3.1% power variation 2.19 V 2s in 1:1 Mode 1.6% power variation 1.56 V 1s in 1:1 Mode 1.6% power variation 0.94 V 0.4s in 1:1 Mode 1.6% power variation 0.31 V 0.2s in 1:1 Mode 1.6% power variation The user can also select the output voltage slew rate, minimum current threshold and duration of Panel Mode after the soft-start period has finished, by changing the voltage level on pin A6 which is the input of ADC channel 6. A6 Output Voltage Slew Rate Limit Starting Panel Mode Time 4.69 V Slow Not applicable 4.06 V Slow 60s 3.44 V Slow 0s 2.81 V Slow 120s 2.19 V Slow 1.56 V 0.94 V 0.31 V MPPT Exit Threshold MPPT Start Threshold Starting boost ratio 0 mA 0 mA 1:1 75mA 125mA 1:1 300mA 500mA 1:1 300mA 500mA 1:1 Not applicable 300mA 500mA 1:1.2 Slow 60s 300mA 500mA 1:1 Fast 60s 300mA 500mA 1:1 No slew rate limit 60s 300mA 500mA 1:1 PARAMETER DEFINITIONS Output Voltage Slew Rate Limit Settling Time: Time constant of the internal filter used to limit output voltage change. For fast slew rate, every 1V increase, the output voltage will be held for 30 ms whereas in a slow slew rate, the output voltage will be held for 62 ms for every 1V increase. (See Figure 6). Starting PM Time: After initial power-up or reset, the output soft-starts and then enters Panel Mode for this amount of time. MPPT Exit Threshold and MPPT Start Threshold: These are the hysteretic thresholds for Iout_th. Starting Boost Ratio – This is the end-point of the soft-start voltage ramp. 1:1 ratio means it stops when Vout = Vin, 1:1.2 means it stops when Vout = 1.2 x Vin. PANEL MODE PIN (PM) PIN The SM72442 can be forced into Panel Mode by pulling the PM pin low. One sample application is to connect this pin to the output of an external temperature sensor; therefore whenever an over-temperature condition is detected the chip will enter a Panel Mode. Once Panel Mode is enabled either when buck-boost mode is entered for a certain period of time (adjustable on channel 2 of ADC) or when PM is pulled low, the PM_OUT pin will output a 400 kHz square wave signal. Using a gate driver and transformer, this square wave signal can then be used to drive a Panel Mode FET as shown in Figure 7. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 9 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Fast 40V No Slew Slow 'V = 10V 30V 20 ± 40 ms (Frequency dependent) 600 ms 1200 ms Figure 6. Slew Rate Limitation Circuit 10 V OUT _A OUT_ B SM72482 VC C SM72442 P M Pulse High 0.47 PF 400 kHz Square Wave IN _A IN_ B PM_O UT 499 10k 150 pF VE E VOUT (+) PV (+) 10k 499 0.47 PF 2.0 0k Figure 7. Sample Application for Panel Mode Operation RESET PIN When the reset pin is pulled low, the chip will cease its normal operation and turn-off all of its PWM outputs including the output of PM_OUT pin. Below is an oscilloscope capture of a forced reset condition. Figure 8. Forced Reset Condition As seen in Figure 8, the initial value for output voltage and load current are 28V and 1A respectively. After the reset pin is grounded both the output voltage and load current decreases immediately. MOSFET switching on the buck-boost converter also stops immediately. VLOB indicates the low side boost output from the SM72295. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 ANALOG INPUT An equivalent circuit for one of the ADC input channels is shown in Figure 9. Diode D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0V to VA. Going beyond this range will cause the ESD diodes to conduct and result in erratic operation. The capacitor C1 in Figure 9 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch; it is typically 500Ω. Capacitor C2 is the ADC sampling capacitor; it is typically 30 pF. The ADC will deliver best performance when driven by a low-impedance source (less than 100Ω). This is specially important when sampling dynamic signals. Also important when sampling dynamic signals is a band-pass or low-pass filter which reduces harmonic and noise in the input. These filters are often referred to as anti-aliasing filters. VA D1 R1 C2 VIN C1 3 pF 30 pF D2 Conversion Phase: Switch Open Track Phase: Switch Close Figure 9. Equivalent Input Circuit DIGITAL INPUTS and OUTPUTS The digital input signals have an operating range of 0V to VA, where VA = VDDA – VSSA. They are not prone to latch-up and may be asserted before the digital supply VD, where VD = VDDD – VSSD, without any risk. The digital output signals operating range is controlled by VD. The output high voltage is VD – 0.5V (min) while the output low voltage is 0.4V (max). SDA and SCL OPEN DRAIN OUTPUT SCL and SDA output is an open-drain output and does not have internal pull-ups. A “high” level will not be observed on this pin until pull-up current is provided by some external source, typically a pull-up resistor. Choice of resistor value depends on many system factors; load capacitance, trace length, etc. A typical value of pull- up resistor for SM72442 ranges from 2 kΩ to 10 kΩ. For more information, refer to the I2C Bus specification for selecting the pull-up resistor value . The SCL and SDA outputs can operate while being pulled up to 5V and 3.3V. I2C CONFIGURATION REGISTERS The operation of the SM72442 can be configured through its I2C interface. Complete register settings for I2C lines are shown below. Table 1. reg0 Register Description Bits Field Reset Value R/W Bit Field Description 55:40 RSVD 16'h0 R Reserved for future use. 39:30 ADC6 10'h0 R Analog Channel 6 (slew rate detection time constant, see adc config worksheet) 29:20 ADC4 10'h0 R Analog Channel 4 (iout_max: maximum allowed output current) 19:10 ADC2 10'h0 R Analog Channel 2 (operating mode, see adc_config worksheet) 9:0 ADC0 10'h0 R Analog Channel 0 (vout_max: maximum allowed output voltage) Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 11 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com Table 2. reg1 Register Description Bits Field Reset Value R/W Bit Field Description 55:41 RSVD 15'h0 R Reserved for future use. 40 mppt_ok 1'h0 R Internal mppt_start signal (test only) 39:30 Vout 10'h0 R Voltage out 29:20 Iout 10'h0 R Current out 19:10 Vin 10'h0 R Voltage in 9:0 Iin 10'h0 R Current in Table 3. reg3 Register Description Bits Field Reset Value R/W Bit Field Description 55:47 RSVD 9'd0 R/W Reserved 46 overide_adcprog 1'b0 R/W When set to 1'b1,the below overide registers used instead of ADC 45 RSVD 1'b0 R/W Reserved 44:43 RSVD 2'b01 R/W Reserved 42 power_thr_sel 1'b0 R/W Register override alternative for ADC2[9] when reg3[46] is set ( 1/2^^5 or 1/2^^6 ) 41:40 bb_in_ptmode_se l 2'd0 R/W Register override alternative for ADC2[8:7] when reg3[46] is set ( 5%,10%,25% or 50%) 39:30 iout_max 10'd1023 R/W Register override alternative when reg3[46] is set for maximum current threshold instead of ADC ch4 29:20 vout_max 10'd1023 R/W Register override alternative when reg3[46] is set for maximum voltage threshold instead of ADC ch0 19:17 tdoff 3'h3 R/W Dead time Off Time 16:14 tdon 3'h3 R/W Dead time On time 13:5 dc_open 9'hFF R/W Open loop duty cycle (test only) 4 pass_through_sel 1'b0 R/W Overrides PM pin 28 and use reg3[3] 3 pass_through_ma nual 1'b0 R/W Control Panel Mode when pass_through_sel bit is 1'b1 2 bb_reset 1'b0 R/W Soft reset 1 clk_oe_manual 1'b0 R/W Enable the PLL clock to appear on pin 5 0 Open Loop operation 1'b0 R/W Open Loop operation (MPPT disabled, receives duty cycle command from reg 3b13:5); set to 1 and then assert & deassert bb_reset to put the device in openloop (test only) Table 4. reg4 Register Description Bits Field Reset Value R/W Bit Field Description 55:32 RSVD 24'd0 R/W Reserved 31:24 Vout offset 8'h0 R/W Voltage out offset 23:16 Iout offset 8'h0 R/W Current out offset 15:8 Vin offset 8'h0 R/W Voltage in offset 7:0 Iin offset 8'h0 R/W Current in offset Table 5. reg5 Register Description 12 Bits Field Reset Value R/W Bit Field Description 55:40 RSVD 15'd0 R/W Reserved 39:30 iin_hi_th 10'd40 R/W Current in high threshold for start 29:20 iin_lo_th 10'd24 R/W Current in low threshold for start 19:10 iout_hi_th 10'd40 R/W Current out high threshold for start 9:0 iout_lo_th 10'd24 R/W Current out low threshold for start Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Using the I2C port, the user will be able to control the duty cycle of the PWM signal. Input and output voltage and current offset can also be controlled using I2C on register 4. Control registers are available for additional flexibility. The thresholds iin_hi_th, iin_lo_th, iout_hi_th, iout_lo_th, in reg5 are compared to the values read in by the ADC on the AIIN and AIOUT pins. Scaling is set by the scaling of the analog signal fed into AIIN and AIOUT. These 10–bit values determine the entry and exit conditions for MPPT. COMMUNICATING WITH THE SM72442 The SCL line is an input, the SDA line is bidirectional, and the device address can be set by I2C0, I2C1 and I2C2 pins. Three device address pins allow connection of up to 7 SM72444s to the same I2C master. A pull-up resistor (10k) to a 5V supply is used to set a bit 1 on the device address. Device addressing for slaves are as follows: I2C0 I2C1 I2C2 Hex 0 0 1 0x1 0 1 0 0x2 0 1 1 0x3 1 0 0 0x4 1 0 1 0x5 1 1 0 0x6 1 1 1 0x7 The data registers in the SM72442 are selected by the Command Register. The Command Register is offset from base address 0xE0. Each data register in the SM72442 falls into one of two types of user accessibility: 1) Read only (Reg0, Reg1) 2) Write/Read same address (Reg3, Reg4, Reg5) There are 7 bytes in each register (56 bits), and data must be read and written in blocks of 7 bytes. Figure 10 depicts the ordering of the bytes transmitted in each frame and the bits within each byte. In the read sequence depicted in Figure 11 the data bytes are transmitted in Frames 5 through 11, starting from the LSByte, DATA1, and ending with MSByte, DATA7. In the write sequence depicted in Figure 12, the data bytes are transmitted in Frames 4 through 11. Only the 100kHz data rate is supported. Please refer to “The I2C Bus Specification” version 2.1 (Doc#: 939839340011) for more documentation on the I2C bus. 7 Byte Data Frame: DATA 1 DATA 2 DATA 3 DATA 6 DATA 7 LSByte MSByte Each Byte contains 8 bits data: D7 D6 D5 D1 D0 LSBit MSBit Figure 10. Endianness Diagram Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 13 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 D7 Ack by SM72442 D6 R/W Start by Master D5 1 SDA (Continued) 9 A6 A5 A4 A3 A2 A1 D7 Ack by SM72442 D6 D5 D4 D3 D2 D0 Ack Repeat Start by by SM72442 Master D6 D5 D4 D3 D2 D1 D0 Ack by SM72442 Frame 4 Length Byte = 7 9 D7 D1 9 A0 R/W 1 SDA (Continued) D2 1 Frame 3 Serial Bus Address Byte SCL (Continued) D3 Frame 2 Command Register Byte Frame 1 Serial Bus Address Byte SCL (Continued) D4 D1 1 9 D0 D7 Ack by SM72442 D6 D5 D4 Frame 10 Data 6 D3 D2 D1 D0 Stop No Ack by by SM72442 Master Frame 11 Data 7 Figure 11. I2C Read Sequence 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 D7 Ack by SM72442 D6 R/W Start by Master D5 SDA (Continued) 1 D7 9 D6 D5 D4 D3 D2 D1 D3 SDA (Continued) D0 D7 Ack by SM72442 9 D6 D5 D4 D3 D2 D0 Ack by SM72442 9 D6 D5 D4 D3 D2 D1 D0 Ack by SM72442 Frame 4 Data 1 1 D7 D1 1 Frame 3 Length Byte = 7 SCL (Continued) D2 Frame 2 Command Register Byte Frame 1 Serial Bus Address Byte SCL (Continued) D4 D1 D0 1 D7 Ack by SM72442 9 D6 D5 D4 Frame 10 Data 6 D3 D2 Frame 11 Data 7 D1 D0 Stop No Ack by by SM72442 Master Figure 12. I2C Write Sequence 14 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 SM72442 www.ti.com SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 Noise coupling into digital lines greater than 400 mVp-p (typical hysteresis) and undershoot less than 500 mV GND, may prevent successful I2C communication with SM72442. I2C no acknowledge is the most common symptom, causing unnecessary traffic on the bus although the I2C maximum frequency of communication is rather low (400 kHz max), care still needs to be taken to ensure proper termination within a system with multiple parts on the bus and long printed board traces. Additional resistance can be added in series with the SDA and SCL lines to further help filter noise and ringing. Minimize noise coupling by keeping digital races out of switching power supply areas as well as ensuring that digital lines containing high speed data communications cross at right angles to the SDA and SCL lines. Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 15 SM72442 SNVS689H – OCTOBER 2010 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision G (April 2013) to Revision H • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: SM72442 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SM72442MT/NOPB ACTIVE TSSOP PW 28 48 RoHS & Green SN Level-3-260C-168 HR -40 to 125 SO2442 SM72442MTE/NOPB ACTIVE TSSOP PW 28 250 RoHS & Green SN Level-3-260C-168 HR -40 to 125 SO2442 SM72442MTX/NOPB ACTIVE TSSOP PW 28 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 125 SO2442 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of