SM73201
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SNOSB89B – JUNE 2011 – REVISED JUNE 2013
SM73201 16-Bit, 50 to 250 kSPS, Differential Input, MicroPower ADC
Check for Samples: SM73201
FEATURES
DESCRIPTION
•
•
•
•
•
The SM73201 is a 16-bit successive-approximation
register (SAR) Analog-to-Digital converter (ADC) with
a maximum sampling rate of 250 kSPS. The
converter features a differential analog input with an
excellent common-mode signal rejection ratio of 85
dB, making the SM73201 suitable for noisy
environments.
1
234
•
•
•
•
Renewable Energy Grade
Specified Performance from 50 to 250 kSPS
Separate Digital Input/Output Supply
True Differential Input
External Voltage Reference Range of +0.5V to
VA
Wide Input Common-Mode Voltage Range of
0V to VA
SPI™/ QSPI™/MICROWIRE Compatible Serial
Interface
Operating Temperature Range of −40°C to
+85°C
Small VSSOP-10 Package
The SM73201 operates with a single analog supply
(VA) and a separate digital input/output (VIO) supply.
VA can range from +4.5V to +5.5V and VIO can range
from +2.7V to +5.5V. This allows a system designer
to maximize performance and minimize power
consumption by operating the analog portion of the
ADC at a VA of +5V while interfacing with a +3.3V
controller. The serial data output is binary 2's
complement and is SPI compatible.
The performance of the SM73201 is specified over
temperature at clock rates of 1 MHz to 5 MHz and
reference voltages of +2.5V to +5.5V. The SM73201
is available in a small 10-lead VSSOP package. The
high accuracy, differential input, low power
consumption, and small size make the SM73201
ideal for direct connection to bridge sensors and
transducers in battery operated systems or remote
data acquisition applications.
APPLICATIONS
•
•
•
•
PV DC Arc Detect System
I/O Modules
Solar Data Acquisition
Instrumentation and Control Systems
KEY SPECIFICATIONS
•
•
•
•
•
Conversion Rate: 50 kSPS to 250 kSPS
SNR: 93.2 dBc
SFDR: 108 dBc
THD: −104 dBc
Power Consumption
– 200 kSPS, 5V: 5.3 mW
– 250 kSPS, 5V: 5.8 mW
– Power-Down, 5V: 10 μW
Typical Application
Vdig
Vana
Vref Vana
PV
String
1:100
Impedance
Match &
Clamping
Controller
Gain & Filtering
ADC
FFT(DSP)
Filtering
UART
& I/O
16Bit/250KSPS
Vref
Array
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
QSPI is a trademark of Motorola Incorporated.
SPI is a trademark of Motorola, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
SM73201
SNOSB89B – JUNE 2011 – REVISED JUNE 2013
www.ti.com
Block Diagram
SAR
CONTROL
VREF
SERIAL
INTERFACE
+IN
S/H
CDAC
-IN
COMPARATOR
Connection Diagram
VREF
1
10
VA
+IN
2
9
VIO
SM73201
- IN
3
8
SCLK
GND
4
7
DOUT
GND
5
6
CS
Figure 1. 10-Lead VSSOP
See Package Number DGS0010A
Pin Descriptions
Pin No.
2
Name
Description
1
VREF
Voltage Reference
+0.5V < VREF < VA
2
+IN
Non-Inverting Input
3
−IN
Inverting Input
4
GND
Ground
5
GND
Ground
6
CS
7
DOUT
Serial Data Output
8
SCLK
Serial Clock
9
VIO
Digital Input/Output Power
+2.7V < VREF < +5.5V
10
VA
Analog Power
+4.5V < VREF < +5.5V
Chip Select Bar
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
−0.3V to 6.5V
Analog Supply Voltage VA
−0.3V to 6.5V
Digital I/O Supply Voltage VIO
Voltage on Any Analog Input Pin to GND
−0.3V to (VA + 0.3V)
Voltage on Any Digital Input Pin to GND
−0.3V to (VIO + 0.3V)
Input Current at Any Pin (4)
±10 mA
Package Input Current (4)
±50 mA
See (5)
Power Consumption at TA = 25°C
(6)
ESD Susceptibility
Human Body Model
Machine Model
Charge Device Model
2500V
250V
1250V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications
All voltages are measured with respect to GND = 0V, unless otherwise specified.
When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited
to 10 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to five.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the SM73201 is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply
polarity is reversed). Such conditions should always be avoided.
Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged
through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an
automated assembler) then rapidly being discharged.
Operating Ratings (1) (2)
−40°C ≤ TA ≤ +85°C
Operating Temperature Range
Supply Voltage, VA
+4.5V to +5.5V
Supply Voltage, VIO
+2.7V to +5.5V
Reference Voltage, VREF
+0.5V to VA
Analog Input Pins Voltage Range
0V to VA
−VREF to +VREF
Differential Analog Input Voltage
Input Common-Mode Voltage, VCM
See Figure 31 Input Common Mode Voltage
Digital Input Pins Voltage Range
0V to VIO
Clock Frequency
(1)
(2)
1 MHz to 5 MHz
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
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SM73201
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Package Thermal Resistance
θJA
Package
10-lead VSSOP
Soldering process must comply with Reflow Temperature Profile specifications. Refer to SNOA549 Reflow
temperature profiles are different for lead-free packages.
SM73201 Converter Electrical Characteristics (1)
The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4
MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and
minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C.
Parameter
Test Conditions
Min
Typ
Max
Units
STATIC CONVERTER CHARACTERISTICS
Resolution
DNL
Differential Non-Linearity
INL
Integral Non-Linearity
OE
Offset Error
OEDRIFT
FSE
GE
GEDRIFT
16
Bits
-0.5/+0.8
LSB
±0.8
LSB
VREF = 2.5V
−0.1
mV
VREF = 5V
−0.4
mV
VREF = 2.5V
3.7
µV/°C
VREF = 5V
2.5
µV/°C
Positive Full-Scale Error
−0.003
%FS
Negative Full-Scale Error
−0.002
%FS
Positive Gain Error
−0.002
%FS
Negative Gain Error
−0.0001
%FS
0.3
ppm/°
C
Offset Error Temperature Drift
Gain Error Temperature Drift
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
SNR
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
SFDR
Spurious-Free Dynamic Range
ENOB
Effective Number of Bits
VREF = 2.5V
85
88
dBc
VREF = 4.5V to 5.5V
89
93.0
dBc
VREF = 2.5V
85
88
dBc
VREF = 4.5V to 5.5V
89
93.2
dBc
VREF = 2.5V
−104
dBc
VREF = 4.5V to 5.5V
−106
dBc
VREF = 2.5V
108
dBc
VREF = 4.5V to 5.5V
111
dBc
VREF = 2.5V
13.8
14.3
bits
VREF = 4.5V to 5.5V
14.5
15.2
bits
ANALOG INPUT CHARACTERISTICS
VIN
−VREF
Differential Input Range
CS high
IINA
Analog Input Current
CINA
CMRR
(1)
4
Input Capacitance (+IN or −IN)
Common Mode Rejection Ratio
+VREF
V
±1
µA
VREF = 5V, VIN = 0V, fS = 50 kSPS
3.2
nA
VREF = 5V, VIN = 0V, fS = 200 kSPS
10.3
nA
In Acquisition Mode
20
pF
In Conversion Mode
4
pF
See the Specification Definitions for
the test condition
85
dB
Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing
Quality Level).
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SM73201 Converter Electrical Characteristics(1) (continued)
The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4
MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and
minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C.
Parameter
Test Conditions
Min
Typ
Max
Units
DIGITAL INPUT CHARACTERISTICS
VIH
Input High Voltage
fIN = 0 Hz
0.7 x VIO
1.9
VIL
Input Low Voltage
fIN = 0 Hz
0.3 x VIO
V
IIND
Digital Input Current
±1
µA
CIND
Input Capacitance
4
pF
1.7
V
DIGITAL OUTPUT CHARACTERISTICS
VOH
Output High Voltage
VIO − 0.2
ISOURCE = 200 µA
VIO − 0.03
ISOURCE = 200 µA
0.01
ISOURCE = 1 mA
0.07
VOL
Output Low Voltage
IOZH, IOZL
TRI-STATE Leakage Current
Force 0V or VA
COUT
TRI-STATE Output Capacitance
Force 0V or VA
V
VIO − 0.09
ISOURCE = 1 mA
V
0.4
V
±1
µA
V
4
Output Coding
pF
Binary 2'S Complement
POWER SUPPLY CHARACTERISTICS
VA
Analog Supply Voltage Range
VIO
Digital Input/Output Supply Voltage
Range
VREF
Reference Voltage Range
IVA (Conv)
Analog Supply Current, Conversion
Mode
Digital I/O Supply Current, Conversion
IVIO (Conv)
Mode
See (2)
4.5
5
5.5
V
2.7
3
5.5
V
0.5
5
VA
V
VA = 5V, fSCLK = 4 MHz, fS = 200
kSPS
1060
VA = 5V, fSCLK = 5 MHz, fS = 250
kSPS
1160
VIO = 3V, fSCLK = 4 MHz, fS = 200
kSPS
80
µA
VIO = 3V, fSCLK = 5 MHz, fS = 250
kSPS
100
µA
VA = 5V, fSCLK = 4 MHz, fS = 200
kSPS
80
µA
VA = 5V, fSCLK = 5 MHz, fS = 250
kSPS
100
IVREF
(Conv)
Reference Current, Conversion Mode
IVA (PD)
Analog Supply Current, Power Down
Mode (CS high)
fSCLK = 5 MHz, VA = 5V
7
fSCLK = 0 Hz, VA = 5V (3)
2
IVIO (PD)
Digital I/O Supply Current, Power Down
Mode (CS high)
fSCLK = 5 MHz, VIO = 3V
1
IVREF (PD)
Reference Current, Power Down Mode
(CS high)
fSCLK = 5 MHz, VREF = 5V
0.5
fSCLK = 0 Hz, VREF = 5V (3)
0.5
VA = 5V, fSCLK = 4 MHz, fS = 200
kSPS, and fIN = 20 kHz,
5.3
VA = 5V, fSCLK = 5 MHz, fS = 250
kSPS, and fIN = 20
5.8
fSCLK = 0 Hz, VIO = 3V
(3)
PWR
(Conv)
Power Consumption, Conversion Mode
PWR (PD)
fSCLK = 5 MHz, VA = 5.0V
(3)
Power Consumption, Power Down Mode
(CS high)
fSCLK = 0 Hz, VA = 5.0V
(3)
PSRR
(2)
(3)
Power Supply Rejection Ratio
See the Specification Definitions for
the test condition
0.3
µA
1340
170
µA
µA
3
µA
µA
0.5
µA
µA
0.7
µA
mW
6.7
35
10
µA
mW
µW
15
−78
µW
dB
The value of VIO is independent of the value of VA. For example, VIO could be operating at 5.5V while VA is operating at 4.5V or VIO
could be operating at 2.7V while VA is operating at 5.5V.
This parameter is ensured by design and/or characterization and is not tested in production.
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SM73201 Converter Electrical Characteristics(1) (continued)
The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, and VREF = 2.5V to 5.5V for fSCLK = 1 MHz to 4
MHz or VREF = 4.5V to 5.5V for fSCLK = 1 MHz to 5 MHz; fIN = 20 kHz, and CL = 25 pF, unless otherwise noted. Maximum and
minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = 25°C.
Parameter
Test Conditions
Min
Typ
Max
Units
1
5
MHz
50
250
kSPS
17
SCLK
cycles
AC ELECTRICAL CHARACTERISTICS
fSCLK
Maximum Clock Frequency
fS
Maximum Sample Rate
tACQ
Acquisition/Track Time
tCONV
Conversion/Hold Time
tAD
Aperture Delay
(4)
See
(4)
600
ns
See the Specification Definitions
6
ns
While the maximum sample rate is fSCLK / 20, the actual sample rate may be lower than this by having the CS rate slower than fSCLK /
20.
SM73201 Timing Specifications
(1)
The following specifications apply for VA = 4.5V to 5.5V, VIO = 2.7V to 5.5V, VREF = 2.5V to 5.5V, fSCLK = 1Mz to 5MHz, and CL
= 25 pF, unless otherwise noted. Maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA =
25°C.
Parameter
Min
Typ
Max
Units
tCSS
CS Setup Time prior to an SCLK rising edge
8
3
tCSH
CS Hold Time after an SCLK rising edge
8
3
tDH
DOUT Hold Time after an SCLK falling edge
6
11
tDA
DOUT Access Time after an SCLK falling edge
18
41
ns
tDIS
DOUT Disable Time after the rising edge of CS (2)
20
30
ns
tCS
Minimum CS Pulse Width
tEN
DOUT Enable Time after the 2nd falling edge of SCLK
20
70
tCH
SCLK High Time
20
tCL
SCLK Low Time
20
tr
DOUT Rise Time
7
ns
tf
DOUT Fall Time
7
ns
(1)
(2)
ns
ns
20
ns
ns
ns
ns
Typical values are at TJ = 25°C and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing
Quality Level).
tDIS is the time for DOUT to change 10% while being loaded by the Timing Test Circuit.
Timing Diagrams
tACQ
tCONV (Power-Up)
(Power-Down)
tCS
CS
1
2
3
4
tCH
5
13
14
15
16
17
18
1
2
SCLK
tCL
tEN
DOUT
0
D15
D14
tDIS
D5
D4
D3
D2
D1
D0
0
Figure 2. SM73201 Single Conversion Timing Diagram
6
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IOL
2 mA
TO OUTPUT
PIN
1.6V
CL
25 pF
IOH
2 mA
Figure 3. Timing Test Circuit
0.9 x VIO
DOUT
0.1 x VIO
tr
tf
Figure 4. DOUT Rise and Fall Times
SCLK
VIL
tDA
0.7 x VIO
DOUT
0.3 x VIO
tDH
Figure 5. DOUT Hold and Access Times
SCLK
1
2
tCSH
tCSS
CS
Figure 6. Valid CS Assertion Times
CS
VIH
90%
90%
DOUT
10%
tDIS
90%
DOUT
10%
10%
Figure 7. Voltage Waveform for tDIS
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Specification Definitions
APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is
sampled for conversion.
COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input
pins are rejected.
To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed
from 2V to 3V.
CMRR = 20 LOG ( Δ Common Input / Δ Output Offset)
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input
voltage to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to
a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive
Full-Scale Error and Negative Full-Scale Error and can be calculated as:
Gain Error = Positive Full-Scale Error − Negative Full-Scale Error
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given
code from this straight line is measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The SM73201 is specified
not to have any missing codes.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from code 0x8001h to 0x8000h and −VREF + 1 LSB.
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from
code 0x0000h to 0x0001h and 1 LSB.
POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions from code 0xFFFEh to 0xFFFFh and VREF - 1 LSB.
POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage
is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage,
expressed in dB. For the SM73201, VA is changed from 4.5V to 5.5V.
PSRR = 20 LOG (ΔOutput Offset / ΔVA)
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below one-half the sampling frequency,
including harmonics but excluding d.c.
8
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SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component below one-half the sampling frequency,
where a spurious spectral component is any signal present in the output spectrum that is not present at the input
and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first five harmonic components at the
output to the rms level of the input signal frequency as seen at the output, expressed in dB. THD is calculated as
THD = 20 x log10
Af 2 2 + / + Af 6 2
Af 12
where
•
Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5
harmonic frequencies.
THROUGHPUT TIME is the minimum time required between the start of two successive conversion.
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Typical Performance Characteristics
VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
10
SINAD vs. VA
THD vs. VA
Figure 8.
Figure 9.
SINAD vs. VREF
THD vs. VREF
Figure 10.
Figure 11.
SINAD vs. SCLK FREQUENCY
THD vs. SCLK FREQUENCY
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
SINAD vs. INPUT FREQUENCY
THD vs. INPUT FREQUENCY
Figure 14.
Figure 15.
SINAD vs. TEMPERATURE
THD vs. TEMPERATURE
Figure 16.
Figure 17.
VA CURRENT vs. VA
VA CURRENT vs. SCLK FREQUENCY
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
12
VA CURRENT vs. TEMPERATURE
VREF CURRENT vs. VREF
Figure 20.
Figure 21.
VREF CURRENT vs. SCLK FREQUENCY
VREF CURRENT vs. TEMPERATURE
Figure 22.
Figure 23.
VIO CURRENT vs. VIO
VIO CURRENT vs. SCLK FREQUENCY
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
VA = VIO = VREF = +5V, fSCLK = 5 MHz, fSAMPLE = 250 kSPS, TA = +25°C, and fIN = 20 kHz unless otherwise stated.
VIO CURRENT vs. TEMPERATURE
SPECTRAL RESPONSE - 250 kSPS
Figure 26.
Figure 27.
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FUNCTIONAL DESCRIPTION
The SM73201 is a 16-bit, 50 kSPS to 250 kSPS sampling Analog-to-Digital (A/D) converter. The converter uses
a successive approximation register (SAR) architecture based upon capacitive redistribution containing an
inherent sample-and-hold function. The differential nature of the analog inputs is maintained from the internal
sample-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection.
The SM73201 operates from independent analog and digital supplies. The analog supply (VA) can range from
4.5V to 5.5V and the digital input/output supply (VIO) can range from 2.7V to 5.5V. The SM73201 utilizes an
external reference (VREF), which can be any voltage between 0.5V and VA. The value of VREF determines the
range of the analog input, while the reference input current (IREF) depends upon the conversion rate.
The analog input is presented to two input pins: +IN and –IN. Upon initiation of a conversion, the differential input
at these pins is sampled on the internal capacitor array. The inputs are disconnected from the internal circuitry
while a conversion is in progress. The SM73201 features a zero-power track mode (ZPTM) where the ADC is
consuming the minimum amount of power (Power-Down Mode) while the internal sampling capacitor array is
tracking the applied analog input voltage. The converter enters ZPTM at the end of each conversion window and
experiences no delay when the ADC enters into Conversion Mode. This feature allows the user an easy means
for optimizing system performance based on the settling capability of the analog source while minimizing power
consumption. ZPTM is exercised by bringing chip select bar (CS) high or when CS is held low after the
conversion is complete (after the 18th falling edge of the serial clock).
The SM73201 communicates with other devices via a Serial Peripheral Interface (SPI), a synchronous serial
interface that operates using three pins: chip select bar (CS), serial clock (SCLK), and serial data out (DOUT). The
external SCLK controls data transfer and serves as the conversion clock. The duty cycle of SCLK is essentially
unimportant, provided the minimum clock high and low times are met. The minimum SCLK frequency is set by
internal capacitor leakage. Each conversion requires a minimum of 18 SCLK cycles to complete. If less than 16
bits of conversion data are required, CS can be brought high at any point during the conversion. This procedure
of terminating a conversion prior to completion is commonly referred to as short cycling.
The digital conversion result is clocked out by the SCLK input and is provided serially, most significant bit (MSB)
first, at the DOUT pin. The digital data that is provided at the DOUT pin is that of the conversion currently in
progress and thus there is no pipe line delay or latency.
REFERENCE INPUT (VREF)
The externally supplied reference voltage (VREF) sets the analog input range. The SM73201 will operate with
VREF in the range of 0.5V to VA.
Operation with VREF below 2.5V is possible with slightly diminished performance. As VREF is reduced, the range
of acceptable analog input voltages is reduced. Assuming a proper common-mode input voltage (VCM), the
differential peak-to-peak input range is limited to (2 x VREF). See Input Common Mode Voltage for more details.
Reducing VREF also reduces the size of the least significant bit (LSB). For example, the size of one LSB is equal
to [(2 x VREF) / 2n], which is 152.6 µV where n is 16 bits and VREF is 5V. When the LSB size goes below the noise
floor of the SM73201, the noise will span an increasing number of codes and overall performance will suffer.
Dynamic signals will have their SNR degrade; while, D.C. measurements will have their code uncertainty
increase. Since the noise is Gaussian in nature, the effects of this noise can be reduced by averaging the results
of a number of consecutive conversions.
VREF and analog inputs (+IN and -IN) are connected to the capacitor array through a switch matrix when the input
is sampled. Hence, IREF, I+IN, and I-IN are a series of transient spikes that occur at a frequency dependent on the
operating sample rate of the SM73201.
IREF changes only slightly with temperature. See the curves, “Figure 20” and “Figure 22” in the Typical
Performance Characteristics section for additional details.
ANALOG SIGNAL INPUTS
The SM73201 has a differential input where the effective input voltage that is digitized is (+IN) − (−IN).
14
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Differential Input Operation
The transfer curve of the SM73201 for a fully differential input signal is shown in Figure 28. A positive full scale
output code (0111 1111 1111 1111b or 7FFFh or 32,767d) will be obtained when (+IN) − (−IN) is greater than or
equal to (VREF − 1 LSB). A negative full scale code (1000 0000 0000 0000b or 8000h or -32,768d) will be
obtained when [(+IN) − (−IN)] is less than or equal to (−VREF + 1 LSB). This ignores gain, offset and linearity
errors, which will affect the exact differential input voltage that will determine any given output code.
0111 1111 1111 1111b
|
-1 LSB
|
0000 0000 0000 0000b
|
+1 LSB
- VREF +1LSB
+VREF - 1LSB
|
|
ADC Output Code
|
1000 0000 0000 0000b
Analog Input
Figure 28. ADC Transfer Curve
Both inputs should be biased at a common mode voltage (VCM), which will be thoroughly discussed in Input
Common Mode Voltage Figure 29 shows the SM73201 being driven by a full-scale differential source.
VREF
2
VCM
VCM +
RS
VCM
VREF
2
-
VREF
SRC
CS
RS
+
SM73201
-
VREF
2
VCM
VCM +
VCM
-
VREF
2
Figure 29. Differential Input
Single-Ended Input Operation
For single-ended operation, the non-inverting input (+IN) of the SM73201 can be driven with a signal that has a
peak-to-peak range that is equal to or less than (2 x VREF). The inverting input (−IN) should be biased at a stable
VCM that is halfway between these maximum and minimum values. In order to utilize the entire dynamic range of
the SM73201, VREF is limited to (VA / 2). This allows +IN a maximum swing range of ground to VA. Figure 30
shows the SM73201 being driven by a full-scale single-ended source.
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VCM + VREF
VCM
VCM
- VREF
RS
VREF
SRC
+
SM73201
CS
-
VCM
Figure 30. Single-Ended Input
Since the design of the SM73201 is optimized for a differential input, the performance degrades slightly when
driven with a single-ended input. Linearity characteristics such as INL and DNL typically degrade by 0.1 LSB and
dynamic characteristics such as SINAD typically degrade by 2 dB. Note that single-ended operation should only
be used if the performance degradation (compared with differential operation) is acceptable.
Input Common Mode Voltage
The allowable input common mode voltage (VCM) range depends upon VA and VREF used for the SM73201. The
ranges of VCM are depicted in Figure 31 and Figure 32. Note that these figures only apply to a VA of 5V.
Equations for calculating the minimum and maximum VCM for differential and single-ended operations are shown
in Table 1.
6
COMMON-MODE VOLTAGE (V)
Differential Input
5
VA = 5.0V
3.75
2.5
1.25
0
-1
0.0
1.0
2.0 2.5 3.0
4.0
5.0
VREF (V)
Figure 31. VCM range for Differential Input operation
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6
COMMON-MODE VOLTAGE (V)
Single-Ended Input
5
VA = 5.0V
3.75
2.5
1.25
0
-1
0.0
1.25
0.75
1.75
2.5
VREF (V)
Figure 32. VCM range for single-ended operation
Table 1. Allowable VCM Range
Input Signal
Differential
Single-Ended
Minimum VCM
Maximum VCM
VREF / 2
VA − VREF / 2
VREF
VA − VREF
CMRR
By using this differential input, small signals common to both inputs are rejected. As shown in Figure 33, noise is
immune at low frequencies where the common-mode rejection ratio (CMRR) is 90 dB. As the frequency
increases to 1 MHz, the CMRR rolls off to 40 dB . In general, operation with a fully differential input signal or
voltage will provide better performance than with a single-ended input. However, if desired, the SM73201 can be
presented with a single-ended input.
Figure 33. Analog Input CMRR vs. Frequency
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Input Settling
When the SM73201 enters acquisition (tACQ) mode at the end of the conversion window, the internal sampling
capacitor (CSAMPLE) is connected to the ADC input via an internal switch and a series resistor (RSAMPLE), as
shown in Figure 34. Typical values for CSAMPLE and RSAMPLE are 20 pF and 200 ohms respectively. If there is not
a large external capacitor (CEXT) at the analog input of the ADC, a voltage spike will be observed at the input
pins. This is a result of CSAMPLE and CEXT being at different voltage potentials. The magnitude and direction of the
voltage spike depend on the difference between the voltage of CSAMPLE and CEXT. If the voltage at CSAMPLE is
greater than the voltage at CEXT, a positive voltage spike will occur. If the opposite is true, a negative voltage
spike will occur. It is not critical for the performance of the SM73201 to filter out the voltage spike. Rather, ensure
that the transient of the spike settles out within tACQ; for recommended solutions, see ANALOG INPUT
CONSIDERATIONS in the Application Information.
REXT+
VIN +-
SW+
+
RSAMPLE+ CSAMPLE+
CEXT
REXT-
SW- RSAMPLE- CSAMPLE-
Figure 34. ADC Input Capacitors
SERIAL DIGITAL INTERFACE
The SM73201 communicates via a synchronous 3-wire serial interface as shown in Figure 2 or re-shown in
Figure 35 for convenience. CS, chip select bar, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of the serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. The SM73201's DOUT pin
is in a high impedance state when CS is high and for the first clock period after CS is asserted; DOUT is active for
the remainder of time when CS is asserted.
The SM73201 samples the differential input upon the assertion of CS. Assertion is defined as bringing the CS pin
to a logic low state. For the first 17 periods of the SCLK following the assertion of CS, the SM73201 is converting
the analog input voltage. On the 18th falling edge of SCLK, the SM73201 enters acquisition (tACQ) mode. For the
next three periods of SCLK, the SM73201 is operating in acquisition mode where the ADC input is tracking the
analog input signal applied across +IN and -IN. During acquisition mode, the SM73201 is consuming a minimal
amount of power.
The SM73201 can enter conversion mode (tCONV) under three different conditions. The first condition involves CS
going low (asserted) with SCLK high. In this case, the SM73201 enters conversion mode on the first falling edge
of SCLK after CS is asserted. In the second condition, CS goes low with SCLK low. Under this condition, the
SM73201 automatically enters conversion mode and the falling edge of CS is seen as the first falling edge of
SCLK. In the third condition, CS and SCLK go low simultaneously and the SM73201 enters conversion mode.
While there is no timing restriction with respect to the falling edges of CS and SCLK, there are minimum setup
and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK. See Figure 6 in
the Timing Diagram section for more information.
CS Input
The CS (chip select bar) input is active low and is CMOS compatible. The SM73201 enters conversion mode
when CS is asserted and the SCLK pin is in a logic low state. When CS is high, the SM73201 is always in
acquisition mode and thus consuming the minimum amount of power. Since CS must be asserted to begin a
conversion, the sample rate of the SM73201 is equal to the assertion rate of CS.
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Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS
occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is
clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,
and the characteristics of the individual device. To ensure that the MSB is always clocked out at a given time
(the 3rd falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in
the Timing Specification table.
SCLK Input
The SCLK (serial clock) is used as the conversion clock to shift out the conversion result. SCLK is CMOS
compatible. Internal settling time requirements limit the maximum clock frequency while internal capacitor
leakage limits the minimum clock frequency. The SM73201 offers specified performance with the clock rates
indicated in the electrical table.
The SM73201 enters acquisition mode on the 18th falling edge of SCLK during a conversion frame. Assuming
that the LSB is clocked into a controller on the 18th rising edge of SCLK, there is a minimum acquisition time
period that must be met before a new conversion frame can begin. Other than the 18th rising edge of SCLK that
was used to latch the LSB into a controller, there is no requirement for the SCLK to transition during acquisition
mode. Therefore, it is acceptable to idle SCLK after the LSB has been latched into the controller.
Data Output
The data output format of the SM73201 is two’s complement as shown in Figure 28. This figure indicates the
ideal output code for a given input voltage and does not include the effects of offset, gain error, linearity errors, or
noise. Each data output bit is output on the falling edges of SCLK. DOUT is in a high impedance state for the 1st
falling edge of SCLK while the 2nd SCLK falling edge clocks out a leading zero. The 3rd to 18th SCLK falling
edges clock out the conversion result, MSB first.
While most receiving systems will capture the digital output bits on the rising edges of SCLK, the falling edges of
SCLK may be used to capture the conversion result if the minimum hold time for DOUT is acceptable. See
Figure 5 for DOUT hold (tDH) and access (tDA) times.
DOUT is enabled on the second falling edge of SCLK after the assertion of CS and is disabled on the rising edge
of CS. If CS is raised prior to the 18th falling edge of SCLK, the current conversion is aborted and DOUT will go
into its high impedance state. A new conversion will begin when CS is driven LOW.
tACQ
tCONV (Power-Up)
(Power-Down)
tCS
CS
1
2
3
4
tCH
5
13
14
15
16
17
18
1
2
SCLK
tCL
tEN
DOUT
0
D15
D14
tDIS
D5
D4
D3
D2
D1
D0
0
Figure 35. SM73201 Single Conversion Timing Diagram
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Applications Information
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the SM73201:
−40°C ≤ TA ≤ +85°C
+4.5V ≤ VA ≤ +5.5V
+2.7V ≤ VIO ≤ +5.5V
+0.5V ≤ VREF ≤ +5.5V
1 MHz ≤ fSCLK ≤ 5 MHz
VCM: See Input Common Mode Voltage
ANALOG INPUT CONSIDERATIONS
As stated previously in Input Settling, it is not critical for the performance of the SM73201 to filter out the voltage
spike that occurs when the SM73201 enters acquisition (tACQ) mode at the end of the conversion window.
However, it is critical that a system designer ensures that the transients of the spike settle out within tACQ. The
burden of this task can be placed on the analog source itself or the burden can be shared by the source and an
external capacitor, CEXT as shown in Figure 34. The external capacitor acts as a local charge reservoir for the
internal sampling capacitor and thus reduces the size of the voltage spike. For low frequency analog sources
such as sensors with DC-like output behaviors, CEXT values greater than 1 nF are recommended. However,
some sensors and signal conditioning circuitry will not be able to maintain their stability in the presence of the
external capacitive load. In these instances, a series resistor (REXT) is recommended. The magnitude of REXT is
dependent on the output capability of the analog source and the settling requirement of the ADC. Independent of
the presence of an external capacitor, the system designer always has the option of lowering the sample rate of
the SM73201 which directly controls the amount of time allowed for the voltage spike to settle. The slower the
sample rate, the longer the tACQ time or settling time. This is possible with the SM73201 since the converter
enters tACQ at the end of the prior conversion and thus is tracking the analog input source the entire time
between conversions.
POWER CONSUMPTION
The architecture, design, and fabrication process allow the SM73201 to operate at conversion rates up to 250
kSPS while consuming very little power. The SM73201 consumes the least amount of power while operating in
acquisition (power-down) mode. For applications where power consumption is critical, the SM73201 should be
operated in acquisition mode as often as the application will tolerate. To further reduce power consumption, stop
the SCLK while CS is high.
Short Cycling
Short cycling refers to the process of halting a conversion after the last needed bit is outputted. Short cycling can
be used to lower the power consumption in those applications that do not need a full 16-bit resolution, or where
an analog signal is being monitored until some condition occurs. In some circumstances, the conversion could be
terminated after the first few bits. This will lower power consumption in the converter since the SM73201 spends
more time in acquisition mode and less time in conversion mode.
Short cycling is accomplished by pulling CS high after the last required bit is received from the SM73201 output.
This is possible because the SM73201 places the latest converted data bit on DOUT as it is generated. If only 10bits of the conversion result are needed, for example, the conversion can be terminated by pulling CS high after
the 10th bit has been clocked out.
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Burst Mode Operation
Normal operation of the SM73201 requires the SCLK frequency to be 20 times the sample rate and the CS rate
to be the same as the sample rate. However, in order to minimize power consumption in applications requiring
sample rates below 250 kSPS, the SM73201 should be run with an SCLK frequency of 5 MHz and a CS rate as
slow as the system requires. When this is accomplished, the SM73201 is operating in burst mode. The SM73201
enters into acquisition mode at the end of each conversion, minimizing power consumption. This causes the
converter to spend the longest possible time in acquisition mode. Since power consumption scales directly with
conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy
the requirements of the system.
PCB LAYOUT AND CIRCUIT CONSIDERATIONS
For best performance, care should be taken with the physical layout of the printed circuit board. This is especially
true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so it is
important that any noise settles out before the conversion begins.
Analog and Digital Power Supplies
Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may
originate from switching power supplies, digital logic, high power devices, and other sources. Power to the
SM73201 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor
should be used to bypass the SM73201 supply, with the 0.1 µF capacitor placed as close to the SM73201
package as possible.
Since the SM73201 has both the VA and VIO pins, the user has three options on how to connect these pins. The
first option is to tie VA and VIO together and power them with the same power supply. This is the most cost
effective way of powering the SM73201 but is also the least ideal. As stated previously, noise from VIO can
couple into VA and adversely affect performance. The other two options involve the user powering VA and VIO
with separate supply voltages. These supply voltages can have the same amplitude or they can be different. VA
can be set to any value between +4.5V and +5.5V; while VIO can be set to any value between +2.7V and +5.5V.
Best performance will typically be achieved with VA operating at 5V and VIO at 3V. Operating VA at 5V offers the
best linearity and dynamic performance when VREF is also set to 5V; while operating VIO at 3V reduces the power
consumption of the digital logic. Operating the digital interface at 3V also has the added benefit of decreasing the
noise created by charging and discharging the capacitance of the digital interface pins.
Voltage Reference
The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor
value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the
SM73201 draws very little current from the reference on average, there are higher instantaneous current spikes
at the reference.
VREF of the SM73201, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if
VREF is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external
reference circuitry will appear in the digital results. The use of an active reference source is recommended. The
LM4040 and LM4050 shunt reference families and the SM74601, LM4120, and LM4140 series reference families
are excellent choices for a reference source.
PCB Layout
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible. Digital circuits create substantial supply and ground current transients. The logic noise
generated could have significant impact upon system noise performance. To avoid performance degradation of
the SM73201 due to supply noise, avoid using the same supply for the VA and VREF of the SM73201 that is used
for digital circuitry on the board.
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Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the
clock line should also be treated as a transmission line and be properly terminated. The analog input should be
isolated from noisy signal traces to avoid coupling of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin
and ground should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power planes are recommended. The power planes should be
located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog power plane. All digital circuitry should be placed over the digital power plane.
Furthermore, the GND pins on the SM73201 and all the components in the reference circuitry and input signal
chain that are connected to ground should be connected to the ground plane at a quiet point. Avoid connecting
these points too close to the ground point of a microprocessor, microcontroller, digital signal processor, or other
high power digital device.
APPLICATION CIRCUITS
The following figures are examples of the SM73201 in typical application circuits. These circuits are basic and
will generally require modification for specific circumstances.
Data Acquisition
Figure 36 shows a typical connection diagram for the SM73201 operating at VA of +5V. VREF is connected to a
2.5V shunt reference, the LM4020-2.5, to define the analog input range of the SM73201 independent of supply
variation on the +5V supply line. The VREF pin should be de-coupled to the ground plane by a 0.1 µF ceramic
capacitor and a tantalum capacitor of 10 µF. It is important that the 0.1 µF capacitor be placed as close as
possible to the VREF pin while the placement of the tantalum capacitor is less critical. It is also recommended that
the VA and VIO pins of the SM73201 be de-coupled to ground by a 0.1 µF ceramic capacitor in parallel with a 10
µF tantalum capacitor.
+5V
+
100:
SM73201
+
LM4020-2.5
10 PF
VREF
10 PF
VA
0.1 PF
0.1 PF
VIO
+IN
SCLK
- IN
DOUT
GND
CSB
Controller
Figure 36. Low cost, low power Data Acquisition System
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SM73201IMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
S201
SM73201IMME/NOPB
ACTIVE
VSSOP
DGS
10
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
S201
SM73201IMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 85
S201
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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