SM73307
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SNOSB88B – JUNE 2011 – REVISED APRIL 2013
Dual Precision, 17 MHz, Low Noise, CMOS Input Amplifier
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FEATURES
DESCRIPTION
•
The SM73307 is a dual, low noise, low offset, CMOS
input, rail-to-rail output precision amplifier with a high
gain bandwidth product. The SM73307 is ideal for a
variety of instrumentation applications including solar
photovoltaic.
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•
•
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Unless Otherwise Noted, Typical Values at VS
= 5V.
Renewable Energy Grade
Input Offset Voltage ±150 μV (max)
Input Bias Current 100 fA
Input Voltage Noise 5.8 nV/√Hz
Gain Bandwidth Product 17 MHz
Supply Current 1.30 mA
Supply Voltage Range 1.8V to 5.5V
THD+N @ f = 1 kHz 0.001%
Operating Temperature Range −40°C to 125°C
Rail-to-rail Output Swing
8-Pin VSSOP Package
APPLICATIONS
•
•
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Photovoltaic Electronics
Active Filters and Buffers
Sensor Interface Applications
Transimpedance Amplifiers
Automotive
Utilizing a CMOS input stage, the SM73307 achieves
an input bias current of 100 fA, an input referred
voltage noise of 5.8 nV/√Hz, and an input offset
voltage of less than ±150 μV. These features make
the SM73307 a superior choice for precision
applications.
Consuming only 1.30 mA of supply current per
channel, the SM73307 offers a high gain bandwidth
product of 17 MHz, enabling accurate amplification at
high closed loop gains.
The SM73307 has a supply voltage range of 1.8V to
5.5V, which makes it an ideal choice for portable low
power applications with low supply voltage
requirements.
The SM73307 is built with TI’s advanced VIP50
process technology and is offered in an 8-pin VSSOP
package.
The SM73307 incorporates enhanced manufacturing
and support processes for the photovoltaic and
automotive market, including defect detection
methodologies. Reliability qualification is compliant
with the requirements and temperature grades
defined in the Renewable Energy Grade and AECQ100 standards.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
SM73307
SNOSB88B – JUNE 2011 – REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance (3)
Human Body Model
2000V
Machine Model
200V
Charge-Device Model
1000V
VIN Differential
±0.3V
Supply Voltage (VS = V+ – V−)
6.0V
Voltage on Input/Output Pins
V+ +0.3V, V− −0.3V
Storage Temperature Range
−65°C to 150°C
Junction Temperature (4)
+150°C
Soldering Information
(1)
(2)
(3)
(4)
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temp. (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional. For specifications and the test conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings (1)
Temperature Range (2)
−40°C to 125°C
−
+
Supply Voltage (VS = V – V )
Package Thermal Resistance (θJA (2))
(1)
(2)
0°C ≤ TA ≤ 125°C
1.8V to 5.5V
−40°C ≤ TA ≤ 125°C
2.0V to 5.5V
8-Pin VSSOP
236°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional. For specifications and the test conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC Board.
2.5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2. Boldface limits apply
at the temperature extremes.
Symbol
VOS
(1)
(2)
(3)
(4)
(5)
2
Min (1)
Max (1)
−20°C ≤ TA ≤ 85°C
±20
±180
±330
−40°C ≤ TA ≤ 125°C
±20
±180
±430
–1.75
±4
−40°C ≤ TA ≤ 85°C
0.05
1
25
−40°C ≤ TA ≤ 125°C
0.05
1
100
Conditions
Input Offset Voltage
TC VOS
IB
Typ (2)
Parameter
Input Offset Voltage Temperature
Drift (3) (4)
Input Bias Current
VCM = 1.0V
(5) (4)
Units
μV
μV/°C
pA
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
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2.5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 2.5V, V− = 0V ,VO = VCM = V+/2. Boldface limits apply
at the temperature extremes.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
0.006
0.5
50
pA
IOS
Input Offset Current
VCM = 1V (4)
CMRR
Common Mode Rejection Ratio
0V ≤ VCM ≤ 1.4V
83
80
100
2.0V ≤ V+ ≤ 5.5V
V− = 0V, VCM = 0
85
80
100
1.8V ≤ V+ ≤ 5.5V
V− = 0V, VCM = 0
85
98
PSRR
CMVR
AVOL
Power Supply Rejection Ratio
Common Mode Voltage Range
Open Loop Voltage Gain
Output Voltage Swing
High
CMRR ≥ 80 dB
CMRR ≥ 78 dB
dB
−0.3
–0.3
1.5
1.5
VO = 0.15 to 2.2V
RL = 2 kΩ to V+/2
84
80
92
VO = 0.15 to 2.2V
RL = 10 kΩ to V+/2
90
86
95
IOUT
Output Current
IS
Supply Current
RL = 2 kΩ to V+/2
25
70
77
RL = 10 kΩ to V+/2
20
60
66
RL = 2 kΩ to V+/2
30
70
73
RL = 10 kΩ to V+/2
15
60
62
SR
Slew Rate
GBW
Gain Bandwidth
en
Input Referred Voltage Noise Density
in
Input Referred Current Noise Density
THD+N
(6)
Total Harmonic Distortion + Noise
Sourcing to V−
VIN = 200 mV (6)
36
30
52
Sinking to V+
VIN = −200 mV (6)
7.5
5.0
15
Per Channel
V
dB
VOUT
Output Voltage Swing
Low
dB
mV from
either rail
mA
1.10
AV = +1, Rising (10% to 90%)
8.3
AV = +1, Falling (90% to 10%)
10.3
f = 400 Hz
6.8
f = 1 kHz
5.8
f = 1 kHz
0.01
f = 1 kHz, AV = 1, RL = 100 kΩ
VO = 0.9 VPP
0.003
f = 1 kHz, AV = 1, RL = 600Ω
VO = 0.9 VPP
0.004
1.50
1.85
mA
V/μs
14
MHz
nV/√Hz
pA/√Hz
%
The short circuit test is a momentary open loop test.
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5V Electrical Characteristics
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2. Boldface limits apply at the
temperature extremes.
Symbol
VOS
Typ (2)
Max (1)
−20°C ≤ TA ≤ 85°C
±10
±150
±300
−40°C ≤ TA ≤ 125°C
±10
±150
±400
–1.75
±4
−40°C ≤ TA ≤ 85°C
0.1
1
25
−40°C ≤ TA ≤ 125°C
0.1
1
100
0.01
0.5
50
Parameter
Min (1)
Conditions
Input Offset Voltage
TC VOS
IB
Input Offset Voltage Temperature
Drift (3) (4)
Input Bias Current
VCM = 2.0V
(5) (4)
IOS
Input Offset Current
VCM = 2.0V (4)
CMRR
Common Mode Rejection Ratio
0V ≤ VCM ≤ 3.7V
85
82
100
2.0V ≤ V ≤ 5.5V
V− = 0V, VCM = 0
85
80
100
1.8V ≤ V+ ≤ 5.5V
V− = 0V, VCM = 0
85
98
+
PSRR
CMVR
AVOL
Power Supply Rejection Ratio
Common Mode Voltage Range
Open Loop Voltage Gain
Output Voltage Swing
High
CMRR ≥ 80 dB
CMRR ≥ 78 dB
IOUT
IS
(1)
(2)
(3)
(4)
(5)
(6)
4
Output Current
Supply Current
VO = 0.3 to 4.7V
RL = 2 kΩ to V+/2
84
80
90
VO = 0.3 to 4.7V
RL = 10 kΩ to V+/2
90
86
95
pA
pA
V
dB
RL = 2 kΩ to V+/2
32
70
77
RL = 10 kΩ to V+/2
22
60
66
RL = 2 kΩ to V /2
45
75
78
RL = 10 kΩ to V+/2
20
60
62
Sourcing to V−
VIN = 200 mV (6)
46
38
66
Sinking to V+
VIN = −200 mV (6)
10.5
6.5
23
(per channel)
μV/°C
dB
4
4
VOUT
Output Voltage Swing
Low
μV
dB
−0.3
–0.3
+
Units
mV from
either rail
mA
1.30
1.70
2.05
mA
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration.
Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
This parameter is specified by design and/or characterization and is not tested in production.
Positive current corresponds to current flowing into the device.
The short circuit test is a momentary open loop test.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2. Boldface limits apply at the
temperature extremes.
Symbol
SR
Slew Rate
GBW
Gain Bandwidth
Typ (2)
AV = +1, Rising (10% to 90%)
6.0
9.5
AV = +1, Falling (90% to 10%)
7.5
11.5
Conditions
17
en
Input Referred Voltage Noise Density
in
Input Referred Current Noise Density
THD+N
Min (1)
Parameter
Total Harmonic Distortion + Noise
f = 400 Hz
7.0
f = 1 kHz
5.8
f = 1 kHz
0.01
f = 1 kHz, AV = 1, RL = 100 kΩ
VO = 4 VPP
0.001
f = 1 kHz, AV = 1, RL = 600Ω
VO = 4 VPP
0.004
Max (1)
Units
V/μs
MHz
nV/√Hz
pA/√Hz
%
Connection Diagram
-IN A
+IN A
V
-
8
1
2
3
4
-
OUT A
7
+
+-
6
5
+
V
OUT B
-IN B
+IN B
Figure 1. 8-Pin VSSOP – Top View
See Package Number DGK
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Typical Performance Characteristics
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Offset Voltage Distribution
25
VS = 5.5V
VCM = VS/2
UNITS TESTED: 10,000
VOLTAGE NOISE (nV/ Hz)
20
PERCENTAGE (%)
Input Referred Voltage Noise
100
VS = 5V
15
10
5
0
-200
VS = 2.5V
10
1
-100
0
100
1
200
10
Figure 2.
Figure 3.
VCM = VS/2
UNITS TESTED:10,000
PERCENTAGE (%)
PERCENTAGE (%)
20
15
10
5
-100
0
100
VCM = VS/2
UNITS TESTED: 10,000
15
10
0
-200
200
-100
0
100
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
Figure 4.
Figure 5.
TCVOS Distribution
Offset Voltage
vs.
VCM
200
200
-40°C d TA d 125°C
VS = 1.8V
VS = 2.5V, 5V
150
20 VCM = VS/2
UNITS TESTED:
10,000
15
OFFSET VOLTAGE (PV)
PERCENTAGE (%)
VS = 5V
5
0
-200
25
100k
Offset Voltage Distribution
25
VS = 2.5V
20
10k
FREQUENCY (Hz)
Offset Voltage Distribution
25
1k
100
OFFSET VOLTAGE (PV)
10
5
-40°C
100
50
25°C
0
-50
125°C
-100
-150
0
-4
-3
-2
-1
-200
-0.3
0
TCVOS (PV/°C)
0.3
0.6
0.9
1.2
1.5
VCM (V)
Figure 6.
6
0
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Offset Voltage
vs.
VCM
Offset Voltage
vs.
VCM
200
200
VS = 2.5V
VS = 5V
150
-40°C
OFFSET VOLTAGE (PV)
OFFSET VOLTAGE (PV)
150
100
25°C
50
0
125°C
-50
-100
-150
-40°C
50
25°C
0
125°C
-50
-100
-150
-200
-0.3
0
0.3
0.6
0.9
1.2
1.5
1.8
-200
-0.3
2.1
1.7
2.7
VCM (V)
Figure 8.
Figure 9.
Offset Voltage
vs.
Supply Voltage
CMRR
vs.
Frequency
200
120
150
100
100
0.7
VCM (V)
3.7
4.7
VS = 2.5V
-40°C
80
50
CMRR (dB)
OFFSET VOLTAGE (PV)
100
25°C
0
125°C
-50
VS = 5V
60
40
-100
20
-150
0
10
-200
1.5
2.5
3.5
4.5
VS (V)
5.5
6
10k
1k
100k
1M
FREQUENCY (Hz)
Figure 10.
Figure 11.
Input Bias Current
vs.
VCM
Input Bias Current
vs.
VCM
50
1000
VS = 5V
0
-500
-40°C
-1000
VS = 5V
40
INPUT BIAS CURRENT (pA)
25°C
500
INPUT BIAS CURRENT (fA)
100
-1500
-2000
-2500
30
20
125°C
10
0
-10
85°C
-20
-30
-40
-50
-3000
0
1
2
3
4
0
1
2
3
4
VCM (V)
VCM (V)
Figure 12.
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Supply Current
vs.
Supply Voltage
Crosstalk Rejection Ratio
160
CROSSTALK REJECTION RATIO (dB)
2
SUPPLY CURRENT (mA)
125°C
1.6
25°C
1.2
-40°C
0.8
0.4
140
120
100
80
60
40
20
0
0
1.5
2.5
3.5
4.5
1k
5.5
Figure 14.
Figure 15.
Sourcing Current
vs.
Supply Voltage
Sinking Current
vs.
Supply Voltage
35
30
60
125°C
25
50
ISINK (mA)
ISOURCE (mA)
100M
125°C
70
-40°C
25°C
40
30
25°C
20
15
10
20
-40°C
5
10
0
1.5
2.5
3.5
4.5
0
1.5
5.5
2.5
3.5
VS (V)
4.5
5.5
VS (V)
Figure 16.
Figure 17.
Sourcing Current
vs.
Output Voltage
Sinking Current
vs.
Output Voltage
70
30
125°C
60
125°C
25
50
20
-40°C
40
ISINK (mA)
ISOURCE (mA)
10M
FREQUENCY (Hz)
80
25°C
30
25°C
15
10
20
-40°C
5
10
0
0
0
8
1M
100k
10k
VS (V)
1
2
3
4
5
0
1
2
3
VOUT (V)
VOUT (V)
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Output Swing High
vs.
Supply Voltage
Output Swing Low
vs.
Supply Voltage
50
50
RL =10 k:
40
30
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
RL = 10 k:
25°C
125°C
20
-40°C
10
40
30
-40°C
20
125°C
10
0
25°C
0
1.5
2.5
3.5
4.5
5.5
1.5
2.5
3.5
4.5
VS (V)
VS (V)
Figure 20.
Figure 21.
Output Swing High
vs.
Supply Voltage
Output Swing Low
vs.
Supply Voltage
50
5.5
50
RL = 2 k:
125°C
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
-40°C
40
25°C
30
20
-40°C
10
40
125°C
30
25°C
20
10
RL = 2 k:
0
1.5
2.5
3.5
4.5
0
1.5
5.5
2.5
3.5
4.5
VS (V)
VS (V)
Figure 22.
Figure 23.
Output Swing High
vs.
Supply Voltage
Output Swing Low
vs.
Supply Voltage
150
150
RL = 600:
RL = 600:
120
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
5.5
90
125°C
25°C
60
30
120
25°C
125°C
90
-40°C
60
30
-40°C
0
0
1.5
2.5
3.5
4.5
5.5
1.5
2.5
3.5
VS (V)
VS (V)
Figure 24.
Figure 25.
4.5
5.5
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Open Loop Frequency Response
CL = 50 pF
GAIN (dB)
GAIN
40
CL = 100 pF
100
80
80
80
60
60
60
40
20
20
0
-20
CL = 50 pF
-40
CL = 100 pF
1k
10k
100k
1M
10M
40
GAIN
20
20
0
0
-20
-20
-40
-40
-20
-40
RL = 600: 10 k: 10 M:
-60
10k
100k
1M
-60
100M
-60
Figure 26.
Figure 27.
Phase Margin
vs.
Capacitive Load
Phase Margin
vs.
Capacitive Load
50
50
RL = 600:
40
RL = 600:
PHASE MARGIN (°)
PHASE MARGIN (°)
40
30
RL = 10 k:
RL = 10 M:
20
10
RL = 10 k:
30
20
RL = 10 M:
10
VS = 2.5V
VS = 5V
0
0
10
100
1000
10
100
1000
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 28.
Figure 29.
Overshoot and Undershoot
vs.
Capacitive Load
Slew Rate
vs.
Supply Voltage
12
70
UNDERSHOOT%
60
FALLING EDGE
11
50
SLEW RATE (V/Ps)
OVERSHOOT AND UNDERSHOOT (%)
10M
-60
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
OVERSHOOT %
40
30
20
10
9
RISING EDGE
8
10
0
10
100
40
0
CL = 20 pF
PHASE
100
PHASE (°)
CL = 20 pF
80
120
120
GAIN (dB)
100
60
Open Loop Frequency Response
120
PHASE
PHASE (°)
120
0
20
40
60
80
100
120
7
1.5
2.5
3.5
4.5
CAPACITIVE LOAD (pF)
VS (V)
Figure 30.
Figure 31.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Large Signal Step Response
10 mV/DIV
200 mV/DIV
Small Signal Step Response
VIN = 20 mVPP
f = 1 MHz, AV = +1
VIN = 1 VPP
f = 200 kHz, AV = +1
VS = 2.5V, CL = 10 pF
VS = 2.5V, CL = 10 pF
800 ns/DIV
Figure 33.
Small Signal Step Response
Large Signal Step Response
10 mV/DIV
200 mV/DIV
200 ns/DIV
Figure 32.
VIN = 20 mVPP
VIN = 1 VPP
f = 200 kHz, AV = +1
VS = 5V, CL = 10 pF
f = 1 MHz, AV = +1
VS = 5V, CL = 10 pF
200 ns/DIV
800 ns/DIV
Figure 34.
Figure 35.
THD+N
vs.
Output Voltage
THD+N
vs.
Output Voltage
0
0
-20
AV = +2
AV = +2
-60
RL = 600:
-80
-60
RL = 600:
-80
-100
-100
-120
RL = 100 k:
-120
0.01
VS = 5.5V
f = 1 kHz
-40
-40
THD+N (dB)
THD+N (dB)
-20
VS = 1.8V
f = 1 kHz
0.1
1
10
-140
0.01
RL = 100 k:
0.1
1
OUTPUT AMPLITUDE (VPP)
OUTPUT AMPLITUDE (VPP)
Figure 36.
Figure 37.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
THD+N
vs.
Frequency
0.006
THD+N
vs.
Frequency
0.006
VS = 1.8V
VS = 5V
VO = 0.9 VPP
0.005
AV = +2
AV = +2
0.004
THD+N (%)
0.004
THD+N (%)
VO = 4 VPP
0.005
RL = 600:
RL = 100 k:
0.003
RL = 600:
0.003
0.002
0.002
0.001
0.001
0
0
RL = 100 k:
10
100
1k
10k
10
100k
100
FREQUENCY (Hz)
10k
100k
Figure 38.
Figure 39.
PSRR
vs.
Frequency
Input Referred Voltage Noise
vs.
Frequency
100
120
VS = 5.5V
VS = 5.5V, -PSRR
VOLTAGE NOISE (nV/ Hz)
VS = 1.8V, -PSRR
80
VS = 5.5V, +PSRR
60
40
VS = 1.8V, +PSRR
20
VS = 2.5V
10
1
0
10
100
1k
10k
100k
1M
1
10M
10
1k
100
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 40.
Figure 41.
Time Domain Voltage Noise
Closed Loop Frequency Response
5
VS = ±2.5V
VCM = 0.0V
GAIN (dB)
400 nV/DIV
100k
225
VS = 5V
4
RL = 2 k:
180
3
CL = 20 pF
135
2
VO = 2 VPP
90
1
AV = +1
45
0
0
-45
-1
PHASE
-2
-90
-135
-3
GAIN
-4
-5
1 s/DIV
PHASE (°)
100
PSRR (dB)
1k
FREQUENCY (Hz)
100
1k
10k
100 k
1M
-180
-225
10M
FREQUENCY (Hz)
Figure 42.
12
Figure 43.
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Typical Performance Characteristics (continued)
Unless otherwise noted: TA = 25°C, VS = 5V, VCM = VS/2.
Closed Loop Output Impedance
vs.
Frequency
OUTPUT IMPEDANCE (:)
100
10
1
0.1
0.01
10
100
1k
10k 100k
1M
10M 100M
FREQUENCY (Hz)
Figure 44.
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APPLICATION INFORMATION
The SM73307 is a dual, low noise, low offset, rail-to-rail output precision amplifier with a wide gain bandwidth
product of 17 MHz and low supply current. The wide bandwidth makes the SM73307 an ideal choice for wideband amplification in photovoltaic and portable applications.
The SM73307 is superior for sensor applications. The very low input referred voltage noise of only 5.8 nV/√Hz at
1 kHz and very low input referred current noise of only 10 fA/√Hz mean more signal fidelity and higher signal-tonoise ratio.
The SM73307 has a supply voltage range of 1.8V to 5.5V over a wide temperature range of 0°C to 125°C. This
is optimal for low voltage commercial applications. For applications where the ambient temperature might be less
than 0°C, the SM73307 is fully operational at supply voltages of 2.0V to 5.5V over the temperature range of
−40°C to 125°C.
The outputs of the SM73307 swing within 25 mV of either rail providing maximum dynamic range in applications
requiring low supply voltage. The input common mode range of the SM73307 extends to 300 mV below ground.
This feature enables users to utilize this device in single supply applications.
The use of a very innovative feedback topology has enhanced the current drive capability of the SM73307,
resulting in sourcing currents of as much as 47 mA with a supply voltage of only 1.8V.
The SM73307 is offered in an 8-pin VSSOP package. This small package is an ideal solution for applications
requiring minimum PC board footprint.
CAPACITIVE LOAD
The unity gain follower is the most sensitive configuration to capacitive loading. The combination of a capacitive
load placed directly on the output of an amplifier along with the output impedance of the amplifier creates a
phase lag which in turn reduces the phase margin of the amplifier. If phase margin is significantly reduced, the
response will be either under-damped or the amplifier will oscillate.
The SM73307 can directly drive capacitive loads of up to 120 pF without oscillating. To drive heavier capacitive
loads, an isolation resistor, RISO as shown in Figure 45, should be used. This resistor and CL form a pole and
hence delay the phase lag or increase the phase margin of the overall system. The larger the value of RISO, the
more stable the output voltage will be. However, larger values of RISO result in reduced output swing and
reduced output current drive.
Figure 45. Isolating Capacitive Load
INPUT CAPACITANCE
CMOS input stages inherently have low input bias current and higher input referred voltage noise. The SM73307
enhances this performance by having the low input bias current of only 50 fA, as well as, a very low input
referred voltage noise of 5.8 nV/ . In order to achieve this a larger input stage has been used. This larger input
stage increases the input capacitance of the SM73307. Figure 46 shows typical input common mode capacitance
of the SM73307.
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25
VS = 5V
CCM (pF)
20
15
10
5
0
0
1
2
3
4
VCM (V)
Figure 46. Input Common Mode Capacitance
This input capacitance will interact with other impedances, such as gain and feedback resistors which are seen
on the inputs of the amplifier, to form a pole. This pole will have little or no effect on the output of the amplifier at
low frequencies and under DC conditions, but will play a bigger role as the frequency increases. At higher
frequencies, the presence of this pole will decrease phase margin and also cause gain peaking. In order to
compensate for the input capacitance, care must be taken in choosing feedback resistors. In addition to being
selective in picking values for the feedback resistor, a capacitor can be added to the feedback path to increase
stability.
The DC gain of the circuit shown in Figure 47 is simply −R2/R1.
CF
R2
R1
+
VIN
CIN
+
+
-
-
AV = -
VOUT
VIN
=-
VOUT
R2
R1
Figure 47. Compensating for Input Capacitance
For the time being, ignore CF. The AC gain of the circuit in Figure 47 can be calculated as follows:
-R2/R1
(s) =
1+
s2
s
+
§ A0 R 1
§ A0
¨
¨C R
+
R
R
2
1
©
© IN 2
§
¨
©
VIN
§
¨
©
VOUT
(1)
This equation is rearranged to find the location of the two poles:
1
1
+
r
R1
R2
§1
1
+
¨
R2
© R1
§
¨
©
-1
P1,2 =
2CIN
2
-
4 A0CIN
R2
(2)
As shown in Equation 2, as the values of R1 and R2 are increased, the magnitude of the poles are reduced,
which in turn decreases the bandwidth of the amplifier. Figure 48 shows the frequency response with different
value resistors for R1 and R2. Whenever possible, it is best to choose smaller feedback resistors.
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15
AV = -1
10
GAIN (dB)
5
0
-5
R1, R2 = 30 k:
-10
R1, R2 = 10 k:
-15
R1, R2 = 1 k:
-20
-25
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 48. Closed Loop Frequency Response
As mentioned before, adding a capacitor to the feedback path will decrease the peaking. This is because CF will
form yet another pole in the system and will prevent pairs of poles, or complex conjugates from forming. It is the
presence of pairs of poles that cause the peaking of gain. Figure 49 shows the frequency response of the
schematic presented in Figure 47 with different values of CF. As can be seen, using a small value capacitor
significantly reduces or eliminates the peaking.
20
R1, R2 = 30 k:
10
CF = 0 pF
AV = -1
GAIN (dB)
0
CF = 5 pF
-10
CF = 2 pF
-20
-30
-40
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 49. Closed Loop Frequency Response
TRANSIMPEDANCE AMPLIFIER
In many applications the signal of interest is a very small amount of current that needs to be detected. Current
that is transmitted through a photodiode is a good example. Barcode scanners, light meters, fiber optic receivers,
and industrial sensors are some typical applications utilizing photodiodes for current detection. This current
needs to be amplified before it can be further processed. This amplification is performed using a current-tovoltage converter configuration or transimpedance amplifier. The signal of interest is fed to the inverting input of
an op amp with a feedback resistor in the current path. The voltage at the output of this amplifier will be equal to
the negative of the input current times the value of the feedback resistor. Figure 50 shows a transimpedance
amplifier configuration. CD represents the photodiode parasitic capacitance and CCM denotes the common-mode
capacitance of the amplifier. The presence of all of these capacitances at higher frequencies might lead to less
stable topologies at higher frequencies. Care must be taken when designing a transimpedance amplifier to
prevent the circuit from oscillating.
With a wide gain bandwidth product, low input bias current and low input voltage and current noise, the SM73307
is ideal for wideband transimpedance applications.
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CF
RF
IIN
CCM
+
+
VOUT
CD
-
VB
CIN = CD + CCM
VOUT
= - RF
IIN
Figure 50. Transimpedance Amplifier
A feedback capacitance CF is usually added in parallel with RF to maintain circuit stability and to control the
frequency response. To achieve a maximally flat, 2nd order response, RF and CF should be chosen by using
Equation 3:
CF =
CIN
GBWP
2 S RF
(3)
Calculating CF from Equation 3 can sometimes result in capacitor values which are less than 2 pF. This is
especially the case for high speed applications. In these instances, it is often more practical to use the circuit
shown in Figure 51 in order to allow more sensible choices for CF. The new feedback capacitor, CF′, is (1+
RB/RA) CF. This relationship holds as long as RA
