SN10KHT5574NTG4

   
  
 
 
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 • • • • • DW OR NT PACKAGE (TOP VIEW) 10KH Compatible ECL Clock and TTL Control Inputs 1Q 2Q 3Q 4Q VCC GND GND GND 5Q 6Q 7Q 8Q Flow-Through Architecture Optimizes PCB Layout Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include “Small Outline” Packages and Standard Plastic DIPs description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1D 2D 3D 4D OE(TTL) VEE GND CLK(ECL) 5D 6D 7D 8D 13 12 This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs. A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off. The SN10KHT5574 is characterized for operation from 0°C to 75°C. FUNCTION TABLE OUTPUT (TTL) INPUTS OE CLK D L ↑ L Q L L ↑ H H L L X Qo H X X Z Copyright  1990, Texas Instruments Incorporated    !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 
   
  
 
 
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 logic symbol† CLK 17 20 OE 1D 2D 3D 4D 5D 6D 7D 8D 24 logic diagram (positive logic) ECL/TTL C1 OE EN 1D CLK ECL/TTL 1 23 2 22 3 21 4 16 9 15 10 14 11 13 12 1Q 1D 20 17 24 ECL/TTL ECL/TTL C1 1D 1 C1 2 2Q 3Q 2D 4Q 23 ECL/TTL 5Q 3D 6Q 22 ECL/TTL 7Q 4D 5D 6D 7D 21 16 15 14 ECL/TTL C1 8D • 9 1D C1 1D 10 ECL/TTL C1 11 ECL/TTL POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 4 ECL/TTL ECL/TTL 3Q 4Q 1D 5Q 6Q 7Q 1D C1 13 3 1D C1 8Q 2Q 1D C1 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1Q 1D 12 8Q 
   
  
 
 
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 absolute maximum ratings over operating temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to 0 V Input voltage range: TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Input current range, (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions MIN NOM MAX UNIT VCC VEE TTL supply voltage 4.5 5 5.5 V ECL supply voltage −4.94 −5.2 −5.46 V VIH VIL TTL high-level input voltage VIH VIL IIK IOH 2 TTL low-level input voltage V 0.8 ECL high-level input voltage‡ ECL low-level input voltage‡ TA = 0°C TA = 25°C −1170 −840 −1130 −810 TA = 75°C TA = 0°C −1070 −735 −1950 −1480 TA = 25°C TA = 75°C −1950 −1480 −1950 −1450 V mV mV TTL input clamp current −18 mA High-level output current −15 mA IOL Low-level output current 48 mA TA Operating free-air temperature range 0 75 °C ‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 
   
  
 
 
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK OE only VOH VOL II OE only IIH IIL IIH IIL OE only OE only Data inputs and CLK Data inputs and CLK IOZH IOZL IOS‡ ICCH ICCL ICCZ IEE Ci TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V, VEE = − 4.94 V, VEE = − 5.2 V ±5%, II = − 18 mA IOH = − 3 mA VCC = 4.5 V, VCC = 4.5 V, VEE = − 5.2 V ±5%, VEE = − 5.2 V ±5%, IOH = − 15 mA IOL = 48 mA VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V, VI = 7 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V, VI = 0.5 V VI = − 840 mV VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V, VI = − 810 mV VI = − 735 mV VCC = 5.5 V, VEE = − 5.46 V, VI = − 1950 mV VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V, VO = 2.7 V VO = 0.5 V VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V VO = 0 V VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TYP† 2.4 3.3 2 3.1 0.38 MAX UNIT −1.2 V V 0.55 V 0.1 mA 20 µA −0.5 mA TA = 0°C TA = 25°C 350 TA = 75°C TA = 0°C 350 350 µA 0.5 TA = 25°C TA = 75°C µA 0.5 0.5 −100 50 µA −50 µA −225 mA 66 95 mA VEE = − 5.46 V VEE = − 5.46 V 76 110 mA 74 106 mA VEE = − 5.46 V VEE = − 5.2 V, −43 −61 mA f = 10 MHz Co VCC = 5.5 V, VEE = − 5.2 V, f = 10 MHz † All typical values are at VCC = 5 V, VEE = − 5.2 V, TA = 25°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. 5 pF 7 pF timing requirements VCC = 4.5 V to 5.5 V, VEE = − 4.94 V to − 5.46 V, TA = MIN to MAX§ MIN tw Pulse duration tsu Setup time before CLK↑ th Hold time after CLK↑ CLK high 4 CLK low 4 Data high 1 Data low 1 Data high 1 Data low 1 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT MAX ns ns ns 
   
  
 
 
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 switching characteristics over recommended ranges of operating free-air temperature and supply voltage (see Figure 1) PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ FROM TO (INPUT) (OUTPUT) CLK Q OE Q Q OE tPLZ † All typical values are at VCC = 5 V, VEE = − 5.2 V, TA = 25°C. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω MIN TYP† MAX UNIT 200 300 MHz 2.3 4.1 7 2.9 4.6 7.4 1.9 3.6 6.3 2.7 4.8 7.7 2.1 3.9 6.1 0.5 3.4 6.3 ns ns ns 5 
   
  
 
 
SDZS010 − JANUARY 1990 − REVISED OCTOBER 1990 PARAMETER MEASUREMENT INFORMATION 7V Open SWITCH POSITION TABLE S1 From Output Under Test Test Point CL (See Note A) S1 Open Open Open Closed Open Closed TEST tPLH tPHL tPZH tPZL tPHZ tPLZ R1 R2 LOAD CIRCUIT tf tr ECL Input (See Note C) 80% 80% 50% 20% −890 mV 50% 20% −1690 mV −1690 mV −890 mV Low-Level Input VOH Out-of-Phase TTL Output tPHL VOH 1.5 V 1.5 V tr tf 80% 80% 50% 50% 1.5 V tPLZ Output Waveform 1 (See Note D) −890 mV Output Waveform 2 (See Note D) −890 mV 50% 20% tr 3.5 V 1.5 V −1690 mV th 80% 80% 50% 1.5 V 0 tPZH tsu 20% 20% 3V tPZL VOLTAGE WAVEFORMS ECL-INPUT PROPAGATION DELAY TIMES Data Input −1690 mV Output Control (Low-Level Enabling) VOL 20% 50% VOLTAGE WAVEFORMS PULSE DURATION VOL tPLH Timing Input 50% 1.5 V 1.5 V In-Phase TTL Output 50% 50% tw tPLH tPHL −890 mV High-Level Input tPHZ VOL 0.3 V VOH 1.5 V 0.3 V 0 −1690 mV VOLTAGE WAVEFORMS TTL ENABLE AND DISABLE TIMES tf VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A.CL includes probe and jig capacitance. B. For TTL inputs, input pulses are supplied by generators having the following characteristics PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 1.5 ns, tf ≤ 1.5 ns. D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load circuit and voltage waveforms 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN10KHT5574DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 10KHT5574 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of