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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs
1 Features
3 Description
•
The SNx4LS24x, SNx4S24x octal buffers and line
drivers are designed specifically to improve both the
performance and density of three-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. The designer has a choice
of selected combinations of inverting and noninverting outputs, symmetrical, active-low outputcontrol (G) inputs, and complementary output-control
(G and G) inputs. These devices feature high fan-out,
improved fan-in, and 400-mV noise margin. The
SN74LS24x and SN74S24x devices can be used to
drive terminated lines down to 133 Ω.
1
•
•
•
•
Inputs Tolerant Down to 2 V, Compatible With
3.3-V or 2.5-V Logic Inputs
Maximum tpd of 15 ns at 5 V
3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
PNP Inputs Reduce DC Loading
Hysteresis at Inputs Improves Noise Margins
2 Applications
•
•
•
•
•
•
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
CDIP (20) – J
24.20 mm × 6.92 mm
CFP (20) – W
7.02 mm × 13.72 mm
LCCC (20) – FK
8.89 mm × 8.89 mm
SSOP (20) – DB
7.20 mm × 5.30 mm
SN74LS24x,
SN74S24x
SOIC (20) – DW
12.80 mm × 7.50 mm
PDIP (20) – N
24.33 mm × 6.35 mm
SN74LS24x
SOP (20) – NS
7.80 mm × 12.60 mm
SN54LS24x,
SN54S24x
SN74LS240,
SN74LS244
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
µ/6240, µ6240
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics – SNx4LS24x....................
Electrical Characteristics – SNx4S24x......................
Switching Characteristics – SNx4LS24x...................
Switching Characteristics – SNx4S24x.....................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
7.1 SN54LS24x and SN74LS24x Devices...................... 7
7.2 SN54S24x and SN74S24x Devices.......................... 9
8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
9.3 System Examples ................................................... 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (May 2010) to Revision D
Page
•
Added Applications section, ESD Ratings table, Feature Description section, Device Functional Modes, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
•
Changed RθJA values in the Thermal Information table from 70 to 94.3 (DB), from 58 to 90.3 (DW), from 69 to 50.6
(N), and from 60 to 76.6 (NS)................................................................................................................................................. 5
2
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SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
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SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
5 Pin Configuration and Functions
DB, DW, J, N, NS, or W Package
20-Pin SSOP, SOIC, CDIP, PDIP, SOP, or CFP
Top View
2Y3
5
16
1Y2
1A3
6
15
2A3
2Y2
7
14
1A4
8
2Y1
GND
2G/2G
2A4
19
1Y1
17
VCC
18
4
20
3
1A2
1G
2Y4
1
2G/2G
1A1
VCC
19
2
20
2
2Y4
1
3
1G
1A1
FK Package
20-Pin LCCC
Top View
1Y3
2Y3
5
17
2A4
13
2A2
1A3
6
16
1Y2
9
12
1Y4
2Y2
7
15
2A3
10
11
2A1
1A4
8
14
1Y3
2A2
1Y4
2A1
GND
2Y1
9
Not to scale
13
1Y1
12
18
11
4
10
1A2
Not to scale
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
1G
I
Channel 1 output enable
2
1A1
I
Channel 1, A side 1
3
2Y4
O
Channel 2, Y side 4
4
1A2
I
Channel 1, A side 2
5
2Y3
O
Channel 2, Y side 3
6
1A3
I
Channel 1, A side 3
7
2Y2
O
Channel 2, Y side 2
8
1A4
I
Channel 1, A side 4
9
2Y1
O
Channel 2, Y side 1
10
GND
—
Ground
11
2A1
I
Channel 2, A side 1
12
1Y4
O
Channel 1, Y side 4
13
2A2
I
Channel 2, A side 2
14
1Y3
O
Channel 1, Y side 3
15
2A3
I
Channel 2, A side 3
16
1Y2
O
Channel 1, Y side 2
17
2A4
I
Channel 2, A side 4
18
1Y1
O
Channel 1, Y side 1
I
Channel 2 output enable
19
2G/2G
20
VCC
(1)
(1)
—
Power supply
2G for SNx4LS241 and SNx4S241 or 2G for all other drivers.
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SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage, VCC (2)
Input voltage, VI
V
7
SNx4S24x
5.5
Storage temperature, Tstg
(2)
UNIT
7
SNx4LS24x
Off-state output voltage
(1)
MAX
–65
V
5.5
V
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
500
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
500
V
ALL PACKAGES
V(ESD)
Electrostatic discharge
N PACKAGE
V(ESD)
(1)
(2)
Electrostatic discharge
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage (1)
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
MIN
NOM
MAX
SN54xS24x
4.5
5
5.5
SN74xS24x
4.75
5
5.25
2
(1)
(2)
4
Operating free-air temperature (2)
V
V
SN54LS24x
0.7
SN54S24x, SN74xS24x
0.8
SN54xS24x
–12
SN74xS24x
–15
SN54LS24x
12
SN54S24x
48
SN74LS24x
24
SN74S24x
64
External resistance between any input and VCC or ground (SNx4S24x only)
TA
UNIT
40
SN54xS24x
–55
125
SN74xS24x
0
70
V
mA
mA
kΩ
°C
Voltage values are with respect to network ground terminal.
An SN54S241J operating at free-air temperature above 116°C requires a heat sink that provides a thermal resistance from case to free
air, RθCA, of not more that 40°C/W.
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SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
6.4 Thermal Information
THERMAL METRIC
SN74LS240,
SN74LS244
(1)
SN74LS24x, SN74S24x
SN74LS24x
DB (SSOP)
DW (SOIC)
N (PDIP)
NS (SOP)
20 PINS
20 PINS
20 PINS
20 PINS
(2) (3)
UNIT
RθJA
Junction-to-ambient thermal resistance
94.3
90.3
50.6
76.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.9
45.5
37.4
42.9
°C/W
RθJB
Junction-to-board thermal resistance
49.5
48.1
31.5
44.1
°C/W
ψJT
Junction-to-top characterization parameter
21.3
19.4
24
19.2
°C/W
ψJB
Junction-to-board characterization parameter
49.1
47.6
31.4
43.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Voltage values are with respect to network ground terminal.
The package thermal impedance is calculated in accordance with JESD 51-7.
(2)
(3)
6.5 Electrical Characteristics – SNx4LS24x
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP (2)
VIK
VCC = MIN, II = –18 mA
Hysteresis
(VT+ − VT−)
VCC = MIN
0.2
0.4
VCC = MIN, IOH = –3 mA, VIH = 2 V, VIL = MAX
2.4
3.4
VOH
VCC = MIN, IOH = MAX, VIH = 2 V, VIL = 0.5 V
MAX
UNIT
–1.5
V
V
V
2
IOL = 12 mA, SN54LS24x
0.4
IOL = 24 mA, SN74LS24x
0.5
VOL
VCC = MIN, VIL = MAX, VIH = 2 V
IOZH
VCC = MAX, VIL = MAX, VIH = 2 V, VO = 2.7 V
20
IOZL
VCC = MAX, VIL = MAX, VIH = 2 V, VO = 0.4 V
–20
µA
II
VCC = MAX, VI = 7 V
0.1
mA
IIH
VCC = MAX, VI = 2.7 V
IIL
VCC = MAX, VIL = 0.4 V
IOS (3)
VCC = MAX
–40
Outputs high
ICC
Outputs low
VCC = MAX, output open
Outputs disabled
(1)
(2)
(3)
V
µA
20
µA
–0.2
mA
–225
mA
All
17
27
SNx4LS240
26
44
SNx4LS241, SNx4LS244
27
46
SNx4LS240
29
50
SNx4LS241, SNx4LS244
32
54
mA
For conditions shown as minimum or maximum, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V and TA = 25°C.
Not more than one output must be shorted at a time, and duration of the short-circuit must not exceed one second.
6.6 Electrical Characteristics – SNx4S24x
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
VIK
VCC = MIN, II = –18 mA
Hysteresis
(VT+ − VT−)
VCC = MIN
0.2
VCC = MIN, IOH = –1 mA, VIH = 2 V, VIL = 0.8 V, SN74S24x only
2.7
VCC = MIN, IOH = –3 mA, VIH = 2 V, VIL = 0.8 V
2.4
VOH
VCC = MIN, IOH = MAX, VIH = 2 V, VIL = 0.5 V
VOL
(1)
(2)
VCC = MIN, VIL = MAX, VIH = 2 V, IOL = 0.8 V
TYP (2)
MAX
UNIT
–1.2
V
0.4
V
3.4
V
2
0.55
V
For conditions shown as minimum or maximum, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, TA = 25°C.
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Electrical Characteristics – SNx4S24x (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN
TYP (2)
MAX
UNIT
IOZH
VCC = MAX, VIL = 0.8 V, VIH = 2 V, VO = 2.4 V
50
IOZL
VCC = MAX, VIL = MAX, VIH = 2 V, VO = 0.5 V
–50
µA
II
VCC = MAX, VI = 5.5 V
1
mA
IIH
VCC = MAX, VI = 2.7 V
50
µA
IIL
VCC = MAX, VIL = 0.5 V
IOS (3)
VCC = MAX
Any A
–400
µA
Any G
–2
mA
–225
mA
–50
Outputs high
SN54S240
80
123
SN74S240
80
135
SN54S241, SN54S244
95
147
SN74S241, SN74S244
ICC
VCC = MAX, output open
Outputs low
Outputs disabled
(3)
µA
95
160
SN54S240
100
145
SN74S240
100
150
SN54S241, SN54S244
120
170
SN74S241, SN74S244
120
180
SN54S240
100
145
SN74S240
100
150
SN54S241, SN54S244
120
170
SN74S241, SN74S244
120
180
mA
Not more than one output must be shorted at a time, and duration of the short-circuit must not exceed one second.
6.7 Switching Characteristics – SNx4LS24x
VCC = 5 V, TA = 25°C (see SN54LS24x and SN74LS24x Devices)
PARAMETER
TEST CONDITIONS
MIN
SNx4LS240
TYP
MAX
9
14
12
18
UNIT
tPLH
RL = 667 Ω, CL = 45 pF
tPHL
RL = 667 Ω, CL = 45 pF
12
18
ns
tPZL
RL = 667 Ω, CL = 45 pF
20
30
ns
tPZH
RL = 667 Ω, CL = 45 pF
15
23
ns
tPLZ
RL = 667 Ω, CL = 5 pF
10
20
ns
tPHZ
RL = 667 Ω, CL = 5 pF
15
25
ns
TYP
MAX
4.5
7
6
9
4.5
7
6
9
10
15
6.5
10
8
12
SNx4LS241, SNx4LS244
ns
6.8 Switching Characteristics – SNx4S24x
VCC = 5 V and TA = 25°C (see SN54S24x and SN74S24x Devices)
PARAMETER
TEST CONDITIONS
SNx4S240
MIN
UNIT
tPLH
RL = 90 Ω, CL = 50 pF
tPHL
RL = 90 Ω, CL = 50 pF
tPZL
RL = 90 Ω, CL = 50 pF
tPZH
RL = 90 Ω, CL = 50 pF
tPLZ
RL = 90 Ω, CL = 5 pF
10
15
ns
tPHZ
RL = 90 Ω, CL = 5 pF
6
9
ns
6
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SNx4S241, SNx4S244
SNx4S240
SNx4S241, SNx4S244
SNx4S240
SNx4S241, SNx4S244
ns
ns
ns
ns
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SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
6.9 Typical Characteristics
VCC = 5 V, TA = 25°C, CL = 45 pF, and RL = 667 Ω (unless otherwise noted)
5.5
4.5
Voltage (V)
3.5
2.5
1.5
0.5
Input
Output
-0.5
0
5
10
Time (ns)
15
20
D001
Figure 1. Simulated Propagation Delay From Input to Output
7 Parameter Measurement Information
7.1 SN54LS24x and SN74LS24x Devices
Test
Point
VCC
VCC
Test
Point
RL
From Output
Under Test
(see Note B)
CL
(see Note A)
RL
S1
From Output
Under Test
CL
(see Note A)
(see Note B)
5 kΩ
S2
Figure 2. Load Circuit,
For 2-State Totem-Pole Outputs
Figure 4. Load Circuit,
For 3-State Outputs
VCC
RL
From Output
Under Test
CL
(see Note A)
Test
Point
Figure 3. Load Circuit,
For Open-Collector Outputs
Copyright © 1985–2016, Texas Instruments Incorporated
High-Level
Pulse
1.3 V
1.3 V
tw
Low-Level
Pulse
1.3 V
1.3 V
Figure 5. Voltage Waveforms,
Pulse Durations
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3V
3V
Timing
Input
Input
1.3 V
1.3 V
1.3 V
0V
0V
th
tsu
Data
Input
tPLH
3V
1.3 V
In-Phase
Output
(see Note D)
1.3 V
0V
Figure 6. Voltage Waveforms,
Setup and Hold Times
tPHL
VOH
1.3 V
1.3 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
tPLH
VOH
1.3 V
1.3 V
VOL
Figure 7. Voltage Waveforms,
Propagation Delay Times
Output
Control
(low-level
enabling)
3V
1.3 V
0V
tPZL
Waveform 1
(see Notes C
and D)
tPLZ
≈1.5 V
1.3 V
VOL + 0.3 V
VOL
tPZH
Waveform 2
(see Notes C
and D)
1.3 V
tPHZ
VOH
1.3 V
VOH – 0.3 V
≈1.5 V
A.
CL includes probe and jig capacitance.
B.
All diodes are 1N3064 or equivalent.
C.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
D.
S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E.
Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO is approximately
50 Ω, tr ≤ 15 ns, tf ≤ 6 ns.
G.
The outputs are measured one at a time with one input transition per measurement.
Figure 8. Voltage Waveforms,
Enable and Disable Times, 3-State Outputs
8
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7.2 SN54S24x and SN74S24x Devices
Test
Point
VCC
High-Level
Pulse
1.5 V
RL
From Output
Under Test
(see Note B)
CL
(see Note A)
tw
Low-Level
Pulse
1.5 V
1.5 V
0V
th
tsu
3V
Data
Input
RL
From Output
Under Test
CL
(see Note A)
3V
Timing
Input
VCC
Test
Point
1.5 V
1.5 V
0V
Figure 13. Voltage Waveforms,
Setup and Hold Times
3V
Input
RL
S1
(see Note B)
1 kΩ
1.5 V
tPLH
In-Phase
Output
(see Note D)
VCC
From Output
Under Test
1.5 V
0V
Figure 10. Load Circuit,
For Open-Collector Outputs
CL
(see Note A)
1.5 V
Figure 12. Voltage Waveforms,
Pulse Durations
Figure 9. Load Circuit,
For 2-State Totem-Pole Outputs
Test
Point
1.5 V
tPHL
VOH
1.5 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
1.5 V
tPLH
VOH
1.5 V
1.5 V
VOL
Figure 14. Voltage Waveforms,
Propagation Delay Times
S2
Figure 11. Load Circuit,
For 3-State Outputs
Copyright © 1985–2016, Texas Instruments Incorporated
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9
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
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3V
Output
Control
(low-level
enabling)
1.5 V
0V
tPZL
Waveform 1
(see Notes C
and D)
tPLZ
≈1.5 V
1.5 V
VOL
VOL + 0.5 V
tPHZ
tPZH
Waveform 2
(see Notes C
and D)
1.5 V
VOH
1.5 V
VOH − 0.5 V
≈1.5 V
A.
CL includes probe and jig capacitance.
B.
All diodes are 1N3064 or equivalent.
C.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
D.
S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO is approximately
50 Ω; tr and tf ≤ 7 ns for SN54LS24x and SN74LS24x devices, and tr and tf ≤ 2.5 ns for SN54S24x and SN74S24x
devices.
F.
The outputs are measured one at a time with one input transition per measurement.
Figure 15. Voltage Waveforms,
Enable and Disable Times, 3-State Outputs
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SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
www.ti.com
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
8 Detailed Description
8.1 Overview
This device is organized as two 4-bit buffers and drivers with separate output-enable (G) inputs. When G is low,
the device passes data from the A inputs to the Y outputs. When G is high, the outputs are in the high
impedance state. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device
as a translator in a mixed 3.3-V and 5-V system environment. To ensure the high-impedance state during power
up or power down, G must be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.
8.2 Functional Block Diagrams
1G
1
1G
1A1
2
18
1Y1
1A1
1A2
4
16
1Y2
1A2
1A3
6
14
1Y3
1A3
1A4
8
12
1Y4
1A4
2G
2A1
2A2
2A3
2A4
19
2G
11
13
15
17
9
7
5
3
2Y1
2A1
2Y2
2A2
2Y3
2A3
2Y4
2A4
1
2
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
1Y4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Pin numbers shown are for DB, DW, J, N,
NS, and W packages
Pin numbers shown are for DB, DW, J, N,
NS, and W packages
Figure 16. SNx4LS240 and SNx4S240
Logic Diagram
Copyright © 1985–2016, Texas Instruments Incorporated
Figure 17. SNx4LS241 and SNx4S241
Logic Diagram
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11
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
www.ti.com
1
1G
1A1
1A2
1A3
1A4
2G
2A1
2A2
2A3
2A4
2
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
1Y4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Copyright © 2016, Texas Instruments Incorporated
Pin numbers shown are for DB, DW, J, N, NS, and W packages
Figure 18. SNx4LS244 and SNx4S244
Logic Diagram
8.3 Feature Description
8.3.1 3-State Outputs
The 3-state outputs can drive bus lines directly. All outputs can be put into high impedance mode through the G
pin.
8.3.2 PNP Inputs
This device has PNP inputs which reduce dc loading on bus lines.
8.3.3 Hysteresis on Bus Inputs
The bus inputs have built-in hysteresis that improves noise margins.
8.4 Device Functional Modes
The SNx4LS24x and SNx4S24x devices can be used as inverting and non-inverting bus buffers for data line
transmission and can isolate input to output by setting the G pin HIGH. Table 1, Table 2, and Table 3 list the
function tables for all devices.
Table 1. SNx4LS240 and SNx4S240
Function Table
INPUTS
G
12
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OUTPUTS
A
Y
L
L
H
L
H
L
H
X
Z
Copyright © 1985–2016, Texas Instruments Incorporated
Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240
SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
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SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
Table 2. SNx4LS241 and SNx4S241
Function Table
CHANNEL 1
CHANNEL 2
INPUTS
OUTPUT
INPUTS
OUTPUT
1G
1A
1Y
2G
2A
2Y
L
L
L
H
L
L
L
H
H
H
H
H
H
X
Z
L
X
Z
Table 3. SNx4LS244 and SNx4S244
Function Table
INPUTS
OUTPUTS
G
A
Y
L
L
L
L
H
H
H
X
Z
VCC
VCC
9 kΩ NOM
R
Input
Output
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 19. SNx4LS240, SNx4LS241, SNx4LS244
Equivalent of Each Input
Copyright © 2016, Texas Instruments Incorporated
VCC
Req
SNx4LS240, SNx4LS241, SNx4LS244:
R = 50 Ω NOM
SNx4S240, SNx4S241, SNx4S244:
R = 25 Ω NOM
Figure 21. Typical of All Outputs
Input
Copyright © 2016, Texas Instruments Incorporated
G and G inputs: Req = 2 kΩ NOM
A inputs: Req = 2.8 kΩ NOM
Figure 20. SNx4S240, SNx4S241, SNx4S244
Equivalent of Each Input
Copyright © 1985–2016, Texas Instruments Incorporated
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13
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4LS24x, SNx4S24x octal buffers and line drivers are designed to be used for a multitude of bus
interface type applications where output drive or PCB trace length is a concern.
9.2 Typical Application
Driver
1/8 'LS241/'S241
Long-Line
Repeater
1/8 'LS241/'S241
Repeater
1/8 'LS241/'S241
Input
Repeater
1/8 'LS241/'S241
Receiver
1/8 'LS241/'S241
Output
CL
2.9 V
1.6 V
1.2 V
0.3 V
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Copyright © 2016, Texas Instruments Incorporated
Figure 22. SNx4LS241 and SNx4S241 Used as Repeater or Level Restorer
9.2.1 Design Requirements
This device uses Schottky transistor logic technology. Take care to avoid bus contention because it can drive
currents that would exceed maximum limits. The high drive creates fast edges into light loads, so routing and
load conditions must be considered to prevent ringing.
9.2.2 Detailed Design Procedure
• Power Supply
– Each device must maintain a supply voltage between 4.5 V and 5.5 V.
• Inputs
– Input signals must meet the VIH and VIL specifications in Electrical Characteristics – SNx4LS24x.
– Inputs leakage values (II, IIH, IIL) from Electrical Characteristics – SNx4LS24x must be considered.
• Outputs
– Output signals are specified to meet the VOH and VOL specifications in Electrical Characteristics –
SNx4LS24x as a minimum (the values could be closer to VCC for high signals or GND for low signals).
– TI recommends maintaining output currents as specified in Recommended Operating Conditions.
– The part can be damaged by sourcing or sinking too much current (see Electrical Characteristics –
SNx4LS24x for details).
14
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SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
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SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
Typical Application (continued)
9.2.3 Application Curve
0.5
0.4
VCC
@ 4.75 V
VOL
(max) V
0.3
0.2
0.1
0
3
6
9
12
15
18
21
24
27
I OL (mA)
Figure 23. VOL vs IOL
9.3 System Examples
The SNx4LS240 and SNx4S240 devices can be used to buffer signals along a memory bus. The increased
output drive helps data transmission reliability. Figure 24 shows a schematic of this example.
Control or Microprogram ROM/PROM
or
Memory Address Register
'Ls240/
'S240
Output
Control
System and/or Memory-Address Bus
Copyright © 2016, Texas Instruments Incorporated
4-bit organization can be applied to handle binary or BCD
Figure 24. SNx4LS240 and SNx4S240 Used as System or Memory Bus Driver
The SNx4LS240 and SNx4S240 devices have two independently controlled 4-bit drivers, and can be used to
buffer signals in a bidirectional manner along a data bus. Figure 25 shows the SNx4LS240 or SNx4S240 used in
this manner.
Copyright © 1985–2016, Texas Instruments Incorporated
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15
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
www.ti.com
System Examples (continued)
'LS240/'S240
From
Data
Bus
Output
Ports
G
Output-Port
Control
From
Data
Bus
Input
Ports
G
Input-Port
Control
Copyright © 2016, Texas Instruments Incorporated
Figure 25. Independent 4-Bit But Drivers/Receivers in a Single Package
The enable pins on the SNx4LS241 and SNx4S241 devices can be used to help direct signals along a shared
party-line bus. Figure 26 shows a general configuration of how to implement this structure. Take care to ensure
that bus contention does not occur.
Party-Line
Multiple-Input/Output Bus
1/4 'LS241/'S241
Driver
1/4 'LS241/'S241
Driver
Input A
To Other
Buffers
Input B
To Other
Buffers
Output A
Output B
Bus
Control
H
H
L
L
H
H
L
L
H
L
Receivers
Input
Output
Bus
Control
B
A
L
L
B
B
H L
A
B
H H
A
A
L H
None
None
L H
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Party-Line Bus System With Multiple Inputs, Outputs, and Receivers
16
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SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
www.ti.com
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-µF bypass capacitor. If there are multiple
VCC pins, TI recommends a 0.01-µF or 0.022-µF bypass capacitors for each power pin. It is acceptable to parallel
multiple bypass capacitors to reject different frequencies of noise. Two bypass capacitors of value 0.1 µF and
1 µF are commonly used in parallel. For best results, install the bypass capacitor(s) as close to the power pin as
possible.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not be left floating. In many applications, some channels of the
SNx4LS24x, SNx4S24x are unused, and thus must be terminated properly. Because each transceiver channel
pin can be either an input or an output, they must be treated as both when being terminated. Ground or VCC
(whichever is more convenient) can be used to terminate unused inputs; however, each unused channel should
be terminated to the same logic level on both the A and Y side. For example, in Figure 27 unused channels are
terminated correctly with both sides connected to the same voltage, while channel 8 is terminated incorrectly with
each side being tied to a different voltage. The G input is also unused in this example, and is terminated directly
to ground to permanently enable all outputs.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 27. Example Demonstrating How to Terminate Unused Inputs and Channels of a Transceiver
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17
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
SUPPORT &
COMMUNITY
SN54LS240
Click here
Click here
Click here
Click here
SN74LS241
Click here
Click here
Click here
Click here
SN74LS244
Click here
Click here
Click here
Click here
SN54S240
Click here
Click here
Click here
Click here
SN54S241
Click here
Click here
Click here
Click here
SN54S244
Click here
Click here
Click here
Click here
SN74LS240
Click here
Click here
Click here
Click here
SN74LS241
Click here
Click here
Click here
Click here
SN74LS244
Click here
Click here
Click here
Click here
SN74S240
Click here
Click here
Click here
Click here
SN74S241
Click here
Click here
Click here
Click here
SN74S241
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
18
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SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244
www.ti.com
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1985–2016, Texas Instruments Incorporated
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Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240
SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
19
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-7801201VSA
ACTIVE
CFP
W
20
25
TBD
A42
N / A for Pkg Type
-55 to 125
5962-7801201VS
A
SNV54LS240W
7705701RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7705701RA
SNJ54LS244J
7705701SA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7705701SA
SNJ54LS244W
78012012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
78012012A
SNJ54LS
240FK
7801201RA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7801201RA
SNJ54LS240J
7801201SA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7801201SA
SNJ54LS240W
JM38510/32401B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
32401B2A
JM38510/32401BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32401BRA
JM38510/32401BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32401BSA
JM38510/32402B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
32402B2A
JM38510/32402BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32402BRA
JM38510/32402BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32402BSA
JM38510/32403B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
32403B2A
JM38510/32403BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403BRA
JM38510/32403BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403BSA
JM38510/32403SRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403SRA
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
JM38510/32403SSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403SSA
M38510/32401B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
32401B2A
M38510/32401BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32401BRA
M38510/32401BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32401BSA
M38510/32402B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
32402B2A
M38510/32402BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32402BRA
M38510/32402BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32402BSA
M38510/32403B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
32403B2A
M38510/32403BRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403BRA
M38510/32403BSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403BSA
M38510/32403SRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403SRA
M38510/32403SSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
32403SSA
SN54LS240J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54LS240J
SN54LS241J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54LS241J
SN54LS244J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54LS244J
SN54S240J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54S240J
SN54S241J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54S241J
SN54S244J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54S244J
SN74LS240DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 2
LS240
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LS240DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS240
SN74LS240DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS240
SN74LS240DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS240
SN74LS240N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74LS240N
SN74LS240NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74LS240N
SN74LS240NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS240
SN74LS241DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS241
SN74LS241DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS241
SN74LS241N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74LS241N
SN74LS241NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS241
SN74LS244DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244DBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244DWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS244
SN74LS244N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74LS244N
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LS244NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74LS244N
SN74LS244NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS244
SN74LS244NSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS244
SN74S240DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S240
SN74S240DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S240
SN74S240N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74S240N
SN74S240NE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74S240N
SN74S241DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S241
SN74S241N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74S241N
SN74S244DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S244
SN74S244DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S244
SN74S244DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
S244
SN74S244N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
SN74S244N
SNJ54LS240FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
78012012A
SNJ54LS
240FK
SNJ54LS240J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7801201RA
SNJ54LS240J
SNJ54LS240W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7801201SA
SNJ54LS240W
SNJ54LS241FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
SNJ54LS
241FK
SNJ54LS241J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54LS241J
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SNJ54LS241W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54LS241W
SNJ54LS244FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
SNJ54LS
244FK
SNJ54LS244J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7705701RA
SNJ54LS244J
SNJ54LS244W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
7705701SA
SNJ54LS244W
SNJ54S240FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
SNJ54S
240FK
SNJ54S240J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54S240J
SNJ54S240W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54S240W
SNJ54S241FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
SNJ54S
241FK
SNJ54S241J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54S241J
SNJ54S244J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54S244J
SNJ54S244W
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
SNJ54S244W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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