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SN55HVD75-EP
SLOS913A – OCTOBER 2015 – REVISED FEBRUARY 2017
SN55HVD75-EP 3.3-V Supply RS-485 With IEC ESD Protection
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
Bus I/O Protection
– >±15-kV HBM Protection
– >±12-kV IEC 61000-4-2 Contact Discharge
– >±4-kV IEC 61000-4-4 Fast Transient Burst
Extended Industrial Temperature Range
–55°C to 125°C
Large Receiver Hysteresis (80 mV) for Noise
Rejection
Low-Unit-Loading Allows Over 200 Connected
Nodes
Low-Power Consumption
– Low-Standby Supply Current: < 2 µA
– ICC < 1-mA Quiescent During Operation
5-V Tolerant Logic Inputs Compatible With
3.3-V or 5-V Controllers
Signaling Rate Options Optimized for:
250 kbps, 20 Mbps, 50 Mbps
Available in a Small VSON Package
Supports Defense, Aerospace, and Medical
Applications:
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Available in Extended (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
Factory Automation
Telecommunications Infrastructure
Motion Control
3 Description
These devices have robust 3.3-V drivers and
receivers in a small package for demanding industrial
applications. The bus pins are robust to ESD events
with high levels of protection to human-body model
and IEC contact discharge specifications.
Each of these devices combines a differential driver
and a differential receiver which operate from a single
3.3-V power supply. The driver differential outputs
and the receiver differential inputs are connected
internally to form a bus port suitable for half-duplex
(two-wire bus) communication. These devices feature
a wide common-mode voltage range making the
devices suitable for multi-point applications over long
cable runs. These devices are characterized from
–55°C to 125°C.
Device Information(1)
PART NUMBER
PACKAGE
SN55HVD75-EP
VSON (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
R
B
A
D
R RE DE D
R
RE
B
DE
D
B
D
D
R RE DE D
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55HVD75-EP
SLOS913A – OCTOBER 2015 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ...................................... 3
ESD Ratings.............................................................. 3
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Switching Characteristics: 20 Mbps Device, Bit Time
≥50 ns ........................................................................ 6
6.7 Typical Characteristics .............................................. 7
7
8
Parameter Measurement Information .................. 8
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 15
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Original (October 2015) to Revision A
Page
•
Deleted reference to RS-422 throughout the data sheet ....................................................................................................... 1
•
Deleted TJ and VCC test conditions from |VOD|, RL = 100 Ω ................................................................................................... 5
•
Changed |VOD|, RL = 100 Ω minimum from 2 V : to 1.8 V ..................................................................................................... 5
•
Added Receiving Notification of Documentation Updates section to Device and Documentation Support section............. 24
2
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SLOS913A – OCTOBER 2015 – REVISED FEBRUARY 2017
5 Pin Configuration and Functions
DRB Package
8-Pin VSON
Top View
R
1
8
VCC
RE
2
7
B
DE
3
6
A
D
4
5
GND
Pin Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
A
6
Bus I/O
Driver output or receiver input (complementary to B).
B
7
Bus I/O
Driver output or receiver input (complementary to A).
D
4
Digital input
Driver data input.
DE
3
Digital input
Active-high driver enable.
GND
5
Reference potential
Local device ground.
R
1
Digital output
Receive data output .
RE
2
Digital input
VCC
8
Supply
Active-low receiver enable.
3-V to 3.6-V supply.
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating range (unless otherwise specified)
(1)
MIN
MAX
UNIT
Supply voltage, VCC
–0.5
5.5
V
Voltage at A or B inputs
–13
16.5
V
Input voltage at any logic pin
–0.3
5.7
V
Voltage input, transient pulse, A and B, through 100 Ω
–100
100
V
Receiver output current
–24
24
mA
170
°C
150
°C
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
Electrostatic
discharge
(1)
All pins
±8000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
All pins
±1500
JEDEC standard 22, test method A115 (machine model)
All pins
±300
IEC 61000-4-2 ESD (air-gap discharge)
(3)
Pins 5 to 7
±12000
IEC 61000-4-2 ESD (contact discharge)
Pins 5 to 7
±12000
IEC 61000-4-4 EFT (fast transient or burst)
Pins 5 to 7
±4000
IEC 60749-26 ESD HBM
Pins 5 to 7
±15000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
By inference from contact discharge results, see Application and Implementation.
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6.3 Recommended Operating Conditions
VCC
Supply voltage
(1)
MIN
NOM
MAX
3
3.3
3.6
UNIT
V
VI
Input voltage at any bus terminal (separately or common mode)
–7
12
V
VIH
High-level input voltage (driver, driver enable, and receiver enable inputs)
2
VCC
V
VIL
Low-level input voltage (driver, driver enable, and receiver enable inputs)
0
0.8
V
VID
Differential input voltage
–12
12
V
IO
Output current, driver
–60
60
mA
IO
Output current, receiver
–8
8
mA
RL
Differential load resistance
54
CL
Differential load capacitance
1/tUI
Signaling rate
20
Mbps
TA (2)
Operating free-air temperature (see Thermal Information)
–55
125
°C
TJ
Junction temperature
–55
150
°C
(1)
(2)
60
Ω
50
pF
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables
the driver outputs when the junction temperature reaches 170°C.
6.4 Thermal Information
SN55HVD75-EP
THERMAL METRIC (1)
DRB (VSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
40.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.9
°C/W
RθJB
Junction-to-board thermal resistance
15.5
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
15.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating range (unless otherwise specified)
PARAMETER
|VOD|
TEST CONDITIONS
RL = 60 Ω, 375 Ω on each output to
–7 V to 12 V
Driver differential output
voltage magnitude
RL = 54 Ω (RS-485)
See
Figure 6
RL = 100 Ω
Δ|VOD|
Change in magnitude of
driver differential output RL = 54 Ω, CL = 50 pF
voltage
VOC(SS)
Steady-state commonmode output voltage
ΔVOC
Change in differential
driver output commonmode voltage
VOC(PP)
Peak-to-peak driver
common-mode output
voltage
COD
Differential output
capacitance
VIT+
Positive-going receiver
differential input voltage
threshold
VIT–
Negative-going receiver
differential input voltage
threshold
VHYS
Receiver differential
input voltage threshold
hysteresis (VIT+ – VIT–)
VOH
Receiver high-level
output voltage
IOH = –8 mA
VOL
Receiver low-level
output voltage
IOL = 8 mA
II
Driver input, driver
enable, and receiver
enable input current
IOZ
Receiver output highimpedance current
IOS
Driver short-circuit
output current
II
Bus input current
(disabled driver)
ICC
Supply current
(quiescent)
Supply current
(dynamic)
(1)
MIN
TYP
1.5
2
1.5
2
1.8
2.5
–50
0
50
mV
1
VCC/2
3
V
–50
0
50
mV
See
Figure 7
Center of two 27-Ω load resistors
V
mV
15
pF
–70
–200
–150
50
80
2.4
VCC – 0.3
0.2
VO = 0 V or VCC, RE at VCC
–20
mV
(1)
mV
See
mV
V
0.4
V
–2.75
2.75
µA
–1
1
µA
–165
165
mA
VCC = 3 V to 3.6 V
or
VCC = 0 V
DE at 0 V
VI = 12 V
Driver and receiver
enabled
DE = VCC, RE = GND
No load
750
950
Driver enabled,
receiver disabled
DE = VCC, RE = VCC
No load
300
500
Driver disabled,
receiver enabled
DE = GND, RE = GND
No load
600
800
Driver and receiver
disabled
DE = GND, D = open
RE = VCC, No load
0.1
2
VI = –7 V
UNIT
200
(1)
See
MAX
75
–100
150
µA
–40
µA
See Typical Characteristics
Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.
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6.6 Switching Characteristics: 20 Mbps Device, Bit Time ≥50 ns
over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
7
14
ns
6
11
17
ns
DRIVER
Driver differential output rise or
fall time
tr, tf
tPHL, tPLH
Driver propagation delay
tSK(P)
Driver pulse skew, |tPHL – tPLH|
tPHZ, tPLZ
Driver disable time
tPZH, tPZL
Driver enable time
RL = 54 Ω
CL = 50 pF
Receiver enabled
See Figure 8
See Figure 9 and
Figure 10
Receiver disabled
0
2
ns
12
50
ns
10
20
ns
3
7
µs
5
10
ns
60
70
ns
RECEIVER
tr, tf
Receiver output rise or fall time
tPHL, tPLH
Receiver propagation delay time
tSK(P)
Receiver pulse skew, |tPHL – tPLH|
tPLZ, tPHZ
Receiver disable time
tpZL(1), tPZH(1),
Receiver enable time
tPZL(2), tPZH(2)
6
CL = 15 pF
See Figure 11
0
6
ns
15
30
ns
Driver enabled
See Figure 12
10
50
ns
Driver disabled
See Figure 13
3
8
µs
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6.7 Typical Characteristics
3.5
VO - Driver Differential Output Voltage - V
VO - Driver Output Voltage - V
3.5
VOH
3
2.5
2
1.5
VOL
1
0.5
0
0
20
40
60
80
IO - Driver Output Current - mA
VCC = 3.3 V
DE = VCC
2
1.5
1
0.5
0
D=0V
60 W
2.5
100
0
20
40
60
80
IO - Driver Output Current - mA
VCC = 3.3 V
Figure 1. Driver Output Voltage vs Driver Output Current
100
DE = VCC
D=0V
Figure 2. Driver Differential Output Voltage vs Driver Output
Current
40
70
35
60
30
50
ICC - Supply Current - mA
IO - Driver Output Current - mA
100 W
3
25
20
15
10
40
30
20
10
5
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
2
4
VCC Supply Voltage - V
TA = 25°C
DE = VCC
6
8
10
12
14
16
18
20
Signaling Rate - Mbps
RL = 54 Ω
D = VCC
RL = 54 Ω
Figure 3. Driver Output Current vs Supply Voltage
Figure 4. Supply Current vs Signal Rate
3.5
Receiver Output (R) V
3
2.5
VIT- (-7V)
2
VIT-(0V)
VIT-(12V)
1.5
VIT+(-7V)
VIT+(0V)
1
VIT+(12V)
0.5
0
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
Differential Input Voltage (VID) mV
Figure 5. Receiver Output vs Input
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7 Parameter Measurement Information
Input generator rate is 100 kbps, 50% duty cycle, rise or fall time is less than 6 ns, output impedance is 50 Ω.
375 W ±1%
VCC
DE
0 V or 3 V
D
A
VOD
60 W ±1%
B
+
_
–7 V < V(test) < 12 V
375 W ±1%
S0301-01
Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
VA
B
VB
RL/2
A
0 V or 3 V
A
D
VOD
VOC(PP)
B
RL/2
CL
DVOC(SS)
VOC
VOC
S0302-01
Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
50%
50%
A
:
|
:
B
|
Copyright © 2016, Texas Instruments Incorporated
Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
3V
D
DE
Input
Generator
VI
50 W
A
3V
S1
B
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
VO
VI
RL = 110 W
± 1%
50%
50%
0.5 V
tPZH
VO
0V
VOH
90%
50%
tPHZ
»0V
S0304-01
D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
8
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Parameter Measurement Information (continued)
3V
A
D
3V
S1
VO
»3V
VI
50%
50%
0V
B
DE
Input
Generator
RL = 110 W
±1%
tPZL
tPLZ
CL = 50 pF ±20%
VI
50 W
»3V
CL Includes Fixture
and Instrumentation
Capacitance
VO
50%
10%
VOL
S0305-01
D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active Low Output and Pullup Load
3V
A
Input
Generator
R
VI
50 W
1.5 V
0V
VI
VO
50%
50%
0V
B
tPLH
CL = 15 pF ±20%
RE
VO
CL Includes Fixture
and Instrumentation
Capacitance
tPHL
90% 90%
50%
10%
50%
10%
tr
VOH
VOL
tf
S0306-01
Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
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Parameter Measurement Information (continued)
3V
VCC
DE
A
0 V or 3 V D
B
RE
Input
Generator
VI
1 kW ± 1%
R VO
S1
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
50%
0V
tPZH(1)
tPHZ
VOH
90%
VO
50%
D at 3 V
S1 to GND
»0V
tPZL(1)
tPLZ
VCC
VO
50%
D at 0 V
S1 to VCC
10%
VOL
S0307-01
Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled
10
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Parameter Measurement Information (continued)
VCC
A
0 V or 1.5 V
R VO
S1
B
1.5 V or 0 V
RE
Input
Generator
VI
1 kW ± 1%
CL = 15 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
50 W
3V
VI
50%
0V
tPZH(2)
VOH
VO
A at 1.5 V
B at 0 V
S1 to GND
50%
GND
tPZL(2)
VCC
VO
50%
VOL
A at 0 V
B at 1.5 V
S1 to VCC
S0308-01
Figure 13. Measurement of Receiver Enable Times With Driver Disabled
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8 Detailed Description
8.1 Overview
The SN55HVD75-EP is a low-power, half-duplex RS-485 transceiver available in a speed grade suitable for data
transmission up to 20 Mbps.
This device has active-high driver enables and active-low receiver enables. A standby current of less than 2 µA
can be achieved by disabling both driver and receiver.
8.2 Functional Block Diagram
8.3 Feature Description
Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±12 kV, and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to
±4 kV.
The SN55HVD75-EP half-duplex family provides internal biasing of the receiver input thresholds in combination
with large input threshold hysteresis. At a positive input threshold of VIT+ = –20 mV and an input hysteresis of
VHYS = 50 mV, the receiver output remains logic high under a bus-idle or bus-short condition even in the
presence of 140-mVPP differential noise without the need for external failsafe biasing resistors.
Device operation is specified over a wide ambient temperature range from –55°C to 125°C.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pulldown resistor to ground; thus, when left open, the driver is disabled (high-impedance) by
default. The D pin has an internal pullup resistor to VCC; thus, when left open while the driver is enabled, output A
turns high and B turns low.
Table 1. Driver Function Table
12
INPUT
ENABLE
OUTPUTS
D
DE
A
H
H
H
L
Actively drive bus high.
L
H
L
H
Actively drive bus low.
X
L
Z
Z
Driver disabled.
X
OPEN
Z
Z
Driver disabled by default.
OPEN
H
H
L
Actively drive bus high by default.
DESCRIPTION
B
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output turns low.
If VID is between VIT+ and VIT–, the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = VA – VB
RE
R
VIT+ < VID
L
H
Receive valid bus high.
VIT– < VID < VIT+
L
?
Indeterminate bus state.
VID < VIT–
L
L
Receive valid bus low.
X
H
Z
Receiver disabled.
X
OPEN
Z
Receiver disabled by default.
Open-circuit bus
L
H
Failsafe high output.
Short-circuit bus
L
H
Failsafe high output.
Idle (terminated) bus
L
H
Failsafe high output.
D and RE Inputs
D , RE
DESCRIPTION
DE Input
Vcc
3M
1. 5 k
Vcc
R Output
Vcc
1. 5 k
DE
R
9V
9V
9V
1M
Receiver Inputs
Vcc
Driver Outputs
Vcc
R2
R2
R1
A
B
A
R
R1
B
16 V
R3
R3
16 V
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Figure 14. Equivalent Input and Output Circuit Diagrams
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN55HVD75-EP is a half-duplex RS-485 transceiver commonly used for asynchronous data transmission.
The driver and receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
R
R
RE
A
RE
A
RE
A
DE
B
DE
B
DE
B
D
D
a) Independent driver and
receiver enable signals
D
D
D
b) Combined enable signals for
use as directional control pin
D
c) Receiver always on
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Transceiver Configurations
Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be
turned on and off individually. While this configuration requires two control lines, it allows for selective listening
into the bus traffic, whether the driver is transmitting data or not.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver
when the direction-control line is low.
Additionally, only one line is required when connecting the receiver-enable input to ground and controlling only
the driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.
14
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9.2 Typical Application
An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over
long cable lengths.
R
R
RE
B
DE
D
R
A
R
A
RT
RT
D
A
B
R
A
R RE DE D
DE
D
B
R
D
RE
B
D
D
R RE DE D
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Typical RS-485 Network With SN55HVD75-EP Transceivers
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and
RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for
small signal jitter of up to 5 or 10%.
10000
Cable Length (ft)
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
Data Rate (bps)
Figure 17. Cable Length vs Data Rate Characteristic
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Typical Application (continued)
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
Lstub ≤ 0.1 × tr × v × c
where:
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
Per Equation 1, Table 3 shows the maximum cable-stub lengths for the minimum driver output rise times of the
SN55HVD75-EP half-duplex transceiver for a signal velocity of 78%.
Table 3. Maximum Stub Length
DEVICE
MINIMUM DRIVER OUTPUT RISE TIME
(ns)
SN55HVD75-EP
2
MAXIMUM STUB LENGTH
(m)
(ft)
0.05
0.16
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a receiver input current of 1 mA at 12 V, or a load impedance of approximately 12 kΩ. Because the
SN55HVD75-EP has a receiver input current of 150 µA at 12 V, they are 3/20 UL transceivers, and no more than
213 transceivers should be connected to the bus.
9.2.1.4
Receiver Failsafe
The differential receiver is failsafe to invalid bus states caused by:
• Open bus conditions such as a disconnected connector
• Shorted bus conditions such as cable damage shorting the twisted-pair together, or
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high so that the output of the receiver is
not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input-indeterminate range
does not include 0-V differential. To comply with RS-485 standards, the receiver output must output a high when
the differential input VID is more positive than 200 mV, and must output a low when VID is more negative than
–200 mV. The receiver parameters which determine the failsafe performance are VIT+, VIT–, and VHYS (the
separation between VIT+ and VIT–). As shown in Electrical Characteristics, differential signals more negative than
–200 mV will always cause a low receiver output, and differential signals more positive than 200 mV will always
cause a high receiver output.
When the differential input signal is close to zero, it is still above the maximum VIT+ threshold of –20 mV, and the
receiver output will be high. Only when the differential input is more than VHYS below VIT+ will the receiver output
transition to a low state. Therefore, the noise immunity of the receiver inputs during a bus fault condition includes
the receiver hysteresis value, VHYS, as well as the value of VIT+.
16
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R
VHYS-min
50mV
-70
-20
VID - mV
70
0
Vnoise-max = 140mVpp
Figure 18. Noise Immunity
9.2.1.5 Transient Protection
The bus pins of the SN55HVD75-EP transceiver family possess on-chip ESD protection against ±15-kV human
body model (HBM) and ±12-kV IEC 61000-4-2 contact discharge. The IEC-ESD test is far more severe than the
HBM-ESD test. The 50% higher charge capacitance, CS, and 78% lower discharge resistance, RD, of the IECmodel produce significantly higher discharge currents than the HBM-model.
As stated in the IEC 61000-4-2 standard, contact discharge is the preferred test method; although IEC air-gap
testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact
discharge test results.
RD
50M
(1M)
High-Voltage
Pulse
Generator
330
(1.5k)
CS
150pF
(100pF)
Device
Under
Test
Current - A
RC
40
35
30
25
20
15
10
5
0
10kV IEC
10kV HBM
0
50
100
150
200
250
300
Time - ns
Copyright © 2016, Texas Instruments Incorporated
Figure 19. HBM and IEC-ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur due to human contact with connectors and cables. Designers may choose to implement
protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 20 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left-hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right-hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
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SN55HVD75-EP
22
20
18
16
14
12
10
8
6
4
2
0
www.ti.com
Pulse Power (MW)
Pulse Power (kW)
SLOS913A – OCTOBER 2015 – REVISED FEBRUARY 2017
0.5-kV Surge
4-kV EFT
10-kV ESD
0
5
10
15
20
25
30
35
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
0.5-kV Surge
0
40
5
10
15
20
25
30
35
40
Time (µs)
Time (µs)
Figure 20. Power Comparison of ESD, EFT, and Surge Transients
In the case of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy which heats and destroys the protection cells, thus destroying the transceiver.
Figure 21 shows the large differences in transient energies for single ESD, EFT, and surge transients, as well as
for an EFT pulse train, commonly applied during compliance testing.
1000
100
Surge
10
1
Pulse Energy (J)
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 21. Comparison of Transient Energies
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9.2.2 Detailed Design Procedure
9.2.2.1 External Transient Protection
To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is necessary. Figure 22 suggests two circuits that provide protection against light and heavy surge transients, in
addition to ESD and EFT transients. Table 4 presents the associated bill of materials.
Table 4. Bill of Materials
DEVICE
FUNCTION
ORDER NUMBER
MANUFACTURER
XCVR
3.3-V, 250-kbps RS-485 transceiver
SN55HVD75DRBREP
R1, R2
10-Ω, pulse-proof thick-film resistor
CRCW060310RJNEAHP
Vishay
TVS
Bidirectional 400-W transient suppressor
CDSOT23-SM712
Bourns
TBU1, TBU2
Bidirectional surge suppressor
TBU-CA-065-200-WH
Bourns
MOV1, MOV2
200-mA Transient blocking unit, 200-V, metal-oxide
varistor
MOV-10D201K
Bourns
Vcc
Vcc
Vcc
10k
1
R
2
RE
DIR
3
DE
TxD
4
D
RxD
MCU
TI
Vcc
8
B
7
A
6
GND
5
XCVR
0.1 F
Vcc
10k
R1
1
R
2
RE
DIR
3
DE
TxD
4
D
RxD
TVS
MCU
Vcc
8
B
7
A
6
GND
5
XCVR
R2
10k
0.1 F
R1
TBU1
MOV1
TVS
MOV2
R2
10k
TBU2
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Transient Protections against ESD, EFT, and Surge Transients
The left-hand circuit provides surge protection of ≥500-V surge transients, while the right-hand circuit can
withstand surge transients of up to 5 kV.
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9.2.2.2 Isolated Bus Node Design
Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their
disruptive impact on signal integrity. An isolated bus node typically includes a microcontroller that connects to the
bus transceiver via a multi-channel, digital isolator (Figure 23).
0.1 F
2
Vcc D2 3
1:1.33 MBR0520L
SN6501
GND D1
N
3
1
10 F
IN
OUT
1
3.3VISO
TLV70733
10 F 0.1 F
4,5
L1
4
EN
GND
2
10 F
MBR0520L
ISO-BARRIER
3.3V
0.1 F
PSU
0.1 F
PE
0.1 F
4.7k
PE
2
DVcc
5
6
XOUT
XIN
UCA0RXD
P3.0
MSP430
F2132
DVss
P3.1
UCA0TXD
4
16
11
12
15
1
16
Vcc1
Vcc2
7
10
EN1 ISO7241 EN2
11
6
OUTD
IND
3
14
INA
OUTA
4
13
OUTB
INB
5
12
INC
OUTC
GND1
GND2
2,8
0.1 F
4.7k
1
R
8
Vcc
7
B
RE SN65
3
DE HVD72 6
A
4
D GND2
2
5
R1
R2
TVS
9,15
R HV
Short thick Earth wire or Chassis
Protective Earth Ground,
Equipment Safety Ground
Floating RS-485 Common
C HV
PE
island
R1,R2, TVS: see Table 1
RHV = 1M , 2kV high-voltage resistor, TT electronics, HVC 2010 1M0 G T3
CHV = 4.7nF, 2kV high-voltage capacitor, NOVACAP, 1812 B 472 K 202 N T
Copyright © 2016, Texas Instruments Incorporated
Figure 23. Isolated Bus Node with Transient Protection
Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.
Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are
pulled up via 4.7-kΩ resistors to limit their input currents during transient events.
While the transient protection is similar to the one in Figure 22 (left circuit), an additional high-voltage capacitor is
used to divert transient energy from the floating RS-485 common further toward Protective Earth (PE) ground.
This is necessary as noise transients on the bus are usually referred to Earth potential.
RHV refers to a high voltage resistor, and in some applications even a varistor. This resistance is applied to
prevent charging of the floating ground to dangerous potentials during normal operation.
Occasionally varistors are used instead of resistors to rapidly discharge CHV, if it is expected that fast transients
might charge CHV to high-potentials.
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire
connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically
the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are
connecting to the chassis at the other end.
20
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9.2.3 Application Curve
RL = 60 Ω
Figure 24. 20 Mbps
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10 Power Supply Recommendations
To assure reliable operation at all data rates and supply voltages, each supply should be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 is a linear voltage regulator
suitable for the 3.3-V supply.
See SN6501 Transformer Driver for Isolated Power Supplies (SLLSEA0) for isolated power supply designs.
11 Layout
11.1 Layout Guidelines
On-chip IEC ESD protection is sufficient for laboratory and portable equipment but often insufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the
use of external transient protection devices.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.
For a successful PCB design, start with the design of the protection circuit in mind.
• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
• Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during
transient events.
• Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into
the transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to 200 mA.
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11.2 Layout Example
5
Via to ground
Via to VCC
4
6 R
1
R
MCU
R
7
5
R
6 R
SN65HVD7x
JMP
C
R
TVS
5
Figure 25. SN55HVD75-EP Half-Duplex Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN55HVD75DRBREP
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
HVD75M
V62/15608-01XE
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
HVD75M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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